HI-8588
ARINC 429 LINE RECEIVER
August 2006
DESCRIPTION
PIN CONFIGURATION
The HI-8588 is an ARINC 429 bus interface receiver and is
available in a SO 8 pin package. The technology is
analog/digital CMOS. The circuitry requires only a 5 volt
supply.
The ARINC bus can be connected directly to the chip. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are
just below the standard 6.5 volt minimum ARINC data
threshold and just above the standard 2.5 volt maximum
ARINC null threshold.
The TESTA and TESTB inputs bypass the analog for
testing purposes. Also if TESTA and TESTB are both taken
high, the analog powers down and the digital outputs tristate allowing wire-or possibilities.
Please refer to the HI-8588-10 for applications where an
external resistance in series with the ARINC inputs is
required for lightning protection or when the digital outputs
need to be a logic zero rather than open circuit when
TESTA and TESTB are both high.
See Holt Application Note AN-300 for more information on
lightning protection.
FEATURES
!
!
!
!
!
VCC - 1
8 - TESTB
TESTA - 2
7 - ROUTB
8588PS
RINB - 3
6 - ROUTA
RINA - 4
5 - GND
8 - PIN PLASTIC NARROW BODY SOIC
SUPPLY VOLTAGES
vcc = 5.0V ± 5%
FUNCTION TABLE
RECEIVER
RINA
RINB
TESTA
TESTB
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
-3.25V to -6.5V
3.25V to 6.5V
0
0
0
1
3.25V to 6.5V
-3.25V to -6.5V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
HI-Z
HI-Z
Direct ARINC 429 line receiver interface
in a small outline package
ROUTA ROUTB
Receiver input hystersis at least 2 volts
Test inputs that bypass analog input and
can power down and tri-state outputs
PIN DESCRIPTION TABLE
PIN
Plastic and ceramic package options surface mount and DIP
Mil processing available
(DS8588 Rev. C)
SYMBOL
FUNCTION
DESCRIPTION
1
VCC
SUPPLY
5 VOLT SUPPLY
2
TESTA
LOGIC INPUT
CMOS
3
RINB
ARINC INPUT
RECEIVER B INPUT
4
RINA
ARINC INPUT
RECEIVER A INPUT
5
GND
POWER
GROUND
6
ROUTA
7
ROUTB
LOGIC OUTPUT
RECEIVER CMOS OUTPUT B
8
TESTB
LOGIC INPUT
CMOS
HOLT INTEGRATED CIRCUITS
www.holtic.com
LOGIC OUTPUT
RECEIVER CMOS OUTPUT A
08/06
HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typically 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resistors at the ARINC input.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
TEST
ONE
S
Q
ROUTA
LATCH
TEST
R
TESTA ' TESTB
TESTA
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
Q
ROUTB
LATCH
TEST
R
TESTA ' TESTB
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
HARDWIRE
OR
DRIVE FROM LOGIC
{
2
8
4
APPLICATION INFORMATION
ARINC
Channel
3
VCC
TESTA
ROUTA
TESTB
ROUTB
6
RXD1
7
RXD0
HI-8588
RINA
HI-6010
RINB
5
Figure 2 shows a possible application
of the HI-8588 interfacing an ARINC receive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
15V
1
6
ARINC
Channel
7
8
SLP1.5
V+
TXAOUT
TX1IN
HI-8586
TXBOUT
TX0IN
GND
4
V-
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
8 BIT BUS
3
TXD1
2
TXD0
HI-8588
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Voltages referenced to Ground
Supply voltages
VCC...................................................7V
Supply Voltages
VCC...........................................5V ± 5%
ARINC input - pins 3 & 4
Voltage at either pin......+29V to -29V
Temperature Range
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
DC current per input pin................ ±10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
NOTE: Stresses above absolute maximum
ratings or outside recommended operating conditions may cause permanent damage to the
device. These are stress ratings only. Operation at the limits is not recommended.
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL
TEST CONDITIONS
ARINC input voltage
one or zero
null
common mode
V DIN
VNIN
VCOM
logic input voltage
high
low
V IH
V IL
ARINC input resistance
RINA to RINB
RINA or RINB to Gnd or VCC
R DIFF
R SUP
supplies floating
"
"
logic input current
source
sink
I IH
I IL
V IN = 0 V
V IN = 5 V
logic output drive current
one
zero
I OH
I OL
V = 4.6V
OH
V = 0.4V
OL
Current drain
operating
powerdown
I CC1
I CC2
pins 2, 8 = 0V; pins 3, 4 open
pins 2, 8 = 5V; pins 3, 4 open
differential voltage, pins 3 & 4
"
"
"
with respect to Ground
HOLT INTEGRATED CIRCUITS
3
MIN
TYP
MAX
UNITS
6.5
-
10
-
13
2.5
5.0
volts
volts
volts
3.5
-
-
1.5
volts
volts
30
19
75
40
-
Kohm
Kohm
-
-
0.1
0.1
µA
µA
3.6
-1.6
5.6
-0.8
-
mA
mA
-
2.3
0.36
6.3
0.6
mA
mA
HI-8588
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver propagation delay
Output high to low
Output low to high
t phlr
t plhr
-
600
600
-
ns
ns
Receiver output transition times
Output high to low
Output low to high
t fr
t rr
-
50
50
80
80
ns
ns
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
CAD
CAS
C IN
-
5
-
10
10
10
pF
pF
pF
defined in Figure 3, C L= 50pF
Notes: 1. Guaranteed but not tested
10V
VDIFF
pin 4 - pin 3
0V
-10V
t plhr
t rr
t phlr
5V
0V
90%
pin 6
10%
t plhr
t phlr
t fr
5V
0V
pin 7
FIGURE 3 - RECEIVER TIMING
ORDERING INFORMATION
HI - 8588 xx x x
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
M
-55°C TO +125°C
M
YES
PART
NUMBER
PD
PS
CR
PACKAGE
DESCRIPTION
8 PIN PLASTIC DIP (not available with “M” flow)
8 PIN PLASTIC NARROW BODY SOIC
8 PIN CERDIP (not available Pb-free)
HOLT INTEGRATED CIRCUITS
4
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385 ± .015
(4.699 ± .381)
.250 ± .010
(6.350 ± .254)
.100 ± .010
(3.540 ± .254)
.300 ± .010
(7.620 ± .254)
7° TYP.
.025 ± .010
(.635 ± .254)
.135 ± .015
(3.429 ± .381)
.1375 ± .0125
(3.493 ± .318)
.0115 ± .0035
(.292 ± .089)
.055 ± .010
(1.397 ± .254)
.019 ± .002
(.483 ± .102)
.335 ± .035
(8.509 ± .889)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
Package Type: 8HN
.1935 ± .0035
(4.915 ± .085)
.0086 ± .0012
(.2184 ± .0305)
.236 ± .008
(5.994 ± .203)
PIN 1
.1535 ± .0035
(3.90 ± .09)
.0165 ± .0035
(.4191 ± .0889)
Detail A
.055 ± .005
(1.397 ± .127)
0° to 8°
.050 ± .010
(1.27 ± .254)
.033 ± .017
(.8382 ± .4318)
Detail A
HOLT INTEGRATED CIRCUITS
5
.0069 ± .0029
(.1753 ± .0737)
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERDIP
Package Type: 8D
.380 ± .004
(9.652 ± .102)
.005 MIN.
(.127 MIN.)
.248 ± .003
(6.299 ± .076)
.039 ± .006
(.991 ± .154)
.100 ± .008
(2.540 ± .203)
.015 MIN.
(.381 MIN.)
.200 MAX.
(5.080 MAX.)
.314 ± .003
(7.976 ± .076)
Base Plane
.010 ± .006
(.254 ± .152`)
Seating Plane
.163 ± .037
(4.140 ± .940)
.056 ± .006
(1.422 ± .152)
.018 ± .006
(.457 ± .152)
HOLT INTEGRATED CIRCUITS
6
.350 ± .030
(8.890 ± .762)