ON NB7L11MMNR2 2.5v/3.3v differential 1:2 clock/data fanout buffer/ translator with cml outputs and internal termination Datasheet

NB7L11M
2.5V/3.3V Differential 1:2
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
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MARKING
DIAGRAM*
Description
The NB7L11M is a differential 1−to−2 clock/data distribution chip
with internal source termination and CML output structure, optimized
for low skew and minimal jitter. The device is functionally equivalent to
the EP11, LVEP11, or SG11 devices. Device produces two identical
output copies of clock or data operating up to 8 GHz or 12 Gb/s,
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML output provides matching internal 50 W
terminations, and 400 mV output swings when externally terminated,
50 W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
•
•
•
•
•
•
•
•
•
•
•
•
16
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB7L
11M
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
ORDERING INFORMATION
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
110 ps Typical Propagation Delay
3 ps Typical Within Device Skew
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV Peak−to−Peak Output) Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
Pb−Free Packages are Available*
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and
soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
Q0
VTCLK
Q0
50 W
CLK
CLK
50 W
VTCLK
Q1
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 1
Q1
1
Publication Order Number:
NB7L11M/D
NB7L11M
VTCLK
1
CLK
2
VCC
Q0
Q0
VCC
16
15
14
13
Exposed Pad (EP)
12
VEE
11
VEE
NB7L11M
CLK
3
10
VEE
VTCLK
4
9
VEE
5
6
7
8
VCC
Q1
Q1
VCC
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
1
VTCLK
−
Description
2
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Noninverted Differential Clock/Data Input. (Note 1)
4
VTCLK
−
Internal 50 W Termination Pin for CLK
5,8,13,16
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply
to guarantee proper operation.
6
Q1
CML Output
Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
7
Q1
CML Output
Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
9,10,11,12
VEE
−
14
Q0
CML Output
Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
15
Q0
CML Output
Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
−
EP
−
Internal 50 W Termination Pin for CLK
Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply
to guarantee proper operation.
Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must
be attached to a heatsinking conduit. It is recommended to connect the EP to the lower
potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation.
2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
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NB7L11M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 3)
QFN−16
Flammability Rating
Oxygen Index: 28 to 34
> 1500 V
> 50 V
> 500 V
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
285
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Rating
Unit
3.6
V
3.6
V
2.8
|VCC − VEE|
V
Static
Surge
45
80
mA
mA
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
QFN−16
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
36
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 4)
QFN−16
3 to 4
°C/W
Tsol
Wave Solder
265
265
°C
VCC
Positive Power Supply
VEE = 0 V
VI
Input Voltage
VEE = 0 V
VINPP
Differential Input Voltage |CLK − CLK|
VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
IIN
Input Current Through RT (50 W Resistor)
Iout
Pb
Pb−Free
Condition 2
VEE v VI v VCC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB7L11M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C)
(Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
85
105
mA
ICC
Power Supply Current (Input and Outputs open)
VOH
Output HIGH Voltage (Note 6)
VCC − 60
VCC − 20
VCC
mV
VOL
Output LOW Voltage (Note 6)
VCC − 530
VCC − 420
VCC − 360
mV
Differential Input Driven Single−Ended (see Figures 10 & 12) (Note 8)
Vth
Input Threshold Reference Voltage Range (Note 7)
1125
VCC − 75
mV
VIH
Single−ended Input HIGH Voltage (Note 8)
Vth + 75
VCC
mV
VIL
Single−ended Input LOW Voltage (Note 8)
VEE
Vth − 75
mV
Differential Inputs Driven Differentially (see Figures 11 & 13) (Note 8)
VIHCLK
Differential Input HIGH Voltage
1200
VCC
mV
VILCLK
Differential Input LOW Voltage
VEE
VCC − 75
mV
VCMR
Input Common Mode Range (Differential Configuration)
1163
VCC – 38
mV
VID
Differential Input Voltage (VIHCLK − VILCLK)
75
2500
mV
IIH
Input HIGH Current
CLK / CLK
(VTCLK/VTCLK Open)
0
25
100
mA
IIL
Input LOW Current
CLK / CLK
(VTCLK/VTCLK Open)
−10
0
10
mA
RTIN
Internal Input Termination Resistor
45
50
55
W
RTOUT
Internal Output Termination Resistor
45
50
55
W
RTemp Coef
Internal I/O Termination Resistor Temperature Coefficient
6.38
mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
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NB7L11M
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 9)
Characteristic
Symbol
−40°C
Min
Typ
400
300
25°C
Max
VOUTPP
Output Voltage Amplitude (@VINPPmin)
fin ≤ 6 GHz
(See Figure 3)
fin ≤ 8 GHz
280
140
fdata
Maximum Operating Data Rate
10
12
tPLH,
tPHL
Propagation Delay to Output Differential
70
110
150
tSKEW
Duty Cycle Skew (Note 10)
Within−Device Skew
Device−to−Device Skew (Note 11)
2.0
3.0
20
tJITTER
RMS Random Clock Jitter (Note 12)
fin = 6 GHz
fin =8 GHz
Peak/Peak Data Dependent Jitter
fin = 2.488 Gb/s
(Note 13) fdata =5 Gb/s
fdata =10 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% − 80%)
75
Min
Typ
280
140
400
300
Max
10
12
70
110
150
5.0
15
50
2.0
3.0
20
0.2
0.2
2.0
3.0
5.0
0.5
0.5
5.0
8.0
10
400
2500
30
60
75
Unit
85°C
Min
Typ
280
140
400
300
Max
mV
10
12
70
110
150
ps
5.0
15
50
2.0
3.0
20
5.0
15
50
ps
0.2
0.2
2.0
3.0
5.0
0.5
0.5
5.0
8.0
10
0.2
0.2
2.0
3.0
5.0
0.5
0.5
5.0
8.0
10
ps
400
2500
400
2500
mV
30
60
30
60
ps
75
Gb/s
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% − 80%).
10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz.
11. Device to device skew is measured between outputs under identical transition @ 1 GHz.
12. Additive RMS jitter with 50% duty cycle clock signal at 8 GHz & 10 GHz.
13. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1.
14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE (mV)
500
VCC = 3.3 V
400
VCC = 2.5 V
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
(VINPP = 400 mV)
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Voltage (50 mV/div)
Voltage (50 mV/div)
NB7L11M
DDJ = 1 ps*
Time (80.4 ps/div)
Time (40 ps/div)
Figure 4. Typical Output Waveform at 2.488 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Figure 5. Typical Output Waveform at 5 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
**Input signal DDJ = 7.2 ps
Voltage (50 mV/div)
*Input signal DDJ = 6.4 ps
Voltage (50 mV/div)
DDJ = 1.2 ps**
DDJ = 2 ps***
DDJ = 2 ps***
Time (18.6 ps/div)
Time (18.2 ps/div)
Figure 6. Typical Output Waveform at 10.7 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Figure 7. Typical Output Waveform at 12 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
***Input signal DDJ = 11 ps
***Input signal DDJ = 13 ps
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NB7L11M
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 8. AC Reference Measurement
NB7L11M
VCC
50 W
Receiver
Device
VCC
50 W
50 W
50 W
Q
CLK
Z = 50 W
Q
CLK
Z = 50 W
Figure 9. Typical Termination for Output Driver Using External Termination Resistor
(Refer to Application Notes AND8020/D and AND8173/D)
CLK
CLK
CLK
CLK
Vth
Vth
Figure 10. Differential Input Driven
Single−Ended
VCC
Vthmax
Vthmin
GND
VCC
VIHmax
VILmax
CLK
Vth
Figure 11. Differential Inputs Driven
Differentially
VIHCLKmax
VCMmax
CLK
VIH
Vth
VIL
VCMR
CLK
VIHmin
VILmin
VCMmax
GND
Figure 12. Vth Diagram
VILCLKmax
V(CLK) = VIHCLK − VILCLK
VIHCLKtyp
VILCLKtyp
VIHCLKmin
VILCLKmin
Figure 13. VCMR Diagram
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NB7L11M
VCC
50 W
50 W
Q
Q
16 mA
VEE
Figure 14. CML Output Structure
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK, VTCLK to VCC
LVDS
Connect VTCLK, VTCLK together CLK input
AC−COUPLED
Bias VTCLK, VTCLK Inputs within (VCMR) Common Mode Range
RSECL, LVPECL
Standard ECL Termination Techniques. See AND8020/D.
LVTTL, LVCMOS
An external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
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NB7L11M
Application Information
minimum input swing of 75 mV and the maximum input
swing of 2500 mV. Within these conditions, the input
voltage can range from VCC to 1.2 V. Examples interfaces
are illustrated below in a 50 W environment (Z = 50 W).
All NB7L11M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
VCC
VCC
50 W
50 W
Q
CLK
Z
CML Driver
VCC
VCC
VTCLK
50 W
VTCLK
50 W
NB7L11M
Z
Q
CLK
VEE
VEE
Figure 15. CML to CML Interface
VCC
VCC
50 W
VBias
PECL
Driver
VBias
Recommended RT Values
VCC
50 W
RT
RT
5.0 V 290 W
CLK
Z
VTCLK
50 W
NB7L11M
VTCLK
50 W
Z
CLK
RT
3.3 V 150 W
2.5 V 80 W
VEE
VEE
VEE
Figure 16. PECL to CML Receiver Interface
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NB7L11M
VCC
VCC
CLK
Z
50 W
VTCLK
LVDS
Driver
NB7L11M
VTCLK
50 W
Z
CLK
VEE
VEE
Figure 17. LVDS to CML Receiver Interface
VCC
VCC
CLK
Z
LVTTL/
LVCMOS
Driver
VTCLK
No Connect*
No Connect
NB7L11M
VTCLK
VREF
VEE
50 W
*or 60 pF to GND
50 W
Recommended VREF Values
VREF
CLK
VCC
LVCMOS VCC − VEE
2
LVTTL
1.5 V
Figure 18. LVCMOS/LVTTL to CML Receiver Interface
ORDERING INFORMATION
Package
Shipping †
QFN−16
123 Units/Rail
NB7L11MMNG
QFN−16
(Pb−Free)
123 Units/Rail
NB7L11MMNR2
QFN−16
3000 Tape & Reel
QFN−16
(Pb−Free)
3000 Tape & Reel
Device
NB7L11MMN
NB7L11MMNR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB7L11M
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE B
ÇÇÇ
ÇÇÇ
ÇÇÇ
D
PIN 1
LOCATION
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
SEATING
PLANE
A1
C
D2
16X
L
5
NOTE 5
16X
e
4
9
1
12
E2
K
16
16X
e
13
b
0.10 C A B
0.05 C
EXPOSED PAD
8
BOTTOM VIEW
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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For additional information, please contact your
local Sales Representative.
NB7L11M/D
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