Renesas H8/38522 Renesas 16-bit single-chip microcomputer h8 family / h8/300h super low power sery Datasheet

REJ09B0409-0100
16
H8/38524 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Super Low Power Series
H8/38524
H8/38523
H8/38522
H8/38521
H8/38520
Rev.1.00
Revision Date: Dec. 19, 2007
Rev. 1.00 Dec. 19, 2007 Page ii of xx
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 1.00 Dec. 19, 2007 Page iii of xx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev. 1.00 Dec. 19, 2007 Page iv of xx
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8/38524 Group. Before using any of the
documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type
Contents
Document Title
Document No.
Data Sheet
Overview of hardware and electrical 
characteristics
Hardware Manual
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8/38524 Group
Hardware Manual
This manual
Software Manual
Detailed descriptions of the CPU
and instruction set
H8/300H Series Software
Manual
REJ09B0213
Application Note
Examples of applications and
sample programs
The latest versions are available from our
web site.
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.

Rev. 1.00 Dec. 19, 2007 Page v of xx
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
(2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev. 1.00 Dec. 19, 2007 Page vi of xx
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
(1)
[Table of Bits]
Bit
(2)
(3)
(4)
(5)
Bit Name
−
−
Initial Value R/W
Description
0
0
R
R
Reserved
These bits are always read as 0.
13 to 11
ASID2 to
ASID0
All 0
R/W
Address Identifier
These bits enable or disable the pin function.
10
−
0
R
Reserved
This bit is always read as 0.
9
−
1
R
Reserved
This bit is always read as 1.
−
0
15
14
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W: The bit or field is readable and writable.
R/(W): The bit or field is readable and writable.
However, writing is only performed to flag clearing.
R:
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
W:
The bit or field is writable.
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Rev. 1.00 Dec. 19, 2007 Page vii of xx
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations used in this manual
Abbreviation
Description
ACIA
Asynchronous communication interface adapter
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Bits per second
Cyclic redundancy check
Direct memory access
Direct memory access controller
Global System for Mobile Communications
High impedance
Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
Input/output
Infrared Data Association
Least significant bit
Most significant bit
No connection
Phase-locked loop
Pulse width modulation
Special function register
Subscriber Identity Module
Universal asynchronous receiver/transmitter
Voltage-controlled oscillator
Rev. 1.00 Dec. 19, 2007 Page viii of xx
5. List of Product Specifications
Below is a table listing the product specifications for each group.
H8/38524 Group
Item
Flash Memory
Mask ROM
Memory
16 K, 32 Kbytes
1 Kbyte
20 MHz
20 MHz
—
—
—
9
6
50
1
8 K, 12 K, 16 K, 24 K, 32 Kbytes
512 bytes, 1 Kbyte
20 MHz
20 MHz
—
—
—
9
6
50
1
Reload (timer C)
Compare (timer F)
1
1
1
1
Capture (timer G)
AEC
WDT
WDT (discrete)
UART/Synchronous
1
1
—
1
1 ch
10 bit × 8 ch
1
1
—
1
1 ch
10 bit × 8 ch
32
4
13(8)
32
4
13(8)
1
1
1
1
ROM
RAM
Operating 4.5 to 5.5 V
voltage
2.7 to 5.5 V
and
operating 1.8 to 5.5 V
frequency 2.7 to 3.6 V
1.8 to 3.6 V
I/O ports Input
Output
I/O
Timers
Clock (timer A)
SCI
A-D
(resolution × input channels)
LCD
seg
com
External interrupt
(internal wakeup)
POR (power-on reset)
LVD
(low-voltage detection circuit)
Package
Operating temperature
FP-80A
FP-80A
TFP-80C
TFP-80C
Standard specifications: –20 to 75°C, WTR: –40 to 85°C
All trademarks and registered trademarks are the property of their respective owners.
Rev. 1.00 Dec. 19, 2007 Page ix of xx
Contents
Section 1 Overview ...............................................................................................1
1.1
1.2
1.3
1.4
1.5
Features................................................................................................................................. 1
1.1.1
Application ........................................................................................................... 1
1.1.2
Overview of Specifications................................................................................... 2
List of Products..................................................................................................................... 6
Block Diagram...................................................................................................................... 8
Pin Assignment..................................................................................................................... 9
Pin Functions ...................................................................................................................... 10
Section 2 CPU .....................................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Address Space and Memory Map ....................................................................................... 17
Register Configuration........................................................................................................ 22
2.2.1
General Registers................................................................................................ 23
2.2.2
Program Counter (PC) ........................................................................................ 24
2.2.3
Condition-Code Register (CCR)......................................................................... 24
Data Formats....................................................................................................................... 26
2.3.1
General Register Data Formats........................................................................... 26
2.3.2
Memory Data Formats ........................................................................................ 28
Instruction Set..................................................................................................................... 29
2.4.1
Table of Instructions Classified by Function ...................................................... 29
2.4.2
Basic Instruction Formats ................................................................................... 39
Addressing Modes and Effective Address Calculation....................................................... 40
2.5.1
Addressing Modes .............................................................................................. 40
2.5.2
Effective Address Calculation ............................................................................ 44
Basic Bus Cycle .................................................................................................................. 46
2.6.1
Access to On-Chip Memory (RAM, ROM)........................................................ 46
2.6.2
On-Chip Peripheral Modules .............................................................................. 47
CPU States .......................................................................................................................... 48
Usage Notes ........................................................................................................................ 49
2.8.1
Notes on Data Access to Empty Areas ............................................................... 49
2.8.2
EEPMOV Instruction.......................................................................................... 49
2.8.3
Bit-Manipulation Instruction .............................................................................. 50
Section 3 Exception Handling ............................................................................. 55
3.1
3.2
Overview ............................................................................................................................ 55
Reset ................................................................................................................................... 55
Rev. 1.00 Dec. 19, 2007 Page x of xx
3.3
3.4
3.2.1
Overview............................................................................................................. 55
3.2.2
Reset Sequence ................................................................................................... 55
3.2.3
Interrupt Immediately after Reset ....................................................................... 57
Interrupts............................................................................................................................. 57
3.3.1
Overview............................................................................................................. 57
3.3.2
Interrupt Control Registers ................................................................................. 59
3.3.3
External Interrupts .............................................................................................. 71
3.3.4
Internal Interrupts ............................................................................................... 72
3.3.5
Interrupt Operations............................................................................................ 73
3.3.6
Interrupt Response Time..................................................................................... 78
Application Notes ............................................................................................................... 79
3.4.1
Notes on Stack Area Use .................................................................................... 79
3.4.2
Notes on Rewriting Port Mode Registers ........................................................... 80
3.4.3
Method for Clearing Interrupt Request Flags ..................................................... 83
Section 4 Clock Pulse Generators........................................................................85
4.1
4.2
4.3
4.4
4.5
4.6
Overview ............................................................................................................................ 85
4.1.1
Block Diagram.................................................................................................... 85
4.1.2
System Clock and Subclock................................................................................ 86
4.1.3
Register Descriptions.......................................................................................... 86
System Clock Generator ..................................................................................................... 88
Subclock Generator ............................................................................................................ 92
Prescalers ............................................................................................................................ 94
Note on Oscillators ............................................................................................................. 95
4.5.1
Definition of Oscillation Stabilization Wait Time .............................................. 96
4.5.2
Notes on Use of Crystal Oscillator Element
(Excluding Ceramic Oscillator Element) ............................................................ 99
Usage Note.......................................................................................................................... 99
Section 5 Power-Down Modes ..........................................................................101
5.1
5.2
5.3
Overview .......................................................................................................................... 101
5.1.1
System Control Registers.................................................................................. 104
Sleep Mode ....................................................................................................................... 108
5.2.1
Transition to Sleep Mode.................................................................................. 108
5.2.2
Clearing Sleep Mode ........................................................................................ 109
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode........................................... 109
Standby Mode................................................................................................................... 110
5.3.1
Transition to Standby Mode.............................................................................. 110
5.3.2
Clearing Standby Mode .................................................................................... 110
5.3.3
Oscillator Stabilization Time after Standby Mode is Cleared........................... 111
Rev. 1.00 Dec. 19, 2007 Page xi of xx
5.4
5.5
5.6
5.7
5.8
5.9
5.3.4
Standby Mode Transition and Pin States .......................................................... 112
5.3.5
Notes on External Input Signal Changes before/after Standby Mode............... 113
Watch Mode...................................................................................................................... 114
5.4.1
Transition to Watch Mode ................................................................................ 114
5.4.2
Clearing Watch Mode....................................................................................... 115
5.4.3
Oscillator Stabilization Time after Watch Mode is Cleared ............................. 115
5.4.4
Notes on External Input Signal Changes before/after Watch Mode ................. 115
Subsleep Mode.................................................................................................................. 116
5.5.1
Transition to Subsleep Mode ............................................................................ 116
5.5.2
Clearing Subsleep Mode................................................................................... 116
Subactive Mode ................................................................................................................ 117
5.6.1
Transition to Subactive Mode........................................................................... 117
5.6.2
Clearing Subactive Mode.................................................................................. 117
5.6.3
Operating Frequency in Subactive Mode.......................................................... 117
Active (Medium-Speed) Mode ......................................................................................... 118
5.7.1
Transition to Active (Medium-Speed) Mode.................................................... 118
5.7.2
Clearing Active (Medium-Speed) Mode........................................................... 118
5.7.3
Operating Frequency in Active (Medium-Speed) Mode................................... 118
Direct Transfer.................................................................................................................. 119
5.8.1
Overview of Direct Transfer............................................................................. 119
5.8.2
Direct Transition Times .................................................................................... 120
5.8.3
Notes on External Input Signal Changes before/after Direct Transition........... 122
Module Standby Mode...................................................................................................... 123
5.9.1
Setting Module Standby Mode ......................................................................... 123
5.9.2
Clearing Module Standby Mode....................................................................... 123
Section 6 ROM ..................................................................................................125
6.1
6.2
6.3
Overview .......................................................................................................................... 125
Flash Memory Overview .................................................................................................. 126
6.2.1
Features............................................................................................................. 126
6.2.2
Block Diagram.................................................................................................. 127
6.2.3
Block Configuration ......................................................................................... 128
6.2.4
Register Configuration...................................................................................... 130
Descriptions of Registers of the Flash Memory................................................................ 130
6.3.1
Flash Memory Control Register 1 (FLMCR1).................................................. 130
6.3.2
Flash Memory Control Register 2 (FLMCR2).................................................. 133
6.3.3
Erase Block Register (EBR) ............................................................................. 134
6.3.4
Flash Memory Power Control Register (FLPWCR) ......................................... 134
6.3.5
Flash Memory Enable Register (FENR)........................................................... 135
Rev. 1.00 Dec. 19, 2007 Page xii of xx
6.4
6.5
6.6
6.7
6.8
On-Board Programming Modes........................................................................................ 136
6.4.1
Boot Mode ........................................................................................................ 136
6.4.2
Programming/Erasing in User Program Mode.................................................. 139
6.4.3
Notes on On-Board Programming .................................................................... 140
Flash Memory Programming/Erasing............................................................................... 140
6.5.1
Program/Program-Verify .................................................................................. 141
6.5.2
Erase/Erase-Verify............................................................................................ 144
6.5.3
Interrupt Handling when Programming/Erasing Flash Memory....................... 144
Program/Erase Protection ................................................................................................. 146
6.6.1
Hardware Protection ......................................................................................... 146
6.6.2
Software Protection........................................................................................... 146
6.6.3
Error Protection ................................................................................................ 147
Programmer Mode ............................................................................................................ 147
6.7.1
Socket Adapter.................................................................................................. 147
6.7.2
Programmer Mode Commands ......................................................................... 148
6.7.3
Memory Read Mode ......................................................................................... 150
6.7.4
Auto-Program Mode ......................................................................................... 153
6.7.5
Auto-Erase Mode.............................................................................................. 155
6.7.6
Status Read Mode ............................................................................................. 156
6.7.7
Status Polling .................................................................................................... 158
6.7.8
Programmer Mode Transition Time ................................................................. 159
6.7.9
Notes on Memory Programming ...................................................................... 159
Power-Down States for Flash Memory............................................................................. 160
Section 7 RAM ..................................................................................................161
7.1
Overview .......................................................................................................................... 161
7.1.1
Block Diagram.................................................................................................. 161
Section 8 I/O Ports.............................................................................................163
8.1
8.2
8.3
Overview .......................................................................................................................... 163
Port 1................................................................................................................................. 165
8.2.1
Overview........................................................................................................... 165
8.2.2
Register Configuration and Description ........................................................... 165
8.2.3
Pin Functions .................................................................................................... 170
8.2.4
Pin States .......................................................................................................... 171
8.2.5
MOS Input Pull-Up........................................................................................... 171
Port 3................................................................................................................................. 172
8.3.1
Overview........................................................................................................... 172
8.3.2
Register Configuration and Description ........................................................... 172
8.3.3
Pin Functions .................................................................................................... 177
Rev. 1.00 Dec. 19, 2007 Page xiii of xx
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.3.4
Pin States .......................................................................................................... 178
8.3.5
MOS Input Pull-Up........................................................................................... 178
Port 4................................................................................................................................. 179
8.4.1
Overview........................................................................................................... 179
8.4.2
Register Configuration and Description ........................................................... 179
8.4.3
Pin Functions .................................................................................................... 182
8.4.4
Pin States .......................................................................................................... 183
Port 5................................................................................................................................. 183
8.5.1
Overview........................................................................................................... 183
8.5.2
Register Configuration and Description ........................................................... 184
8.5.3
Pin Functions .................................................................................................... 186
8.5.4
Pin States .......................................................................................................... 187
8.5.5
MOS Input Pull-Up........................................................................................... 187
Port 6................................................................................................................................. 188
8.6.1
Overview........................................................................................................... 188
8.6.2
Register Configuration and Description ........................................................... 188
8.6.3
Pin Functions .................................................................................................... 190
8.6.4
Pin States .......................................................................................................... 191
8.6.5
MOS Input Pull-Up........................................................................................... 191
Port 7................................................................................................................................. 192
8.7.1
Overview........................................................................................................... 192
8.7.2
Register Configuration and Description ........................................................... 192
8.7.3
Pin Functions .................................................................................................... 194
8.7.4
Pin States .......................................................................................................... 194
Port 8................................................................................................................................. 195
8.8.1
Overview........................................................................................................... 195
8.8.2
Register Configuration and Description ........................................................... 195
8.8.3
Pin Functions .................................................................................................... 197
8.8.4
Pin States .......................................................................................................... 197
Port 9................................................................................................................................. 198
8.9.1
Overview........................................................................................................... 198
8.9.2
Register Configuration and Description ........................................................... 198
8.9.3
Pin Functions .................................................................................................... 200
8.9.4
Pin States .......................................................................................................... 200
Port A................................................................................................................................ 201
8.10.1
Overview........................................................................................................... 201
8.10.2
Register Configuration and Description ........................................................... 201
8.10.3
Pin Functions .................................................................................................... 203
8.10.4
Pin States .......................................................................................................... 204
Rev. 1.00 Dec. 19, 2007 Page xiv of xx
8.11
8.12
8.13
Port B................................................................................................................................ 204
8.11.1
Overview........................................................................................................... 204
8.11.2
Register Configuration and Description ........................................................... 205
8.11.3
Pin Functions .................................................................................................... 207
Input/Output Data Inversion Function .............................................................................. 208
8.12.1
Overview........................................................................................................... 208
8.12.2
Register Configuration and Descriptions.......................................................... 209
8.12.3
Note on Modification of Serial Port Control Register ...................................... 210
Application Note............................................................................................................... 211
8.13.1
The Management of the Un-Use Terminal ....................................................... 211
Section 9 Timers ................................................................................................213
9.1
9.2
9.3
9.4
9.5
9.6
Overview .......................................................................................................................... 213
Timer A............................................................................................................................. 214
9.2.1
Overview........................................................................................................... 214
9.2.2
Register Descriptions........................................................................................ 216
9.2.3
Timer Operation................................................................................................ 219
9.2.4
Timer A Operation States ................................................................................. 220
9.2.5
Application Note............................................................................................... 220
Timer C............................................................................................................................. 221
9.3.1
Overview........................................................................................................... 221
9.3.2
Register Descriptions........................................................................................ 223
9.3.3
Timer Operation................................................................................................ 226
9.3.4
Timer C Operation States ................................................................................. 228
Timer F ............................................................................................................................. 229
9.4.1
Overview........................................................................................................... 229
9.4.2
Register Descriptions........................................................................................ 233
9.4.3
CPU Interface ................................................................................................... 241
9.4.4
Operation .......................................................................................................... 244
9.4.5
Application Notes ............................................................................................. 247
Timer G............................................................................................................................. 251
9.5.1
Overview........................................................................................................... 251
9.5.2
Register Descriptions........................................................................................ 253
9.5.3
Noise Canceler.................................................................................................. 258
9.5.4
Operation .......................................................................................................... 260
9.5.5
Application Notes ............................................................................................. 265
9.5.6
Timer G Application Example.......................................................................... 269
Watchdog Timer ............................................................................................................... 270
9.6.1
Overview........................................................................................................... 270
9.6.2
Register Descriptions........................................................................................ 272
Rev. 1.00 Dec. 19, 2007 Page xv of xx
9.7
9.6.3
Timer Operation................................................................................................ 278
9.6.4
Watchdog Timer Operation States.................................................................... 279
Asynchronous Event Counter (AEC)................................................................................ 280
9.7.1
Overview........................................................................................................... 280
9.7.2
Register Configurations .................................................................................... 283
9.7.3
Operation .......................................................................................................... 293
9.7.4
Asynchronous Event Counter Operation Modes............................................... 298
9.7.5
Application Notes ............................................................................................. 299
Section 10 Serial Communication Interface...................................................... 301
10.1
10.2
10.3
10.4
10.5
Overview .......................................................................................................................... 301
10.1.1
Features............................................................................................................. 301
10.1.2
Block Diagram.................................................................................................. 303
10.1.3
Pin Configuration.............................................................................................. 304
10.1.4
Register Configuration...................................................................................... 304
Register Descriptions........................................................................................................ 305
10.2.1
Receive Shift Register (RSR) ........................................................................... 305
10.2.2
Receive Data Register (RDR)........................................................................... 305
10.2.3
Transmit Shift Register (TSR) .......................................................................... 306
10.2.4
Transmit Data Register (TDR).......................................................................... 306
10.2.5
Serial Mode Register (SMR) ............................................................................ 307
10.2.6
Serial Control Register 3 (SCR3) ..................................................................... 310
10.2.7
Serial Status Register (SSR) ............................................................................. 314
10.2.8
Bit Rate Register (BRR) ................................................................................... 317
10.2.9
Clock stop register 1 (CKSTPR1)..................................................................... 323
10.2.10 Serial Port Control Register (SPCR)................................................................. 324
Operation .......................................................................................................................... 325
10.3.1
Overview........................................................................................................... 325
10.3.2
Operation in Asynchronous Mode .................................................................... 329
10.3.3
Operation in Synchronous Mode ...................................................................... 338
Interrupts........................................................................................................................... 345
Application Notes ............................................................................................................. 346
Section 11 10-Bit PWM ....................................................................................353
11.1
Overview .......................................................................................................................... 353
11.1.1
Features............................................................................................................. 353
11.1.2
Block Diagram.................................................................................................. 354
11.1.3
Pin Configuration.............................................................................................. 354
11.1.4
Register Configuration...................................................................................... 355
Rev. 1.00 Dec. 19, 2007 Page xvi of xx
11.2
11.3
Register Descriptions........................................................................................................ 355
11.2.1
PWM Control Register (PWCRm) ................................................................... 355
11.2.2
PWM Data Registers U and L (PWDRUm, PWDRLm) .................................. 357
11.2.3
Clock Stop Register 2 (CKSTPR2)................................................................... 358
Operation .......................................................................................................................... 359
11.3.1
Operation .......................................................................................................... 359
11.3.2
PWM Operation Modes .................................................................................... 360
Section 12 A/D Converter..................................................................................361
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Overview .......................................................................................................................... 361
12.1.1
Features............................................................................................................. 361
12.1.2
Block Diagram.................................................................................................. 362
12.1.3
Pin Configuration.............................................................................................. 363
12.1.4
Register Configuration...................................................................................... 363
Register Descriptions........................................................................................................ 364
12.2.1
A/D Result Registers (ADRRH, ADRRL) ....................................................... 364
12.2.2
A/D Mode Register (AMR) .............................................................................. 364
12.2.3
A/D Start Register (ADSR) .............................................................................. 366
12.2.4
Clock Stop Register 1 (CKSTPR1)................................................................... 367
Operation .......................................................................................................................... 368
12.3.1
A/D Conversion Operation ............................................................................... 368
12.3.2
Start of A/D Conversion by External Trigger Input.......................................... 368
12.3.3
A/D Converter Operation Modes...................................................................... 369
Interrupts........................................................................................................................... 369
Typical Use....................................................................................................................... 370
A/D Conversion Accuracy Definitions ............................................................................. 374
Application Notes ............................................................................................................. 376
12.7.1
Permissible Signal Source Impedance .............................................................. 376
12.7.2
Influences on Absolute Precision...................................................................... 376
12.7.3
Additional Usage Notes .................................................................................... 377
Section 13 LCD Controller/Driver ....................................................................379
13.1
13.2
Overview .......................................................................................................................... 379
13.1.1
Features............................................................................................................. 379
13.1.2
Block Diagram.................................................................................................. 380
13.1.3
Pin Configuration.............................................................................................. 381
13.1.4
Register Configuration...................................................................................... 381
Register Descriptions........................................................................................................ 382
13.2.1
LCD Port Control Register (LPCR).................................................................. 382
13.2.2
LCD Control Register (LCR)............................................................................ 384
Rev. 1.00 Dec. 19, 2007 Page xvii of xx
13.3
13.2.3
LCD Control Register 2 (LCR2)....................................................................... 386
13.2.4
Clock Stop Register 2 (CKSTPR2)................................................................... 388
Operation .......................................................................................................................... 389
13.3.1
Settings up to LCD Display .............................................................................. 389
13.3.2
Relationship between LCD RAM and Display................................................. 391
13.3.3
Operation in Power-Down Modes .................................................................... 396
13.3.4
Boosting the LCD Drive Power Supply............................................................ 397
Section 14 Power-On Reset and Low-Voltage Detection Circuits ................... 399
14.1
14.2
14.3
Overview .......................................................................................................................... 399
14.1.1
Features............................................................................................................. 400
14.1.2
Block Diagram.................................................................................................. 401
14.1.3
Pin Description ................................................................................................. 402
14.1.4
Register Descriptions........................................................................................ 402
Individual Register Descriptions....................................................................................... 402
14.2.1
Low-Voltage Detection Control Register (LVDCR) ........................................ 402
14.2.2
Low-Voltage Detection Status Register (LVDSR) ........................................... 405
14.2.3
Low-Voltage Detection Counter (LVDCNT) ................................................... 407
14.2.4
Clock Stop Register 2 (CKSTPR2)................................................................... 407
Operation .......................................................................................................................... 408
14.3.1
Power-On Reset Circuit .................................................................................... 408
14.3.2
Low-Voltage Detection Circuit......................................................................... 409
Section 15 Power Supply Circuit ......................................................................417
15.1
15.2
When Using Internal Power Supply Step-Down Circuit .................................................. 417
When Not Using Internal Power Supply Step-Down Circuit ........................................... 418
Section 16 List of Registers............................................................................... 419
16.1
16.2
16.3
Register Addresses (Address Order)................................................................................. 420
Register Bits...................................................................................................................... 424
Register States in Each Operating Mode .......................................................................... 428
Section 17 Electrical Characteristics .................................................................433
17.1
17.2
Absolute Maximum Ratings (Flash Memory Version and Mask ROM Version)............. 433
Electrical Characteristics (Flash Memory Version and Mask ROM Version).................. 434
17.2.1
Power Supply Voltage and Operating Ranges .................................................. 434
17.2.2
DC Characteristics ............................................................................................ 438
17.2.3
AC Characteristics ............................................................................................ 447
17.2.4
A/D Converter Characteristics.......................................................................... 450
17.2.5
LCD Characteristics.......................................................................................... 451
Rev. 1.00 Dec. 19, 2007 Page xviii of xx
17.3
17.4
17.5
17.6
17.2.6
Flash Memory Characteristics .......................................................................... 452
17.2.7
Power Supply Voltage Detection Circuit Characteristics ................................. 454
17.2.8
Power-On Reset Circuit Characteristics ........................................................... 457
17.2.9
Watchdog Timer Characteristics....................................................................... 458
Operation Timing.............................................................................................................. 458
Output Load Circuit .......................................................................................................... 461
Resonator Equivalent Circuit............................................................................................ 461
Usage Note........................................................................................................................ 462
Appendix..............................................................................................................463
A.
B.
C.
D.
E.
Instruction Set................................................................................................................... 463
A.1
Instruction List.................................................................................................. 463
A.2
Operation Code Map......................................................................................... 478
A.3
Number of Execution States ............................................................................. 481
A.4
Combinations of Instructions and Addressing Modes ...................................... 492
I/O Port Block Diagrams .................................................................................................. 493
B.1
Block Diagrams of Port 1 ................................................................................. 493
B.2
Block Diagrams of Port 3 ................................................................................. 495
B.3
Block Diagrams of Port 4 ................................................................................. 500
B.4
Block Diagram of Port 5................................................................................... 504
B.5
Block Diagram of Port 6................................................................................... 505
B.6
Block Diagram of Port 7................................................................................... 506
B.7
Block Diagram of Port 8................................................................................... 507
B.8
Block Diagrams of Port 9 ................................................................................. 508
B.9
Block Diagram of Port A .................................................................................. 510
B.10
Block Diagrams of Port B................................................................................. 511
Port States in the Different Processing States ................................................................... 514
List of Product Codes ....................................................................................................... 515
Package Dimensions ......................................................................................................... 516
Index ....................................................................................................................519
Rev. 1.00 Dec. 19, 2007 Page xix of xx
Rev. 1.00 Dec. 19, 2007 Page xx of xx
Section 1 Overview
Section 1 Overview
1.1
Features
Microcontrollers of the H8/38524 Group are CISC (complex instruction set computer)
microcontrollers whose core is an H8/300H CPU, which has an internal 32-bit architecture. The
H8/300H CPU provides upward compatibility with the H8/300 CPUs of other Renesas
Technology-original microcontrollers.
As peripheral functions, each LSI of this Group includes various timer functions that realize lowcost configurations for end systems. The power consumption of these modules can be kept down
dynamically by power-down mode.
1.1.1
Application
Examples of the applications of this LSI include motor control, power meter, and health
equipment.
Rev. 1.00 Dec. 19, 2007 Page 1 of 520
REJ09B0409-0100
Section 1 Overview
1.1.2
Overview of Specifications
Table 1.1 lists the functions of H8/38524 Group products in outline.
Table 1.1
Overview of Functions
Classification
Module/
Function
Description
Memory
ROM
•
ROM lineup: Flash memory version and mask Rom version
•
ROM capacity: 8 K, 12 K, 16 K, 24 K, and 32 Kbytes
•
•
RAM capacity: 512 and 1024 bytes
H8/300H CPU (CISC type)
RAM
CPU
CPU
Upward compatibility for H8/300 CPU at object level
•
Sixteen 16-bit general registers
•
Eight addressing modes
•
64-Kbyte address space
Program: 64 Kbytes available
Data: 64 Kbytes available
Interrupt
(source)
•
62 basic instructions, classifiable as bit arithmetic and logic
instructions, multiply and divide instructions, bit manipulation
instructions, and others
•
Minimum instruction execution time: 400 ns (for an ADD
instruction while system clock φ = 5 MHz and
VCC = 2.7 to 3.6 V)
•
On-chip multiplier (16 × 16 → 32 bits)
Operating
mode
•
Normal mode
MCU
operating
mode
Mode: Single-chip mode
•
Low power consumption state (transition driven by the SLEEP
instruction)
Interrupt
controller
(INTC)
•
Thirteen external interrupt pins (IRQAEC, IRQ4, IRQ3, IRQ1,
IRQ0, WKP7 to WKP0)
•
Nine internal interrupt sources
•
Independent vector addresses
Rev. 1.00 Dec. 19, 2007 Page 2 of 520
REJ09B0409-0100
Section 1 Overview
Classification
Clock
A/D converter
Timer
Module/
Function
Description
Clock pulse •
generator
•
(CPG)
A/D
converter
(ADC)
Includes frequency division circuit, so the operating frequency
is selectable
•
Seven low-power-consumption modes: Active (medium speed)
mode, sleep (high speed or medium speed) mode, subactive
mode, subsleep mode, standby mode, and watch mode
•
Equipped with an on-chip oscillator
•
•
•
10-bit resolution × eight input channels
Sample and hold function included
Conversion time:
12.4 µs per channel (with φ at 5-MHz operation) /
6.2 µs per channel (with φ at 10-MHz operation)
A/D conversion can be started by external trigger input
10 bits × two channels
Four conversion periods selectable
Pulse division method for less ripple
8-bit timer
Interval timer functionality: Eight internal clock sources are
selectable
Clock time base functionality: Four overflow periods are
selectable
Generates an interrupt upon overflow
8-bit timer
Eight clocks are selectable
Auto-reload function supported
Generates an interrupt upon overflow
Up/down-counter switching is possible
16-bit timer (also can be used as two independent 8-bit timers)
Five clocks are selectable
Output compare function supported
Toggle output function supported
Two interrupt sources: Compare match and overflow
•
Timer F
Separate clock signals are provided for each of functional
modules
•
•
10-bit PWM •
•
•
•
Timer A
•
Timer C
Two clock generation circuits available
•
•
•
•
•
•
•
•
•
•
•
Rev. 1.00 Dec. 19, 2007 Page 3 of 520
REJ09B0409-0100
Section 1 Overview
Classification
Module/
Function
Timer
Timer G
Description
•
•
•
•
•
•
Asynchron- •
ous event
•
counter
(AEC)
8-bit timer
Four counter input clocks are selectable
Input capture functions supported (a built-in noise canceller)
Level detection at counter overflow is possible
Counter clearing option
Two interrupt sources: Input capture and overflow
16-bit pulse timer (also can be used as 8 bits × two channels)
Can count asynchronously-input external events
Watchdog timer Watchdog 8 bits × one channel (selectable from ten counter input clocks)
timer (WDT)
Serial interface
Serial
communication
interface 3
(SCI3)
I/O ports
LCD (Liquid
LCD
Crystal Display) controller/
drive
driver
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
For both asynchronous and clock synchronous serial
communications
Full-duplex communications capability
Select the desired bit rate
Six interrupt sources
Nine CMOS input-only pins
Six CMOS output-only pins
50 CMOS input/output pins
Six large-current-drive pins (port 9)
27 pull-up resistors
Seven open drains
A maximum of 32 segment pins and four common pins
Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
LCD RAM capacity: 8 bits × 16 bytes (128 bits)
Word access to LCD RAM
All four segment output pins can be used individually as port
pins
Common output pins not used because of the duty cycle can be
used for common double-buffering (parallel connection)
Display possible in operating modes other than standby mode
Choice of 11 frame frequencies
Built-in power supply split-resistance, supplying LCD drive
power
A or B waveform selectable by software
Removal of split-resistance can be controlled in software
Rev. 1.00 Dec. 19, 2007 Page 4 of 520
REJ09B0409-0100
Section 1 Overview
Classification
Module/
Function
Description
Measures in
power supply
drops
•
Power-on
reset and
low-voltage
•
detection
circuits
Internal power
supply stepdown circuit
Power
supply
circuit
Package
•
•
Power-on reset circuit:
An internal reset signal can be issued at power-on by
connecting an external capacitor
Low-voltage detection circuit:
Monitors the power supply voltage and issues an internal reset
signal or interrupt if the voltage goes below or above a specified
range
The internal power supply can be fixed at a constant level of
approximately 3.0 V, independently of the voltage of the power
supply connected to the external VCC pin
It is also possible to use the same level of external power
supply voltage and internal power supply voltage without using
the internal power supply step-down circuit
QFP-80: package code: FP-80A
(package dimensions: 14 × 14 mm, pin pitch: 0.65 mm)
TQFP-80: package code: TFP-80C
(package dimensions: 12 × 12 mm, pin pitch: 0.50 mm)
Operating frequency: 2 to 20 MHz
Power supply voltage:
•
Vcc = 2.7 to 5.5 V, AVcc = 2.7 to 5.5 V
Supply current:
•
•
•
•
Operating frequency/
Power supply voltage
Flash memory version: 4.0 mA (typ.)
(Vcc = 5.0 V, AVcc = 5.0 V, φ = 10 MHz)
Mask ROM version: 3.3 mA (typ.)
(Vcc = 5.0 V, AVcc = 5.0 V, φ = 10 MHz)
Operating peripheral
temperature (°C)
•
•
−20 to +75°C (regular specifications)
−40 to +85°C (wide-range specifications)
Rev. 1.00 Dec. 19, 2007 Page 5 of 520
REJ09B0409-0100
Section 1 Overview
1.2
List of Products
Table 1.2 and figure 1.1 show the list of products and the structure of a product number,
respectively.
Table 1.2
List of Products
Group
Product Type
ROM
Size
H8/38524
Group
HD64F38524
32 Kbytes 1 Kbyte
HD64338524
32 Kbytes 1 Kbyte
Mask ROM
version
HD64338523
24 Kbytes 1 Kbyte
Mask ROM
version
HD64F38522
16 Kbytes 1 Kbyte
Flash memory
version
HD64338522
16 Kbytes 1 Kbyte
Mask ROM
version
HD64338521
12 Kbytes 512 bytes
Mask ROM
version
HD64338520
8 Kbytes
Mask ROM
version
Rev. 1.00 Dec. 19, 2007 Page 6 of 520
REJ09B0409-0100
RAM Size
512 bytes
Package
Remarks
FP-80A,
TFP-80C
Flash memory
version
Section 1 Overview
Product type no. HD
64
F
38524
H
Indicates the package.
H: QFP
W: TQFP
Indicates the product-specific number.
H8/38524 Group
Indicates the type of ROM device.
F: Flash memory
3: Mask ROM
Indicates the product family classification
H8 Family
Indicates the microcontroller.
Figure 1.1 How to Read the Product Name Code
Rev. 1.00 Dec. 19, 2007 Page 7 of 520
REJ09B0409-0100
Section 1 Overview
Block Diagram
System clock
OSC
10-bit PWM1
Power-on reset and
low-voltage detect circuits
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
10-bit PWM2
Port 4
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Timer A
Timer C
Timer F
Port 5
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
P17/IRQ3/TMIF
Timer G
WDT
A/D
(10 bits)
LCD
controller
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
AVCC
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
Large-current (15 mA/pin)
Figure 1.2 Block Diagram of H8/38524 Group
Rev. 1.00 Dec. 19, 2007 Page 8 of 520
REJ09B0409-0100
P95
P94
P93/Vref
P92
P91/PWM2
P90/PWM1
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port 6
RAM
(512 bytes to 1 Kbyte)
Serial
communication
interface
(SCI3)
Port 9
ROM
(8 Kbytes to 32 Kbytes)
IRQAEC
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 8
Port 1
P13/TMIG
P14/IRQ4/ADTRG
Asynchronous
counter
(16 bits)
Port 7
OSC1
OSC2
H8/300H
CPU
Port A
Sub clock
OSC
LCD power
supply
x1
x2
CVCC
VSS
VSS = AVSS
VCC
RES
TEST
Port B
1.3
V1
V2
V3
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
Section 1 Overview
Pin Assignment
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
FP-80A,TFP-80C
(Top view)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
AVCC
P13/TMIG
P14/IRQ4/ADTRG
CVCC
P17/IRQ3/TMIF
X1
X2
VSS=AVSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0/extD
PB1/AN1/extU
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IRQAEC
P95
P94
P93/Vref
P92
P91/PWM2
P90/PWM1
VSS
VCC
V1
V2
V3
PA0/COM1
PA1/COM2
PA2/COM3
PA3/COM4
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
1.4
Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user.
Figure 1.3 Pin Assignment of H8/38524 Group
(FP-80A and TFP-80C)
Rev. 1.00 Dec. 19, 2007 Page 9 of 520
REJ09B0409-0100
Section 1 Overview
1.5
Pin Functions
Table 1.3
Pin Functions
Pin No.
Type
Symbol
FP-80A, TFP-80C
I/O
Functions
Power
source pins
VCC
52
Input
Power supply: All VCC pins should be
connected to the system power supply.
VSS
8 (= AVSS), 53
Input
Ground: All VSS pins should be
connected to the system power supply
(0 V).
AVCC
1
Input
Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
AVSS
8 (= VSS)
Input
Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
V1
51
Input
V2
50
V3
49
LCD power supply: These are the
power supply pins for the LCD
controller/driver.
CVCC
4
Input
Power supply: This is the internal
step-down power supply pin. To
ensure stability, a capacitor with a
rating of about 0.1 µF should be
connected between this pin and the VSS
pin.
OSC1
10
Input
OSC2
9
Output
These pins connect to a crystal or
ceramic oscillator, or can be used to
input an external clock. See section 4,
Clock Pulse Generators, for a typical
connection diagram.
X1
6
Input
X2
7
Output
Clock pins
Rev. 1.00 Dec. 19, 2007 Page 10 of 520
REJ09B0409-0100
These pins connect to a 32.768-kHz
crystal oscillator. See section 4, Clock
Pulse Generators, for a typical
connection diagram.
Section 1 Overview
Pin No.
Type
Symbol
FP-80A, TFP-80C
I/O
Functions
System
control
RES
12
Input
Reset: When this pin is driven low, the
chip is reset.
TEST
11
Input
Test pin: This pin is reserved and
cannot be used. It should be
connected to VSS.
IRQ0
72
Input
IRQ1
76
IRQ3
5
IRQ interrupt request 4, 3, 1, and 0:
These are input pins for edge-sensitive
external interrupts, with a selection of
rising or falling edge.
Input
Asynchronous event counter event
signal: This is an interrupt input pin for
enabling asynchronous event input.
Interrupt
pins
IRQ4
3
IRQAEC
60
This must be fixed at VCC or GND
because the oscillator is selected by
the input level during resets. Refer to
section 4, Clock Pulse Generators, for
information on the selection method.
Timer
WKP7 to
WKP0
20 to 13
Input
Wakeup interrupt request 7 to 0:
These are input pins for rising or
falling-edge-sensitive external
interrupts.
AEVL
68
Input
AEVH
67
Asynchronous event counter event
input: These are event input pins for
input to the asynchronous event
counter.
TMIC
76
Input
Timer C event input: This is an event
input pin for input to the timer C
counter.
UD
61
Input
Timer C up/down select: This pin
selects up- or down-counting for the
timer C counter. The counter operates
as a down-counter when this pin is
high, and as an up-counter when low.
TMIF
5
Input
Timer F event input: This is an event
input pin for input to the timer F
counter.
Rev. 1.00 Dec. 19, 2007 Page 11 of 520
REJ09B0409-0100
Section 1 Overview
Pin No.
Type
Symbol
FP-80A, TFP-80C
I/O
Functions
Timer
TMOFL
62
Output
Timer FL output: This is an output pin
for waveforms generated by the timer
FL output compare function.
TMOFH
63
Output
Timer FH output: This is an output pin
for waveforms generated by the timer
FH output compare function.
TMIG
2
Input
Timer G capture input: This is an
input pin for timer G input capture.
10-bit PWM PWM1
54
Output
PWM2
55
10-bit PWM output: These are output
pins for waveforms generated by the
channel 1 and 2 10-bit PWMs.
P17
5
I/O
P14
3
P13
2
Port 1: This is a 3-bit I/O port. Input or
output can be designated for each bit
by means of port control register 1
(PCR1).
P37 to P30
68 to 61
I/O
Port 3: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 3
(PCR3).
I/O ports
If the on-chip emulator is used, pins
33, 34, and 35 are reserved for the
emulator and not available to the user.
P43
72
Input
Port 4 (bit 3): This is a 1-bit input port.
P42 to P40
71 to 69
I/O
Port 4 (bits 2 to 0): This is a 3-bit I/O
port. Input or output can be designated
for each bit by means of port control
register 4 (PCR4).
P57 to P50
20 to 13
I/O
Port 5: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 5
(PCR5).
P67 to P60
28 to 21
I/O
Port 6: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 6
(PCR6).
Rev. 1.00 Dec. 19, 2007 Page 12 of 520
REJ09B0409-0100
Section 1 Overview
Pin No.
Type
Symbol
FP-80A, TFP-80C
I/O
Functions
I/O ports
P77 to P70
36 to 29
I/O
Port 7: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 7
(PCR7).
P87 to P80
44 to 37
I/O
Port 8: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 8
(PCR8).
P95 to P90
59 to 54
Output
Port 9: This is a 6-bit output port. If the
on-chip emulator is used, pin 95 is
reserved for the emulator and not
available to the user. In the case of the
flash memory version, pin 95 should
not be left open in the user mode, and
should instead be pulled up to high
level.
PA3 to PA0 45 to 48
I/O
Port A: This is a 4-bit I/O port. Input or
output can be designated for each bit
by means of port control register A
(PCRA).
PB7 to PB0 80 to 73
Input
Port B: This is an 8-bit input port.
RXD32
70
Input
SCI3 receive data input: This is the
SCI3 data input pin.
TXD32
71
Output
SCI3 transmit data output: This is the
SCI3 data output pin.
SCK32
69
I/O
SCI3 clock I/O: This is the SCI3 clock
I/O pin.
AN7 to AN0 80 to 73
Input
Analog input channels 7 to 0: These
are analog data input channels to the
A/D converter.
ADTRG
3
Input
A/D converter trigger input: This is
the external trigger input pin to the A/D
converter.
COM4 to
COM1
45 to 48
Output
LCD common output: These are the
LCD common output pins.
SEG32 to
SEG1
44 to 13
Output
LCD segment output: These are the
LCD segment output pins.
Serial communication
interface
(SCI)
A/D
converter
LCD
controller/
driver
Rev. 1.00 Dec. 19, 2007 Page 13 of 520
REJ09B0409-0100
Section 1 Overview
Pin No.
Type
Symbol
FP-80A, TFP-80C
I/O
Functions
Low-voltage Vref
detection
circuit (LVD) extD
57
Input
LVD reference voltage input: This is
the LVD reference voltage input pin.
73
Input
LVD power supply drop detect
voltage input: This is the LVD power
supply drop detect voltage input pin.
extU
74
Input
LVD power supply rise detect
voltage input: This is the LVD power
supply rise detect voltage input pin.
NC


NC pin
NC
Rev. 1.00 Dec. 19, 2007 Page 14 of 520
REJ09B0409-0100
Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space.
• Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers,
or eight 32-bit registers
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 64-Kbyte address space
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract : 2 state
8 × 8-bit register-register multiply
: 14 states
16 ÷ 8-bit register-register divide
: 14 states
16 × 16-bit register-register multiply
: 22 states
32 ÷ 16-bit register-register divide
: 22 states
Rev. 1.00 Dec. 19, 2007 Page 15 of 520
REJ09B0409-0100
Section 2 CPU
• Power-down state
Transition to power-down state by SLEEP instruction
Rev. 1.00 Dec. 19, 2007 Page 16 of 520
REJ09B0409-0100
Section 2 CPU
2.1
Address Space and Memory Map
The memory map of the H8/38524 is shown in figure 2.1(1), that of the H8/38523 in figure
2.16(2), that of the H8/38522 in figure 2.1(3), that of the H8/38521 in figure 2.1(4), and that of the
H8/38520 in figure 2.1(5).
Flash memory version
Mask ROM version
H'0000
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
32 Kbytes
(32768 bytes)
On-chip ROM
32 Kbytes
(32768 bytes)
On-chip ROM
H'7000
Firmware
for on-chip emulator*1
H'7FFF
H'7FFF
Not used
H'F020
H'F02B
Not used
Internal I/O register
Not used
H'F740
H'F740
H'F74F
LCD RAM (16 bytes)
H'F74F
LCD RAM (16 bytes)
Not used
H'F780
H'FB7F
H'FB80
Not used
(Workarea for reprogramming
flash memory: 1 Kbyte)*2
On-chip RAM
(2 Kbytes)
H'FB80
User area
(1 Kbyte)
On-chip RAM
1024 bytes
H'FF80
H'FF80
Internal I/O register
(128 bytes)
Internal I/O register
(128 bytes)
H'FFFF
1024 bytes
H'FF7F
H'FF7F
H'FFFF
Notes: 1. Not available to the user if the on-chip emulator is used.
2. Used by the programming control program when programming flash memory. Also, not available to the user
if the on-chip emulator is used.
Figure 2.1(1) H8/38524 Memory Map
Rev. 1.00 Dec. 19, 2007 Page 17 of 520
REJ09B0409-0100
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
24 Kbytes
On-chip ROM
(24576 bytes)
H'5FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FB80
On-chip RAM
1024 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.1(2) H8/38523 Memory Map
Rev. 1.00 Dec. 19, 2007 Page 18 of 520
REJ09B0409-0100
Section 2 CPU
Flash memory version
Mask ROM version
H'0000
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
On-chip ROM
16 Kbytes
(16384 bytes)
H'3FFF
16 Kbytes
(16384 bytes)
H'3FFF
Not used
H'7000
Firmware
for on-chip emulator
H'7FFF
Not used
Not used
H'F020
H'F02B
Internal I/O register
Not used
H'F740
H'F740
H'F74F
LCD RAM (16 bytes)
H'F74F
LCD RAM (16 bytes)
Not used
H'F780
H'FB7F
H'FB80
Not used
(Workarea for reprogramming
flash memory: 1 Kbyte)*
On-chip RAM
(2 Kbytes)
H'FB80
User area
(1 Kbyte)
On-chip RAM
1024 bytes
H'FF7F
H'FF7F
H'FF80
H'FF80
Internal I/O register
(128 bytes)
Internal I/O register
(128 bytes)
H'FFFF
1024 bytes
H'FFFF
Note: * Used by the programming control program when programming flash memory. Also, not available to the user if
the on-chip emulator is used.
Figure 2.1(3) H8/38522 Memory Map
Rev. 1.00 Dec. 19, 2007 Page 19 of 520
REJ09B0409-0100
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
12 Kbytes
On-chip ROM
(12288 bytes)
H'2FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.1(4) H8/38521 Memory Map
Rev. 1.00 Dec. 19, 2007 Page 20 of 520
REJ09B0409-0100
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
8 Kbytes
On-chip ROM
(8192 bytes)
H'1FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.1(5) H8/38520 Memory Map
Rev. 1.00 Dec. 19, 2007 Page 21 of 520
REJ09B0409-0100
Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.2 CPU Registers
Rev. 1.00 Dec. 19, 2007 Page 22 of 520
REJ09B0409-0100
Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Registers
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
Rev. 1.00 Dec. 19, 2007 Page 23 of 520
REJ09B0409-0100
Section 2 CPU
Empty area
SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Rev. 1.00 Dec. 19, 2007 Page 24 of 520
REJ09B0409-0100
Section 2 CPU
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Rev. 1.00 Dec. 19, 2007 Page 25 of 520
REJ09B0409-0100
Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1
General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
General Register
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
Figure 2.5 General Register Data Formats (1)
REJ09B0409-0100
0
Don't care
MSB
Rev. 1.00 Dec. 19, 2007 Page 26 of 520
0
Lower
LSB
Section 2 CPU
Data Type
General
Register
Word data
Rn
Data Format
15
Word data
MSB
En
15
MSB
Longword
data
0
LSB
0
LSB
ERn
31
16 15
MSB
0
LSB
[Legend]
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
Rev. 1.00 Dec. 19, 2007 Page 27 of 520
REJ09B0409-0100
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.6 Memory Data Formats
Rev. 1.00 Dec. 19, 2007 Page 28 of 520
REJ09B0409-0100
LSB
Section 2 CPU
2.4
Instruction Set
2.4.1
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1.
Table 2.1
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
¬
NOT (logical complement)
Rev. 1.00 Dec. 19, 2007 Page 29 of 520
REJ09B0409-0100
Section 2 CPU
Symbol
Description
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in this LSI.
MOVTPE
B
Rs → (EAs)
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00 Dec. 19, 2007 Page 30 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.3
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00 Dec. 19, 2007 Page 31 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.3
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00 Dec. 19, 2007 Page 32 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.4
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00 Dec. 19, 2007 Page 33 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.6
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
Rev. 1.00 Dec. 19, 2007 Page 34 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.6
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
Rev. 1.00 Dec. 19, 2007 Page 35 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.7
Branch Instructions
Instruction
Size
Function
Bcc*

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP

Branches unconditionally to a specified address.
BSR

Branches to a subroutine at a specified address.
JSR

Branches to a subroutine at a specified address.
RTS

Returns from a subroutine
Note:
*
Bcc is the general name for conditional branch instructions.
Rev. 1.00 Dec. 19, 2007 Page 36 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.8
System Control Instructions
Instruction
Size*
Function
RTE

Returns from an exception-handling routine.
SLEEP

Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by
word access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP

PC + 2 → PC
Only increments the program counter.
Note:
*
Refers to the operand size.
B: Byte
W: Word
Rev. 1.00 Dec. 19, 2007 Page 37 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.9
Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 1.00 Dec. 19, 2007 Page 38 of 520
REJ09B0409-0100
Section 2 CPU
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
(1)
Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried out
on the operand. The operation field always includes the first four bits of the instruction. Some
instructions have two operation fields.
(2)
Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
(3)
Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
(4)
Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:8
Figure 2.7 Instruction Formats
Rev. 1.00 Dec. 19, 2007 Page 39 of 520
REJ09B0409-0100
Section 2 CPU
2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:24,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
(1)
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Rev. 1.00 Dec. 19, 2007 Page 40 of 520
REJ09B0409-0100
Section 2 CPU
(2)
Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3)
Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4)
Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
• Register indirect with post-increment@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
(5)
Absolute Address@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the
upper 8 bits are ignored.
Rev. 1.00 Dec. 19, 2007 Page 41 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.11 Absolute Address Access Ranges
Absolute Address
Access Range
8 bits (@aa:8)
H'FF00 to H'FFFF
16 bits (@aa:16)
H'0000 to H'FFFF
24 bits (@aa:24)
H'0000 to H'FFFF
(6)
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number.
(7)
Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
(8)
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows
how to specify branch address for in memory indirect mode. The upper bits of the absolute address
are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Rev. 1.00 Dec. 19, 2007 Page 42 of 520
REJ09B0409-0100
Section 2 CPU
Specified
by @aa:8
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
Rev. 1.00 Dec. 19, 2007 Page 43 of 520
REJ09B0409-0100
Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
23
0
23
0
23
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
0
31
General register contents
op
r
disp
0
31
Sign extension
4
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
31
0
General register contents
r
•Register indirect with pre-decrement @-ERn
disp
1, 2, or 4
31
0
General register contents
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Rev. 1.00 Dec. 19, 2007 Page 44 of 520
REJ09B0409-0100
Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
8 7
23
op
abs
0
H'FFFF
@aa:16
23
op
abs
16 15
0
Sign extension
@aa:24
op
0
23
abs
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
8
disp
23
0
Memory indirect @@aa:8
23
op
abs
8 7
0
abs
H'0000
15
0
Memory contents
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
23
16 15
0
H'00
Register field
Operation field
Displacement
Immediate data
Absolute address
Rev. 1.00 Dec. 19, 2007 Page 45 of 520
REJ09B0409-0100
Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φor φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
Rev. 1.00 Dec. 19, 2007 Page 46 of 520
REJ09B0409-0100
Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 16.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 1.00 Dec. 19, 2007 Page 47 of 520
REJ09B0409-0100
Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in
figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and
program halt state, refer to section 5, Power-Down Modes. For details on exception handling, refer
to section 3, Exception Handling.
CPU state
Reset state
The CPU is initialized
Program execution state
Active (high-speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active (medium-speed) mode
Subactive mode
The CPU executes successive
program instructions at reduced
speed, synchronized by the subclock
Program halt state
A state in which the CPU
operation is stopped to
reduce power consumption
Sleep (high-speed) mode
Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Exception-handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operating States
Rev. 1.00 Dec. 19, 2007 Page 48 of 520
REJ09B0409-0100
Power-down modes
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
Program halt state
Interrupt
source
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
2.8
Usage Notes
2.8.1
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2
EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
Rev. 1.00 Dec. 19, 2007 Page 49 of 520
REJ09B0409-0100
Section 2 CPU
2.8.3
Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
(1)
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address
Rev. 1.00 Dec. 19, 2007 Page 50 of 520
REJ09B0409-0100
Section 2 CPU
Example 2: When the BSET instruction is executed for port 5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BSET instruction executed
BSET
#0,
@PDR5
The BSET instruction is executed for port 5.
• After executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
0
1
0
0
0
0
0
1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Rev. 1.00 Dec. 19, 2007 Page 51 of 520
REJ09B0409-0100
Section 2 CPU
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
• Prior to executing BSET instruction
MOV.B
MOV.B
MOV.B
#H'80, R0L
R0L,
@RAM0
R0L,
@PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
• BSET instruction executed
BSET
#0,
@RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PDR5
The work area (RAM0) value is written to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
Rev. 1.00 Dec. 19, 2007 Page 52 of 520
REJ09B0409-0100
Section 2 CPU
(2)
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BCLR instruction executed
BCLR
#0,
@PCR5
The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
1
1
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
Rev. 1.00 Dec. 19, 2007 Page 53 of 520
REJ09B0409-0100
Section 2 CPU
• Prior to executing BCLR instruction
MOV.B
MOV.B
MOV.B
#H'3F, R0L
R0L,
@RAM0
R0L,
@PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
• BCLR instruction executed
BCLR
#0,
@RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
Rev. 1.00 Dec. 19, 2007 Page 54 of 520
REJ09B0409-0100
Section 3 Exception Handling
Section 3 Exception Handling
3.1
Overview
Exception handling is performed when a reset or interrupt occurs. Table 3.1 shows the priorities of
these two types of exception handling.
Table 3.1
Exception Handling Types and Priorities
Priority
Exception Source
Time of Start of Exception Handling
High
Reset
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
Rev. 1.00 Dec. 19, 2007 Page 55 of 520
REJ09B0409-0100
Section 3 Exception Handling
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
See section 14.3.1, Power-On Reset Circuit.
Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
Rev. 1.00 Dec. 19, 2007 Page 56 of 520
REJ09B0409-0100
(3)
Section 3 Exception Handling
3.2.3
Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3
3.3.1
Interrupts
Overview
The interrupt sources include 13 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0,
IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt
sources, their priorities, and their vector addresses. When more than one interrupt is requested, the
interrupt with the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0 can be set to either rising edge sensing or falling
edge sensing, and IRQAEC can be set to either rising edge sensing, falling edge sensing, or
both edge sensing.
Rev. 1.00 Dec. 19, 2007 Page 57 of 520
REJ09B0409-0100
Section 3 Exception Handling
Table 3.2
Interrupt Sources and Their Priorities
Interrupt Source
Interrupt
Vector Number Vector Address
Priority
RES
Reset
0
H'0000 to H'0001
High
IRQ0
LVDI
IRQ0
Low-voltage detect interrupt
4
H'0008 to H'0009
IRQ1
IRQ1
5
H'000A to H'000B
IRQAEC
IRQAEC
6
H'000C to H'000D
IRQ3
IRQ3
7
H'000E to H'000F
IRQ4
IRQ4
8
H'0010 to H'0011
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
9
H'0012 to H'0013
Timer A
Timer A overflow
11
H'0016 to H'0017
Asynchronous
event counter
Asynchronous event
counter overflow
12
H'0018 to H'0019
Timer C
Timer C overflow or underflow 13
H'001A to H'001B
Timer FL
Timer FL compare match
Timer FL overflow
14
H'001C to H'001D
Timer FH
Timer FH compare match
Timer FH overflow
15
H'001E to H'001F
Timer G
Timer G input capture
Timer G overflow
16
H'0020 to H'0021
SCI3
SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
18
H'0024 to H'0025
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction
executed)
Direct transfer
20
H'0028 to H'0029
Watchdog timer
Low
Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved
and cannot be used.
Rev. 1.00 Dec. 19, 2007 Page 58 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Name
Abbreviation
R/W
Initial Value
Address
IRQ edge select register
IEGR
R/W
—
H'FFF2
Interrupt enable register 1
IENR1
R/W
—
H'FFF3
Interrupt enable register 2
IENR2
—
H'FFF4
Interrupt request register 1
IRR1
R/W
R/W*
Wakeup interrupt request register
IWPR
R/W*
R/W*
Wakeup edge select register
WEGR
R/W
Interrupt request register 2
Note:
(1)
*
IRR2
—
H'FFF6
—
H'FFF7
H'00
H'FFF9
H'00
H'FF90
Write is enabled only for writing of 0 to clear a flag.
IRQ Edge Select Register (IEGR)
Bit
7
6
5
4
3
2
1
0



IEG4
IEG3

IEG1
IEG0
Initial value
1
1
1
0
0

0
0
Read/Write



R/W
R/W
W
R/W
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ4, IRQ3, IRQ1, and IRQ0 are
set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 59 of 520
REJ09B0409-0100
Section 3 Exception Handling
Bit 4—IRQ4 Edge Select (IEG4)
Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin.
Bit 4
IEG4
Description
0
Falling edge of IRQ4 and ADTRG pin input is detected
1
Rising edge of IRQ4 and ADTRG pin input is detected
(initial value)
Bit 3—IRQ3 Edge Select (IEG3)
Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Bit 3
IEG3
Description
0
Falling edge of IRQ3 and TMIF pin input is detected
1
Rising edge of IRQ3 and TMIF pin input is detected
(initial value)
Bit 2—Reserved
Bit 2 is reserved: it can only be written with 0.
Bit 1—IRQ1 Edge Select (IEG1)
Bit 1 selects the input sensing of the IRQ1 pin and TMIC pin.
Bit 1
IEG1
Description
0
Falling edge of IRQ1 and TMIC pin input is detected
1
Rising edge of IRQ1 and TMIC pin input is detected
(initial value)
Bit 0—IRQ0 Edge Select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0
Falling edge of IRQ0 pin input is detected
1
Rising edge of IRQ0 pin input is detected
Rev. 1.00 Dec. 19, 2007 Page 60 of 520
REJ09B0409-0100
(initial value)
Section 3 Exception Handling
(2)
Interrupt Enable Register 1 (IENR1)
Bit
7
6
5
4
3
2
1
0
IENTA

IENWP
IEN4
IEN3
IENEC2
IEN1
IEN0
Initial value
0

0
0
0
0
0
0
Read/Write
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Timer A Interrupt Enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
(initial value)
Bit 6—Reserved
Bit 6 is reserved: it can only be written with 0.
Bit 5—Wakeup Interrupt Enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0
Disables WKP7 to WKP0 interrupt requests
1
Enables WKP7 to WKP0 interrupt requests
(initial value)
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Enable (IEN4 and IEN3)
Bits 4 and 3 enable or disable IRQ4 and IRQ3 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 or 3)
Rev. 1.00 Dec. 19, 2007 Page 61 of 520
REJ09B0409-0100
Section 3 Exception Handling
Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2
Description
0
Disables IRQAEC interrupt requests
1
Enables IRQAEC interrupt requests
(initial value)
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 1 or 0)
Rev. 1.00 Dec. 19, 2007 Page 62 of 520
REJ09B0409-0100
Section 3 Exception Handling
(3)
Interrupt Enable Register 2 (IENR2)
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
3
1
0
IENTC
IENEC
2
IENTFH IENTFL
Initial value
0
0
—
0
0
0
0
0
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
Disables direct transfer interrupt requests
1
Enables direct transfer interrupt requests
(initial value)
Bit 6—A/D Converter Interrupt Enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
Disables A/D converter interrupt requests
1
Enables A/D converter interrupt requests
(initial value)
Bit 5—Reserved
Bit 5 is reserved bit: it can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 63 of 520
REJ09B0409-0100
Section 3 Exception Handling
Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
Disables timer G interrupt requests
1
Enables timer G interrupt requests
(initial value)
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
(initial value)
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
(initial value)
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
Disables timer C interrupt requests
1
Enables timer C interrupt requests
Rev. 1.00 Dec. 19, 2007 Page 64 of 520
REJ09B0409-0100
(initial value)
Section 3 Exception Handling
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3 interrupt control, see section 10.2.6, Serial control register 3 (SCR3).
(4)
Interrupt Request Register 1 (IRR1)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
IRRTA


IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
0
R/(W)*

1
W

0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ4, IRQ3, IRQ1, or IRQ0 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows
(initial value)
Bit 6—Reserved
Bit 6 is reserved; it can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 65 of 520
REJ09B0409-0100
Section 3 Exception Handling
Bit 5—Reserved
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Request Flags (IRRI4 and IRRI3)
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 4 or 3)
Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Bit 2
IRREC2
Description
0
Clearing conditions:
When IRREC2 = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQAEC is designated for interrupt input and the designated signal edge
is input
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0)
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 1 or 0)
Rev. 1.00 Dec. 19, 2007 Page 66 of 520
REJ09B0409-0100
Section 3 Exception Handling
(5)
Interrupt Request Register 2 (IRR2)
Bit
Initial value
Read/Write
7
6
5
IRRDT
IRRAD

0
R/(W)*
0
R/(W)*

W
4
3
1
0
IRRTG IRRTFH IRRTFL
IRRTC
IRREC
0
0
R/(W)* R/(W)*
0
0
R/(W)* R/(W)*
2
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 67 of 520
REJ09B0409-0100
Section 3 Exception Handling
Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4
IRRTG
Description
0
Clearing conditions:
When IRRTG = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2—Timer FL Interrupt Request Flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing conditions:
When IRRTFL = 1, it is cleared by writing 0
1
Setting conditions:
When TCFL and OCRFL match in 8-bit timer mode
(initial value)
Bit 1—Timer C Interrupt Request Flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing conditions:
When IRRTC = 1, it is cleared by writing 0
1
Setting conditions:
When the timer C counter value overflows or underflows
Rev. 1.00 Dec. 19, 2007 Page 68 of 520
REJ09B0409-0100
(initial value)
Section 3 Exception Handling
Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC)
Bit 0
IRREC
Description
0
Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1
Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
(6)
(initial value)
Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the corresponding
interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing conditions:
When IWPFn= 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin WKPn is designated for wakeup input and a rising or falling edge is input
at that pin
(n = 7 to 0)
Rev. 1.00 Dec. 19, 2007 Page 69 of 520
REJ09B0409-0100
Section 3 Exception Handling
(7)
Wakeup Edge Select Register (WEGR)
Bit
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n—WKPn Edge Select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
Rev. 1.00 Dec. 19, 2007 Page 70 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.3.3
External Interrupts
There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.
(1)
Interrupts WKP7 to WKP0
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising
or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
(2)
Interrupts IRQ4, IRQ3, IRQ1 and IRQ0
Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ4, IRQ3, IRQ1,
and IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
When these pins are designated as pins IRQ4, IRQ3, IRQ1, and IRQ0 in port mode register B, 2, and
1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits
IEN4, IEN3, IEN1, and IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I
bit to 1 in CCR.
When IRQ4, IRQ3, IRQ1, and IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in
CCR. Vector numbers 8, 7, 5, and 4 are assigned to interrupts IRQ4, IRQ3, IRQ1, and IRQ0. The
order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details.
Rev. 1.00 Dec. 19, 2007 Page 71 of 520
REJ09B0409-0100
Section 3 Exception Handling
(3)
IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC and IECPWM (output of
PWM for AEC). When the IRQAEC input pin is to be used as an external interrupt, set ECPWME
in AEGSR to 0. This interrupt is detected by rising edge, falling edge, or both edge sensing,
depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt exception handling. Table 3.2 gives details.
3.3.4
Internal Interrupts
There are 9 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18
and 16 to 11 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts
from on-chip peripheral modules.
Rev. 1.00 Dec. 19, 2007 Page 72 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.3.5
Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Priority decision logic
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
Rev. 1.00 Dec. 19, 2007 Page 73 of 520
REJ09B0409-0100
Section 3 Exception Handling
• If the interrupt request is accepted, after processing of the current instruction is completed,
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Rev. 1.00 Dec. 19, 2007 Page 74 of 520
REJ09B0409-0100
Section 3 Exception Handling
Program execution state
IRRI0 = 1
No
Yes
IEN0 = 1
No
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRREC2 = 1
No
Yes
IENEC2 = 1
No
Yes
IRRDT = 1
No
Yes
IENDT = 1
No
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt
handling routine
[Legend]
PC: Program counter
CCR: Condition code register
I bit of CCR
I:
Figure 3.3 Flow up to Interrupt Acceptance
Rev. 1.00 Dec. 19, 2007 Page 75 of 520
REJ09B0409-0100
Section 3 Exception Handling
SP − 4
SP (R7)
CCR
SP − 3
SP + 1
CCR*
SP − 2
SP + 2
PCH
SP − 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
[Legend]
PCH: Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
PCL:
CCR: Condition code register
Stack pointer
SP:
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
Rev. 1.00 Dec. 19, 2007 Page 76 of 520
REJ09B0409-0100
Internal data
bus (16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request
signal
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP − 2
(6) SP − 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(2)
(1)
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Section 3 Exception Handling
Figure 3.5 Interrupt Sequence
Rev. 1.00 Dec. 19, 2007 Page 77 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.3.6
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Not including EEPMOV instruction.
Rev. 1.00 Dec. 19, 2007 Page 78 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.4
Application Notes
3.4.1
Notes on Stack Area Use
When word data is accessed in the LSI, the least significant bit of the address is regarded as 0.
Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never
indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to
save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP →
SP →
PCH
PC L
R1L
PC L
SP →
H'FEFC
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF
MOV. B R1L, @−R7
Stack accessed beyond SP
Contents of PCH are lost
[Legend]
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
Rev. 1.00 Dec. 19, 2007 Page 79 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins and when
the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of
IRQAEC, the following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at
the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear
the interrupt request flag to 0 after switching pin functions. When the value of ECPWME in
AEGSR that sets selection/non-selection of IRQAEC is rewritten, the interrupt request flag may
be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM
output for AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin
function. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this
way.
Table 3.5
Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1
IRRI4
Conditions
When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit
IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit
IEG4 = 1.
IRRI3
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit
IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit
IEG3 = 1.
IRREC2
When an edge as designated by AIEGS1 and AIEGS0 in AEGSR is detected
because the values on the IRQAEC pin and of IECPWM at switching are different
(e.g., when the rising edge has been selected and ECPWME in AEGSR is changed
from 1 to 0 while pin IRQAEC is low and IECPWM = 1).
IRRI1
When PMRB bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit
IEG1 = 0.
When PMRB bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit
IEG1 = 1.
IRRI0
When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit
IEG0 = 0.
When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit
IEG0 = 1.
Rev. 1.00 Dec. 19, 2007 Page 80 of 520
REJ09B0409-0100
Section 3 Exception Handling
Interrupt Request
Flags Set to 1
IWPR
IWPF7
Conditions
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit
WKEGS7 = 0.
When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit
WKEGS7 = 1.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit
WKEGS6 = 0.
When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit
WKEGS6 = 1.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low and WEGR bit
WKEGS5 = 0.
When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low and WEGR bit
WKEGS5 = 1.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low and WEGR bit
WKEGS4 = 0.
When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low and WEGR bit
WKEGS4 = 1.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low and WEGR bit
WKEGS3 = 0.
When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low and WEGR bit
WKEGS3 = 1.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit
WKEGS2 = 0.
When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low and WEGR bit
WKEGS2 = 1.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low and WEGR bit
WKEGS1 = 0.
When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low and WEGR bit
WKEGS1 = 1.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low and WEGR bit
WKEGS0 = 0.
When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low and WEGR bit
WKEGS0 = 1.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
Rev. 1.00 Dec. 19, 2007 Page 81 of 520
REJ09B0409-0100
Section 3 Exception Handling
When switching a pin function, mask the interrupt before setting the bit in the port mode register
(or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction
(e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is
executed immediately after the port mode register (or AEGSR) access without executing an
intervening instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and
determining its value is complicated.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register (or AEGSR) bit
Execute NOP instruction
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clearing Procedure
Rev. 1.00 Dec. 19, 2007 Page 82 of 520
REJ09B0409-0100
Section 3 Exception Handling
3.4.3
Method for Clearing Interrupt Request Flags
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR #1, @IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 of IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
Rev. 1.00 Dec. 19, 2007 Page 83 of 520
REJ09B0409-0100
Section 3 Exception Handling
Rev. 1.00 Dec. 19, 2007 Page 84 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1
Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
In the H8/38524 Group, the system clock pulse generator includes an on-chip oscillator.
4.1.1
Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
IRQAEC
OSC1
OSC2
D
Latch
Q
System
clock
oscillator
On-chip
oscillator
φOSC
(fOSC)
φOSC/2
System
clock
divider
(1/2)
System
clock
divider
φ
φOSC/16
φOSC/32
φOSC/64
φOSC/128
Prescaler S
(13 bits)
ROSC
φ/2
to
φ/8192
System clock pulse generator
φW
φW/2
X1
X2
Subclock
oscillator
φW
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
φW/4
φSUB
φW/8
Subclock pulse generator
φW/2
φW/4
Prescaler W
(5 bits)
φW/8
to
φW/128
Figure 4.1 Block Diagram of Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 85 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.1.2
System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. Four of
the clock signals have names: φ is the system clock, φSUB is the subclock, φOSC is the oscillator
clock, and φW is the watch clock.
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW, φW/2, φW/4, φW/8, φW/16, φW/32, φW/64,
and φW/128. The clock requirements differ from one module to another.
4.1.3
Register Descriptions
Table 4.1 lists the registers that control the clock pulse generators.
Table 4.1
Clock Pulse Generator Control Registers
Name
Abbreviation
R/W
Initial Value
Address
Clock pulse generator control
register
OSCCR
R/W
—
H'FFF5
(1)
Clock Pulse Generator Control Register (OSCCR)
Bit
7
6
5
4
3
2
1
SUBSTP
—
—
—
—
Initial value
0
0
0
0
0
—
—
0
Read/Write
R/W
R
R/W
R/W
R/W
R
R
R/W
IRQAECF OSCF
0
—
OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system
clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets,
and controls whether the subclock oscillator operates or not.
Bit 7—Subclock Oscillator Stop Control (SUBSTP)
Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active
mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to
stop operating.
Rev. 1.00 Dec. 19, 2007 Page 86 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
Bit 7
SUBSTP
Description
0
Subclock oscillator operates
1
Subclock oscillator stopped
(initial value)
Bit 6—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bits 5 to 3—Reserved
These bits are read/write enabled reserved bits.
Bit 2—IRQAEC Flag (IRQAECF)
This bit indicates the IRQAEC pin input level set during resets.
Bit 2
IRQAECF
Description
0
IRQAEC pin set to GND during resets
1
IRQAEC pin set to VCC during resets
Bit 1—OSC Flag (OSCF)
This bit indicates the oscillator operating with the system clock pulse generator.
Bit 1
OSCF
Description
0
System clock oscillator operating (on-chip oscillator stopped)
1
On-chip oscillator operating (system clock oscillator stopped)
Bit 0—Reserved
This bit is reserved. Never write 1 to this bit, as it can cause the LSI to malfunction.
Rev. 1.00 Dec. 19, 2007 Page 87 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input. As shown in figure 4.1, the selection between a
system clock oscillator and an on-chip oscillator is supported. See section 4.2 (5), On-Chip
Oscillator Selection Method, for information on selecting the on-chip oscillator.
(1)
Connecting a Crystal Oscillator
Figure 4.2 shows a typical method of connecting a crystal oscillator.
C1
R f = 1 MΩ ±20%
OSC1
Rf
C2
OSC2
Frequency
Crystal
oscillator
4.0 MHz
NDK
C1, C2
Products
Recommendation
name
value
NR-18
12 pF ±20%
Note: Circuit constants should be determined in consultation
with the resonator manufacturer.
Figure 4.2 Typical Connection to Crystal Oscillator
Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4.2 should be used.
CS
LS
RS
OSC 1
OSC 2
C0
Figure 4.3 Equivalent Circuit of Crystal Oscillator
Rev. 1.00 Dec. 19, 2007 Page 88 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
Table 4.2
Crystal Oscillator Parameters
Frequency (MHz)
4
4.193
RS max (Ω)
100
100
C0 max (pF)
16
16
(2)
Connecting a Ceramic Oscillator
Figure 4.4 shows a typical method of connecting a ceramic oscillator.
C1
OSC1
Rf
C2
OSC2
Ceramic oscillator
Rf = 1 MΩ ±20%
Frequency
2.0 MHz
10.0 MHz
16.0 MHz
20.0 MHz
Ceramic
oscillator
Murata
Products name
C1, C2
Recommendation
value
CSTCC2M00G53-B0
CSTCC2M00G56-B0
CSTLS10M0G53-B0
CSTLS10M0G56-B0
CSTLS16M0X53-B0
CSTLS20M0X53-B0
15 pF ±20%
47 pF ±20%
15 pF ±20%
47 pF ±20%
15 pF ±20%
15 pF ±20%
Notes: Circuit constants should be determined in consultation
with the resonator manufacturer.
Figure 4.4 Typical Connection to Ceramic Oscillator
Rev. 1.00 Dec. 19, 2007 Page 89 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
(3)
Notes on Board Design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
Signal A
To be avoided
C1
Signal B
× ×
OSC 1
OSC 2
C2
Figure 4.5 Board Design of Oscillator Circuit
Note: The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer.
The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal
or ceramic oscillator manufacturer to determine the circuit parameters.
Rev. 1.00 Dec. 19, 2007 Page 90 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
(4)
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical
connection.
OSC1
External clock input
OSC2
Open
Figure 4.6 External Clock Input (Example)
Frequency
Oscillator Clock (φOSC)
Duty cycle
45% to 55%
(5)
On-Chip Oscillator Selection Method
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3
lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC
pin input level set during resets must be fixed at VCC or GND, based on the oscillator to be
selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip
oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND.
Note: The system clock oscillator must be selected in order to program or erase flash memory as
part of operations such as on-board programming. Also, when using the on-chip emulator,
an oscillator should be connected, or an external clock input, even if the on-chip oscillator
is selected.
* Other than watchdog timer or low-voltage detect circuit reset.
Table 4.3
System Clock Oscillator and On-Chip Oscillator Selection Methods
IRQAEC pin input level (during resets)
0
1
System clock oscillator
Enabled
Disabled
On-chip oscillator
Disabled
Enabled
Rev. 1.00 Dec. 19, 2007 Page 91 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.3
(1)
Subclock Generator
Connecting a 32.768 kHz Crystal Oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz crystal
oscillator, as shown in figure 4.7. Follow the same precautions as noted under 3. notes on board
design for the system clock in section 4.2.
C1
C1 = C 2 = 7 pF (typ.)
X1
X2
Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
C2
Frequency
Manufacturer
32.768 kHz Epson Toyocom
Products Name
Equivalent Series Resistance
C-001
35 kΩ max
Figure 4.7 Typical Connection to 32.768 kHz Crystal Oscillator (Subclock)
Figure 4.8 shows the equivalent circuit of the 32.768 kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 k Ω typ
f W = 32.768 kHz
Figure 4.8 Equivalent Circuit of 32.768 kHz Crystal Oscillator
Rev. 1.00 Dec. 19, 2007 Page 92 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
When using a resonator other than the above, ensure optimal conditions by conducting sufficient
evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above
resonators or products equivalent to them are implemented, their oscillation characteristics are
affected by the board design. Be sure to use the actual board to evaluate consistency as a system.
The consistency as a system has to be verified not only in a reset state (i.e., the RES pin is driven
low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been
driven high).
(2)
Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4.9.
X1
X2
GND
Open
Figure 4.9 Pin Connection when not Using Subclock
(3)
Method for Disabling Subclock Oscillator
The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR
register to 1. The register setting to disable the subclock oscillator should be made in the active
mode. When restoring operation of the subclock oscillator after it has been disabled using the
OSCCR register, it is necessary to wait for the oscillation stabilization time (typ: 8s) to elapse
before using the subclock.
Rev. 1.00 Dec. 19, 2007 Page 93 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.4
Prescalers
This LSI is equipped with two on-chip prescalers having different input clocks (prescaler S and
prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its
prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a
5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock. Its prescaled outputs
are used by timer A as a time base for timekeeping.
(1)
Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3, the A/D
converter, the LCD controller, watchdog timer, and the 10-bit PWM. The divider ratio can be set
separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or
φosc/128.
(2)
Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
Rev. 1.00 Dec. 19, 2007 Page 94 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
P17
X1
X2
Vss
OSC2
OSC1
TEST
(Vss)
Figure 4.10 Example of Crystal and Ceramic Oscillator Element Arrangement
Figure 4.11 (1) shows an example measuring circuit with the negative resistance suggested by the
resonator manufacturer. Note that if the negative resistance of the circuit is less than that
suggested by the resonator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation is not occurring because the negative resistance is lower than the
level suggested by the resonator manufacturer, the circuit may be modified as shown in figure 4.11
(2) through (4). Which of the modification suggestions to use and the capacitor capacitance should
be decided based upon an evaluation of factors such as the negative resistance and the frequency
deviation.
Rev. 1.00 Dec. 19, 2007 Page 95 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
Modification
point
OSC1
OSC1
C1
C1
Rf
Rf
OSC2
OSC2
C2
C2
Negative resistance,
addition of −R
(1) Negative Resistance Measuring Circuit
(2) Oscillator Circuit Modification Suggestion 1
Modification
point
Modification
point
C3
OSC1
C1
OSC1
C1
Rf
C2
Rf
OSC2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
C2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggestions
4.5.1
Definition of Oscillation Stabilization Wait Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
Rev. 1.00 Dec. 19, 2007 Page 96 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
1. Oscillation stabilization time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
2. Wait time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The wait time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in
system control register 1 (SYSCR1)).
Oscillation
waveform
(OSC2)
System clock
(φ)
Oscillation
stabilization
time
Wait time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time
Rev. 1.00 Dec. 19, 2007 Page 97 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when an oscillator element is
connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is
halted, the time from the point at which this oscillation waveform starts to change until the
amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is,
the oscillation stabilization time—is required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc"
in the AC characteristics.
Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order
for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
= trc + (8 to 131,072 states)
................. (1)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected
by installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
Rev. 1.00 Dec. 19, 2007 Page 98 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
4.5.2
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted,
leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.
For example, if erroneous operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 8,192 states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
4.6
Usage Note
When using the on-chip emulator, system clock precision is necessary for programming or erasing
the flash memory. However, the on-chip oscillator frequency can vary due to changes in
conditions such as voltage or temperature. Consequently, even if the on-chip oscillator is selected
when using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an
external clock should be supplied. In this case, the LSI uses the on-chip oscillator when user
programs are being executed and the system clock oscillator when programming or erasing flash
memory. The process is controlled by the on-chip emulator.
Rev. 1.00 Dec. 19, 2007 Page 99 of 520
REJ09B0409-0100
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 100 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Section 5 Power-Down Modes
5.1
Overview
The LSI has nine modes of operation after a reset. These include eight power-down modes, in
which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating
modes.
Table 5.1
Operating Modes
Operating Mode
Description
Active (high-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in high-speed operation
Active (medium-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in low-speed operation
Subactive mode
The CPU and all on-chip peripheral functions are operable on
the subclock in low-speed operation
Sleep (high-speed) mode
The CPU halts. On-chip peripheral functions are operable on
the system clock
Sleep (medium-speed) mode
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock
frequency
Subsleep mode
The CPU halts. The time-base function of timer A, timer C,
timer F, timer G, SCI3, AEC, and LCD controller/driver are
operable on the subclock
Watch mode
The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
Standby mode
The CPU and all on-chip peripheral functions halt
Module standby mode
Individual on-chip peripheral functions specified by software
enter standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Rev. 1.00 Dec. 19, 2007 Page 101 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Program
execution state
Reset state
SLEEP
instruction*a
Active
(high-speed)
mode
P *d
EE n
SL uctio
r
t
ins
Program
halt state
Program
halt state
*a
SLEEP
instruction*f
SL
instr EEP
uctio *d
n
*1
SLEEP
instruction*e
Watch
mode
*1
SLEEP
instruction*i
P *e
EE tion
L
c
S ru
st
in
Subactive
mode
P
EE tion
SL ruc
st
inin SL
st E
ru EP
ct
io
n *b
SLEEP
instruction*b
*3
Sleep
(medium-speed)
mode
ins SLEE
tru P
cti
on * j
S
ins LE
tru EP
ctio
n *i
Active
(medium-speed)
mode
SLEEP
instruction*h
ins SLEE
tru
ctio P
n *e
*4
*1
SLEEP
instruction*g
*4
Standby
mode
Sleep
(high-speed)
mode
*3
SLEEP
instruction*c
*2
Subsleep
mode
Power-down modes
Mode Transition Conditions (2)
Mode Transition Conditions (1)
LSON MSON SSBY TMA3 DTON
*a
*b
*c
*d
*e
*f
*g
*h
*i
*j
0
0
1
0
*
0
0
0
1
0
0
1
*
*
*
0
1
1
*
0
0
0
0
1
1
0
0
1
1
1
*
*
1
0
1
*
*
1
1
1
0
0
0
0
0
1
1
1
1
1
Interrupt Sources
*1
*3
Timer A, Timer F, Timer G interrupt, IRQ0 interrupt,
WKP7 to WKP0 interrupts
Timer A, Timer C, Timer F, Timer G, SCI3 interrupt,
IRQ4, IRQ3, IRQ1 and IRQ0 interrupts, IRQAEC,
WKP7 to WKP0 interrupts, AEC
All interrupts
*4
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
*2
*: Don't care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupts are enabled.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5.2 to 5.8.
Figure 5.1 Mode Transition Diagram
Rev. 1.00 Dec. 19, 2007 Page 102 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Table 5.2
Internal State in Each Operating Mode
Active Mode
HighSpeed
Function
System clock oscillator
Subclock oscillator
Instructions
CPU
operations RAM
Registers
I/O ports
IRQ0
External
interrupts IRQ1
IRQAEC
IRQ3
IRQ4
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral Timer A
functions Asynchronous
event counter
Timer C
WDT
Timer F
Timer G
SCI3
PWM
A/D converter
LCD
LVD
MediumSpeed
Sleep Mode
HighSpeed
MediumSpeed
Functions Functions Functions Functions
Functions Functions Functions Functions
Functions Functions Halted
Halted
Retained Retained
Watch
Mode
Subactive
Mode
Subsleep
Mode
Standby
Mode
Halted
Functions
Halted
Retained
Halted
Functions
Functions
Halted
Functions
Halted
Retained
Halted
Functions
Halted
Retained
Functions
Functions
Retained*1
Functions
Functions Functions Functions Functions Functions
Retained*6
Retained*6
Functions Functions Functions Functions Functions
Functions
Functions
Functions
Functions Functions Functions Functions Functions*5 Functions*5 Functions*5 Retained
Functions*8 Functions
Functions
Functions*8
Retained
Functions/
Retained*2
Functions/
Retained*2
Retained
Functions/
Retained*10
Functions/
Retained*9
Reset
Functions/
Retained*7
Functions/
Retained*9
Functions/
Retained*3
Retained
Retained
Functions/
Retained*4
Functions
Functions/
Retained*10
Functions/
Retained*9
Functions/
Retained*3
Retained
Retained
Functions/
Retained*4
Functions
Functions/
Retained*11
Retained
Retained
Retained
Functions/
Retained*4
Functions Functions Functions Functions Functions
Reset
Retained
Retained
Retained
Functions
Notes: 1.
2.
3.
4.
5.
6.
7.
Register contents are retained, but output is high-impedance state.
Functions if an external clock or the φW/4 internal clock is selected; otherwise halted and retained.
Functions if φW/2 is selected as the internal clock; otherwise halted and retained.
Functions if φW, φW/2 or φW/4 is selected as the operating clock; otherwise halted and retained.
Functions if the timekeeping time-base function is selected.
External interrupt requests are ignored. Interrupt request register contents are not altered.
Operates when φW/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and
stands by.
8. Incrementing is possible, but interrupt generation is not.
9. Functions if φW/4 is selected as the internal clock; otherwise halted and retained.
10. Operates when φW/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and
stands by.
11. Operates only when the on-chip oscillator is selected; otherwise stops and stands by.
Rev. 1.00 Dec. 19, 2007 Page 103 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
System Control Registers
Name
Abbreviation
R/W
Initial Value
System control register 1
SYSCR1
R/W
H'07
H'FFF0
System control register 2
SYSCR2
R/W
H'F0
H'FFF1
(1)
Address
System Control Register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON

MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W

R/W
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7—Software Standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
•
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
1
Rev. 1.00 Dec. 19, 2007 Page 104 of 520
REJ09B0409-0100
(initial value)
Section 5 Power-Down Modes
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation stabilization time.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 32,768 states
0
1
1
Wait time = 65,536 states
1
0
0
Wait time = 131,072 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock input mode)
Note: If an external clock is being input, set standby timer select to external clock mode before
mode transition. Also, do not set standby timer select to external clock mode if no external
clock is used. 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip
oscillator is used.
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (φ)
1
The CPU operates on the subclock (φSUB)
(initial value)
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 105 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φosc/128, φosc/64, φosc/32, or φosc/16 as the operating clock in active (mediumspeed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (highspeed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
0
0
φosc/16
0
1
φosc/32
1
0
φosc/64
1
1
φosc/128
(2)
(initial value)
System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0



NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write



R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4—Noise Elimination Sampling Frequency Select (NESEL)
This bit selects the frequency at which the watch clock signal (φW) generated by the subclock pulse
generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock pulse
generator. When φOSC = 2 to 20 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
Sampling rate is φOSC/16
1
Sampling rate is φOSC/4
Rev. 1.00 Dec. 19, 2007 Page 106 of 520
REJ09B0409-0100
(initial value)
Section 5 Power-Down Modes
Bit 3—Direct Transfer on Flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of other
control bits.
Bit 3
DTON
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
•
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON =
0, and MSON = 1
1
(initial value)
Bit 2—Medium Speed on Flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0
Operation in active (high-speed) mode
1
Operation in active (medium-speed) mode
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 107 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0 cannot
be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
0
0
φW/8
0
1
φW/4
1
*
φW/2
(initial value)
*: Don’t care
5.2
5.2.1
Sleep Mode
Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
Rev. 1.00 Dec. 19, 2007 Page 108 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.2.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at
the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Rev. 1.00 Dec. 19, 2007 Page 109 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.3
5.3.1
Standby Mode
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the
entire chip, standby mode is cleared, and interrupt exception handling starts. Operation
resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed)
mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.
Rev. 1.00 Dec. 19, 2007 Page 110 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.3.3
Oscillator Stabilization Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When an oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
wait time at least as long as the oscillation stabilization time.
Table 5.4
Clock Frequency and Stabilization Time
(Unit: ms)
STS2
STS1
STS0
Wait Time
5 MHz
2 MHz
0
0
0
8,192 states
1.638
4.1
1
16,384 states
3.277
8.2
0
32,768 states
6.554
16.4
1
65,536 states
13.108
32.8
0
131,072 states
26.216
65.5
1
2 states
(Use prohibited with other than
external clock)
0.0004
0.001
0
8 states
0.002
0.004
1
16 states
0.003
0.008
1
1
0
1
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU
sometimes will start operation before wait time completion.
• When the on-chip oscillator is used
8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used.
Rev. 1.00 Dec. 19, 2007 Page 111 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows
the timing in this case.
φ
Internal data bus
SLEEP instruction fetch
Fetch of next instruction
SLEEP instruction execution
Pins
Internal processing
Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 5.2 Standby Mode Transition and Pin States
Rev. 1.00 Dec. 19, 2007 Page 112 of 520
REJ09B0409-0100
High-impedance
Standby mode
Section 5 Power-Down Modes
5.3.5
Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in 3, Recommended timing of external input signals, below
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in “Capture possible: case 1” in figure 5.3.
External input signal capture is also possible with the timing shown in “Capture possible: case
2” and “Capture possible: case 3” in figure 5.3, in which a 2 tcyc or 2 tsubcyc level width is
secured.
Rev. 1.00 Dec. 19, 2007 Page 113 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Operating
mode
Active (high-speed,
medium-speed) mode
or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Wait for Active (high-speed,
Standby mode oscillation medium-speed) mode
or watch mode to settle or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible:
case 1
Capture possible:
case 2
Capture possible:
case 3
Capture not
possible
Interrupt by different
signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode
4. Input pins to which these notes apply:
IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIC, TMIF, TMIG, ADTRG.
5.4
5.4.1
Watch Mode
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip
RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same
states as before the transition.
Rev. 1.00 Dec. 19, 2007 Page 114 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or
by input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on
the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are
cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a
stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
5.4.3
Oscillator Stabilization Time after Watch Mode is Cleared
The wait time is the same as for standby mode; see section 5.3.3, Oscillator Stabilization Time
after Standby Mode is Cleared.
5.4.4
Notes on External Input Signal Changes before/after Watch Mode
See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
Rev. 1.00 Dec. 19, 2007 Page 115 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.5
5.5.1
Subsleep Mode
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter and PWM is in active state. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0) or by a low input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φSUB(s) delay may
occur after the interrupt request signal occurrence, before the interrupt exception handling
start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
Rev. 1.00 Dec. 19, 2007 Page 116 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.6
5.6.1
Subactive Mode
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter,
SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to
subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φW/2, φW/4, and φW/8.
Rev. 1.00 Dec. 19, 2007 Page 117 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.7
5.7.1
Active (Medium-Speed) Mode
Transition to Active (Medium-Speed) Mode
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby
mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any
interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit
of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
Furthermore, it sometimes acts with half state early timing at the time of transition to active
(medium-speed) mode.
5.7.2
Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See section 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (mediumspeed) mode is cleared.
5.7.3
Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Rev. 1.00 Dec. 19, 2007 Page 118 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.8
5.8.1
Direct Transfer
Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is
made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I
bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear
the resulting mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits
STS2 to STS0 has elapsed.
Rev. 1.00 Dec. 19, 2007 Page 119 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.
5.8.2
Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when φ/8 is selected
as the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
Rev. 1.00 Dec. 19, 2007 Page 120 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as
the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
φw/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
Rev. 1.00 Dec. 19, 2007 Page 121 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when φw/8 or φ/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc:
tw:
tcyc:
tsubcyc:
5.8.3
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
Notes on External Input Signal Changes before/after Direct Transition
1. Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
2. Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
3. Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
4. Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Rev. 1.00 Dec. 19, 2007 Page 122 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.9
Module Standby Mode
5.9.1
Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode, the
system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
5.9.2
Clearing Module Standby Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
Table 5.5
Setting and Clearing Module Standby Mode by Clock Stop Register
Register Name Bit Name
CKSTPR1
TACKSTP
Operation
1
Timer A module standby mode is cleared
0
Timer A is set to module standby mode
TCCKSTP
1
Timer C module standby mode is cleared
0
Timer C is set to module standby mode
TFCKSTP
1
Timer F module standby mode is cleared
0
Timer F is set to module standby mode
1
Timer G module standby mode is cleared
0
Timer G is set to module standby mode
ADCKSTP
1
A/D converter module standby mode is cleared
0
A/D converter is set to module standby mode
S32CKSTP
1
SCI3 module standby mode is cleared
0
SCI3 is set to module standby mode
TGCKSTP
Rev. 1.00 Dec. 19, 2007 Page 123 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
Register Name Bit Name
CKSTPR2
LDCKSTP
PW1CKSTP
WDCKSTP
AECKSTP
PW2CKSTP
LVDCKSTP
Operation
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
1
PWM1 module standby mode is cleared
0
PWM1 is set to module standby mode
1
Watchdog timer module standby mode is cleared
0
Watchdog timer is set to module standby mode
1
Asynchronous event counter module standby mode
is cleared
0
Asynchronous event counter is set to module
standby mode
1
PWM2 module standby mode is cleared
0
PWM2 is set to module standby mode
1
LVD module standby mode is cleared
0
LVD is set to module standby mode
Note: For details of module operation, see the sections on the individual modules.
Rev. 1.00 Dec. 19, 2007 Page 124 of 520
REJ09B0409-0100
Section 6 ROM
Section 6 ROM
6.1
Overview
The H8/38524 has 32 Kbytes of on-chip mask ROM, the H8/38523 has 24 Kbytes, the H8/38522
has 16 Kbytes, the H8/38521 has 12 Kbytes, and the H8/38520 has 8 Kbytes. The ROM is
connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data
and word data. Flash memory versions of the H8/38524 and H8/38522 are available. The former
has 32 Kbytes, and the latter 16 Kbytes, of flash memory.
Rev. 1.00 Dec. 19, 2007 Page 125 of 520
REJ09B0409-0100
Section 6 ROM
6.2
6.2.1
Flash Memory Overview
Features
The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are
summarized below.
• Programming/erase methods
 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. On the HD64F38524, the flash memory is configured as follows: 1 Kbyte × 4 blocks,
28 Kbytes × 1 block. On the HD64F38522, the flash memory is configured as follows: 1
Kbyte × 4 blocks, 12 Kbytes × 1 block. To erase the entire flash memory, each block must
be erased in turn.
Note: The system clock oscillator must be used when programming or erasing the flash
memory.
• Reprogramming capability
 The HD64F38524 and HD64F38522 can be reprogrammed up to 1,000 times.
• On-board programming
 On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
 Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
 Sets software protection against flash memory programming/erasing.
• Power-down mode
 The power supply circuit is partly halted in the subactive mode and can be read in the
power-down mode.
Rev. 1.00 Dec. 19, 2007 Page 126 of 520
REJ09B0409-0100
Section 6 ROM
Block Diagram
Internal address bus
Internal data bus (16 bits)
FLMCR1
Module bus
6.2.2
FLMCR2
Bus interface/controller
EBR
Operating
mode
TES pin
P95 pin
P34 pin
FLPWCR
FENR
Flash memory
[Legend]
FLMCR1:
FLMCR2:
EBR:
FLPWCR:
FENR:
Flash memory control register 1
Flash memory control register 2
Erase block register
Flash memory power control register
Flash memory enable register
Figure 6.1 Block Diagram of Flash Memory
Rev. 1.00 Dec. 19, 2007 Page 127 of 520
REJ09B0409-0100
Section 6 ROM
6.2.3
Block Configuration
Figure 6.2 shows the block configuration of the flash memory. The thick lines indicate erasing
units, the narrow lines indicate programming units, and the values are addresses. In versions with
32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes ×
1 block. In versions with 16 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4
blocks and 12 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in
128-byte units starting from an address with lower eight bits H'00 or H'80.
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
Programming unit: 128 bytes
H'007F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'047F
H'04FF
1 Kbyte
Erase unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1 Kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 Kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'7F80
H'7F81
H'7F82
H'7FFF
H'107F
28 Kbytes
Figure 6.2(1) Block Configuration of 32-Kbyte Flash Memory
Rev. 1.00 Dec. 19, 2007 Page 128 of 520
REJ09B0409-0100
Section 6 ROM
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'04FF
H'0780
H'0781
H'0782
H'07FF
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Programming unit: 128 bytes
H'007F
1 Kbyte
Erase unit
H'047F
Programming unit: 128 bytes
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'087F
H'08FF
1 Kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 Kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
12 Kbytes
Figure 6.2(2) Block Configuration of 16-Kbyte Flash Memory
Rev. 1.00 Dec. 19, 2007 Page 129 of 520
REJ09B0409-0100
Section 6 ROM
6.2.4
Register Configuration
Table 6.1 lists the register configuration to control the flash memory when the built in flash
memory is effective.
Table 6.1
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Flash memory control register 1
FLMCR1
R/W
H'00
H'F020
Flash memory control register 2
FLMCR2
R
H'00
H'F021
Flash memory power control register
FLPWCR
R/W
H'00
H'F022
Erase block register
EBR
R/W
H'00
H'F023
Flash memory enable register
FENR
R/W
H'00
H'F02B
Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is
enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which mask ROM is included does not have these
registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.
6.3
6.3.1
Descriptions of Registers of the Flash Memory
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
—
SWE
ESU
PSU
EV
PV
E
P
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.5, Flash
Memory Programming/Erasing. By setting this register, the flash memory enters program mode,
erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0
of this register are cleared when using flash memory as normal built-in ROM.
Bit 7—Reserved
This bit is always read as 0 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 130 of 520
REJ09B0409-0100
Section 6 ROM
Bit 6—Software Write Enable (SWE)
This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to
0 and the EBR register are to be set).
Bit 6
SWE
Description
0
Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits
cannot be set.
(initial value)
1
Flash memory programming/erasing is enabled.
Bit 5—Erase Setup (ESU)
This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in
FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time).
Bit 5
ESU
Description
0
The erase setup state is cancelled
1
The flash memory changes to the erase setup state. Set this bit to 1 before setting
the E bit to 1 in FLMCR1.
(initial value)
Bit 4—Program Setup (PSU)
This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1 in
FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time).
Bit 4
PSU
Description
0
The program setup state is cancelled
1
The flash memory changes to the program setup state. Set this bit to 1 before
setting the P bit to 1 in FLMCR1.
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 131 of 520
REJ09B0409-0100
Section 6 ROM
Bit 3—Erase-Verify (EV)
This bit is to set changing to or canceling erase-verify mode (do not set SWE, ESU, PSU, PV, E,
and P bits at the same time).
Bit 3
EV
Description
0
Erase-verify mode is cancelled
1
The flash memory changes to erase-verify mode
(initial value)
Bit 2—Program-Verify (PV)
This bit is to set changing to or canceling program-verify mode (do not set SWE, ESU, PSU, EV,
E, and P bits at the same time).
Bit 2
PV
Description
0
Program-verify mode is cancelled
1
The flash memory changes to program-verify mode
(initial value)
Bit 1—Erase (E)
This bit is to set changing to or canceling erase mode (do not set SWE, ESU, PSU, EV, PV, and P
bits at the same time).
Bit 1
E
Description
0
Erase mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and ESU = 1, the flash memory
changes to erase mode.
Rev. 1.00 Dec. 19, 2007 Page 132 of 520
REJ09B0409-0100
(initial value)
Section 6 ROM
Bit 0—Program (P)
This bit is to set changing to or canceling program mode (do not set SWE, ESU, PSU, EV, PV,
and E bits at the same time).
Bit 0
P
Description
0
Program mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory
changes to program mode.
6.3.2
(initial value)
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
—
—
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER)
This bit is set when the flash memory detects an error and goes to the error-protection state during
programming or erasing to the flash memory. See section 6.6.3, Error Protection, for details.
Bit 7
FLER
Description
0
The flash memory operates normally.
1
Indicates that an error has occurred during an operation on flash memory
(programming or erasing).
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 133 of 520
REJ09B0409-0100
Section 6 ROM
6.3.3
Erase Block Register (EBR)
Bit
7
6
5
4
3
2
1
0
—
—
—
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.2 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.2
Division of Blocks to Be Erased
EBR
Bit Name
Block (Size)
Address
0
EB0
EB0 (1 Kbyte)
H'0000 to H'03FF
1
EB1
EB1 (1 Kbyte)
H'0400 to H'07FF
2
EB2
EB2 (1 Kbyte)
H'0800 to H'0BFF
3
EB3
EB3 (1 Kbyte)
H'0C00 to H'0FFF
4
EB4
EB4 (12 Kbytes)
H'1000 to H'3FFF (HD64F38522)
EB4 (28 Kbytes)
H'1000 to H'7FFF (HD64F38524)
6.3.4
Flash Memory Power Control Register (FLPWCR)
Bit
7
6
5
4
3
2
1
0
PDWND
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Rev. 1.00 Dec. 19, 2007 Page 134 of 520
REJ09B0409-0100
Section 6 ROM
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
Description
0
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
(initial value)
1
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.3.5
Flash Memory Enable Register (FENR)
Bit
7
6
5
4
3
2
1
0
FLSHE
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
Description
0
Flash memory control registers cannot be accessed
1
Flash memory control registers can be accessed
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 135 of 520
REJ09B0409-0100
Section 6 ROM
6.4
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, the series of HD64F38524 and HD64F38522 changes
to a mode depending on the TEST pin settings, P95 pin settings, and input level of each port, as
shown in table 6.3. The input level of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 6.3
Setting Programming Modes
TEST
P95
P34
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
X: Don’t care
6.4.1
Boot Mode
Table 6.4 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 6.5, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity. The inversion function of TXD and RXD pins by the SPCR register is set to
“Not to be inverted,” so do not put the circuit for inverting a value between the host and this
LSI.
Rev. 1.00 Dec. 19, 2007 Page 136 of 520
REJ09B0409-0100
Section 6 ROM
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 6.5.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a
WDT overflow occurs.
8. Do not change the TEST pin and P95 pin input levels in boot mode.
Rev. 1.00 Dec. 19, 2007 Page 137 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.4
Boot Mode Operation
Host Operation
LSI Operation
Processing Contents
Item
Processing Contents
Branches to boot program at reset-start.
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Flash memory erase
Transmits data H'55 when data H'00
is received and no error occurs.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Transfer of
programming control
program
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transfer of
programming control
program (repeated for
N times)
Transmits 1-byte of programming
control program
Echobacks received data to host and also
transfers it to RAM.
Transmits 1-byte data H'AA to host.
Execution of
Programming
control program
Table 6.5
Echobacks the 2-byte received data to host.
Branches to programming control program
transferred to on-chip RAM and starts execution.
Oscillating Frequencies (fOSC) for which Automatic Adjustment of LSI Bit Rate
is Possible
Host Bit Rate
Oscillating Frequencies (fOSC) Range of LSI
19,200 bps
16 to 20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
6 to 20 MHz
2,400 bps
2 to 20 MHz
1,200 bps
2 to 20 MHz
Rev. 1.00 Dec. 19, 2007 Page 138 of 520
REJ09B0409-0100
Section 6 ROM
6.4.2
Programming/Erasing in User Program Mode
The term user mode refers to the status when a user program is being executed. On-board
programming/erasing of an individual flash memory block can also be performed in user program
mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 6.3 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 6.5,
Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 6.3 Programming/Erasing Flowchart Example in User Program Mode
Rev. 1.00 Dec. 19, 2007 Page 139 of 520
REJ09B0409-0100
Section 6 ROM
6.4.3
Notes on On-Board Programming
1. You must use the system clock oscillator when programming or erasing flash memory. The onchip oscillator should not be used for programming or erasing flash memory. See section 4.2
(5), On-Chip Oscillator Selection Method, for information on switching between the system
clock oscillator and the on-chip oscillator.
2. The watchdog timer operates after a reset is canceled. When executing a program prepared by
the user that performs programming and erasing in the user mode, the watchdog timer’s
overflow cycle should be set to an appropriate value. Refer to section 6.5.1, Program/ProgramVerify, for information on the appropriate watchdog timer overflow cycle for programming,
and refer to section 6.5.2, Erase/Erase-Verify, for information on the appropriate watchdog
timer overflow cycle for erasing.
6.5
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 6.5.1, Program/Program-Verify and section 6.5.2,
Erase/Erase-Verify, respectively.
Rev. 1.00 Dec. 19, 2007 Page 140 of 520
REJ09B0409-0100
Section 6 ROM
6.5.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 6.4 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.6, and additional programming data
computation according to table 6.7.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 6.8 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent over-programming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Rev. 1.00 Dec. 19, 2007 Page 141 of 520
REJ09B0409-0100
Section 6 ROM
Write pulse application subroutine
Apply Write Pulse
START
WDT enable
Set SWE bit in FLMCR1
Set PSU bit in FLMCR1
Wait 1 µs
Wait 50 µs
Store 128-byte program data in program
data area and reprogram data area
n=1
Set P bit in FLMCR1
m=0
Wait (Wait time = programming time)
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Clear P bit in FLMCR1
Apply Write pulse
Wait 5 µs
Set PV bit in FLMCR1
Clear PSU bit in FLMCR1
Wait 4 µs
Wait 5 µs
Set block start address as
verify address
Disable WDT
n←n+1
H'FF dummy write to verify address
End Sub
Wait 2 µs
Read verify data
Verify data =
write data?
Increment address
No
m=1
Yes
n≤6?
No
Yes
Additional-programming data
computation
Reprogram data computation
No
128-byte
data verification
completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
n ≤ 6?
No
Yes
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
No
n ≤ 1000 ?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure
Figure 6.4 Program/Program-Verify Flowchart
Rev. 1.00 Dec. 19, 2007 Page 142 of 520
REJ09B0409-0100
Yes
Section 6 ROM
Table 6.6
Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 6.7
Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
Comments
Table 6.8
Programming Time
n
(Number of Writes)
Programming
Time
In Additional
Programming
1 to 6
30
10
7 to 1,000
200
—
Note: Time shown in µs.
Rev. 1.00 Dec. 19, 2007 Page 143 of 520
REJ09B0409-0100
Section 6 ROM
6.5.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.5 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent over-erasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
6.5.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, are disabled while flash memory is being programmed or erased, or while the boot
program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 1.00 Dec. 19, 2007 Page 144 of 520
REJ09B0409-0100
Section 6 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
n←n+1
Read verify data
No
Verify data = all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 µs
Wait 4µs
All erase block erased ?
n ≤100 ?
Yes
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Figure 6.5 Erase/Erase-Verify Flowchart
Rev. 1.00 Dec. 19, 2007 Page 145 of 520
REJ09B0409-0100
Section 6 ROM
6.6
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.6.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset
state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.6.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase
protection is set for all blocks.
Rev. 1.00 Dec. 19, 2007 Page 146 of 520
REJ09B0409-0100
Section 6 ROM
6.6.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to over-programming or over-erasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be
made to verify mode. Error protection can be cleared only by a power-on reset.
6.7
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory
(F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to
programmer mode, see table 6.3.
6.7.1
Socket Adapter
The socket adapter converts the pin allocation of the HD64F38524 and HD64F38522 to that of the
discrete flash memory HN28F101. The address of the on-chip flash memory is H'0000 to H'7FFF.
Figure 6.6 shows a socket-adapter-pin correspondence diagram of the HD64F38524 and
HD64F38522.
Rev. 1.00 Dec. 19, 2007 Page 147 of 520
REJ09B0409-0100
Section 6 ROM
6.7.2
Programmer Mode Commands
The following commands are supported in programmer mode.
•
•
•
•
Memory Read Mode
Auto-Program Mode
Auto-Erase Mode
Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read
mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.9 shows the sequence of each command. In auto-programming mode, 129 cycles
are required since 128 bytes are written at the same time. In memory read mode, the number of
cycles depends on the number of address write cycles (n).
Table 6.9
Command Sequence in Programmer Mode
1st Cycle
2nd Cycle
Command Name
Number
of Cycles
Mode
Address
Data
Mode
Address
Data
Memory read
1+n
Write
X
H'00
Read
RA
Dout
Auto-program
129
Write
X
H'40
Write
WA
Din
Auto-erase
2
Write
X
H'20
Write
X
H'20
Status read
2
Write
X
H'71
Write
X
H'71
n: the number of address write cycles
Rev. 1.00 Dec. 19, 2007 Page 148 of 520
REJ09B0409-0100
Section 6 ROM
HD64F38524, HD64F38522
Pin No.
Socket Adapter
(Conversion to
32-Pin
Arrangement)
HN28F101 (32 Pins)
FP-80A
TFP-80C
Pin Name
30
P71
36
P77
A15
3
56
P92
WE
31
21
P60
I/O0
13
22
P61
I/O1
14
23
P62
I/O2
15
24
P63
I/O3
17
25
P64
I/O4
18
26
P65
I/O5
19
27
P66
I/O6
20
28
P67
I/O7
21
69
P40
A0
12
70
P41
A1
11
63
P32
A2
10
64
P33
A3
9
65
P34
A4
8
66
P35
A5
7
67
P36
A6
6
68
P37
A7
5
29
P70
A8
27
71
P42
OE
24
31
P72
A10
23
32
P73
A11
25
33
P74
A12
4
34
P75
A13
28
35
P76
A14
29
72
P43
CE
22
52
Vcc
Vcc
32
1
AVcc
Vss
16
6
X1
11
TEST
51
V1
52
Vcc
58
P94
4, 59
CVcc, P95
8
Vss
53
Vss
73
PB0
74
PB1
Pin Name
Pin No.
FWE
1
A9
26
A16
2
[Legend]
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency
of the oscillator circuit
should be 10 MHz.
75
PB2
10,9
OSC1,OSC2
Oscillator circuit
12
RES
Other than the above
(OPEN)
Power-on
reset circuit
Figure 6.6 Socket Adapter Pin Correspondence Diagram
(HD64F38524, HD64F38522)
Rev. 1.00 Dec. 19, 2007 Page 149 of 520
REJ09B0409-0100
Section 6 ROM
6.7.3
Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read. Once memory
read mode has been entered, consecutive reads can be performed.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. After powering on, memory read mode is entered.
4. Tables 6.10 to 6.12 show the AC characteristics.
Table 6.10 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.7
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Command write
Memory read mode
Address stable
A15−A0
tces
tceh
tnxtc
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Data is latched on the rising edge of WE.
Figure 6.7 Timing Waveforms for Memory Read after Memory Write
Rev. 1.00 Dec. 19, 2007 Page 150 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.11 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.8
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Memory read mode
A15−A0
Other mode command write
Address stable
tnxtc
tces
tceh
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Do not enable WE and OE at the same time.
Figure 6.8 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Rev. 1.00 Dec. 19, 2007 Page 151 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.12 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Access time
tacc
—
20
µs
Figure 6.9
CE output delay time
tce
—
150
ns
Figure 6.10
OE output delay time
toe
—
150
ns
Output disable delay time
tdf
—
100
ns
Data output hold time
toh
5
—
ns
A15−A0
Address stable
Address stable
CE
OE
WE
tacc
tacc
toh
toh
I/O7−I/O0
Figure 6.9 CE and OE Enable State Read Timing Waveforms
A15−A0
Address stable
Address stable
tce
tce
CE
toe
toe
OE
WE
tacc
tacc
toh
tdf
toh
tdf
I/O7−I/O0
Figure 6.10 CE and OE Clock System Read Timing Waveforms
Rev. 1.00 Dec. 19, 2007 Page 152 of 520
REJ09B0409-0100
Section 6 ROM
6.7.4
Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming.
2. Perform auto-programming once only on the same address block. It is not possible to program
an address block that has already been programmed.
3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when
programming fewer than 128 bytes. In this case, H'FF data must be written to the extra
addresses.
4. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
5. Memory address transfer is performed in the second cycle (figure 6.11). Do not perform
transfer after the third cycle.
6. Do not perform a command write during a programming operation.
7. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
10. Table 6.13 shows the AC characteristics.
Rev. 1.00 Dec. 19, 2007 Page 153 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.13 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.11
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
twsts
1
—
ms
Status polling access time
tspa
—
150
ns
Address setup time
tas
0
—
ns
Address hold time
tah
60
—
ns
Memory write time
twrite
1
3000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Address
stable
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tas
tah
twsts
tspa
WE
tds
tdh
I/O7
twrite
Write operation end decision signal
I/O6
I/O5−I/O0
Data transfer
1 to 128 bytes
Write normal end decision signal
H'40
H'00
Figure 6.11 Auto-Program Mode Timing Waveforms
Rev. 1.00 Dec. 19, 2007 Page 154 of 520
REJ09B0409-0100
Section 6 ROM
6.7.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
5. Table 6.14 shows the AC characteristics.
Table 6.14 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.12
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
tests
1
—
ms
Status polling access time
tspa
—
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Rev. 1.00 Dec. 19, 2007 Page 155 of 520
REJ09B0409-0100
Section 6 ROM
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
twep
tf
tr
tests
tspa
WE
tds
terase
tdh
I/O7
Erase end
decision signal
I/O6
Erase normal
end
decision signal
I/O5−I/O0
H'20
H'20
H'00
Figure 6.12 Auto-Erase Mode Timing Waveforms
6.7.6
Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
3. Table 6.15 shows the AC characteristics and 6.16 shows the return codes.
Rev. 1.00 Dec. 19, 2007 Page 156 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.15 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Read time after command write
tnxtc
20
—
µs
Figure 6.13
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
OE output delay time
toe
—
150
ns
Disable delay time
tdf
—
100
ns
CE output delay time
tce
—
150
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
A15−A0
tces
tceh
tnxtc tces
tceh
tnxtc
tnxtc
CE
tce
OE
twep
tf
tr
twep
tf
tr
toe
WE
tds
I/O7−/O0
tdh
H'71
tds
tdf
tdh
H'71
Note: I/O2 and I/O3 are undefined.
Figure 6.13 Status Read Mode Timing Waveforms
Rev. 1.00 Dec. 19, 2007 Page 157 of 520
REJ09B0409-0100
Section 6 ROM
Table 6.16 Status Read Mode Return Codes
Pin Name
Initial Value
Indications
I/O7
0
1: Abnormal end
0: Normal end
I/O6
0
1: Command error
0: Otherwise
I/O5
0
1: Programming error
0: Otherwise
I/O4
0
1: Erasing error
0: Otherwise
I/O3

0
I/O2
0

I/O1
0
1: Over counting of writing or erasing
0: Otherwise
I/O0
0
1: Effective address error
0: Otherwise
6.7.7
Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 6.17 Status Polling Output Truth Table
I/O7
I/O6
I/O0 to 5
Status
0
0
0
During internal operation
1
0
0
Abnormal end
1
1
0
Normal end
0
1
0
—
Rev. 1.00 Dec. 19, 2007 Page 158 of 520
REJ09B0409-0100
Section 6 ROM
6.7.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 6.18 Stipulated Transition Times to Command Wait State
Item
Symbol
Min
Max
Unit
Notes
Oscillation stabilization time(crystal oscillator)
Tosc1
10
—
ms
Figure 6.14
Oscillation stabilization time(ceramic oscillator)
Tosc1
5
—
ms
Programmer mode setup time
Tbmv
10
—
ms
Vcc hold time
Tdwn
0
—
ms
tosc1
tbmv
Auto-program mode
Auto-erase mode
tdwn
Vcc
RES
Figure 6.14 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence
6.7.9
Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
2. The flash memory is initially in the erased state when the device is shipped by Renesas
Technology. For other chips for which the erasure history is unknown, it is recommended that
auto-erasing be executed to check and supplement the initialization (erase) level.
Rev. 1.00 Dec. 19, 2007 Page 159 of 520
REJ09B0409-0100
Section 6 ROM
6.8
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.19 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to
STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external
clock is being used.
Table 6.19 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Watch mode
Standby mode
Standby mode
Rev. 1.00 Dec. 19, 2007 Page 160 of 520
REJ09B0409-0100
Section 7 RAM
Section 7 RAM
7.1
Overview
The H8/38524, H8/38523, and H8/38522 have 1 Kbyte of high-speed static RAM on-chip, and the
H8/38521 and H8/38520 have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus,
allowing high-speed 2-state access for both byte data and word data.
7.1.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB80
H'FB81
H'FB82
H'FB82
H'FB83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7.1 RAM Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 161 of 520
REJ09B0409-0100
Section 7 RAM
Rev. 1.00 Dec. 19, 2007 Page 162 of 520
REJ09B0409-0100
Section 8 I/O Ports
Section 8 I/O Ports
8.1
Overview
The LSI is provided with five 8-bit I/O ports, one 4-bit I/O port, two 3-bit I/O ports, one 8-bit
input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the
functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See section 2.8.3, Bit-Manipulation Instruction, for information on executing bit-manipulation
instructions to write data in PCR or PDR.
Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable
in 4-bit units.
Block diagrams of each port are given in appendix B, I/O Port Block Diagrams.
Table 8.1
Port Functions
Port
Description
Pins
Other Functions
Function
Switching
Registers
Port 1
•
3-bit I/O port
P17/IRQ3/TMIF
•
MOS input pull-up
option
External interrupt 3, timer
event input pin TMIF
PMR1
TCRF
P14/IRQ4/ADTRG
External interrupt 4, A/D
converter external trigger
PMR1
AMR
P13/TMIG
Timer G input capture
PMR1
PMR2
P37/AEVL
P36/AEVH
Asynchronous counter event
input pins AEVL, AEVH
PMR3
ECCR
P35 to P33
None
PMR2
P32, TMOFH
P31, TMOFL
Timer F output compare
output
PMR3
P30/UD
Timer C count up/down
selection input
PMR3
Port 3
•
8-bit I/O port
•
MOS input pull-up
option
•
Large-current port
•
MOS open drain
output selectable
(only P35)
Rev. 1.00 Dec. 19, 2007 Page 163 of 520
REJ09B0409-0100
Section 8 I/O Ports
Port
Description
Pins
Other Functions
Function
Switching
Registers
Port 4
•
1-bit input port
P43/IRQ0
External interrupt 0
PMR2
•
3-bit I/O port
P42/TXD32
P41/RXD32
P40/SCK32
SCI3 data output (TXD32),
data input (RXD32), clock
input/output (SCK32)
SCR3
SMR3
SPCR
•
8-bit I/O port
•
MOS input pull-up
option
P57 to P50/
WKP7 to WKP0/
SEG8 to SEG1
Wakeup input (WKP7 to
WKP0), segment output
(SEG8 to SEG1)
PMR5
LPCR
•
8-bit I/O port
MOS input pull-up
option
Segment output (SEG16 to
SEG9)
LPCR
•
P67 to P60/
SEG16 to SEG9
Port 7
•
8-bit I/O port
P77 to P70/
SEG24 to SEG17
Segment output (SEG24 to
SEG17)
LPCR
Port 8
•
8-bit I/O port
P87 to P80/
SEG32 to SEG25
Segment output (SEG32 to
SEG25)
LPCR
Port 9
•
Dedicated 6-bit
output port
P95, P94, P92,
P93/Vref
LVD reference voltage
external input pin
LVDSR
P91, P90/
PWM2, PWM1
10-bit PWM output
PMR9
Input port
IRQAEC
None
Port A •
4-bit I/O port
PA3 to PA0/
COM4 to COM1
Common output
(COM4 to COM1)
LPCR
Port B •
Dedicated 8-bit
input port
PB7 to PB4/
AN7 to AN4
A/D converter analog input
(AN7 to AN4)
AMR
PB3/AN3/IRQ1
A/D converter analog input
(AN3), external interrupt 1,
timer event input (TMIC)
AMR
PMRB
TMC
PB2/AN2
A/D converter analog input
AMR
PB1/AN1/(extU)
PB0/AN0/(extD)
A/D converter analog input
(LVD detect voltage external
input pin)
AMR
(LVDCR)
Port 5
Port 6
•
Rev. 1.00 Dec. 19, 2007 Page 164 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.2
Port 1
8.2.1
Overview
Port 1 is a 3-bit I/O port. Figure 8.1 shows its pin configuration.
P17/IRQ3/TMIF
P14/IRQ4/ADTRG
Port 1
P13/TMIG
Figure 8.1 Port 1 Pin Configuration
8.2.2
Register Configuration and Description
Table 8.2 shows the port 1 register configuration.
Table 8.2
Port 1 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 1
PDR1
R/W
—
H'FFD4
Port control register 1
PCR1
W
—
H'FFE4
Port pull-up control register 1
PUCR1
R/W
—
H'FFE0
Port mode register 1
PMR1
R/W
—
H'FFC8
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Rev. 1.00 Dec. 19, 2007 Page 165 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 1 (PDR1)
Bit
7
6
5
4
3
2
1
0
P17
—
—
P14
P13
—
—
—
Initial value
0
—
—
0
0
—
—
—
Read/Write
R/W
—
—
R/W
R/W
—
—
—
PDR1 is an 8-bit register that stores data for port 1 pins P17, P14, and P13. If port 1 is read while
PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If
port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
(2)
Port Control Register 1 (PCR1)
Bit
7
6
5
4
3
2
1
0
PCR17
—
—
PCR14
PCR13
—
—
—
Initial value
0
—
—
0
0
—
—
—
Read/Write
W
—
W
W
W
W
W
W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17, P14, and P13 functions
as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin,
while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid
only when the corresponding pin is designated in PMR1 as a general I/O pin.
PCR1 is a write-only register, which is always read as all 1s.
(3)
Port Pull-Up Control Register 1 (PUCR1)
Bit
7
6
5
4
3
2
1
0
PUCR17
—
—
—
—
—
Initial value
0
—
—
0
0
—
—
—
Read/Write
R/W
—
W
R/W
R/W
W
W
W
PUCR14 PUCR13
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17, P14, and P13 is on or off.
When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pullup for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Rev. 1.00 Dec. 19, 2007 Page 166 of 520
REJ09B0409-0100
Section 8 I/O Ports
(4)
Port Mode Register 1 (PMR1)
Bit
7
6
5
4
3
2
1
0
IRQ3
—
—
IRQ4
TMIG
—
—
—
Initial value
0
1
—
0
0
—
1
—
Read/Write
R/W
—
W
R/W
R/W
W
—
W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Bit 7—P17/IRQ3/TMIF Pin Function Switch (IRQ3)
This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF.
Bit 7
IRQ3
Description
0
Functions as P17 I/O pin
1
Functions as IRQ3/TMIF input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ3, TMIF. For details on TMIF
settings, see (3) Timer Control Register F (TCRF) in section 9.4.2, Register Descriptions.
Bit 6—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
Bit 5—Reserved
This bit is reserved; it can only be written with 0.
Bit 4—P14/IRQ4/ADTRG Pin Function Switch (IRQ4)
This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG.
Bit 4
IRQ4
Description
0
Functions as P14 I/O pin
1
Functions as IRQ4/ADTRG input pin
(initial value)
Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External
Trigger Input.
Rev. 1.00 Dec. 19, 2007 Page 167 of 520
REJ09B0409-0100
Section 8 I/O Ports
Bit 3—P13/TMIG Pin Function Switch (TMIG)
This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Bit 3
TMIG
Description
0
Functions as P13 I/O pin
1
Functions as TMIG input pin
(initial value)
Bits 2 and 0—Reserved
These bits are reserved; they can only be written with 0.
Bit 1—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
(5)
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bits related to timer G and the watchdog timer. For the functions
of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0).
Rev. 1.00 Dec. 19, 2007 Page 168 of 520
REJ09B0409-0100
Section 8 I/O Ports
Bit 2—Watchdog Timer Source Clock (WDCKS)
This bit selects the watchdog timer source clock.
Bit 2
WDCKS
Description
0
Selects clock based on timer mode register W (TMW) setting*
1
Selects φW/32
(Initial value)
Note: * See section 9.6, Watchdog Timer, for details.
Bit 1—TMIG Noise Canceller Select (NCS)
This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).
Bit 1
NCS
Description
0
No noise cancellation circuit
1
Noise cancellation circuit
(Initial value)
Rev. 1.00 Dec. 19, 2007 Page 169 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.2.3
Pin Functions
Table 8.3 shows the port 1 pin functions.
Table 8.3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/IRQ3/TMIF
The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR17 in PCR1.
IRQ3
PCR17
0
0
*
CKSL2 to CKSL0
Pin function
1
*
1
Not 0**
0**
P17 output pin IRQ3 input pin
P17 input pin
IRQ3/TMIF
input pin
Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1
to disable the IRQ3 interrupt.
P14/IRQ4
ADTRG
The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR14
in PCR1.
IRQ4
PCR14
0
0
*
1
*
TRGE
Pin function
1
0
1
P14 output pin IRQ4 input pin IRQ4/ADTRG
input pin
P14 input pin
Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in
IENR1 to disable the IRQ4 interrupt.
P13/TMIG
The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG
0
1
PCR13
0
1
*
Pin function
P13 input pin
P13 output pin
TMIG input pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 170 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.2.4
Pin States
Table 8.4 shows the port 1 pin states in each operating mode.
Table 8.4
Port 1 Pin States
Pins
Reset
Sleep
Subsleep Standby
HighRetains Retains
P17/IRQ3/TMIF
P14/IRQ4/ADTRG impedance previous previous
state
state
P13/TMIG
Note:
*
8.2.5
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1
bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for
that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
0
0
1
PUCR1n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7, 4, 3)
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 171 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.3
Port 3
8.3.1
Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8.2.
P3 7 /AEVL
P3 6 /AEVH
P3 5
P3 4
Port 3
P3 3
P3 2 /TMOFH
P3 1 /TMOFL
P3 0 /UD
Figure 8.2 Port 3 Pin Configuration
8.3.2
Register Configuration and Description
Table 8.5 shows the port 3 register configuration.
Table 8.5
Port 3 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 3
PDR3
R/W
H'00
H'FFD6
Port control register 3
PCR3
W
H'00
H'FFE6
Port pull-up control register 3
PUCR3
R/W
H'00
H'FFE1
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Port mode register 3
PMR3
R/W
—
H'FFCA
Rev. 1.00 Dec. 19, 2007 Page 172 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 3 (PDR3)
Bit
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P3 3
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
(2)
Port Control Register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR34
PCR3 3
PCR3 2
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 173 of 520
REJ09B0409-0100
Section 8 I/O Ports
(3)
Port Pull-Up Control Register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
(4)
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls whether the PMOS transistor internal to pin P35 is
on or off. For the functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and
port 4 (IRQ0).
Bit 5—Pin P35 PMOS Transistor Control (POF1)
This bit selects whether the PMOS transistor of the output buffer for pin P35 is on or off.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
Note: The pin is an NMOS open-drain output when this bit is set to 1 and P35 is an output.
Rev. 1.00 Dec. 19, 2007 Page 174 of 520
REJ09B0409-0100
Section 8 I/O Ports
(5)
Port Mode Register 3 (PMR3)
Bit
7
6
5
4
3
2
1
0
AEVL
AEVH



TMOFH
TMOFL
UD
Initial value
0
0



0
0
0
Read/Write
R/W
R/W
W
W
W
R/W
R/W
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Bit 7—P37/AEVL Pin Function Switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0
Functions as P37 I/O pin
1
Functions as AEVL input pin
(initial value)
Bit 6—P36/AEVH Pin Function Switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0
Functions as P36 I/O pin
1
Functions as AEVH input pin
(initial value)
Bits 5 to 3—Reserved
These bits are reserved; they can only be written with 0.
Bit 2—P32/TMOFH Pin Function Switch (TMOFH)
This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH.
Bit 2
TMOFH
Description
0
Functions as P32 I/O pin
1
Functions as TMOFH output pin
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 175 of 520
REJ09B0409-0100
Section 8 I/O Ports
Bit 1—P31/TMOFL Pin Function Switch (TMOFL)
This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL.
Bit 1
TMOFL
Description
0
Functions as P31 I/O pin
1
Functions as TMOFL output pin
(initial value)
Bit 0—P30/UD Pin Function Switch (UD)
This bit selects whether pin P30/UD is used as P30 or as UD.
Bit 0
UD
Description
0
Functions as P30 I/O pin
1
Functions as UD input pin
Rev. 1.00 Dec. 19, 2007 Page 176 of 520
REJ09B0409-0100
(initial value)
Section 8 I/O Ports
8.3.3
Pin Functions
Table 8.6 shows the port 3 pin functions.
Table 8.6
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P37/AEVL
The pin function depends on bit AEVL in PMR3 and bit PCR37 in PCR3.
AEVL
P36/AEVH
0
PCR37
0
1
*
Pin function
P37 input pin
P37 output pin
AEVL input pin
The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH
P35 to P33
1
0
1
PCR36
0
1
*
Pin function
P36 input pin
P36 output pin
AEVH input pin
The pin function depends on the corresponding bit in PCR3.
PCR3n
0
1
Pin function
P3n input pin
P3n output pin
(n = 5 to 3)
P32/TMOFH
The pin function depends on bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH
P31/TMOFL
0
PCR32
0
1
*
Pin function
P32 input pin
P32 output pin
TMOFH output pin
The pin function depends on bit TMOFL in PMR3 and bit PCR31 in PCR3.
TMOFL
P30/UD
1
0
1
PCR31
0
1
*
Pin function
P31 input pin
P31 output pin
THOFL output pin
The pin function depends on bit UD in PMR3 and bit PCR30 in PCR3.
UD
0
1
PCR30
0
1
*
Pin function
P30 input pin
P30 output pin
UD input pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 177 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.3.4
Pin States
Table 8.7 shows the port 3 pin states in each operating mode.
Table 8.7
Port 3 Pin States
Pins
Reset
Sleep
P37/AEVL
P36/AEVH
P35
P34
P33
P32/TMOFH
P31/TMOFL
P30/UD
Highimpedance
Retains Retains
previous previous
state
state
Note:
*
8.3.5
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3
bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR3n
0
0
1
PUCR3n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 178 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.4
Port 4
8.4.1
Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3.
P4 3 /IRQ0
P4 2 /TXD32
Port 4
P4 1 /RXD32
P4 0 /SCK32
Figure 8.3 Port 4 Pin Configuration
8.4.2
Register Configuration and Description
Table 8.8 shows the port 4 register configuration.
Table 8.8
Port 4 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'F8
H'FFD7
Port control register 4
PCR4
W
H'F8
H'FFE7
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Rev. 1.00 Dec. 19, 2007 Page 179 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P43
P4 2
P4 1
P4
0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
(2)
Port Control Register 4 (PCR4)
Bit
7
6
5
4
3
2
1
0





PCR42
PCR4 1
PCR4 0
Initial value
1
1
1
1
1
0
0
0
Read/Write





W
W
W
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 180 of 520
REJ09B0409-0100
Section 8 I/O Ports
(3)
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0


POF1


WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write


R/W


R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls switching of the P43/IRQ0 pin functions. For the
functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and port 3 (POF1).
Bit 0—P43/IRQ0 Pin Function Switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 0
IRQ0
Description
0
Functions as P43 input pin
1
Functions as IRQ0 input pin
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 181 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.4.3
Pin Functions
Table 8.9 shows the port 4 pin functions.
Table 8.9
Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P43/IRQ0
The pin function depends on bit IRQ0 in PMR2.
P42/TXD32
P41/RXD32
IRQ0
0
1
Pin function
P43 input pin
IRQ0 input pin
The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit
PCR42 in PCR4.
SPC32
0
1
TE
0
1
PCR42
0
1
*
Pin function
P42 input pin
P42 output pin
TXD32 output pin
The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4.
RE
P40/SCK32
0
1
PCR41
0
1
*
Pin function
P41 input pin
P41 output pin
RXD32 input pin
The pin function depends on bit CKE1 and CKE0 in SCR3, bit COM in SMR3,
and bit PCR40 in PCR4.
CKE1
0
CKE0
0
COM
PCR40
Pin function
1
0
0
1
1
1
*
*
*
*
P40 input pin P40 output pin SCK32 output
pin
*
SCK32 input
pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 182 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.4.4
Pin States
Table 8.10 shows the port 4 pin states in each operating mode.
Table 8.10 Port 4 Pin States
Pins
Reset
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK32
HighRetains Retains
impedance previous previous
state
state
8.5
Port 5
8.5.1
Overview
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Port 5 is an 8-bit I/O port, configured as shown in figure 8.4.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
Port 5
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Figure 8.4 Port 5 Pin Configuration
Rev. 1.00 Dec. 19, 2007 Page 183 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.5.2
Register Configuration and Description
Table 8.11 shows the port 5 register configuration.
Table 8.11 Port 5 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD8
Port control register 5
PCR5
W
H'00
H'FFE8
Port pull-up control register 5
PUCR5
R/W
H'00
H'FFE2
Port mode register 5
PMR5
R/W
H'00
H'FFCC
(1)
Port Data Register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
(2)
Port Control Register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
Rev. 1.00 Dec. 19, 2007 Page 184 of 520
REJ09B0409-0100
Section 8 I/O Ports
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
(3)
Port Pull-Up Control Register 5 (PUCR5)
Bit
7
6
5
4
3
2
0
1
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
(4)
Port Mode Register 5 (PMR5)
Bit
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n—P5n/WKPn/SEGn+1 Pin Function Switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as
P5n or WKPn.
Bit n
WKPn
Description
0
Functions as P5n I/O pin
1
Functions as WKPn input pin
(initial value)
(n = 7 to 0)
Note: For use as SEGn+1, see section 13.2.1, LCD Port Control Register (LPCR).
Rev. 1.00 Dec. 19, 2007 Page 185 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.5.3
Pin Functions
Table 8.12 shows the port 5 pin functions.
Table 8.12 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP7/
SEG8 to
The pin function depends on bits WKP7 to WKP0 in PMR5, bits PCR57 to PCR50
in PCR5, and bits SGS3 to SGS0 in LPCR.
P50/WKP0/
SEG1
P57 to P54
SGS3 to SGS0
(n = 7 to 4)
Other than 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001
WKPn
PCR5n
Pin function
0
0
1
P5n input pin P5n output pin
1
*
*
*
WKPn input
pin
SEGn+1
output pin
P53 to P50
SGS3 to SGS0
(m= 3 to 0)
Other than 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000
WKPm
PCR5m
Pin function
0010, 0011,
0100, 0101,
0110, 0111,
1000, 1001
0
0
1
0001, 0010,
0011, 0100,
0101, 0110,
0111, 1000
1
*
*
*
P5m input pin P5m output pin WKPm output
pin
SEGm+1
output pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 186 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.5.4
Pin States
Table 8.13 shows the port 5 pin states in each operating mode.
Table 8.13 Port 5 Pin States
Pins
Reset
P57/WKP7/
SEG8 to P50/
WKP0/SEG1
HighRetains Retains
impedance previous previous
state
state
Note:
*
8.5.5
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5
bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR5n
0
0
1
PUCR5n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 187 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.6
Port 6
8.6.1
Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
Port 6
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8.5 Port 6 Pin Configuration
8.6.2
Register Configuration and Description
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD9
Port control register 6
PCR6
W
H'00
H'FFE9
Port pull-up control register 6
PUCR6
R/W
H'00
H'FFE3
Rev. 1.00 Dec. 19, 2007 Page 188 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P6 3
P62
P61
P6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
(2)
Port Control Register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P67 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 189 of 520
REJ09B0409-0100
Section 8 I/O Ports
(3)
Port Pull-Up Control Register 6 (PUCR6)
Bit
7
6
5
4
3
2
0
1
PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
8.6.3
Pin Functions
Table 8.15 shows the port 6 pin functions.
Table 8.15 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG16 to
P60/SEG9
The pin function depends on bits PCR67 to PCR60 in PCR6 and bits SGS3 to
SGS0 in LPCR.
P67 to P64
SGS3 to SGS0
(n = 7 to 4)
Other than 0100, 0101, 0110, 0111,
1000, 1001, 1010, 1011
0100, 0101, 0110,
0111, 1000, 1001,
1010, 1011
PCR6n
0
1
*
Pin function
P6n input pin
P6n output pin
SEGn+9 output pin
P63 to P60
SGS3 to SGS0
(m = 3 to 0)
Other than 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010
0011, 0100, 0101,
0110, 0111, 1000,
1001, 1010
PCR6m
0
1
*
Pin function
P6m input pin
P6m output pin
SEGm+9 output pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 190 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.6.4
Pin States
Table 8.16 shows the port 6 pin states in each operating mode.
Table 8.16 Port 6 Pin States
Pin
Reset
P67/SEG16 to
P60/SEG9
HighRetains Retains
impedance previous previous
state
state
Note:
*
8.6.5
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n
0
0
1
PUCR6n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 191 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.7
Port 7
8.7.1
Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8.6.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
Port 7
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8.6 Port 7 Pin Configuration
8.7.2
Register Configuration and Description
Table 8.17 shows the port 7 register configuration.
Table 8.17 Port 7 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFDA
Port control register 7
PCR7
W
H'00
H'FFEA
Rev. 1.00 Dec. 19, 2007 Page 192 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
P7 7
P7 6
P75
P7 4
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
(2)
Port Control Register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 193 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.7.3
Pin Functions
Table 8.18 shows the port 7 pin functions.
Table 8.18 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG24 to
P70/SEG17
The pin function depends on bits PCR77 to PCR70 in PCR7 and bits SGS3 to
SGS0 in LPCR.
P77 to P74
(n = 7 to 4)
SGS3 to SGS0
Other than 0110, 0111, 1000, 1001,
1010, 1011, 1100, 1101
0110, 0111, 1000,
1001, 1010, 1011,
1100, 1101
PCR7n
0
1
*
Pin function
P7n input pin
P7n output pin
SEGn+17 output pin
P73 to P70
(m = 3 to 0)
SGS3 to SGS0
Other than 0101, 0110, 0111, 1000,
1001, 1010, 1011, 1100
0101, 0110, 0111,
1000, 1001, 1010,
1011, 1100
PCR7m
0
1
*
Pin function
P7m input pin
P7m output pin
SEGm+17 output pin
*: Don’t care
8.7.4
Pin States
Table 8.19 shows the port 7 pin states in each operating mode.
Table 8.19 Port 7 Pin States
Pins
Reset
Sleep
P77/SEG24 to
P70/SEG17
HighRetains Retains
impedance previous previous
state
state
Rev. 1.00 Dec. 19, 2007 Page 194 of 520
REJ09B0409-0100
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Section 8 I/O Ports
8.8
Port 8
8.8.1
Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8.7.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
Port 8
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Figure 8.7 Port 8 Pin Configuration
8.8.2
Register Configuration and Description
Table 8.20 shows the port 8 register configuration.
Table 8.20 Port 8 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 8
PDR8
R/W
H'00
H'FFDB
Port control register 8
PCR8
W
H'00
H'FFEB
Rev. 1.00 Dec. 19, 2007 Page 195 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 8 (PDR8)
Bit
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P8 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
(2)
Port Control Register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether the port 8 pins P87 to P80 functions as an input or
output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 196 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.8.3
Pin Functions
Table 8.21 shows the port 8 pin functions.
Table 8.21 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P87/SEG32
to
P80/SEG25
The pin function depends on bits PCR87 to PCR80 in PCR8 and bits SGS3 to SGS0
in LPCR.
P87 to P84
(n = 7 to 4)
SGS3 to SGS0
Other than 1000, 1001, 1010, 1011, 1100,
1101, 1110, 1111
1000, 1001, 1010,
1011, 1100, 1101,
1110, 1111
PCR8n
0
1
*
Pin function
P8n input pin
P8n output pin
SEGn+25 output pin
P83 to P80
(m = 3 to 0)
SGS3 to SGS0
Other than 0111, 1000, 1001, 1010, 1011,
1100, 1101, 1110
0111, 1000, 1001,
1010, 1011, 1100,
1101, 1110
PCR8m
0
1
*
Pin function
P8m input pin
P8m output pin
SEGm+25 output pin
*: Don’t care
8.8.4
Pin States
Table 8.22 shows the port 8 pin states in each operating mode.
Table 8.22 Port 8 Pin States
Pins
Reset
Sleep
Subsleep Standby
P87/SEG32 to
P80/SEG25
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Rev. 1.00 Dec. 19, 2007 Page 197 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.9
Port 9
8.9.1
Overview
Port 9 is a 6-bit output port, configured as shown in figure 8.8.
P95
P94
Port 9
P93/Vref
P92
P91/PWM2
P90/PWM1
Figure 8.8 Port 9 Pin Configuration
8.9.2
Register Configuration and Description
Table 8.23 shows the port 9 register configuration.
Table 8.23 Port 9 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 9
PDR9
R/W
H'FF
H'FFDC
Port mode register 9
PMR9
R/W
—
H'FFEC
Rev. 1.00 Dec. 19, 2007 Page 198 of 520
REJ09B0409-0100
Section 8 I/O Ports
(1)
Port Data Register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
—
—
P95
P9 4
P93
P92
P91
P9 0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P95 to P90.
Upon reset, PDR9 is initialized to H'FF.
(2)
Port Mode Register 9 (PMR9)
Bit
7
6
5
4
3
2
1
0






PWM2
PWM1
Initial value
1
1
1
1
0

0
0
Read/Write




R/W
W
R/W
R/W
PMR9 is an 8-bit read/write register controlling the selection of the P90 and P91 pin functions.
Bit 3—Reserved
This bit is reserved; it is readable/writable.
Bit 2—Reserved
This bit is reserved; it can only be written with 0.
Bits 1 and 0—P9n/PWM Pin Function Switches
These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1.
Bit n
PWMn+1
Description
0
Functions as P9n output pin
1
Functions as PWMn+1 output pin
(initial value)
(n = 0 or 1)
Rev. 1.00 Dec. 19, 2007 Page 199 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.9.3
Pin Functions
Table 8.24 shows the port 9 pin functions.
Table 8.24 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P93/Vref*
VREFSEL
0
1
Pin function
P93 output pin
Vref input pin
P91/PWMn+1 to
P9 /PWM
0
Note:
8.9.4
(n = 1 or 0)
PMR9n
0
1
Pin function
P9n output pin
PWMn+1 output pin
n+1
*
The Vref pin is the input pin for the LVD’s external reference voltage.
Pin States
Table 8.25 shows the port 9 pin states in each operating mode.
Table 8.25 Port 9 Pin States
Pins
Reset
Sleep
Subsleep Standby
P95 to P92
P9n/PWMn+1 to
P9n/PWMn+1
HighRetains Retains
impedance previous previous
state
state
Highimpedance
Watch
Subactive Active
Retains Functional Functional
previous
state
(n = 1 or 0)
Rev. 1.00 Dec. 19, 2007 Page 200 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.10
Port A
8.10.1
Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.9.
PA3/COM4
PA2/COM3
Port A
PA1/COM2
PA0/COM1
Figure 8.9 Port A Pin Configuration
8.10.2
Register Configuration and Description
Table 8.26 shows the port A register configuration.
Table 8.26 Port A Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register A
PDRA
R/W
H'F0
H'FFDD
Port control register A
PCRA
W
H'F0
H'FFED
(1)
Port Data Register A (PDRA)
Bit
7
6
5
4
3
2
1




PA 3
PA 2
PA 1
0
PA 0
Initial value
1
1
1
1
0
0
0
0
Read/Write




R/W
R/W
R/W
R/W
PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while PCRA
bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is
read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
Rev. 1.00 Dec. 19, 2007 Page 201 of 520
REJ09B0409-0100
Section 8 I/O Ports
(2)
Port Control Register A (PCRA)
Bit
7
6
5
4
3
2
1




PCRA 3
PCRA 2
PCRA 1
0
PCRA 0
Initial value
1
1
1
1
0
0
0
0
Read/Write




W
W
W
W
PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which is always read as all 1s.
Rev. 1.00 Dec. 19, 2007 Page 202 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.10.3
Pin Functions
Table 8.27 shows the port A pin functions.
Table 8.27 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PA2/COM3
PA1/COM2
PA0/COM1
0000
0000
Not 0000
PCRA3
0
1
*
Pin function
PA3 input pin
PA3 output pin
COM4 output pin
The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
0000
Not 0000
PCRA2
0
1
*
Pin function
PA2 input pin
PA2 output pin
COM3 output pin
The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
0000
Not 0000
PCRA1
0
1
*
Pin function
PA1 input pin
PA1 output pin
COM2 output pin
The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
Not 0000
PCRA0
0
1
*
Pin function
PA0 input pin
PA0 output pin
COM1 output pin
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 203 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.10.4
Pin States
Table 8.28 shows the port A pin states in each operating mode.
Table 8.28 Port A Pin States
Pins
Reset
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
HighRetains Retains
impedance previous previous
state
state
8.11
Port B
8.11.1
Overview
Sleep
Subsleep Standby
Watch
HighRetains Functional Functional
impedance previous
state
Port B is an 8-bit input-only port, configured as shown in figure 8.10.
PB7/AN7
PB6/AN6
PB5/AN5
Port B
PB4/AN4
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
Figure 8.10 Port B Pin Configuration
Rev. 1.00 Dec. 19, 2007 Page 204 of 520
REJ09B0409-0100
Subactive Active
Section 8 I/O Ports
8.11.2
Register Configuration and Description
Table 8.29 shows the port B register configuration.
Table 8.29 Port B Register
Name
Abbr.
R/W
Initial Value
Address
Port data register B
PDRB
R
—
H'FFDE
Port mode register B
PMRB
R/W
H'F7
H'FFEE
(1)
Port Data Register B (PDRB)
Bit
Read/Write
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB 0
R
R
R
R
R
R
R
R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
(2)
Port Mode Register B (PMRB)
Bit
7
6
5
4
3
2
1
0




IRQ1



Initial value
1
1
1
1
0
1
1
1
Read/Write




R/W



PMRB is an 8-bit read/write register controlling the selection of the PB3 pin function. Upon reset,
PMRB is initialized to H'F7.
Bits 7 to 4 and 2 to 0—Reserved
Bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 205 of 520
REJ09B0409-0100
Section 8 I/O Ports
Bit 3—PB3/AN3/IRQ1 Pin Function Switch (IRQ1)
These bits select whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1/TMIC.
Bit 3
IRQ1
Description
0
Functions as PB3/AN3 input pin
1
Functions as IRQ1/TMIC input pin
(initial value)
Note: Rising or falling edge sensing can be selected for the IRQ1/TMIC pin.
For TMIC pin setting information, see the Timer Mode Register C (TMC) description in section
9.3.2, Register Descriptions.
Rev. 1.00 Dec. 19, 2007 Page 206 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.11.3
Pin Functions
Table 8.30 shows the port B pin functions.
Table 8.30 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/AN7
The pin function depends on bits CH3 to CH0 in AMR.
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/
TMIC
CH3 to CH0
Not 1011
1011
Pin function
PB7 input pin
AN7 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1010
1010
Pin function
PB6 input pin
AN6 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1001
1001
Pin function
PB5 input pin
AN5 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1000
1000
Pin function
PB4 input pin
AN4 input pin
The pin function depends on bits CH3 to CH0 in AMR and bit IRQ1 in PMRB and
bits TMC2 to TMC0 in TMC.
IRQ1
CH3 to CH0
0
Not 0111
*
0111
*
TMC2 to TMC0
Pin function
1
PB3 input pin
Not 111
111
AN3 input pin IRQ1 input pin
TMIC input
pin
Note: When this pin is used as the TMIC input pin, clear IEN1 to 0 in IENR1 to
disable the IRQ1 interrupt.
PB2/AN2
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 0110
0110
Pin function
PB2 input pin
AN2 input pin
Rev. 1.00 Dec. 19, 2007 Page 207 of 520
REJ09B0409-0100
Section 8 I/O Ports
Pin
Pin Functions and Selection Method
PB1/AN1/extU
Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in
LVDCR as shown below.
VINTUSEL
PB0/AN0/extD
0
1
CH3 to CH0
Not B'0101
B'0101
*
Pin function
PB1 input pin
AN1 input pin
extU input pin
Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in
LVDCR as shown below.
VINTDSEL
0
1
CH3 to CH0
Not B'0100
B'0100
*
Pin function
PB0 input pin
AN0 input pin
extD input pin
*: Don’t care
8.12
Input/Output Data Inversion Function
8.12.1
Overview
With input pin RXD32 and output pin TXD32, the data can be handled in inverted form.
SCINV2
RXD32
P41/RXD32
SCINV3
P42/TXD32
TXD32
Figure 8.11 Input/Output Data Inversion Function
Rev. 1.00 Dec. 19, 2007 Page 208 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.12.2
Register Configuration and Descriptions
Table 8.31 shows the registers used by the input/output data inversion function.
Table 8.31 Register Configuration
Name
Abbr.
R/W
Address
Serial port control register
SPCR
R/W
H'FF91
(1)
Serial Port Control Register (SPCR)
Bit
7
6
5
4


SPC32

Initial value
1
1
0

0
Read/Write


R/W
W
R/W
3
1
0


0


R/W
W
W
2
SCINV3 SCINV2
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Functions as TXD32 output pin*
(initial value)
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; it can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 209 of 520
REJ09B0409-0100
Section 8 I/O Ports
Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; they can only be written with 0.
8.12.3
Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated.
Rev. 1.00 Dec. 19, 2007 Page 210 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.13
Application Note
8.13.1
The Management of the Un-Use Terminal
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
 Pull it up to VCC with an on-chip pull-up MOS.
 Pull it up to VCC with an external resistor of approximately 100 kΩ.
 Pull it down to VSS with an external resistor of approximately 100 kΩ.
 For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways:
 Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS.
 Set the output of the unused pin to high and pull it up to VCC with an external resistor of
approximately 100 kΩ.
 Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
Rev. 1.00 Dec. 19, 2007 Page 211 of 520
REJ09B0409-0100
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 212 of 520
REJ09B0409-0100
Section 9 Timers
Section 9 Timers
9.1
Overview
This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event
counter. The functions of these timers are outlined in table 9.1.
Table 9.1
Name
Timer A
Timer C
Timer F
Timer G
Watchdog
timer
Timer Functions
Functions
Internal Clock
φ/8 to φ/8192
(8 choices)
Event
Input Pin
Waveform
Output Pin
—
—
•
8-bit timer
•
Interval function
•
Time base
φw/128 (choice of 4
overflow periods)
•
8-bit timer
—
Interval function
φ/4 to φ/8192, φW/4
(7 choices)
TMIC
•
•
Event counting function
•
Up-count/down-count
selectable
•
16-bit timer
Event counting function
φ/4 to φ/32, φw/4
(4 choices)
TMIF
•
TMOFL
TMOFH
•
Also usable as two
independent 8-bit timers
•
Output compare output
function
•
8-bit timer
—
Input capture function
φ/2 to φ/64, φW/4
(4 choices)
TMIG
•
•
Interval function
•
Reset signal generated
when 8-bit counter
overflows
Remarks
Up-count/
down-count
controllable by
software or
hardware
Counter
clearing option
Built-in capture
input signal
noise canceler
φ/64 to φ/8192
φW/32
On-chip oscillator
—
—
Rev. 1.00 Dec. 19, 2007 Page 213 of 520
REJ09B0409-0100
Section 9 Timers
Name
Functions
Asynchro- •
nous event •
counter
9.2
9.2.1
16-bit counter
Also usable as two
independent 8-bit
counters
•
Counts events
asynchronous to φ and φw
•
Can count asynchronous
events (rising/falling/both
edges) independ-ently of
the MCU's internal clock
Internal Clock
φ/2 to φ/8
(3 choices)
Event
Input Pin
Waveform
Output Pin
AEVL
AEVH
IRQAEC
—
Remarks
Timer A
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768 kHz crystal resonator is connected as the subclock.
(1)
Features
Features of timer A are given below.
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32,
φ/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal resonator is connected as the subclock).
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 214 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.1 shows a block diagram of timer A.
φW
1/4
TMA
PSW
Internal data bus
φW /4
φW/128
φ
+256*
+128*
+64*
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
+8*
TCA
PSS
IRRTA
[Legend]
TMA:
TCA:
IRRTA:
PSW:
PSS:
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Note: * Can be selected only when the prescaler W output (φW /128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A
Rev. 1.00 Dec. 19, 2007 Page 215 of 520
REJ09B0409-0100
Section 9 Timers
(3)
Register Configuration
Table 9.2 shows the register configuration of timer A.
Table 9.2
Timer A Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register A
TMA
R/W
—
H'FFB0
Timer counter A
TCA
R
H'00
H'FFB1
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.2.2
(1)
Register Descriptions
Timer Mode Register A (TMA)
Bit
7
6
5
4
3
2
1
0




TMA3
TMA2
TMA1
TMA0
Initial value



1
0
0
0
0
Read/Write
W
W
W

R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, and input clock.
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved; only 0 can be written to these bits.
Bit 4—Reserved
Bit 4 is reserved; it is always read as 1, and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 216 of 520
REJ09B0409-0100
Section 9 Timers
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3
Bit 2
TMA2
Bit 1
TMA1
0
0
0
1
1
0
1
1
0
0
1
1
0
Bit 0
TMA0
Prescaler and Divider Ratio
or Overflow Period
Function
0
PSS, φ/8192
1
PSS, φ/4096
0
PSS, φ/2048
1
PSS, φ/512
0
PSS, φ/256
1
PSS, φ/128
0
PSS, φ/32
1
PSS, φ/8
0
PSW, 1 s
Clock time
1
PSW, 0.5 s
base
(initial value) Interval timer
0
PSW, 0.25 s
(when using
1
PSW, 0.03125 s
32.768 kHz)
0
PSW and TCA are reset
1
1
0
1
Rev. 1.00 Dec. 19, 2007 Page 217 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Timer Counter A (TCA)
Bit
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
(3)
Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0


Initial value:
1
1
1
1
1
1
1
1
Read/Write:


R/W
R/W
R/W
R/W
R/W
R/W
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0—Timer A Module Standby Mode Control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP
Description
0
Timer A is set to module standby mode
1
Timer A module standby mode is cleared
Rev. 1.00 Dec. 19, 2007 Page 218 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
9.2.3
(1)
Timer Operation
Interval Timer Operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see section 3.3, Interrupts.
(2) Real-Time Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
Rev. 1.00 Dec. 19, 2007 Page 219 of 520
REJ09B0409-0100
Section 9 Timers
9.2.4
Timer A Operation States
Table 9.3 summarizes the timer A operation states.
Table 9.3
Timer A Operation States
Watch
Subactive
Subsleep
Standby
Module
Standby
Functions Functions Halted
Halted
Halted
Halted
Halted
Functions Functions Functions Functions Functions Halted
Halted
Functions Retained
Retained
Operation Mode
Reset Active
TCA Interval
Reset
Clock time base Reset
TMA
Reset
Sleep
Retained
Functions Retained
Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in
the count cycle.
9.2.5
Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
Rev. 1.00 Dec. 19, 2007 Page 220 of 520
REJ09B0409-0100
Section 9 Timers
9.3
9.3.1
Timer C
Overview
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
(1)
Features
Features of timer C are given below.
• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode or subsleep mode operation is possible when φW/4 is selected as the internal
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 221 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.2 shows a block diagram of timer C.
Internal data bus
TMC
UD
TCC
φ
PSS
TMIC
TLC
φW /4
IRRTC
[Legend]
TMC: Timer mode register C
TCC: Timer counter C
Timer load register C
TLC:
IRRTC: Timer C overflow interrupt request flag
Prescaler S
PSS:
Figure 9.2 Block Diagram of Timer C
(3)
Pin Configuration
Table 9.4 shows the timer C pin configuration.
Table 9.4
Pin Configuration
Name
Abbr.
I/O
Function
Timer C event input
TMIC
Input
Input pin for event input to TCC
Timer C up/down select
UD
Input
Timer C up/down-count selection
Rev. 1.00 Dec. 19, 2007 Page 222 of 520
REJ09B0409-0100
Section 9 Timers
(4)
Register Configuration
Table 9.5 shows the register configuration of timer C.
Table 9.5
Timer C Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register C
TMC
R/W
H'18
H'FFB4
Timer counter C
TCC
R
H'00
H'FFB5
Timer load register C
TLC
W
H'00
H'FFB5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.3.2
(1)
Register Descriptions
Timer Mode Register C (TMC)
Bit
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5


TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W


R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and
performing up/down-counter control.
Upon reset, TMC is initialized to H'18.
Bit 7—Auto-Reload Function Select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0
Interval timer function selected
1
Auto-reload function selected
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 223 of 520
REJ09B0409-0100
Section 9 Timers
Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6
Bit 5
TMC5
Description
0
0
TCC is an up-counter
0
1
TCC is a down-counter
1
*
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
(initial value)
*: Don't care
Bits 4 and 3—Reserved
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
Bit 1
TMC1
Bit 0
TMC0
Description
0
0
0
Internal clock: φ/8192
0
0
1
Internal clock: φ/2048
0
1
0
Internal clock: φ/512
0
1
1
Internal clock: φ/64
1
0
0
Internal clock: φ/16
1
0
1
Internal clock: φ/4
1
1
0
Internal clock: φW/4
1
1
1
External event (TMIC): rising or falling edge*
Note:
*
(initial value)
The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt
Control Registers, for details. IRQ1 in port mode register B (PMRB) must be set to 1
before setting 111 in bits TMC2 to TMC0.
Rev. 1.00 Dec. 19, 2007 Page 224 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Timer Counter C (TCC)
Bit
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal
clock or external event input. The clock source for input to this counter is selected by bits TMC2
to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
(3)
Timer Load Register C (TLC)
Bit
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up/down from that value. When TCC overflows or underflows during operation in
auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period can
be set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
Rev. 1.00 Dec. 19, 2007 Page 225 of 520
REJ09B0409-0100
Section 9 Timers
(4)
Clock Stop Register 1 (CKSTPR1)
Bit:
7
6


5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:


R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1—Timer C Module Standby Mode Control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP
Description
0
Timer C is set to module standby mode
1
Timer C module standby mode is cleared
9.3.3
(1)
(initial value)
Timer Operation
Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
Rev. 1.00 Dec. 19, 2007 Page 226 of 520
REJ09B0409-0100
Section 9 Timers
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: For details on interrupts, see section 3.3, Interrupts.
(2)
Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
(3)
Event Counter Operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C (TMC) to all 1s (111). TCC counts up/down at the rising/falling edge of an
external event signal input at pin TMIC.
When timer C is used to count external event input, bit IRQ1 in PMRB should be set to 1 and bit
IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests.
(4)
TCC Up/Down Control by Hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC
is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter
when high.
When using UD pin input, set bit UD in PMR3 to 1.
Rev. 1.00 Dec. 19, 2007 Page 227 of 520
REJ09B0409-0100
Section 9 Timers
9.3.4
Timer C Operation States
Table 9.6 summarizes the timer C operation states.
Table 9.6
Timer C Operation States
TCC
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Auto reload Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Functions Retained
Functions Retained
Retained
Note:
Reset
*
Retained
Standby
Module
Standby
Active
TMC
Watch
Subsleep
Reset
Interval
Sleep
Subactive
Operation Mode
Retained
When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode or subsleep mode, either
select φw/4 as the internal clock or select an external clock. The counter will not operate
on any other internal clock. If φw/4 is selected as the internal clock for the counter when
φw/8 has been selected as subclock φSUB, the lower 2 bits of the counter operate on the
same cycle, and the operation of the least significant bit is unrelated to the operation of
the counter.
Rev. 1.00 Dec. 19, 2007 Page 228 of 520
REJ09B0409-0100
Section 9 Timers
9.4
9.4.1
Timer F
Overview
Timer F is a 16-bit timer with a built-in output compare function. As well as counting external
events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH
and timer FL).
(1)
Features
Features of timer F are given below.
• Choice of four internal clock sources (φ/32, φ/16, φ/4, φw/4) or an external clock (can be used
as an external event counter)
• TMOFH/TMOFL pin toggle output provided using a single compare match signal (toggle
output initial value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer*
Timer FL
8-Bit Timer/Event Counter
Internal clock
Choice of 4 (φ/32, φ/16, φ/4, φw/4)
Event input
—
TMIF pin
Toggle output
One compare match signal, output to
TMOFH pin(initial value settable)
One compare match signal, output to
TMOFL pin (initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources
One compare match
One overflow
Note:
*
When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
Rev. 1.00 Dec. 19, 2007 Page 229 of 520
REJ09B0409-0100
Section 9 Timers
• Operation in watch mode, subactive mode, and subsleep mode
When φw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 230 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.3 shows a block diagram of timer F.
φ
PSS
IRRTFL
TCRF
φW/4
TMIF
TCFL
Toggle
circuit
Comparator
Internal data bus
TMOFL
OCRFL
TCFH
TMOFH
Toggle
circuit
Comparator
Match
OCRFH
TCSRF
IRRTFH
[Legend]
TCRF:
Timer control register F
TCSRF: Timer control/status register F
TCFH:
8-bit timer counter FH
TCFL:
8-bit timer counter FL
OCRFH: Output compare register FH
OCRFL: Output compare register FL
IRRTFH: Timer FH interrupt request flag
IRRTFL: Timer FL interrupt request flag
PSS:
Prescaler S
Figure 9.3 Block Diagram of Timer F
Rev. 1.00 Dec. 19, 2007 Page 231 of 520
REJ09B0409-0100
Section 9 Timers
(3)
Pin Configuration
Table 9.7 shows the timer F pin configuration.
Table 9.7
Pin Configuration
Name
Abbr.
I/O
Function
Timer F event input
TMIF
Input
Event input pin for input to TCFL
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
(4)
Register Configuration
Table 9.8 shows the register configuration of timer F.
Table 9.8
Timer F Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control register F
TCRF
W
H'00
H'FFB6
Timer control/status register F
TCSRF
R/W
H'00
H'FFB7
8-bit timer counter FH
TCFH
R/W
H'00
H'FFB8
8-bit timer counter FL
TCFL
R/W
H'00
H'FFB9
Output compare register FH
OCRFH
R/W
H'FF
H'FFBA
Output compare register FL
OCRFL
R/W
H'FF
H'FFBB
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Rev. 1.00 Dec. 19, 2007 Page 232 of 520
REJ09B0409-0100
Section 9 Timers
9.4.2
(1)
Register Descriptions
16-bit Timer Counter (TCF)
8-bit Timer Counter (TCFH)
8-bit Timer Counter (TCFL)
TCF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH
TCFL
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.4.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
Rev. 1.00 Dec. 19, 2007 Page 233 of 520
REJ09B0409-0100
Section 9 Timers
b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH, and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL)
in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
(2) 16-bit Output Compare Register (OCRF)
8-bit Output Compare Register (OCRFH)
8-bit Output Compare Register (OCRFL)
OCRF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH
OCRFL
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are
constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At
the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
Rev. 1.00 Dec. 19, 2007 Page 234 of 520
REJ09B0409-0100
Section 9 Timers
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH, and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
(3)
Timer Control Register F (TCRF)
Bit:
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources or external event input, and sets the output
level of the TMOFH and TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7—Toggle Output Level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0
Low level
1
High level
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 235 of 520
REJ09B0409-0100
Section 9 Timers
Bits 6 to 4—Clock Select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL
overflow.
Bit 6
CKSH2
Bit 5
CKSH1
Bit 4
CKSH0
Description
0
0
0
16-bit mode, counting on TCFL overflow signal
0
0
1
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
(initial value)
Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
Description
0
Low level
1
High level
Rev. 1.00 Dec. 19, 2007 Page 236 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external
event input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0
0
0
0
0
0
1
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
Note:
(4)
*
Description
Counting on external event (TMIF) rising/falling edge*
(initial value)
External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control
Registers.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register
1 (PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to
change the TMIF pin function.
Timer Control/Status Register F (TCSRF)
Bit:
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
R/W
R/W
R/W
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Rev. 1.00 Dec. 19, 2007 Page 237 of 520
REJ09B0409-0100
Section 9 Timers
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when TCFH overflows from H’FF to H’00
(initial value)
Bit 6—Compare Match Flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting condition:
Set when the TCFH value matches the OCRFH value
(initial value)
Bit 5—Timer Overflow Interrupt Enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
Rev. 1.00 Dec. 19, 2007 Page 238 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bit 4—Counter Clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
(initial value)
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3—Timer Overflow Flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCFL overflows from H’FF to H’00
(initial value)
Bit 2—Compare Match Flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting condition:
Set when the TCFL value matches the OCRFL value
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 239 of 520
REJ09B0409-0100
Section 9 Timers
Bit 1—Timer Overflow Interrupt Enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
(initial value)
Bit 0—Counter Clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
(5)
(initial value)
Clock Stop Register 1 (CKSTPR1)
7
6


Initial value:
1
1
1
1
1
1
1
1
Read/Write:


R/W
R/W
R/W
R/W
R/W
R/W
Bit:
5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2—Timer F Module Standby Mode Control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
Rev. 1.00 Dec. 19, 2007 Page 240 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
9.4.3
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
In 8-bit mode, there are no restrictions on the order of access.
(1)
Write Access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write
access to the lower byte results in transfer of the data in TEMP to the upper register byte, and
direct transfer of the lower-byte write data to the lower register byte.
Rev. 1.00 Dec. 19, 2007 Page 241 of 520
REJ09B0409-0100
Section 9 Timers
Figure 9.4 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(
)
TCFL
(
)
Write to lower byte
CPU
(H'55)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9.4 Write Access to TCF (CPU → TCF)
Rev. 1.00 Dec. 19, 2007 Page 242 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Read Access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.5 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Read lower byte
CPU
(H'FF)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Note: * H'AB00 if counter has been updated once.
Figure 9.5 Read Access to TCF (TCF → CPU)
Rev. 1.00 Dec. 19, 2007 Page 243 of 520
REJ09B0409-0100
Section 9 Timers
9.4.4
Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
(1)
Timer F Operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit
timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The
external event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
The timer F operating clock can be selected from three internal clocks output by prescaler S or
an external clock by means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set
to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU,
and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared.
TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the
same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1,
TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in
TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is
sent to the CPU.
Rev. 1.00 Dec. 19, 2007 Page 244 of 520
REJ09B0409-0100
Section 9 Timers
(2)
TCF Increment Timing
TCF is incremented by clock input (internal clock or external event input).
a. Internal clock operation
Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock
sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw).
b. External event operation
External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either
the rising or falling edge of external event input. External event edge selection is set by IEG3
in the interrupt controller’s IEGR register. An external event pulse width of at least 2 system
clocks (φ) is necessary. Shorter pulses will not be counted correctly.
(3)
TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9.6 shows the output timing.
φ
TMIF
(when IEG3 = 1)
Count input
clock
TCF
OCRF
N
N+1
N
N
N+1
N
Compare match
signal
TMOFH TMOFL
Figure 9.6 TMOFH/TMOFL Output Timing
Rev. 1.00 Dec. 19, 2007 Page 245 of 520
REJ09B0409-0100
Section 9 Timers
(4)
TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
(5)
Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
(6)
Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
(7)
Timer F Operation Modes
Timer F operation modes are shown in table 9.9.
Table 9.9
Timer F Operation Modes
Subactive
Subsleep
Functions Functions Functions/
Halted*
Functions/
Halted*
Reset
Functions Held
Held
Reset
Functions Held
Held
Reset
Functions Held
Held
Operation Mode
Reset
Active
TCF
Reset
OCRF
TCRF
TCSRF
Note:
*
Sleep
Watch
Standby
Module
Standby
Functions/
Halted*
Halted
Halted
Functions
Held
Held
Held
Functions
Held
Held
Held
Functions
Held
Held
Held
When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φw/4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
Rev. 1.00 Dec. 19, 2007 Page 246 of 520
REJ09B0409-0100
Section 9 Timers
9.4.5
Application Notes
The following types of contention and operation can occur when timer F is used.
(1)
16-bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
(2)
8-bit Timer Mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
Rev. 1.00 Dec. 19, 2007 Page 247 of 520
REJ09B0409-0100
Section 9 Timers
b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match
signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
(3)
Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer
Overflow Flags H, L (OVFH, OVFL) and Compare Match Flags H, L (CMFH, CMFL)
When φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of φw signals. Those signals are outputted with 2 cycles
width of φw (figure 9.7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure
9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term
of validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
Rev. 1.00 Dec. 19, 2007 Page 248 of 520
REJ09B0409-0100
Section 9 Timers
The term of validity of “Interrupt factor generation signal”
= 1 cycle of φw + waiting time for completion of executing instruction
+ interrupt time synchronized with φ = 1/φw + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
4. Operate interrupt permission (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
Rev. 1.00 Dec. 19, 2007 Page 249 of 520
REJ09B0409-0100
Section 9 Timers
Interrupt request
flag clear
Interrupt request
flag clear
(2)
Program process
Interrupt
Interrupt
Normal
φW
Interrupt factor
generation signal
(Internal signal,
nega-active)
Overflow signal,
Compare match signal
(Internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
(1)
Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid
(4)
Timer Counter (TCF) Read/Write
When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal
clock except for φw/4 before read/write.
In subactive mode, even φw/4 is selected as the internal clock, normal read/write TCF is possible.
Rev. 1.00 Dec. 19, 2007 Page 250 of 520
REJ09B0409-0100
Section 9 Timers
9.5
9.5.1
Timer G
Overview
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
(1)
Features
Features of timer G are given below.
• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal
rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
signal.
• Watch mode, subactive mode, or subsleep mode operation is possible when φw/4 is selected as
the internal clock.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 251 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.8 shows a block diagram of timer G.
φ
PSS
Level
detector
φW/4
ICRGF
TMIG
Noise
canceler
Edge
detector
NCS
Internal data bus
TMG
TCG
ICRGR
IRRTG
[Legend]
TMG:
TCG:
ICRGF:
ICRGR:
IRRTG:
NCS:
PSS:
Timer mode register G
Timer counter G
Input capture register GF
Input capture register GR
Timer G interrupt request flag
Noise canceler select
Prescaler S
Figure 9.8 Block Diagram of Timer G
(3)
Pin Configuration
Table 9.10 shows the timer G pin configuration.
Table 9.10 Pin Configuration
Name
Abbr.
I/O
Function
Input capture input
TMIG
Input
Input capture input pin
Rev. 1.00 Dec. 19, 2007 Page 252 of 520
REJ09B0409-0100
Section 9 Timers
(4)
Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register G
TMG
R/W
H'00
H'FFBC
Timer counter G
TCG
—
H'00
—
Input capture register GF
ICRGF
R
H'00
H'FFBD
Input capture register GR
ICRGR
R
H'00
H'FFBE
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.5.2
(1)
Register Descriptions
Timer Counter G (TCG)
7
6
5
4
3
2
1
0
TCG7
TCG6
TCG5
TCG4
TCG3
TCG2
TCG1
TCG0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:








Bit:
TCG is an 8-bit up-counter, which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
Rev. 1.00 Dec. 19, 2007 Page 253 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Input Capture Register GF (ICRGF)
7
6
5
4
3
2
1
0
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
Bit:
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
(3)
Input Capture Register GR (ICRGR)
7
6
5
4
3
2
1
0
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
Bit:
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
Rev. 1.00 Dec. 19, 2007 Page 254 of 520
REJ09B0409-0100
Section 9 Timers
(4)
Timer Mode Register G (TMG)
Bit:
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
0
1
Description
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
(initial value)
Setting condition:
Set when input capture input signal is high level and TCG overflows from H'FF to H'00
Rev. 1.00 Dec. 19, 2007 Page 255 of 520
REJ09B0409-0100
Section 9 Timers
Bit 6—Timer Overflow Flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It
cannot be set by software.
Bit 6
OVFL
0
1
Description
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
(initial value)
Setting condition:
Set when TCG overflows from H'FF to H'00 while input capture input signal is high
level or during interval operation
Bit 5—Timer Overflow Interrupt Enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0
TCG overflow interrupt request is disabled
1
TCG overflow interrupt request is enabled
(initial value)
Bit 4—Input Capture Interrupt Edge Select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0
Interrupt generated on rising edge of input capture input signal
1
Interrupt generated on falling edge of input capture input signal
Rev. 1.00 Dec. 19, 2007 Page 256 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
Bit 2
CCLR0
Description
0
0
TCG clearing is disabled
0
1
TCG cleared by falling edge of input capture input signal
1
0
TCG cleared by rising edge of input capture input signal
1
1
TCG cleared by both edges of input capture input signal
(initial value)
Bits 1 and 0—Clock Select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
Internal clock: counting on φ/64
0
1
Internal clock: counting on φ/32
1
0
Internal clock: counting on φ/2
1
1
Internal clock: counting on φw/4
(5)
(initial value)
Clock Stop Register 1 (CKSTPR1)
Bit:
7
6


5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:


R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Rev. 1.00 Dec. 19, 2007 Page 257 of 520
REJ09B0409-0100
Section 9 Timers
Bit 3—Timer G Module Standby Mode Control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP
Description
0
Timer G is set to module standby mode
1
Timer G module standby mode is cleared
9.5.3
(initial value)
Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR2.
Figure 9.9 shows a block diagram of the noise canceler.
Sampling
clock
C
Input capture
input signal
C
D
Q
D
Latch
Q
Latch
C
D
C
Q
Latch
D
C
Q
Latch
D
Q
Latch
Match
detector
Noise
canceler
output
∆t
Sampling clock
∆t: Set by CKS1 and CKS0
Figure 9.9 Noise Canceler Block Diagram
The noise canceler consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceler output
is initialized when the falling edge of the input capture input signal has been sampled five times.
Rev. 1.00 Dec. 19, 2007 Page 258 of 520
REJ09B0409-0100
Section 9 Timers
Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φSUB is
necessary to ensure that input capture operations are performed properly
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 9.10 shows an example of noise canceler timing.
In this example, high-level input of less than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 9.10 Noise Canceler Timing (Example)
Rev. 1.00 Dec. 19, 2007 Page 259 of 520
REJ09B0409-0100
Section 9 Timers
9.5.4
Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
(1)
Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input
capture timer*.
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts counting on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in
TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by
IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this
time, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3,
Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input
capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input capture
signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these bits are set,
IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt
request to the CPU. For details of the interrupt, see section 3.3, Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise
Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
Rev. 1.00 Dec. 19, 2007 Page 260 of 520
REJ09B0409-0100
Section 9 Timers
b. Interval timer operation
When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer.
Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be
selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments
on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to
1. If the OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit in
IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see
section 3.3, Interrupts.
(2)
Count Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch
clock (φw).
(3)
Input Capture Input Timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and falling
edges.
Figure 9.11 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)
Rev. 1.00 Dec. 19, 2007 Page 261 of 520
REJ09B0409-0100
Section 9 Timers
b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles from
the input capture input signal edge.
Figure 9.12 shows the timing in this case.
Input capture
input signal
Sampling clock
Noise canceler
output
Input capture
signal R
Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function)
(4)
Timing of Input Capture by Input Capture Input
Figure 9.13 shows the timing of input capture by input capture input
Input capture
signal
TCG
N-1
Input capture
register
N+1
N
H'XX
N
Figure 9.13 Timing of Input Capture by Input Capture Input
Rev. 1.00 Dec. 19, 2007 Page 262 of 520
REJ09B0409-0100
Section 9 Timers
(5)
TCG Clear Timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input
signal.
Figure 9.14 shows the timing for clearing by both edges.
Input capture
input signal
Input capture
signal F
Input capture
signal R
TCG
N
H'00
N
H'00
Figure 9.14 TCG Clear Timing
Rev. 1.00 Dec. 19, 2007 Page 263 of 520
REJ09B0409-0100
Section 9 Timers
(6)
Timer G Operation Modes
Timer G operation modes are shown in table 9.12.
Table 9.12 Timer G Operation Modes
Operation
Mode
TCG
Reset Active
Sleep
Watch
Subactive Subsleep Standby
Module
Standby
Input
Reset
capture
Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
Interval Reset
Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
ICRGF
Reset
Functions* Functions* Functions/ Functions/ Functions/ Retained
halted*
halted*
halted*
Retained
ICRGR
Reset
Functions* Functions* Functions/ Functions/ Functions/ Retained
halted*
halted*
halted*
Retained
TMG
Reset
Functions
Retained
Note:
*
Retained
Retained
Functions
Retained
Retained
When φw/4 is selected as the TCG internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ(s). When φw/4 is selected as the TCG internal clock in watch mode, TCG and the
noise canceler operate on the φw/4 internal clock without regard to the φSUB subclock
(φw/8, φw/4, φw/2). Note that when another internal clock is selected, TCG and the
noise canceler do not operate, and input of the input capture input signal does not result
in input capture.
To operate the timer G in subactive mode or subsleep mode, select φw/4 as the TCG
internal clock and φw/2 as the subclock φSUB. Note that when other internal clock is
selected, or when φw/8 or φw/4 is selected as the subclock φSUB, TCG and the noise
canceler do not operate.
Rev. 1.00 Dec. 19, 2007 Page 264 of 520
REJ09B0409-0100
Section 9 Timers
9.5.5
(1)
Application Notes
Internal Clock Switching and TCG Operation
Depending on the timing, TCG may be incremented by a switch between different internal clock
sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (φ) or subclock (φw). For this
reason, in a case like No. 3 in table 9.13 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
Table 9.13 Internal Clock Switching and TCG Operation
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
1
Goes from low level to low level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
Write to CKS1 and CKS0
2
Goes from low level to high level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Rev. 1.00 Dec. 19, 2007 Page 265 of 520
REJ09B0409-0100
Section 9 Timers
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
3
Goes from high level to low level
Clock before
switching
Clock after
switching
*
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
4
Goes from high level to high level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Note:
(2)
*
The switchover is seen as a falling edge, and TCG is incremented.
Notes on Port Mode Register Modification
The following points should be noted when a port mode register is modified to switch the input
capture function or the input capture input noise canceler function.
• Switching input capture input pin function
Note that when the pin function is switched by modifying TMIG in port mode register 1
(PMR1), which performs input capture input pin control, an edge will be regarded as having
been input at the pin even though no valid edge has actually been input. Input capture input
signal input edges, and the conditions for their occurrence, are summarized in table 9.14.
Rev. 1.00 Dec. 19, 2007 Page 266 of 520
REJ09B0409-0100
Section 9 Timers
Table 9.14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Generation of rising edge
Conditions
When TMIG is modified from 0 to 1 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
Generation of falling edge
When TMIG is modified from 1 to 0 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is low, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 1 to 0 after the signal is sampled five times by
the noise canceler
Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input
signal is low.
• Switching input capture input noise canceler function
When performing noise canceler function switching by modifying NCS in port mode register 2
(PMR2), which controls the input capture input noise canceler, TMIG should first be cleared to
0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as
having been input at the pin even though no valid edge has actually been input. Input capture
input signal input edges, and the conditions for their occurrence, are summarized in table 9.15.
Table 9.15 Input Capture Input Signal Input Edges Due to Noise Canceler Function
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When the TMIG pin is modified from 0 to 1 while TMIG is 1, then NCS
is modified from 0 to 1 before the signal is sampled five times by the
noise canceler
Generation of falling edge
When the TMIG pin is modified from 1 to 0 while TMIG is 1, then NCS
is modified from 1 to 0 before the signal is sampled five times by the
noise canceler
Rev. 1.00 Dec. 19, 2007 Page 267 of 520
REJ09B0409-0100
Section 9 Timers
When the pin function is switched and an edge is generated in the input capture input signal, if this
edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt
request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use.
Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the
port mode register, then, after the port mode register operation has been performed, wait for the
time required to confirm the input capture input signal as an input capture signal (at least two
system clocks when the noise canceler is not used; at least five sampling clocks when the noise
canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing
interrupt request flag setting when the pin function is switched: by controlling the pin level so that
the conditions shown in tables 9.14 and 9.15 are not satisfied, or by setting the opposite of the
generated edge in the IIEGS bit in TMG.
Set I bit in CCR to 1
Manipulate port mode register
*TMIG confirmation time
Clear interrupt request flag to 0
Clear I bit in CCR to 0
Disable interrupts. (Interrupts can also be disabled by
manipulating the interrupt enable bit in interrupt enable
register 2.)
After manipulating the port mode register, wait for the
TMIG confirmation time* (at least two system clocks when
the noise canceler is not used; at least five sampling
clocks when the noise canceler is used), then clear the
interrupt enable flag to 0.
Enable interrupts
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure
Rev. 1.00 Dec. 19, 2007 Page 268 of 520
REJ09B0409-0100
Section 9 Timers
9.5.6
Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal
as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1.
Figure 9.16 shows an example of the operation in this case.
Input capture
input signal
H'FF
Input capture
register GF
Input capture
register GR
H'00
TCG
Counter cleared
Figure 9.16 Timer G Application Example
Rev. 1.00 Dec. 19, 2007 Page 269 of 520
REJ09B0409-0100
Section 9 Timers
9.6
9.6.1
Watchdog Timer
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
(1)
Features
Features of the watchdog timer are given below.
• Ten internal clocks (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or
watchdog on-chip oscillator) are available for selection for use by the counter.
• A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times the selected clock (from approximately 4 ms to 1,000 ms when φ = 2.00 MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. See section 5.9, Module Standby Mode, for details.
Rev. 1.00 Dec. 19, 2007 Page 270 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.17 shows a block diagram of the watchdog timer.
Watchdog
on-chip
oscillator
φ
Internal data bus
TMW
TCSRW
PSS
TCW
φW/32
Interrupt/reset
controller
[Legend]
TCSRW:
TCW:
TMW:
PSS:
Internal reset signal or
interrupt request signal
Timer control/status register W
Timer counter W
Timer mode register W
Prescaler S
Figure 9.17 Block Diagram of Watchdog Timer
(3)
Register Configuration
Table 9.16 shows the register configuration of the watchdog timer.
Table 9.16 Watchdog Timer Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control/status register W
TCSRW
R/W
H'AA
H'FFB2
Timer counter W
TCW
R/W
H'00
H'FFB3
Timer mode register W
TMW
R/W
H'FF
H'FFF8
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Rev. 1.00 Dec. 19, 2007 Page 271 of 520
REJ09B0409-0100
Section 9 Timers
9.6.2
(1)
Register Descriptions
Timer Control/Status Register W (TCSRW)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
1
0
1
0
1
1
1
0
R
(R/W)*
R
(R/W)*
R
(R/W)*
R
(R/W)*
Note: * Write is enabled only under certain conditions, which are given in the descriptions
of the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7—Bit 6 Write Disable (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0
Bit 6 is write-enabled
1
Bit 6 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 6—Timer Counter W Write Enable (TCWE)
Bit 6 controls the writing of data to TCW.
Bit 6
TCWE
Description
0
Data cannot be written to TCW
1
Data can be written to TCW
Rev. 1.00 Dec. 19, 2007 Page 272 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bit 5—Bit 4 Write Disable (B4WI)
Bit 5 controls the writing of data to bit 4 in TCSRW.
Bit 5
B4WI
Description
0
Bit 4 is write-enabled
1
Bit 4 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 4—Timer Control/Status Register W Write Enable (TCSRWE)
Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Bit 4
TCSRWE
Description
0
Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
(initial value)
Bit 3—Bit 2 Write Inhibit (B2WI)
Bit 3 controls the writing of data to bit 2 in TCSRW.
Bit 3
B2WI
Description
0
Bit 2 is write-enabled
1
Bit 2 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Rev. 1.00 Dec. 19, 2007 Page 273 of 520
REJ09B0409-0100
Section 9 Timers
Bit 2—Watchdog Timer On (WDON)
Bit 2 enables watchdog timer operation.
Bit 2
WDON
0
Description
Watchdog timer operation is disabled
Clearing condition:
When TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note
that a reset sets WDON to 1.
1
Watchdog timer operation is enabled
(initial value)
Setting condition:
Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and 1 is
written to WDON
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
Description
0
Bit 0 is write-enabled
1
Bit 0 is write-protected
This bit is always read as 1. Data written to this bit is not stored.
Rev. 1.00 Dec. 19, 2007 Page 274 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bit 0—Watchdog Timer Reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
Description
0
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
1
Setting condition:
When TCW overflows and an internal reset signal is generated
(2)
Timer Counter W (TCW)
Bit
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCW is an 8-bit read/write up-counter that counts up by the internal clock. The clock source is
selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS
is 1. TCW is always read or written to by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
Rev. 1.00 Dec. 19, 2007 Page 275 of 520
REJ09B0409-0100
Section 9 Timers
(3)
Timer Mode Register (TMW)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
CKS3
CKS2
CKS1
CKS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
The input clock is selected using combinations of CKS3 to CKS0.
Bits 7 to 4—Reserved
These bits are always read as 1.
Bits 3 to 0—Clock Select (CKS3 to CKS0)
These bits are used to select the clock input to TCW from among 10 internal options. Clock source
selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to
0. If WDCKS is set to 1 the φw/32 clock source is selected, regardless of the settings of the bits in
this register.
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
1
0
0
0
Internal clock: φ/64 count
1
Internal clock: φ/128 count
0
Internal clock: φ/256 count
1
Internal clock: φ/512 count
0
Internal clock: φ/1024 count
1
Internal clock: φ/2048 count
1
0
Internal clock: φ/4096 count
1
Internal clock: φ/8192 count
X
X
Watchdog on-chip oscillator
1
1
0
X
0
Note: X: Don't care
Rev. 1.00 Dec. 19, 2007 Page 276 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
(4)
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP


4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W


R/W
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP
Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
(initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
Rev. 1.00 Dec. 19, 2007 Page 277 of 520
REJ09B0409-0100
Section 9 Timers
(5)
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2.
Only the bit relating to the watchdog timer is described here. For details of the other bits, see
section 8, I/O Ports.
Bit 2—Watchdog Timer Source Clock Select (WDCKS)
This bit selects the watchdog timer source clock.
WDCKS
Description
0
Selects clock based on timer mode register W (TMW) setting
1
φw/32 selected
9.6.3
(initial value)
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input
clock is selected by the WDCKS in port mode register 2 (PMR2). If WDCKS is cleared to 0 the
clock selection is specified by the setting of timer mode register W (TMW), and if WDCKS is set
to 1 the φw/32 clock source is selected. When TCSRWE = 1 in TCSRW, if 0 is written in B2WI
and 1 is simultaneously written in WDON, TCW starts counting up. (Write access to TCSRW is
required twice to turn on the watchdog timer. However, WDON is set to 1 after a reset is
cancelled, TCW starts to be incremented even without gaining write access to TCSRW.) When the
TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and
an internal reset signal is generated one base clock (φ or φSUB) cycle later. The internal reset signal
is output for 512 clock cycles of the φOSC clock. It is possible to write to TCW, causing TCW to
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.18 shows an example of watchdog timer operations.
Rev. 1.00 Dec. 19, 2007 Page 278 of 520
REJ09B0409-0100
Section 9 Timers
Example: φ = 2 MHz and the desired overflow period is 30 ms.
2 • 106
• 30 • 10−3 = 7.3
8192
The value set in TCW should therefore be 256 − 8 = 248 (H'F8).
TCW overflow
H'FF
H'F8
TCW count
value
H'00
Start
H'F8 is written
in TCW
H'F8 is written in TCW
Reset
Internal reset
signal
512 φOSC clock cycles
Figure 9.18 Typical Watchdog Timer Operations (Example)
9.6.4
Watchdog Timer Operation States
Table 9.17 summarizes the watchdog timer operation states for the H8/38524 Group.
Table 9.17 Watchdog Timer Operation States
Operation
Mode
Reset
Active
Sleep
Watch
TCW
Reset
Functions
Functions
Functions/ Functions/ Functions/ Functions/
1
1
1
2
Halted*
Halted*
Halted*
Halted*
TCSRW
Reset
Functions
Functions
Functions/ Functions/ Functions/ Functions/ Retained
1
1
1
2
Retained* Halted*
Retained* Retained*
TMW
Reset
Functions
Functions
Functions/ Functions/ Functions/ Functions/ Retained
1
1
1
2
Retained* Halted*
Retained* Retained*
Subactive Subsleep Standby
Module
Standby
Halted
Notes: 1. Operates when φw/32 or the on-chip oscillator is selected as the internal clock.
2. Operates only when the on-chip oscillator is selected.
Rev. 1.00 Dec. 19, 2007 Page 279 of 520
REJ09B0409-0100
Section 9 Timers
9.7
9.7.1
Asynchronous Event Counter (AEC)
Overview
The asynchronous event counter is incremented by external event clock or internal clock input.
(1)
Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of base clocks
φ and φSUB.
The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Can be used as single-channel independent 16-bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output
(IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, independent interrupt function use is
possible.
• When an event counter PWM is used, event clock input enabling/disabling can be performed
automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and
ECL clock sources. φ/2, φ/4, or φ/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 280 of 520
REJ09B0409-0100
Section 9 Timers
(2)
Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
IRREC
φ
ECCR
PSS
ECCSR
φ/2
φ/4, φ/8
OVH
OVL
AEVL
CK
ECL
(8 bits)
CK
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
IECPWM
IRQAEC
To CPU interrupt
(IRREC2)
Internal data bus
AEVH
ECH
(8 bits)
ECPWCRL
ECPWCRH
PWM waveform generator
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
ECPWDRL
ECPWDRH
AEGSR
[Legend]
ECPWCRH:
ECPWDRH:
AEGSR:
ECCSR:
ECH:
ECL:
Event counter PWM compare register H
Event counter PWM data register H
Input pin edge select register
Event counter control/status register
Event counter H
Event counter L
ECPWCRL:
ECPWDRL:
ECCR:
Event counter PWM compare register L
Event counter PWM data register L
Event counter control register
Figure 9.19 Block Diagram of Asynchronous Event Counter
Rev. 1.00 Dec. 19, 2007 Page 281 of 520
REJ09B0409-0100
Section 9 Timers
(3)
Pin Configuration
Table 9.18 shows the asynchronous event counter pin configuration.
Table 9.18 Pin Configuration
Name
Abbr.
I/O
Function
Asynchronous event input H
AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
Input
Input pin for interrupt enabling event input
Event input enable interrupt input IRQAEC
(4)
Register Configuration
Table 9.19 shows the register configuration of the asynchronous event counter.
Table 9.19 Asynchronous Event Counter Registers
Name
Abbr.
R/W
Initial Value
Address
Event counter PWM compare register H ECPWCRH
R/W
H'FF
H'FF8C
Event counter PWM compare register L ECPWCRL
R/W
H'FF
H'FF8D
Event counter PWM data register H
W
H'00
H'FF8E
ECPWDRH
Event counter PWM data register L
ECPWDRL
W
H'00
H'FF8F
Input pin edge select register
AEGSR
R/W
H'00
H'FF92
Event counter control register
ECCR
R/W
H'00
H'FF94
Event counter control/status register
ECCSR
R/W
H'00
H'FF95
Event counter H
ECH
R
H'00
H'FF96
Event counter L
ECL
R
H'00
H'FF97
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Rev. 1.00 Dec. 19, 2007 Page 282 of 520
REJ09B0409-0100
Section 9 Timers
9.7.2
(1)
Register Configurations
Event Counter PWM Compare Register H (ECPWCRH)
Bit
7
6
5
4
3
2
1
0
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRH.
ECPWCRH is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
(2)
Event Counter PWM Compare Register L (ECPWCRL)
Bit
7
6
5
4
3
2
1
0
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRL
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRL.
ECPWCRL is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
Rev. 1.00 Dec. 19, 2007 Page 283 of 520
REJ09B0409-0100
Section 9 Timers
(3)
Event Counter PWM Data Register H (ECPWDRH)
Bit
7
6
5
4
3
2
1
0
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRH.
ECPWDRH is an 8-bit write-only register that controls event counter PWM waveform generator
data.
(4)
Event Counter PWM Data Register L (ECPWDRL)
Bit
7
6
5
4
3
2
1
0
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRL
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRL.
ECPWDRL is an 8-bit write-only register that controls event counter PWM waveform generator
data.
Rev. 1.00 Dec. 19, 2007 Page 284 of 520
REJ09B0409-0100
Section 9 Timers
(5)
Input Pin Edge Selection Register (AEGSR)
Bit
7
6
5
4
3
2
0
1
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AEGSR is an 8-bit read/write register that selects rising, falling, or both edge sensing for the
AEVH, AEVL, and IRQAEC pins.
Bits 7 and 6—AEC Edge Select H
Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin.
Bit 7
AHEGS1
Bit 6
AHEGS0
Description
0
0
Falling edge on AEVH pin is sensed
1
Rising edge on AEVH pin is sensed
0
Both edges on AEVH pin are sensed
1
Use prohibited
1
(initial value)
Bits 5 and 4—AEC Edge Select L
Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin.
Bit 5
ALEGS1
Bit 4
ALEGS0
Description
0
0
Falling edge on AEVL pin is sensed
1
Rising edge on AEVL pin is sensed
0
Both edges on AEVL pin are sensed
1
Use prohibited
1
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 285 of 520
REJ09B0409-0100
Section 9 Timers
Bits 3 and 2—IRQAEC Edge Select
Bits 3 and 2 select rising, falling, or both edge sensing for the IRQAEC pin.
Bit 3
AIEGS1
0
1
Bit 2
AIEGS0
Description
0
Falling edge on IRQAEC pin is sensed
1
Rising edge on IRQAEC pin is sensed
0
Both edges on IRQAEC pin are sensed
1
Use prohibited
(initial value)
Bit 1—Event Counter PWM Enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
Description
0
AEC PWM halted, IRQAEC selected
1
AEC PWM operation enabled, IRQAEC deselected
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Rev. 1.00 Dec. 19, 2007 Page 286 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
(6)
Event Counter Control Register (ECCR)
Bit
7
6
5
4
ACKH1
ACKH0
ACKL1
ACKL0
3
2
PWCK2 PWCK1
1
0
PWCK0

Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1
Bit 6
ACKH0
Description
0
0
AEVH pin input
1
φ/2
0
φ/4
1
φ/8
1
(initial value)
Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5
ACKL1
0
1
Bit 4
ACKL0
Description
0
AEVL pin input
1
φ/2
0
φ/4
1
φ/8
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 287 of 520
REJ09B0409-0100
Section 9 Timers
Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3
PWCK2
Bit 2
PWCK1
Bit 1
PWCK0
Description
0
0
0
φ/2
1
φ/4
0
φ/8
1
φ/16
0
φ/32
1
φ/64
1
*
1
(initial value)
*: Don’t care
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
(7)
Event Counter Control/Status Register (ECCSR)
7
6
5
4
3
2
1
0
OVH
OVL

CH2
CUEH
CUEL
CRCH
CRCL
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Rev. 1.00 Dec. 19, 2007 Page 288 of 520
REJ09B0409-0100
Section 9 Timers
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading
it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as
a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
(initial value)
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by reading
it when set to 1, then writing 0.
Bit 6
OVL
Description
0
ECL has not overflowed
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
1
ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00
(initial value)
Bit 5—Reserved
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Rev. 1.00 Dec. 19, 2007 Page 289 of 520
REJ09B0409-0100
Section 9 Timers
Bit 4—Channel Select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2
Description
0
ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1
ECH and ECL are used as two independent 8-bit event counter channels
Bit 3—Count-up Enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0
ECH event clock input is disabled
ECH value is held
1
ECH event clock input is enabled
(initial value)
Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0
ECL event clock input is disabled
ECL value is held
1
ECL event clock input is enabled
Rev. 1.00 Dec. 19, 2007 Page 290 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
ECH is reset
1
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
ECL is reset
1
ECL reset is cleared and count-up function is enabled
(8)
(initial value)
Event Counter H (ECH)
Bit
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The
external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software,
and is also initialized to H'00 upon reset.
Rev. 1.00 Dec. 19, 2007 Page 291 of 520
REJ09B0409-0100
Section 9 Timers
(9)
Event Counter L (ECL)
Bit
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input
clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
(10) Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
3
2
1
0
LVDCKSTP


Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W


R/W
R/W
R/W
R/W
R/W
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
Rev. 1.00 Dec. 19, 2007 Page 292 of 520
REJ09B0409-0100
(initial value)
Section 9 Timers
9.7.3
(1)
Operation
16-bit Event Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.20 shows an example of the software processing when ECH and ECL are used as
a 16-bit event counter.
Start
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing). When the next clock is input after the count
value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the
OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting
up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 1.00 Dec. 19, 2007 Page 293 of 520
REJ09B0409-0100
Section 9 Timers
(2)
8-bit Event Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.21 shows an example of the software processing when ECH and ECL are used as
8-bit event counters.
Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1,
AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.21. When the next clock is input after the ECH count value reaches
H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00,
and counting up is restarted. Similarly, when the next clock is input after the ECL count value
reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to
H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the
IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 1.00 Dec. 19, 2007 Page 294 of 520
REJ09B0409-0100
Section 9 Timers
(3)
IRQAEC Operation
When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC
is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and
ECL do not count. ECH and ECL count operations can therefore be controlled from outside by
controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1
and AIAGS0 in AEGSR.
Note: The control of switching between the system clock oscillator and the on-chip oscillator
during resets should be performed by setting the IRQAEC input level. Refer to section 4,
Clock Pulse Generators, for details.
(4)
Event Counter PWM Operation
When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Rev. 1.00 Dec. 19, 2007 Page 295 of 520
REJ09B0409-0100
Section 9 Timers
Figure 9.22 and table 9.20 show examples of event counter PWM operation.
toff = T × (Ndr +1)
Ton :
Toff :
Tcm :
T:
Ndr :
Clock input enabled time
Clock input disabled time
One conversion period
ECPWM input clock cycle
Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
Ncm : Value of ECPWCRH and ECPWCRL
ton
tcm = T × (Ncm +1)
Figure 9.22 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition,
do not set ECPWME in AEGSR to 1.
Table 9.20 Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fφ = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11,
ECPWDR value (Ndr) = H'16E3
Clock Source Clock Source ECPWCR
Selection
Cycle (T)*
Value (Ncm)
ECPWDR
Value (Ndr)
toff = T ×
(Ndr + 1)
tcm = T ×
(Ncm + 1)
ton = tcm – toff
φ/2
1 µs
5.86 ms
31.25 ms
25.39 ms
φ/4
2 µs
H'16E3
D'5859
11.72 ms
62.5 ms
50.78 ms
φ/8
4 µs
23.44 ms
125.0 ms
101.56 ms
φ/16
8 µs
46.88 ms
250.0 ms
203.12 ms
φ/32
16 µs
93.76 ms
500.0 ms
406.24 ms
32 µs
187.52 ms 1000.0 ms 812.48 ms
φ/64
Note:
*
H'7A11
D'31249
toff minimum width
Rev. 1.00 Dec. 19, 2007 Page 296 of 520
REJ09B0409-0100
Section 9 Timers
(5)
Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Figure 9.23 shows an example of the operation of this function.
Input event
IRQAEC or
IECPWM
Edge generated by clock return
Actually counted
clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 9.23 Example of Clock Control Operation
Rev. 1.00 Dec. 19, 2007 Page 297 of 520
REJ09B0409-0100
Section 9 Timers
9.7.4
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9.21.
Table 9.21 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset Active
Sleep
Watch
Subactive
Subsleep
Standby
Functions
Functions
Retained*
Module
Standby
Reset
Functions Functions Retained*
ECCR
Reset
1
Functions Functions Retained*
Functions
Functions
1
Retained*
ECCSR
Reset
Functions Functions Retained*
Functions
Functions
Retained*
ECH
Reset
Functions Functions Functions* * Functions* Functions* Functions* * Halted
ECL
Reset
1 2
2
2
1 2
Functions Functions Functions* * Functions* Functions* Functions* * Halted
IRQAEC
Reset
Functions Functions Retained*
Event
counter
PWM
Reset
Functions Functions Retained
AEGSR
1
1
1 2
3
2
1
Retained
Retained
1
2
Retained
1 2
Functions
Functions
Retained*
Retained
Retained
Retained
3
Retained*
4
Retained
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Operates when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
Rev. 1.00 Dec. 19, 2007 Page 298 of 520
REJ09B0409-0100
Section 9 Timers
9.7.5
Application Notes
1. When reading the values in ECH and ECL, the correct value will not be returned if the event
counter increments during the read operation. Therefore, if the counter is being used in the 8bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the
counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least half the OSC clock cycle duration.
The duty cycle is immaterial.
Maximum AEVH/AEVL Pin Input
Clock Frequency
Mode
Active (high-speed), sleep (high-speed)
16 MHz
Active (medium-speed), sleep (medium-speed) (φ/16)
2 • fOSC
(φ/32)
fOSC
(φ/64)
1/2 • fOSC
fOSC = 1 MHz to 4 MHz
(φ/128)
1/4 • fOSC
Watch, subactive, subsleep, standby
(φw/2)
1000 kHz
(φw/4)
500 kHz
(φw/8)
250 kHz
φw = 32.768 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
Rev. 1.00 Dec. 19, 2007 Page 299 of 520
REJ09B0409-0100
Section 9 Timers
Rev. 1.00 Dec. 19, 2007 Page 300 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Section 10 Serial Communication Interface
10.1
Overview
This LSI is provided with one serial communication interface, SCI3.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode.
10.1.1
Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
 Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA).
There is a choice of 16 data transfer formats.
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD32 pin level directly when a
framing error occurs
 Synchronous mode
Serial data communication is synchronized with a clock. In this mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length
8 bits
Receive error detection
Overrun errors
Rev. 1.00 Dec. 19, 2007 Page 301 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
Note: The system clock generator must be used when carrying out this function.
Rev. 1.00 Dec. 19, 2007 Page 302 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of SCI3.
SCK32
External
clock
Baud rate generator
BRC
Internal clock (φ/64, φ/16, φW/2, φ)
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD32
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD32
Interrupt request
(TEI, TXI, RXI, ERI)
[Legend]
Receive shift register
RSR:
RDR: Receive data register
Transmit shift register
TSR:
Transmit data register
TDR:
SMR: Serial mode register
SCR3: Serial control register 3
Serial status register
SSR:
Bit rate register
BRR:
Bit rate counter
BRC:
SPCR: Serial port control register
Figure 10.1 SCI3 Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 303 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.1.3
Pin Configuration
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Name
Abbr.
I/O
Function
SCI3 clock
SCK32
I/O
SCI3 clock input/output
SCI3 receive data input
RXD32
Input
SCI3 receive data input
SCI3 transmit data output
TXD32
Output
SCI3 transmit data output
10.1.4
Register Configuration
Table 10.2 shows the SCI3 register configuration.
Table 10.2 Registers
Name
Abbr.
R/W
Initial Value
Address
Serial mode register
SMR
R/W
H'00
H'FFA8
Bit rate register
BRR
R/W
H'FF
H'FFA9
Serial control register 3
SCR3
R/W
H'00
H'FFAA
Transmit data register
TDR
R/W
H'FF
H'FFAB
Serial status register
SSR
R/W
H'84
H'FFAC
Receive data register
RDR
R
H'00
H'FFAD
Transmit shift register
TSR
Protected —
—
Receive shift register
RSR
Protected —
—
Bit rate counter
BRC
Protected —
—
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Serial port control register
SPCR
R/W
—
H'FF91
Rev. 1.00 Dec. 19, 2007 Page 304 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2
Register Descriptions
10.2.1
Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write








RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
10.2.2
Receive Data Register (RDR)
Bit
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Rev. 1.00 Dec. 19, 2007 Page 305 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2.3
Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write








TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD32 pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not
performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register
(SSR)).
TSR cannot be read or written directly by the CPU.
10.2.4
Transmit Data Register (TDR)
Bit
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Rev. 1.00 Dec. 19, 2007 Page 306 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2.5
Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Bit 7—Communication Mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0
Asynchronous mode
1
Synchronous mode
(initial value)
Bit 6—Character Length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
0
1
Description
2
8-bit data/5-bit data*
7-bit data*1/5-bit data*2
(initial value)
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
Rev. 1.00 Dec. 19, 2007 Page 307 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bit 5—Parity Enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
0
1
Description
Parity bit addition and checking disabled*2
Parity bit addition and checking enabled*1/*2
(initial value)
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10.11.
Bit 4—Parity Mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
0
1
Description
Even parity*
Odd parity*2
1
(initial value)
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
Rev. 1.00 Dec. 19, 2007 Page 308 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bit 3—Stop Bit Length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
Description
1 stop bit*1
2 stop bits*2
0
1
(initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2— 5-Bit Communication (MP)
When this bit is set to 1, the 5-bit communication format is enabled. When writing 1 to this bit,
always write 1 to bit 5 (RE) at the same time.
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see section
10.2.8, Bit rate register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
φ clock
0
1
φ w/2 clock* /φ w clock*
1
0
φ/16 clock
1
1
φ/64 clock
(initial value)
1
2
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3
can be operated when CPU clock is φw/2 only.
Rev. 1.00 Dec. 19, 2007 Page 309 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2.6
Serial Control Register 3 (SCR3)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Bit 7—Transmit Interrupt Enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
Rev. 1.00 Dec. 19, 2007 Page 310 of 520
REJ09B0409-0100
(initial value)
Section 10 Serial Communication Interface
Bit 6—Receive Interrupt Enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive errors: overrun, framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial
value)
Bit 5—Transmit Enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
0
1
Description
Transmit operation disabled*1 (TXD32 pin is I/O port)
Transmit operation enabled*2 (TXD32 pin is transmit data pin)
(initial value)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDRE in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC32 in SPCR, to decide the transmission format before
setting bit TE to 1.
Rev. 1.00 Dec. 19, 2007 Page 311 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bit 4—Receive Enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
Receive operation disabled*1 (RXD32 pin is I/O port)
Receive operation enabled*2 (RXD32 pin is receive data pin)
0
1
(initial value)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3— Reserved (MPIE)
Bit 3 is reserved.
Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled*
1
Note:
*
(initial value)
TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Rev. 1.00 Dec. 19, 2007 Page 312 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK32 pin.
The combination of CKE1 and CKE0 determines whether the SCK32 pin functions as an I/O port, a
clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.9 in section 10.3.1, Overview.
Description
Bit 1
CKE1
Bit 0
CKE0
Communication Mode
Clock Source
SCK32 Pin Function
0
0
Asynchronous
Internal clock
I/O port*1
Synchronous
Internal clock
Serial clock output*1
Clock output*2
0
1
1
1
0
1
Asynchronous
Internal clock
Synchronous
Reserved
Asynchronous
External clock
Clock input*3
Synchronous
External clock
Serial clock input
Asynchronous
Reserved
Synchronous
Reserved
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
Rev. 1.00 Dec. 19, 2007 Page 313 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2.7
Serial Status Register (SSR)
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE,
RDRF, OER, PER, and FER.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7—Transmit Data Register Empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
Rev. 1.00 Dec. 19, 2007 Page 314 of 520
REJ09B0409-0100
(initial value)
Section 10 Serial Communication Interface
Bit 6—Receive Data Register Full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0
There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
(initial value)
1
There is receive data in RDR
Setting condition:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
Bit 5—Overrun Error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
0
1
Description
1
Reception in progress or completed*
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
An overrun error has occurred during reception*2
Setting condition:
When reception is completed with RDRF set to 1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
Rev. 1.00 Dec. 19, 2007 Page 315 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bit 4—Framing Error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
0
Reception in progress or completed*1
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
Setting condition:
When the stop bit at the end of the receive data is checked for a value
2
of 1 at the end of reception, and the stop bit is 0*
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.
Bit 3—Parity Error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
0
1
Description
1
(initial value)
Reception in progress or completed*
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception*2
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register (SMR)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
Rev. 1.00 Dec. 19, 2007 Page 316 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Bit 2—Transmit End (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmission ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1—Reserved (MPBR)
Bit 1 is read-only and reserved. It cannot be written to.
Bit 0— Reserved (MPBT)
Bit 0 is reserved. The write value should always be 0.
10.2.8
Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Rev. 1.00 Dec. 19, 2007 Page 317 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
φ
19.2 kHz
16.4 kHz
Bit Rate
(bit/s)
N
Error
(%) n
n
110
—
—
—
150
—
—
200
—
250
0
300
600
1 MHz
N
Error
(%) n
—
—
—
—
0
3
0
—
—
0
2
0
2
9
1
2.5
—
—
—
3
1
—
—
—
0
1
0
0
103 0.16
—
—
—
0
0
0
0
51
1200
—
—
—
0
2400
—
—
—
1.2288 MHz
N
Error
(%) n
2
17
2
12
2 MHz
N
Error
(%) n
N
Error
(%)
–1.36 2
21
–0.83 3
8
–1.36
0.16
3
0
2
25
0.16
–2.34 3
2
0
3
4
–2.34
–2.34 0
153 –0.26 2
15
–2.34
3
1
0
2
12
0.16
0.16
3
0
0
0
103 0.16
25
0.16
2
1
0
0
51
0.16
0
12
0.16
2
0
0
0
25
0.16
3
4800
—
—
—
—
—
—
0
7
0
0
12
0.16
9600
—
—
—
—
—
—
0
3
0
—
—
—
19200
—
—
—
—
—
—
0
1
0
—
—
—
31250
—
—
—
0
0
0
—
—
—
0
1
0
38400
—
—
—
—
—
—
0
0
0
—
—
—
Rev. 1.00 Dec. 19, 2007 Page 318 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
φ
8 MHz
5 MHz
Bit Rate
(bit/s)
N
Error
(%) n
n
110
3
21
0.88
150
3
15
200
3
250
3
300
10 MHz
N
Error
(%) n
N
Error
(%)
3
35
–1.36 3
43
0.88
1.73
3
25
0.16
3
32
–1.36
11
1.73
3
19
–2.34 3
23
1.73
9
–2.34 3
15
–2.34 3
19
–2.34
3
7
1.73
3
12
0.16
3
15
1.73
600
3
3
1.73
2
25
0.16
3
7
1.73
1200
3
1
1.73
2
12
0.16
3
3
1.73
2400
3
0
1.73
0
103 0.16
3
1
1.73
4800
2
1
1.73
0
51
0.16
3
0
1.73
9600
2
0
173
0
25
0.16
2
1
1.73
19200
0
7
1.73
0
12
0.16
2
0
1.73
31250
0
4
0
0
7
0
0
9
0
38400
0
3
1.73
—
—
—
0
7
1.73
Notes: No indication: Setting not possible.
—: Setting possible, but errors may result.
1. The value set in BRR is given by the following equation:
N=
where
φ
2n
(32 × 2 × B)
B:
N:
φ:
n:
–1
Bit rate (bit/s)
Baud rate generator BRR setting (0 ≤ N ≤ 255)
System clock frequency
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
2. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.)
R (bit rate in left-hand column in table 10.3.)
× 100
Rev. 1.00 Dec. 19, 2007 Page 319 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw/2*1/φw*2
0
1
2
φ/16
1
0
3
φ/64
1
1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active (highspeed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
OSC (MHz)
φ (MHz)
Maximum Bit Rate
(bit/s)
0.0384*
0.0192
600
Setting
n
N
0
0
2
1
31250
0
0
2.4576
1.2288
38400
0
0
4
2
62500
0
0
10
5
156250
0
0
16
8
250000
0
0
10
312500
0
0
20
Note:
*
When SMR is set up to CKS1 = 0, CKS0 = 1.
Rev. 1.00 Dec. 19, 2007 Page 320 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1)
φ
1 MHz
19.2 kHz
2 MHz
Bit Rate
(bit/s)
n
N
Error
n
N
Error
n
N
Error
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
—
—
—
—
—
—
500
1K
0
249
0
—
—
—
2.5K
0
99
0
0
199
0
5K
0
49
0
0
99
0
10K
0
24
0
0
49
0
25K
0
9
0
0
19
0
50K
0
4
0
0
9
0
100K
—
—
—
0
4
0
250K
0
0
0
0
1
0
0
0
0
500K
1M
Rev. 1.00 Dec. 19, 2007 Page 321 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
φ
8 MHz
5 MHz
10 MHz
Bit Rate
(bit/s)
n
N
Error
n
N
Error
n
N
Error
200
—
—
—
—
—
—
0
12499
0
250
—
—
—
3
124
0
2
624
0
300
—
—
—
—
—
—
0
8332
0
500
—
—
—
2
249
0
0
4999
0
1K
—
—
—
2
124
0
0
2499
0
2.5K
—
—
—
2
49
0
0
999
0
5K
0
249
0
2
24
0
0
499
0
10K
0
124
0
0
199
0
0
249
0
25K
0
49
0
0
79
0
0
99
0
50K
0
24
0
0
39
0
0
49
0
100K
—
—
—
0
19
0
0
24
0
250K
0
4
0
0
7
0
0
9
0
500K
—
—
—
0
3
0
0
4
0
1M
—
—
—
0
1
0
—
—
—
Blank: Cannot be set.
—:
A setting can be made, but an error will result.
Notes: The value set in BRR is given by the following equation:
N=
φ
2n
(4 × 2 × B)
where
B:
N:
φ:
n:
–1
Bit rate (bit/s)
Baud rate generator BRR setting (0 ≤ N ≤ 255)
System clock frequency
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Rev. 1.00 Dec. 19, 2007 Page 322 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw/2*1/φw*2
0
1
2
φ/16
1
0
3
φ/64
1
1
Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φw clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
10.2.9
Clock stop register 1 (CKSTPR1)
Bit
7
6


5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write


R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 5—SCI3 Module Standby Mode Control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI3.
S32CKSTP Description
0
SCI3 is set to module standby mode*
1
SCI3 module standby mode is cleared
Note:
*
(initial value)
All SCI3 register is initialized in module standby mode.
Rev. 1.00 Dec. 19, 2007 Page 323 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.2.10 Serial Port Control Register (SPCR)
Bit
7
6
5
4


SPC32

Initial value
1
1
0

0
Read/Write


R/W
W
R/W
3
1
0


0


R/W
W
W
2
SCINV3 SCINV2
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Functions as TXD32 output pin*
Note:
*
(initial value)
Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; only 0 can be written to this bit.
Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
Rev. 1.00 Dec. 19, 2007 Page 324 of 520
REJ09B0409-0100
(initial value)
Section 10 Serial Communication Interface
Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; only 0 can written to these bits.
10.3
Operation
10.3.1
Overview
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.9.
(1)
Asynchronous Mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition and addition of 1 or 2 stop bits. (The combination of these
parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
Rev. 1.00 Dec. 19, 2007 Page 325 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(2)
Synchronous Mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
Bit 7 Bit 6
COM CHR
Bit 2
MP
Bit 5
PE
Bit 3
STOP Mode
0
0
0
0
0
1
1
Data Length
Asynchronous 8-bit data
mode
Parity Bit
No
0
0
7-bit data
No
1
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1
*
0
*
*
1 bit
2 bits
Yes
1
0
1 bit
2 bits
1
1
1 bit
2 bits
Yes
0
Stop Bit
Length
1 bit
2 bits
Setting
prohibited
Asynchronous 5-bit data
mode
No
1 bit
2 bits
Setting
prohibited
Asynchronous 5-bit data
mode
Yes
Synchronous
mode
No
8-bit data
1 bit
2 bits
No
*: Don’t care
Rev. 1.00 Dec. 19, 2007 Page 326 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
Bit 7 Bit 1
Bit 0
Transmit/Receive Clock
COM CKE1 CKE0 Mode
0
0
0
1
1
1
0
0
0
Clock Source SCK32 Pin Function
Asynchronous Internal
mode
I/O port (SCK32 pin not used)
Outputs clock with same frequency as bit rate
External
Inputs clock with frequency 16 times bit rate
Internal
Outputs serial clock
External
Inputs serial clock
1
0
Synchronous
mode
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
(3)
Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These
interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt Flags
Interrupt Request Conditions
Notes
RXI
RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2(a).)
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
TXI
TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2(b).)
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI
TEND
TEIE
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure
10.2(c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
Rev. 1.00 Dec. 19, 2007 Page 327 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
RDR
RDR
RSR (reception in progress)
RSR↑ (reception completed, transfer)
RXD32 pin
RXD32 pin
RDRF ← 1
(RXI request when RIE = 1)
RDRF = 0
Figure 10.2(a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
↓
TSR (transmission completed, transfer)
TXD32 pin
TXD32 pin
TDRE ← 1
(TXI request when TIE = 1)
TDRE = 0
Figure 10.2(b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (reception completed)
TXD32 pin
TXD32 pin
TEND = 0
TEND ← 1
(TEI request when TEIE = 1)
Figure 10.2(c) TEND Setting and TEI Interrupt
Rev. 1.00 Dec. 19, 2007 Page 328 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
10.3.2
Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
(1)
Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.3.
(LSB)
Serial
data
(MSB)
Start
bit
Transmit/receive data
1 bit
5, 7, or 8 bits
1
Parity
bit
1 bit
or none
Stop
bit(s)
Mark
state
1 or 2 bits
One transfer data unit (character or frame)
Figure 10.3 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period,
so that the transfer data is latched at the center of each bit.
Rev. 1.00 Dec. 19, 2007 Page 329 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
Table 10.11 Data Transfer Formats (Asynchronous Mode)
SMR
CHR PE
Serial Data Transfer Format and Frame Length
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
Setting prohibited
Setting prohibited
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
5-bit data
STOP
S
5-bit data
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
Setting prohibited
Setting prohibited
S
7-bit data
P
STOP
1
S
7-bit data
P
STOP STOP
1
0
S
5-bit data
P
STOP
1
1
S
5-bit data
P
STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
Rev. 1.00 Dec. 19, 2007 Page 330 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(2)
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source
selection.
When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK32 pin. In this case the
frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises
at the center of each bit of transmit/receive data, as shown in figure 10.4.
Clock
Serial
data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (1 frame)
Figure 10.4 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
(3)
Data Transfer Operations
(a)
SCI3 Initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
Rev. 1.00 Dec. 19, 2007 Page 331 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Figure 10.5 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and
RE to 0 in SCR3
Set bits CKE1
and CKE0
[1]
Set data transfer
format in SMR
[2]
Set value in BRR
[3]
Wait
Has 1-bit period
elapsed?
No
[2] Set the data transfer format in the serial
mode register (SMR).
[3] Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
[4] Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE or TE to 1 in SCR3.
Setting bits TE and RE enables the TXD32
and RXD32 pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
Yes
Set bit SPC32 to
1 in SPCR
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE or TE to 1
in SCR3
[1] Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
[4]
End
Figure 10.5 Example of SCI3 Initialization Flowchart
Rev. 1.00 Dec. 19, 2007 Page 332 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(b)
Transmitting
Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1]
No
TDRE = 1?
Yes
Write transmit
data to TDR
[2]
Continue data
transmission?
Yes
[1] Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
[2] When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
[3] If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
Read bit TEND
in SSR
No
TEND = 1?
Yes
[3]
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
End
Figure 10.6 Example of Data Transmission Flowchart (Asynchronous Mode)
Rev. 1.00 Dec. 19, 2007 Page 333 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit
TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
Rev. 1.00 Dec. 19, 2007 Page 334 of 520
REJ09B0409-0100
Mark
state
1
Section 10 Serial Communication Interface
(c)
Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bits OER,
PER, FER in SSR
[1] Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
[1]
Yes
OER + PER
+ FER = 1?
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
No
Read bit RDRF
in SSR
[2]
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
RDRF = 1?
Yes
Read receive
data in RDR
Receive error
processing
[4]
[3]
Continue data
reception?
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
Rev. 1.00 Dec. 19, 2007 Page 335 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Start receive
error processing
[4]
Overrun error
processing
OER = 1?
Yes
No
FER = 1?
Break?
Yes
No
No
PER = 1?
[4] If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD32 pin.
Framing error
processing
Yes
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
(A)
End of receive
error processing
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
Rev. 1.00 Dec. 19, 2007 Page 336 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.12 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.12 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbr.
Detection Conditions
Receive Data Processing
Overrun error
OER
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the parity (odd or even) set Receive data is transferred
in SMR is different from that of
from RSR to RDR
the received data
Rev. 1.00 Dec. 19, 2007 Page 337 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Figure 10.9 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
LSI
operation
RXI request
User
processing
RDRF
cleared to 0
RDR data read
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.9 Example of Operation when Receiving in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
10.3.3
Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
Rev. 1.00 Dec. 19, 2007 Page 338 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(1)
Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.10.
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Don't
care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't
care
8 bits
One transfer data unit (character or frame)
Note: * High level except in continuous transmission/reception
Figure 10.10 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the MSB,
the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity bits cannot be added.
(2)
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in
SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK32 pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
Rev. 1.00 Dec. 19, 2007 Page 339 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(3)
Data Transfer Operations
(a)
SCI3 Initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2
(3), (a) SCI3 Initialization, and shown in figure 10.5.
(b)
Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1]
No
TDRE = 1?
Yes
[2] When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Write transmit
data to TDR
[2]
Continue data
transmission?
[1] Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
Clear bit TE to 0
in SCR3
End
Figure 10.11 Example of Data Transmission Flowchart (Synchronous Mode)
Rev. 1.00 Dec. 19, 2007 Page 340 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is
selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD32 pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10.12 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE cleared
to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.12 Example of Operation when Transmitting in Synchronous Mode
Rev. 1.00 Dec. 19, 2007 Page 341 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(c)
Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bit OER
in SSR
[1]
[1] Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes
OER = 1?
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
No
Read bit RDRF
in SSR
[2]
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
RDRF = 1?
Yes
Read receive
data in RDR
[4]
[4] If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Overrun error
processing
[3]
Continue data
reception?
Yes
No
Clear bit RE to
0 in SCR3
4
End
Start overrun
error processing
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
Rev. 1.00 Dec. 19, 2007 Page 342 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies
an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
RXI request
User
processing
RDRE cleared
to 0
RDR data read
RXI request
ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
Rev. 1.00 Dec. 19, 2007 Page 343 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
(d)
Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1] Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
[1]
No
TDRE = 1?
[2] Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
Yes
Write transmit
data to TDR
[3] When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
Read bit OER
in SSR
Yes
OER = 1?
[4] If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit
OER is set to 1.
See figure 10.13 for details on overrun error
processing.
No
Read bit RDRF
in SSR
[2]
RDRF = 1?
No
Yes
Read receive data
in RDR
[4]
Overrun error
processing
[3]
Continue data
transmission/reception?
Yes
No
Clear bits TE and
RE to 0 in SCR3
End
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
Rev. 1.00 Dec. 19, 2007 Page 344 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that
SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously.
2. When switching from reception to simultaneous transmission/reception, check that
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously.
10.4
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.13.
Table 10.13 SCI3 Interrupt Requests
Interrupt Abbr. Interrupt Request
Vector
Address
RXI
Interrupt request initiated by receive data full flag (RDRF)
H'0024
TXI
Interrupt request initiated by transmit data empty flag (TDRE)
TEI
Interrupt request initiated by transmit end flag (TEND)
ERI
Interrupt request initiated by receive error flag (OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a
TEI interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
Rev. 1.00 Dec. 19, 2007 Page 345 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see section 3.3, Interrupts.
10.5
Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Rev. 1.00 Dec. 19, 2007 Page 346 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Table 10.14 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER
FER
PER
Receive Data Transfer
RSR → RDR
Receive Error Status
1
1
0
0
X
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
X
Overrun error + framing error + parity error
O : Receive data is transferred from RSR to RDR.
X : Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read
after an overrun error has occurred in a frame because reading of the receive data in
the previous frame was delayed, RDRF will be cleared to 0.
3. Break detection and processing
When a framing error is detected, a break can be detected by reading the value of the RXD32 pin
directly. In a break, the input from the RXD32 pin becomes all 0s, with the result that bit FER is set
and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD32 pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD32 pin to the mark
state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD32 pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD32 pin functions as an I/O port, and 0 is output from the TXD32 pin.
Rev. 1.00 Dec. 19, 2007 Page 347 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10.16.
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RXD32)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 –
where
1
D – 0.5
)–
– (L – 0.5) F} × 100 [%]
2N
N
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Rev. 1.00 Dec. 19, 2007 Page 348 of 520
REJ09B0409-0100
..... Equation (1)
Section 10 Serial Communication Interface
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100 [%]
= 46.875%
.... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
7. Relation between RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR
is read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is illustrated in figure 10.17.
Communication
line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10.17 Relation between RDR Read Timing and Data
Rev. 1.00 Dec. 19, 2007 Page 349 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
8. Transmit and receive operations when making a state transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
9. Switching SCK32 function
If pin SCK32 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a
general input/output pin (a pin with a different function), the pin outputs a low level signal for half
a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
a. When an SCK32 function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be
left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should
be pulled up to the VCC level via a resistor, or supplied with output from an external device.
b. When an SCK32 function is switched from clock output to general input/output
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3
to 1 and 0, respectively.
(ii) Clear bit COM in SMR to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK32.
10. Set up at subactive or subsleep mode
At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is φw/2.
Rev. 1.00 Dec. 19, 2007 Page 350 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
11. Oscillator use with serial communications interface
When implementing the serial communications interface, the system clock oscillator must be used.
The on-chip oscillator should not be used in this case. See section 4.2 (5), On-Chip Oscillator
Selection Method, for information on switching between the system clock oscillator and the onchip oscillator.
Rev. 1.00 Dec. 19, 2007 Page 351 of 520
REJ09B0409-0100
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 352 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
Section 11 10-Bit PWM
11.1
Overview
This LSI is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1
and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a
low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in
PWDRLm, which denotes the PWDRL registers for each PWM.
11.1.1
Features
Features of the 10-bit PWMs are as follows.
• Choice of four conversion periods
Any of the following conversion periods can be chosen:
4,096/φ, with a minimum modulation width of 4/φ
2,048/φ, with a minimum modulation width of 2/φ
1,024/φ, with a minimum modulation width of 1/φ
512/φ, with a minimum modulation width of 1/2 φ
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
It is possible to select between two types of PWM output: pulse-division PWM and event counter
PWM (PWM incorporating AEC). Refer to section 9.7, Asynchronous Event Counter (AEC), for
information on event counter PWM.
Rev. 1.00 Dec. 19, 2007 Page 353 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the 10-bit PWM.
PWDRUm
φ/2
φ/4
φ/8
φ
PWM waveform
generator
Internal data bus
PWDRLm
PWCRm
IECPWM
PWMm
(IECPWM)
[Legend]
PWCRm:
PWDRLm:
PWDRUm:
PWMm:
IECPWM:
m = 1 or 2
PWM control register
PWM data register L
PWM data register U
PWM output pin
Event counter PWM (PWM incorporating AEC)
Figure 11.1 Block Diagram of the 10-bit PWM (1-Channel Configuration)
11.1.3
Pin Configuration
Table 11.1 shows the output pin assigned to the 10-bit PWM.
Table 11.1 Pin Configuration
Name
Abbr.
I/O
Function
PWM1 output pin
PWM1
Output
Pulse-division PWM waveform output (PWM1)/
event counter PWM output (IECPWM)
PWM2 output pin
PWM2
Output
Pulse-division PWM waveform output (PWM2)/
event counter PWM output (IECPWM)
Rev. 1.00 Dec. 19, 2007 Page 354 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
11.1.4
Register Configuration
Table 11.2 shows the register configuration of the 10-bit PWM.
Table 11.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
PWM1 control register
PWCR1
W
H'F8
H'FFD0
PWM1 data register U
PWDRU1
W
H'FC
H'FFD1
PWM1 data register L
PWDRL1
W
H'00
H'FFD2
PWM2 control register
PWCR2
W
H'F8
H'FFCD
PWM2 data register U
PWDRU2
W
H'FC
H'FFCE
PWM2 data register L
PWDRL2
W
H'00
H'FFCF
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
11.2
11.2.1
Register Descriptions
PWM Control Register (PWCRm)
Bit
7
6
5
4
3





2
1
0
PWCRm2 PWCRm1 PWCRm0
Initial value
1
1
1
1
1
0
0
0
Read/Write





W
W
W
On the H8/38524 Group, PWCRm is an 8-bit write-only register used to select the input clock and
PWM output type. At reset PWCRm is initialized to H'F8.
Bits 7 to 3—Reserved
Bits 7 to 3 are reserved; they are always read as 1, and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 355 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
Bit 2—Output Format Select (PWCRm2)
This bit selects the format of the output from the PWMm output pin.
This bit is write-only. Reading it always returns 1.
Bit 2
PWCRm2
Description
0
Pulse-division PWM
1
Event counter PWM
(initial value)
Bits 1 and 0—Clock Select 1 and 0 (PWCRm1, PWCRm0)
Bits 1 and 0 select the clock supplied to the 10-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
Bit 0
PWCRm1 PWCRm0 Description
0
0
0
1
1
0
1
1
Note:
*
The input clock is φ (tφ* = 1/φ)
The conversion period is 512/φ, with a minimum modulation
width of 1/2φ
The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 1,024/φ, with a minimum
modulation width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 2,048/φ, with a minimum
modulation width of 2/φ
The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 4,096/φ, with a minimum
modulation width of 4/φ
Period of PWM input clock.
Rev. 1.00 Dec. 19, 2007 Page 356 of 520
REJ09B0409-0100
(initial value)
Section 11 10-Bit PWM
11.2.2
PWM Data Registers U and L (PWDRUm, PWDRLm)
PWDRUm
Bit
7
6
5
4
3
2
1
0






Initial value
1
1
1
1
1
1
0
0
Read/Write






W
W
7
6
5
4
3
2
1
0
PWDRUm1 PWDRUm0
PWDRLm
Bit
PWDRLm7 PWDRLm6 PWDRLm5 PWDRLm4 PWDRLm3 PWDRLm2 PWDRLm1 PWDRLm0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to
PWDRUm and the lower 8 bits to PWDRLm. The value written to PWDRUm and PWDRLm
gives the total high-level width of one PWM waveform cycle.
When 10-bit data is written to PWDRUm and PWDRLm, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 10-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRLm.
2. Write the upper 2 bits to PWDRUm for the same channel.
PWDRUm and PWDRLm are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRUm is initialized to H'FC, and PWDRLm to H'00.
Rev. 1.00 Dec. 19, 2007 Page 357 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
11.2.3
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP
—
—
4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bits 4 and 1—PWM Module Standby Mode Control (PWmCKSTP)
Bits 4 and 1 control setting and clearing of module standby mode for the PWMm.
PWmCKSTP
Description
0
PWMm is set to module standby mode
1
PWMm module standby mode is cleared
Rev. 1.00 Dec. 19, 2007 Page 358 of 520
REJ09B0409-0100
(initial value)
Section 11 10-Bit PWM
11.3
11.3.1
Operation
Operation
When using the 10-bit PWM, set the registers in the following sequence.
1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P90/PWM1 or
P91/PWM2 is designated as the PWM output pin, or both are designated as PWM output pins.
2. Set bits PWCRm1 and PWCRm0 in the PWM control register (PWCRm) to select a
conversion period of 4,096/φ (PWCRm1 = 1, PWCRm0 = 1), 2,048/φ (PWCRm1 = 1,
PWCRm0 = 0), 1,024/φ (PWCRm1 = 0, PWCRm0 = 1), or 512/φ (PWCRm1 = 0, PWCRm0 =
0). In addition, select between pulse-division PWM (PWCRm2 = 0) and event counter PWM
(PWCRm2 = 1) output. Refer to section 9.7, Asynchronous Event Counter (AEC), for
information on the event counter PWM (PWM incorporating AEC) output format.
3. Set the output waveform data in PWDRUm and PWDRLm. Be sure to write in the correct
sequence, first PWDRLm then PWDRUm for the same channel. When data is written to
PWDRUm, the data will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 4 pulses, as shown in figure 11.2. The total of the high-level
pulse widths during this period (TH) corresponds to the data in PWDRUm and PWDRLm. This
relation can be represented as follows.
TH = (data value in PWDRUm and PWDRLm + 4) • tφ/2
where tφ is the PWM input clock period: 1/φ (PWCRm = H'0), 2/φ (PWCRm = H'1), 4/φ
(PWCRm = H'2), or 8/φ (PWCRm = H'3).
Rev. 1.00 Dec. 19, 2007 Page 359 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
Example: Settings in order to obtain a conversion period of 1,024 µs:
When PWCRm1 = 0 and PWCRm0 = 0, the conversion period is 512/φ, so φ must be
0.5 MHz. In this case, tfn = 256 µs, with 1/2φ (resolution) = 1.0 µs.
When PWCRm1 = 0 and PWCRm0 = 1, the conversion period is 1,024/φ, so φ must be
1 MHz. In this case, tfn = 256 µs, with 1/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 0, the conversion period is 2,048/φ , so φ must
be 2 MHz. In this case, tfn = 256 µs, with 2/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 1, the conversion period is 4,096/φ, so φ must be
4 MHz. In this case, tfn = 256 µs, with 4/φ (resolution) = 1.0 µs
Accordingly, for a conversion period of 1,024 µs, the system clock frequency (φ) must
be 0.5 MHz, 1 MHz, 2 MHz, or 4 MHz.
1 conversion period
tf2
tf3
tf1
tH1
tH2
tH3
tf4
tH4
TH = tH1 + tH2 + tH3 + tH4
tf1 = tf2 = tf3 = tf4
Figure 11.2 PWM Output Waveform
11.3.2
PWM Operation Modes
PWM operation modes are shown in table 11.3.
Table 11.3 PWM Operation Modes
Operation
Mode
Reset
Active
Subactive
Subsleep
Standby
PWCRm
Reset
Functions Functions Retained
Retained
Retained
Retained Retained
PWDRUm Reset
Functions Functions Retained
Retained
Retained
Retained Retained
PWDRLm Reset
Functions Functions Retained
Retained
Retained
Retained Retained
Sleep
Rev. 1.00 Dec. 19, 2007 Page 360 of 520
REJ09B0409-0100
Watch
Module
Standby
Section 12 A/D Converter
Section 12 A/D Converter
12.1
Overview
This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital
converter, and can convert up to 8 channels of analog input.
12.1.1
Features
The A/D converter has the following features.
• 10-bit resolution
• Eight input channels
• Conversion time: approx. 12.4 µs per channel (at 5 MHz operation)/6.2 µs (at 10 MHz
operation)
• Built-in sample-and-hold function
• Interrupt requested on completion of A/D conversion
• A/D conversion can be started by external trigger input
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 1.00 Dec. 19, 2007 Page 361 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
ADTRG
AMR
AN0
AN1
AN2
AN3
ADSR
Multiplexer
Internal data bus
AN4
AN5
AN6
AVCC
AN7
+
Comparator
−
AVCC
Reference
voltage
Control logic
AVSS
AVSS
ADRRH
ADRRL
[Legend]
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag
Figure 12.1 Block Diagram of the A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 362 of 520
REJ09B0409-0100
IRRAD
Section 12 A/D Converter
12.1.3
Pin Configuration
Table 12.1 shows the A/D converter pin configuration.
Table 12.1 Pin Configuration
Name
Abbr.
I/O
Function
Analog power supply
AVCC
Input
Power supply and reference voltage of analog part
Analog ground
AVSS
Input
Ground and reference voltage of analog part
Analog input 0
AN0
Input
Analog input channel 0
Analog input 1
AN1
Input
Analog input channel 1
Analog input 2
AN2
Input
Analog input channel 2
Analog input 3
AN3
Input
Analog input channel 3
Analog input 4
AN4
Input
Analog input channel 4
Analog input 5
AN5
Input
Analog input channel 5
Analog input 6
AN6
Input
Analog input channel 6
Analog input 7
AN7
Input
Analog input channel 7
External trigger input
ADTRG
Input
External trigger input for starting A/D conversion
12.1.4
Register Configuration
Table 12.2 shows the A/D converter register configuration.
Table 12.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
A/D mode register
AMR
R/W
H'30
H'FFC6
A/D start register
ADSR
R/W
H'7F
H'FFC7
A/D result register H
ADRRH
R
Not fixed
H'FFC4
A/D result register L
ADRRL
R
Not fixed
H'FFC5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Rev. 1.00 Dec. 19, 2007 Page 363 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.2
Register Descriptions
12.2.1
A/D Result Registers (ADRRH, ADRRL)
Bit
7
Initial value
Read/Write
5
4
3
2
1
0
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
6
5
4
3
2
1
0
7
6






Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined
R
R
R
R
R
R
R
R
R
R












ADRRH
ADRRL
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2 bits
in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2
A/D Mode Register (AMR)
Bit
7
6
5
4
3
2
1
0
CKS
TRGE


CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W


R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Rev. 1.00 Dec. 19, 2007 Page 364 of 520
REJ09B0409-0100
Section 12 A/D Converter
Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7
CKS
Conversion Period
φ = 1 MHz
φ = 5 MHz
φ = 10 MHz
0
62/φ (initial value)
62 µs
31/φ
31 µs
12.4 µs
—*
6.2 µs
—*
1
Note:
*
The operation cannot be guaranteed if the conversion time is less than 6.2 µs. Make
sure to select a setting that gives a conversion time of 6.2 µs or more.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
Disables start of A/D conversion by external trigger
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note:
*
(initial value)
The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See (1) IRQ Edge
Select Register (IEGR) in section 3.3.2, Interrupt Control Registers, for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Rev. 1.00 Dec. 19, 2007 Page 365 of 520
REJ09B0409-0100
Section 12 A/D Converter
Bits 3 to 0—Channel Select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
*
*
No channel selected
0
1
0
0
AN0
0
1
0
1
AN1
0
1
1
0
AN2
0
1
1
1
AN3
1
0
0
0
AN4
1
0
0
1
AN5
1
0
1
0
AN6
1
0
1
1
AN7
1
1
*
*
Setting prohibited
(initial value)
*: Don’t care
12.2.3
A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
Rev. 1.00 Dec. 19, 2007 Page 366 of 520
REJ09B0409-0100
Section 12 A/D Converter
Bit 7—A/D Start Flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read: Indicates the completion of A/D conversion
(initial value)
Write: Stops A/D conversion
1
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0—Reserved
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.2.4
Clock Stop Register 1 (CKSTPR1)
Bit
7
6


5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write


R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4—A/D Converter Module Standby Mode Control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP
Description
0
A/D converter is set to module standby mode
1
A/D converter module standby mode is cleared
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 367 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.3
Operation
12.3.1
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE
in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge
select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D
conversion.
Figure 12.2 shows the timing.
φ
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
A/D conversion
Figure 12.2 External Trigger Input Timing
Rev. 1.00 Dec. 19, 2007 Page 368 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.3.3
A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
AMR
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
ADSR
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
ADRRH
Retained* Functions
Functions
Retained
Retained
Retained
Retained
Retained
ADRRL
Retained* Functions
Functions
Retained
Retained
Retained
Retained
Retained
Note:
12.4
*
Undefined in a power-on reset.
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see section 3.3, Interrupts.
Rev. 1.00 Dec. 19, 2007 Page 369 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter
goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Rev. 1.00 Dec. 19, 2007 Page 370 of 520
REJ09B0409-0100
Idle
A/D conversion starts
A/D conversion (1)
Set*
Set*
Note: * ( ) indicates instruction execution by software.
ADRRH
ADRRL
Channel 1 (AN1)
operation state
ADSF
IENAD
Interrupt
(IRRAD)
A/D conversion (2)
A/D conversion result (1)
Read conversion result
Idle
Set*
A/D conversion result (2)
Read conversion result
Idle
Section 12 A/D Converter
Figure 12.3 Typical A/D Converter Operation Timing
Rev. 1.00 Dec. 19, 2007 Page 371 of 520
REJ09B0409-0100
Section 12 A/D Converter
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
Rev. 1.00 Dec. 19, 2007 Page 372 of 520
REJ09B0409-0100
Section 12 A/D Converter
Start
Set A/D conversion speed
and input channel
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
Rev. 1.00 Dec. 19, 2007 Page 373 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 12.7).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 12.7).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 1.00 Dec. 19, 2007 Page 374 of 520
REJ09B0409-0100
Section 12 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
6
8
7 FS
8
Analog
input voltage
Figure 12.6 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 12.7 A/D Conversion Accuracy Definitions (2)
Rev. 1.00 Dec. 19, 2007 Page 375 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.7
Application Notes
12.7.1
Permissible Signal Source Impedance
This LSI’s analog input is designed such that conversion precision is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee A/D conversion precision. However, a large capacitance
provided externally, the input load will essentially comprise only the internal input resistance of
10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained
in this case, it may not be possible to follow an analog signal with a large differential coefficient
(e.g., 5 mV/µs or greater) (see figure 12.8). When converting a high-speed analog signal, a lowimpedance buffer should be inserted.
12.7.2
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
A/D converter
equivalent circuit
10 kΩ
Up to 10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Figure 12.8 Analog Input Circuit Example
Rev. 1.00 Dec. 19, 2007 Page 376 of 520
REJ09B0409-0100
20 pF
Section 12 A/D Converter
12.7.3
Additional Usage Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock
cycles before starting.
• In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder
resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not
used, it is recommended that AVCC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
Rev. 1.00 Dec. 19, 2007 Page 377 of 520
REJ09B0409-0100
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 378 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Section 13 LCD Controller/Driver
13.1
Overview
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
13.1.1
Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Static
32 seg
1/2
32 seg
1/3
32 seg
1/4
32 seg
• LCD RAM capacity
8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• A or B waveform selectable by software
• Removal of split-resistance can be controlled in software.
Rev. 1.00 Dec. 19, 2007 Page 379 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.1.2
Block Diagram
Figures 13.1 shows a block diagram of the LCD controller/driver.
VCC
V1
LCD drive
power supply
V2
V3
VSS
φ/256 to φ/2
Common
data latch
Internal data bus
φw
Common
driver
COM1
COM4
SEG32
LPCR
LCR
LCR2
32-bit
shift
register
Display timing generator
Segment
driver
LCD RAM
(16 bytes)
SEG1
SEGn
[Legend]
LPCR: LCD port control register
LCR:
LCD control register
LCR2: LCD control register 2
Figure 13.1 Block Diagram of LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 380 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.1.3
Pin Configuration
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name
Abbr.
I/O
Function
Segment output pins
SEG32 to SEG1
Output
LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins
COM4 to COM1
Output
LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
LCD power supply pins
V1, V2, V3
—
Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
13.1.4
Register Configuration
Table 13.2 shows the register configuration of the LCD controller/driver.
Table 13.2 LCD Controller/Driver Registers
Name
Abbr.
R/W
Initial Value
Address
LCD port control register
LPCR
R/W
—
H'FFC0
LCD control register
LCR
R/W
H'80
H'FFC1
LCD control register 2
LCR2
R/W
—
H'FFC2
LCD RAM
—
R/W
Undefined
H'F740 to H'F74F
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Rev. 1.00 Dec. 19, 2007 Page 381 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.2
13.2.1
Register Descriptions
LCD Port Control Register (LPCR)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX

SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0

0
0
0
0
Read/Write
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1
Bit 6
DTS0
Bit 5
CMX
Duty Cycle
Common Drivers
Notes
0
0
0
Static
COM1 (initial value)
Do not use COM4, COM3, and
COM2.
COM4 to COM1
COM4, COM3, and COM2 output the
same waveform as COM1.
COM2 and COM1
Do not use COM4 and COM3.
COM4 to COM1
COM4 outputs the same waveform
as COM3, and COM2 outputs the
same waveform as COM1.
COM3 to COM1
Do not use COM4.
COM4 to COM1
Do not use COM4.
COM4 to COM1
—
1
0
1
0
1/2 duty
1
1
0
0
1/3 duty
1
1
1
0
1/4 duty
1
Bit 4—Reserved
Bit 4 is reserved. It can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 382 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used.
Function of Pins SEG32 to SEG1
Bit 3
Bit 2
Bit 1
Bit 0
SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to
SGS3 SGS2 SGS1 SGS0 SEG29
0
0
0
1
1
0
1
1
0
0
1
1
0
1
SEG25
SEG21
SEG17
SEG13
SEG9
SEG5
SEG1
Notes
(Initial value)
0
Port
Port
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
Port
SEG
0
Port
Port
Port
Port
Port
Port
SEG
SEG
1
Port
Port
Port
Port
Port
SEG
SEG
SEG
0
Port
Port
Port
Port
SEG
SEG
SEG
SEG
1
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
0
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
1
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
0
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
1
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
0
SEG
SEG
SEG
SEG
Port
Port
Port
Port
1
SEG
SEG
SEG
Port
Port
Port
Port
Port
0
SEG
SEG
Port
Port
Port
Port
Port
Port
1
SEG
Port
Port
Port
Port
Port
Port
Port
Rev. 1.00 Dec. 19, 2007 Page 383 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.2.2
LCD Control Register (LCR)
Bit
7
6
5
4
3
2
1
0

PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write

R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7—Reserved
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6—LCD Drive Power Supply On/Off Control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0
LCD drive power supply off
1
LCD drive power supply on
(initial value)
Bit 5—Display Function Activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0
LCD controller/driver operation halted
1
LCD controller/driver operates
Rev. 1.00 Dec. 19, 2007 Page 384 of 520
REJ09B0409-0100
(initial value)
Section 13 LCD Controller/Driver
Bit 4—Display Data Control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0
Blank data is displayed
1
LCD RAM data is display
(initial value)
Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
Frame Frequency*2
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Operating Clock
φ = 2 MHz
0
*
0
0
φw
0
*
0
1
φw/2
128 Hz*3 (initial value)
64 Hz*3
0
*
1
*
φw/4
32 Hz*3
1
0
0
0
φ/2
—
244 Hz
1
0
0
1
φ/4
977 Hz
122 Hz
1
0
1
0
φ/8
488 Hz
61 Hz
1
0
1
1
φ/16
244 Hz
30.5 Hz
1
1
0
0
φ/32
122 Hz
—
1
1
0
1
φ/64
61 Hz
—
1
1
1
0
φ/128
30.5 Hz
—
1
1
1
1
φ/256
—
—
φ = 250 kHz*1
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
Rev. 1.00 Dec. 19, 2007 Page 385 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.2.3
LCD Control Register 2 (LCR2)
Bit
7
6
5
4
3
2
1
0
LCDAB
—
—
—
CDS3
CDS2
CDS1
CDS0
Initial value
0
1
1
—
0
0
0
0
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform and removal of split-resistance. LCR2 is initialized to H'7F upon a reset.
Bit 7—A Waveform/B Waveform Switching Control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0
Drive using A waveform
1
Drive using B waveform
Bits 6 and 5—Reserved
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bit 4—Reserved
Bit 4 is reserved; this can only be written with 0.
Rev. 1.00 Dec. 19, 2007 Page 386 of 520
REJ09B0409-0100
(initial value)
Section 13 LCD Controller/Driver
Bits 3 to 0—Removal of Split-Resistance Control
These bits control whether the split-resistance is removed or connected.
Bit 3
CDS3
Bit 2
CDS2
Bit 1
CDS1
0
0
0
Bit 0
CDS0
0
1
1
Description
(initial value)
Split-resistance connected
0
1
1
0
0
1
1
1
0
0
0
1
Split-resistance removed
0
Split-resistance connected
1
1
0
1
1
0
0
1
1
0
1
Rev. 1.00 Dec. 19, 2007 Page 387 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP


4
3
1
2
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W


R/W
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0—LCD Controller/Driver Module Standby Mode Control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0
LCD controller/driver is set to module standby mode
1
LCD controller/driver module standby mode is cleared
Rev. 1.00 Dec. 19, 2007 Page 388 of 520
REJ09B0409-0100
(initial value)
Section 13 LCD Controller/Driver
13.3
Operation
13.3.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
(1)
Hardware Settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2.
VCC
V1
V2
V3
VSS
Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be suitable
for driving a large panel. If the display lacks sharpness when using a large panel, refer to
section 13.3.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is selected, the
common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle.
In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with
1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform
is output from pins COM4 and COM3.
Rev. 1.00 Dec. 19, 2007 Page 389 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
(2)
Software Settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 13.3.3, Operation in
Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
Rev. 1.00 Dec. 19, 2007 Page 390 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
13.3.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
H'F74F
SEG32
SEG32
SEG32
SEG32
SEG31
SEG31
SEG31
SEG31
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
Rev. 1.00 Dec. 19, 2007 Page 391 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Bit 7
Bit 6
Bit 5
Bit 4
H'F740
SEG2
SEG2
H'F74F
SEG32
COM3
Bit 3
Bit 2
Bit 1
Bit 0
SEG2
SEG1
SEG1
SEG1
SEG32
SEG32
SEG31
SEG31
SEG31
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
Rev. 1.00 Dec. 19, 2007 Page 392 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG32
SEG32
SEG31
SEG31
SEG30
SEG30
SEG29
SEG29
H'F747
Space not used for display
H'F74F
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.5 LCD RAM Map (1/2 Duty)
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display
space
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
H'F743
Space not
used for
display
H'F74F
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.6 LCD RAM Map (Static Mode)
Rev. 1.00 Dec. 19, 2007 Page 393 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
SEGn
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
(c) Waveform with 1/2 duty
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
Rev. 1.00 Dec. 19, 2007 Page 394 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
COM4
V1
V2
V3
VSS
SEGn
1 frame
1 frame
1 frame
1 frame
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
(c) Waveform with 1/2 duty
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)
Rev. 1.00 Dec. 19, 2007 Page 395 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Table 13.3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
M: LCD alternation signal
13.3.3
Operation in Power-Down Modes
This LSI the LCD controller/driver can be operated even in the power-down modes. The operating
state of the LCD controller/driver in the power-down modes is summarized in table 13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to the
LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Rev. 1.00 Dec. 19, 2007 Page 396 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Table 13.4 Power-Down Modes and Display Operation
Reset Active
Sleep
Watch
Module
Sub-active Sub-sleep Standby Standby
φ
Runs
Runs
Runs
Stops
Stops
Stops
Stops
4
Stops*
φw
Runs
Runs
Runs
Runs
Runs
Runs
1
Stops*
4
Stops*
Stops
Stops
Stops
Stops
Stops
Stops
2
Stops*
Stops
Stops
3
3
3
2
Functions Functions Functions* Functions* Functions* Stops*
Stops
Mode
Clock
Display
ACT = 0
operation
ACT = 1
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φw, φw/2, or φw/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
13.3.4
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power
supply capacity is insufficient when VCC is used as the power supply, the power supply impedance
must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins
V1 to V3, as shown in figure 13.9, or by adding a split-resistance externally.
R
VCC
V1
R
This LSI
R = several kΩ to
several MΩ
V2
R
V3
C = 0.1 to 0.3 µF
R
VSS
Figure 13.9 Connection of External Split-Resistance
Rev. 1.00 Dec. 19, 2007 Page 397 of 520
REJ09B0409-0100
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 398 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Section 14 Power-On Reset and Low-Voltage Detection
Circuits
14.1
Overview
This LSI can include a power-on reset circuit and low-voltage detection circuit.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode* when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
Note: * The voltage maintained in standby mode is the same as the RAM data retaining voltage
(VRAM). See section 17.2.2, DC Characteristics, for information on retaining voltage.
Rev. 1.00 Dec. 19, 2007 Page 399 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
14.1.1
Features
The features of the power-on reset circuit and low-voltage detection circuit are described below.
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply
rise/drop detection voltages and a detection voltage reference voltage may be input from an
external source, allowing the detection level to be set freely by the user.
Rev. 1.00 Dec. 19, 2007 Page 400 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
14.1.2
Block Diagram
A block diagram of the power-on reset circuit and low-voltage detection circuit are shown in
figure 14.1.
φ
CK
R
RES
OVF
PSS
R
Noise
canceler
Q
S
Power-on reset circuit
Noise
canceler
Vcc
External
power
supply
Vreset
+
−
Vint
LVDRES
+
−
extD
External
ladder
resistor
Internal data bus
LVDCR
Ladder
resistor
Internal reset
signal
LVDINT
extU
Interrupt
control
circuit
LVDSR
Vref
Interrupt
request
On-chip
reference voltage
generator
External
reference voltage
generator
Low-voltage detection circuit
[Legend]
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
extD:
extU:
Vref:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Power supply drop detection voltage input pin
Power supply rise detection voltage input pin
Reference voltage input pin
Figure 14.1 Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
Rev. 1.00 Dec. 19, 2007 Page 401 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
14.1.3
Pin Description
The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1.
Table 14.1 Pin Description
Pin
Symbol
I/O
Function
Low-voltage detection circuit
reference voltage input pin
Vref
Input
Reference voltage input for lowvoltage detection circuit
Low-voltage detection circuit power extD
supply drop detection voltage input
pin
Input
Power supply drop detection voltage
input pin for low-voltage detection
circuit
Low-voltage detection circuit power extU
supply rise detection voltage input
pin
Input
Power supply rise detection voltage
input pin for low-voltage detection
circuit
14.1.4
Register Descriptions
The registers of the power-on reset circuit and low-voltage detection circuit are listed in table 14.2.
Table 14.2 Register Descriptions
Name
Symbol
R/W
Initial Value
Address
Low-voltage detection control register
LVDCR
R/W
H'00
H'FF86
Low-voltage detection status register
LVDSR
R/W
H'00
H'FF87
Low-voltage detection counter
LVDCNT
R
H'00
H'FFC3
14.2
Individual Register Descriptions
14.2.1
Low-Voltage Detection Control Register (LVDCR)
Bit
7
6
LVDE
—
5
4
3
VINTDSEL VINTUSEL LVDSEL
Initial value
0*
0
0
0
0*
Read/Write
R/W
R/W
R/W
R/W
R/W
Note:
*
2
1
0
LVDRE
0*
LVDDE
LVDUE
0
0
R/W
R/W
R/W
These bits are not initialized by resets trigged by LVDR. They are initialized by poweron resets and watchdog timer resets.
Rev. 1.00 Dec. 19, 2007 Page 402 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage
detection circuit is used, settings for external input of power supply rise and drop detection
voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the lowvoltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power
supply voltage drops or rises.
Bit 7—LVD Enable (LVDE)
This bit is used to control whether or not the low-voltage detection circuit is used.
Bit 7
LVDE
Description
0
Low-voltage detection circuit not used (standby status)
1
Low-voltage detection circuit used
(initial value)
Bit 6—Reserved
This bit is a read/write enabled reserved bit.
Bit 5—Power Supply Drop (LVDD) Detection Level External Input Select (VINTDSEL)
This bit is used to select the power supply drop detection level.
Bit 5
VINTDSEL
Description
0
LVDD detection level generated by on-chip ladder resistor
1
LVDD detection level input to extD pin
(initial value)
Bit 4—Power Supply Rise (LVDU) Detection Level External Input Select (VINTUSEL)
This bit is used to select the power supply rise detection level.
Bit 4
VINTUSEL
Description
0
LVDU detection level generated by on-chip ladder resistor
1
LVDU detection level input to extU pin
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 403 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Bit 3—LVDR Detection Level Select (LVDSEL)
This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and
drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset.
Bit 3
LVDSEL
Description
0
Reset detection voltage 2.3 V (typ.)
1
Reset detection voltage 3.3 V (typ.)
(initial value)
Bit 2—LVDR Enable (LVDRE)
This bit is used to control whether resets triggered by LVDR are enabled or disabled.
Bit 2
LVDRE
Description
0
LVDR resets disabled
1
LVDR resets enabled
(initial value)
Bit 1—Voltage Drop Interrupt Enable (LVDDE)
This bit is used to control whether voltage drop interrupt requests are enabled or disabled.
Bit 1
LVDDE
Description
0
Voltage drop interrupt requests disabled
1
Voltage drop interrupt requests enabled
(initial value)
Bit 0—Voltage Rise Interrupt Enable (LVDUE)
This bit is used to control whether voltage rise interrupt requests are enabled or disabled.
Bit 0
LVDUE
Description
0
Voltage rise interrupt requests disabled
1
Voltage rise interrupt requests enabled
Rev. 1.00 Dec. 19, 2007 Page 404 of 520
REJ09B0409-0100
(initial value)
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table
14.3 when making settings to LVDCR.
Table 14.3 LVDCR Settings and Function Selections
LVDCR Setting Value
Power-on
Reset
Low-Voltage
Detection
Reset
Low-Voltage
Detection
Voltage Drop
Interrupt
Low-Voltage
Detection
Voltage Rise
Interrupt
—
—
—
—
—
LVDE
LVDSEL
LVDRE
LVDDE LVDUE
0
*
*
*
*
1
1
1
0
0
1
0
0
1
0
—
1
0
0
1
1
—
1
0
1
1
1
—
Note: Setting values marked with an asterisk (*) are invalid.
14.2.2
Low-Voltage Detection Status Register (LVDSR)
Bit
7
6
5
4
3
2
1
0
OVF
—
—
—
VREFSEL
—
LVDDF
LVDUF
0*
R/W
Initial value
0*
0
0
0
0
0
0*
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
These bits initialized by resets trigged by LVDR.
LVDSR is an 8-bit read/write register. It is used to control external input selection, indicates when
the reference voltage is stable, and indicates if the power supply voltage goes below or above a
specified range.
Bit 7—LVD Reference Voltage Stabilized Flag (OVF)
This bit indicates when the low-voltage detection counter (LVDCNT) overflows.
Bit 7
OVF
Description
0
[Clearing condition]
When 0 is written after reading 1
(initial value)
1
[Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
Rev. 1.00 Dec. 19, 2007 Page 405 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Bits 6 to 4—Reserved
These bits are read/write enabled reserved bits.
Bit 3—Reference Voltage External Input Select (VREFSEL)
This bit is used to select the reference voltage.
Bit 3
VREFSEL
Description
0
The on-chip circuit is used to generate the reference voltage
1
The reference voltage is input to the Vref pin from an external source
(initial value)
Bit 2—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bit 1—LVD Power Supply Voltage Drop Flag (LVDDF)
This bit indicates when a power supply voltage drop has been detected.
Bit 1
LVDDF
Description
0
[Clearing condition]
When 0 is written after reading 1
1
[Setting condition]
When the power supply voltage drops below Vint(D)
(initial value)
Bit 0—LVD Power Supply Voltage Rise Flag (LVDUF)
This bit indicates when a power supply voltage rise has been detected.
Bit 0
LVDUF
0
1
Description
[Clearing condition]
When 0 is written after reading 1
(initial value)
[Setting condition]
When the power supply voltage drops below Vint(D) while the LVDUE bit in
LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1
Rev. 1.00 Dec. 19, 2007 Page 406 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
14.2.3
Low-Voltage Detection Counter (LVDCNT)
Bit
7
6
5
4
3
2
1
0
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP
—
—
4
3
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
PW2CKSTP AECKSTP
2
1
0
WDCKSTP PW1CKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register. It is used to control the module’s module standby mode.
Only the bits relevant to the LVD function are described in this section. Refer to the sections on
the other modules for information about the other bits.
Bit 7—LVD Module Standby Control (LVDCKSTP)
This bit is used to control setting of the LVD function to module standby status and cancellation of
that status.
Bit 7
LVDCKSTP
Description
0
Sets LVD to module standby status
1
Cancels LVD module standby status
(initial value)
Rev. 1.00 Dec. 19, 2007 Page 407 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
14.3
Operation
14.3.1
Power-On Reset Circuit
Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 80 × CRES (µF) ± 10/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
Rev. 1.00 Dec. 19, 2007 Page 408 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
tPWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.2 Operational Timing of Power-On Reset Circuit
14.3.2
(1)
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit
Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 150 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized, based on overflow of LVDNT, etc., then set the LVDRE bit in LVDCR to 1. After that,
the output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and
LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 1.00 Dec. 19, 2007 Page 409 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
VCC
Vreset
VLVDRmin
VSS
LVDRES
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.3 Operational Timing of LVDR Circuit
(2)
LVDI (Interrupt by Low Voltage Detect) Circuit
Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150
µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized,
based on overflow of LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After
that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first
the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared
to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or watch
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
Rev. 1.00 Dec. 19, 2007 Page 410 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
Vint (U)
Vint (D)
Vcc
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 14.4 Operational Timing of LVDI Circuit
The reference voltage, power supply voltage drop detection level, and power supply voltage rise
detection level can be input to the LSI from external sources via the Vref, extD, and extU pins.
Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins.
First, make sure that the voltages input to pins extD and extU are set to higher levels than the
interrupt detection voltage Vexd. After initial settings are made, a power supply drop interrupt is
generated if the extD input voltage drops below Vexd. After a power supply drop interrupt is
generated, if the external power supply voltage rises and the extU input voltage rises higher than
Vexd, a power supply rise interrupt is generated. As with the on-chip circuit, the above function
should be used in conjunction with LVDR (Vreset1) when the LVDI function is used.
Rev. 1.00 Dec. 19, 2007 Page 411 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
External power
supply voltage
extD input voltage
extU input voltage (1)
(2)
(3)
Vexd
(4) Vreset1
VSS
LVDINTD
LVDDF
LVDINTU
LVDUF
IRQ0 interrupt
generated
IRQ0 interrupt
generated
Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit
(Using Pins Vref, extD, and extU)
Rev. 1.00 Dec. 19, 2007 Page 412 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU.
LVDCR
On-chip
ladder
resistor
R1
R2
D1
External power
supply voltage
R1 =
517 kΩ
U1
D2
U2
+
−
LVDRES
+
−
LVDINT
Interrupt
controller
extD
R2 =
33 kΩ
LVDSR
Interrupt
request
extU
R3 =
450 kΩ
Vref
External reference
voltage 1.3 V
On-chip reference
voltage generator
Setting conditions:
• Vref = 1.3 V external input (This Vref value results in a Vreset value of 2.5 V.)
• Power supply drop detection voltage input of 2.7 V from extD
• Power supply rise detection voltage input of 2.9 V from extU
• 1 MΩ variable resistor connected externally
Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU
Below is an explanation of the method for calculating the external resistor values when using the
Vref, extD, and extU pins for input of reference and detection voltages from sources external to
the LSI.
Procedure:
1. First, determine the overall resistance value, R. The current consumed by the resistor is
determined by the value of R. A lower R will result in a greater current flow, and a higher R
will result in a reduced current flow. The value of R is dependent on the configuration of the
system in which the LSI is installed.
2. Determine the power supply drop detection voltage (Vint(D) and the power supply rise
detection voltage (Vint(U).
3. Using a resistance value calculation table like the one shown below, plug in values for R,
Vreset1, Vint(D), and Vint(U) to calculate the values of Vref, R1, R2, and R3.
Rev. 1.00 Dec. 19, 2007 Page 413 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Resistance Value Calculation Table
Ex. No
Vref (V)
R (kΩ)
Vreset1
Vint(D)
Vint(U)
R1 (kΩ)
R2 (kΩ)
R3 (kΩ)
1
1.30
1000
2.5
2.7
2.9
517
33
450
2
1.41
1000
2.7
2.9
3
514
16
470
3
1.57
1000
3
3.2
3.5
511
42
447
4
2.09
1000
4
4.5
4.7
536
20
444
4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and
Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check
the maximum and minimum values for each value.
Error Calculation Table
R1
Vref (V) (kΩ)
R2
(kΩ)
R3
(kΩ)
1.3
33
450
517
Resistance Value
Error (%)
5
Comparator
Error (V)
Vreset1
(V)
Vint(D)
(V)
Vint(U)
(V)
R1+Err, R2/R3-Err
0.1
2.59
2.94
3.15
0
2.49
2.84
3.05
-0.1
2.39
2.74
2.95
0.1
2.59
2.66
2.85
0
2.49
2.56
2.75
-0.1
2.39
2.46
2.65
0.1
2.59
2.79
2.99
0
2.49
2.69
2.89
-0.1
2.39
2.59
2.79
0.1
2.59
2.93
3.16
0
2.49
2.83
3.06
-0.1
2.39
2.73
2.96
0.1
2.59
2.67
2.84
0
2.49
2.57
2.74
-0.1
2.39
2.47
2.64
R1-Err, R2/R3+Err
R1/R2/R3 No Err
R1/R2+Err, R3-Err
R1/R2-Err, R3+Err
Rev. 1.00 Dec. 19, 2007 Page 414 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
(3)
Operation and Cancellation Setting Procedure Using LVDR and LVDI
Settings should be made as indicated below in order to ensure proper operation of the low voltage
detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage
detection circuit operation and cancellation.
1. To turn on the low voltage detection circuit, first set the LVDE bit in LVDCR to 1.
2. After waiting for LVDCNT overflow, etc., to ensure that the stabilization time (tLVDON = 150 µs)
for the reference voltage and low voltage detection power supply has elapsed, clear bits
LVDDF and LVDUF in LVDSR to 0. If necessary, set the LVDRE, LVDDE, and LVDUE bits
in LVDCR to 1.
3. To cancel operation of the low voltage detection circuit, clear bits LVDRE, LVDDE, and
LVDUE to 0, then clear bit LVDE to 0. Bit LVDE should not be cleared at the same time as
bits LVDRE, LVDDE, and LVDUE to avoid malfunction.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 14.7 Low Voltage Detection Circuit Operation and Cancellation Setting Timing
Rev. 1.00 Dec. 19, 2007 Page 415 of 520
REJ09B0409-0100
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 416 of 520
REJ09B0409-0100
Section 15 Power Supply Circuit
Section 15 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible
to use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
15.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made effective
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to VCC and the GND potential connected to VSS are the reference levels. For
example, for port input/output levels, the VCC level is the reference for the high level, and the VSS
level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 5.5 V
CVCC
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used
Rev. 1.00 Dec. 19, 2007 Page 417 of 520
REJ09B0409-0100
Section 15 Power Supply Circuit
15.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input
directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V
to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more
than 3.6 V) is input.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 3.6 V
CVCC
Internal
power
supply
VSS
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Rev. 1.00 Dec. 19, 2007 Page 418 of 520
REJ09B0409-0100
Section 16 List of Registers
Section 16 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1.
•
•
•
•
Register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified by functional modules.
The data bus width is indicated.
The number of access states is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 1.00 Dec. 19, 2007 Page 419 of 520
REJ09B0409-0100
Section 16 List of Registers
16.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbreviation
Bit No Address
Module
Name
Data Bus
Width
Access
State
Flash memory control register 1
FLMCR1
8
H'F020
ROM
8
2
Flash memory control register 2
FLMCR2
8
H'F021
ROM
8
2
Flash memory power control
register
FLPWCR
8
H'F022
ROM
8
2
Erase block register
EBR
8
H'F023
ROM
8
2
Flash memory enable register
FENR
8
H'F02B
ROM
8
2
Low-voltage detection control
register
LVDCR
8
H'FF86
LVD
8
2
Low-voltage detection status
register
LVDSR
8
H'FF87
LVD
8
2
Event counter PWM compare
register H
ECPWCRH 8
H'FF8C
AEC*
8
2
Event counter PWM compare
register L
ECPWCRL 8
H'FF8D
AEC*
8
2
Event counter PWM data register H ECPWDRH 8
H'FF8E
AEC*
1
8
2
Event counter PWM data register L ECPWDRL 8
H'FF8F
1
AEC*
8
2
Wakeup edge select register
WEGR
8
H'FF90
Interrupts
8
2
Serial port control register
SPCR
8
H'FF91
SCI3
8
2
Input pin edge select register
AEGSR
8
H'FF92
AEC*
8
2
H'FF94
AEC*
8
2
1
Event counter control register
ECCR
8
1
1
1
1
Event counter control/status
register
ECCSR
8
H'FF95
AEC*
8
2
Event counter H
ECH
8
H'FF96
1
AEC*
8
2
H'FF97
1
AEC*
8
2
Event counter L
ECL
8
Serial mode register
SMR
8
H'FFA8
SCI3
8
3
Bit rate register
BRR
8
H'FFA9
SCI3
8
3
Serial control register 3
SCR3
8
H'FFAA
SCI3
8
3
Rev. 1.00 Dec. 19, 2007 Page 420 of 520
REJ09B0409-0100
Section 16 List of Registers
Register Name
Abbreviation
Bit No Address
Module
Name
Data Bus
Width
Access
State
Transmit data register
TDR
8
H’FFAB
SCI3
8
3
Serial status register
SSR
8
H’FFAC
SCI3
8
3
Receive data register
RDR
8
H’FFAD
SCI3
8
3
Timer mode register A
TMA
8
H’FFB0
Timer A
8
2
Timer counter A
TCA
8
H’FFB1
Timer A
8
2
Timer control/status register W
TCSRW
8
H’FFB2
2
WDT*
8
2
Timer counter W
TCW
8
H’FFB3
WDT*
8
2
Timer mode register C
TMC
8
H’FFB4
Timer C
8
2
Timer counter C /
Timer load register C
TCC/
TLC
8
H’FFB5
Timer C
8
2
Timer control register F
TCRF
8
H’FFB6
Timer F
8
2
Timer control status register F
TCSRF
8
H’FFB7
Timer F
8
2
8-bit timer counter FH
TCFH
8
H’FFB8
Timer F
8
2
8-bit timer counter FL
TCFL
8
H’FFB9
Timer F
8
2
Output compare register FH
OCRFH
8
H’FFBA
Timer F
8
2
Output compare register FL
OCRFL
8
H’FFBB
Timer F
8
2
Timer mode register G
TMG
8
H’FFBC
Timer G
8
2
Input capture register GF
ICRGF
8
H’FFBD
Timer G
8
2
Input capture register GR
ICRGR
8
H’FFBE
Timer G
8
2
2
LCD port control register
LPCR
8
H’FFC0
3
LCD*
8
2
LCD control register
LCR
8
H’FFC1
3
LCD*
8
2
LCD control register 2
LCR2
8
H’FFC2
LCD*
8
2
Low-voltage detection counter
LVDCNT
8
H’FFC3
LVD
8
2
A/D result register H
ADRRH
8
H’FFC4
A/D converter
8
2
A/D result register L
ADRRL
8
H’FFC5
A/D converter
8
2
A/D mode register
AMR
8
H’FFC6
A/D converter
8
2
A/D start register
ADSR
8
H’FFC7
A/D converter
8
2
Port mode register 1
PMR1
8
H'FFC8
I/O port
8
2
Port mode register 2
PMR2
8
H'FFC9
I/O port
8
2
Port mode register 3
PMR3
8
H'FFCA
I/O port
8
2
Port mode register 5
PMR5
8
H'FFCC
I/O port
8
2
3
Rev. 1.00 Dec. 19, 2007 Page 421 of 520
REJ09B0409-0100
Section 16 List of Registers
Register Name
Abbreviation
Bit No Address
Module
Name
Data Bus Access
Width
State
PWM2 control register
PWCR2
8
H’FFCD
10-bit PWM
8
2
PWM2 data register U
PWDRU2
8
H’FFCE
10-bit PWM
8
2
PWM2 data register L
PWDRL2
8
H’FFCF
10-bit PWM
8
2
PWM1 control register
PWCR1
8
H’FFD0
10-bit PWM
8
2
PWM1 data register U
PWDRU1
8
H’FFD1
10-bit PWM
8
2
PWM1 data register L
PWDRL1
8
H’FFD2
10-bit PWM
8
2
Port data register 1
PDR1
8
H’FFD4
I/O port
8
2
Port data register 3
PDR3
8
H’FFD6
I/O port
8
2
Port data register 4
PDR4
8
H’FFD7
I/O port
8
2
Port data register 5
PDR5
8
H’FFD8
I/O port
8
2
Port data register 6
PDR6
8
H’FFD9
I/O port
8
2
Port data register 7
PDR7
8
H’FFDA
I/O port
8
2
Port data register 8
PDR8
8
H’FFDB
I/O port
8
2
Port data register 9
PDR9
8
H’FFDC
I/O port
8
2
Port data register A
PDRA
8
H’FFDD
I/O port
8
2
Port data register B
PDRB
8
H’FFDE
I/O port
8
2
Port pull-up control register 1
PUCR1
8
H’FFE0
I/O port
8
2
Port pull-up control register 3
PUCR3
8
H’FFE1
I/O port
8
2
Port pull-up control register 5
PUCR5
8
H’FFE2
I/O port
8
2
Port pull-up control register 6
PUCR6
8
H’FFE3
I/O port
8
2
Port control register 1
PCR1
8
H’FFE4
I/O port
8
2
Port control register 3
PCR3
8
H’FFE6
I/O port
8
2
Port control register 4
PCR4
8
H’FFE7
I/O port
8
2
Port control register 5
PCR5
8
H’FFE8
I/O port
8
2
Port control register 6
PCR6
8
H’FFE9
I/O port
8
2
Port control register 7
PCR7
8
H’FFEA
I/O port
8
2
Port control register 8
PCR8
8
H’FFEB
I/O port
8
2
Port mode register 9
PMR9
8
H’FFEC
I/O port
8
2
Port control register A
PCRA
8
H’FFED
I/O port
8
2
Port mode register B
PMRB
8
H’FFEE
I/O port
8
2
System control register 1
SYSCR1
8
H’FFF0
SYSTEM
8
2
Rev. 1.00 Dec. 19, 2007 Page 422 of 520
REJ09B0409-0100
Section 16 List of Registers
Register Name
Abbreviation
Bit No Address
Module
Name
Data Bus
Width
Access
State
System control register 2
SYSCR2
8
H'FFF1
SYSTEM
8
2
IRQ edge select register
IEGR
8
H'FFF2
Interrupts
8
2
Interrupt enable register 1
IENR1
8
H'FFF3
Interrupts
8
2
Interrupt enable register 2
IENR2
8
H'FFF4
Interrupts
8
2
Oscillator control register
OSCCR
8
H'FFF5
CPG
8
2
Interrupt request register 1
IRR1
8
H'FFF6
Interrupts
8
2
Interrupt request register 2
IRR2
8
H'FFF7
Interrupts
8
2
Timer mode register W
TMW
8
H'FFF8
WDT*
8
2
Wakeup interrupt request register
IWPR
8
H’FFF9
Interrupts
8
2
Clock stop register 1
CKSTPR1
8
H'FFFA
SYSTEM
8
2
Clock stop register 2
CKSTPR2
8
H'FFFB
SYSTEM
8
2
2
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Rev. 1.00 Dec. 19, 2007 Page 423 of 520
REJ09B0409-0100
Section 16 List of Registers
16.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
ROM
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
FLMCR2
FLER
—
—
—
—
—
—
—
FLPWCR
PDWND
—
—
—
—
—
—
—
EBR
—
—
—
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
LVDCR
LVDE
—
VINTDSEL VINTUSEL LVDSEL
LVDRE
LVDDE
LVDUE
LVDSR
OVF
—
—
LVDDF
LVDUF
ECPWCRH
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 AEC*
ECPWCRL
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
ECPWDRH
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
ECPWDRL
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
WEGR
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts
SPCR
—
SCINV3
SCINV2
—
AEGSR
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1
AIEGS0
ECPWME —
ECCR
ACKH1
ACKH0
ACKL1
ACKL0
PWCK2
PWCK1
PWCK0
—
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
—
VREFSEL —
Lowvoltage
detect
circuit
1
—
SPC32
—
—
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
TMA
—
—
—
—
TMA3
TMA2
TMA1
TMA0
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
TCSRW
B6WI
TCWE
B4WI
TCSRWE B2WI
WDON
B0WI
WRST
TCW
TCW7
TCW6
TCW5
TCW4
TCW2
TCW1
TCW0
Rev. 1.00 Dec. 19, 2007 Page 424 of 520
REJ09B0409-0100
TCW3
SCI3
1
AEC*
SCI3
Timer A
WDT*2
Section 16 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TMC
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Timer C
TCC/
TLC
TCC7/
TLC7
TCC6/
TLC6
TCC5/
TLC5
TCC4/
TLC4
TCC3/
TLC3
TCC2/
TLC2
TCC1/
TLC1
TCC0/
TLC0
TCRF
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
TCSRF
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
TCFL
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
OCRFH
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
OCRFL
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Timer F
TMG
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
ICRGF
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
ICRGR
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
LPCR
DTS1
DTS0
CMX
—
SGS3
SGS2
SGS1
SGS0
LCR
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
LCR2
LCDAB
—
—
—
CDS3
CDS2
CDS1
CDS0
LVDCNT
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Lowvoltage
detect
circuit
A/D
converter
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADRRL
ADR1
ADR0
—
—
—
—
—
—
AMR
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
ADSR
ADSF
—
—
—
—
—
—
—
PMR1
IRQ3
—
—
IRQ4
TMIG
—
—
—
PMR2
—
—
POF1
—
—
WDCKS
NCS
IRQ0
PMR3
AEVL
AEVH
—
—
—
TMOFH
TMOFL
UD
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Timer G
LCD*3
I/O port
PWCR2
—
—
—
—
—
PWDRU2
—
—
—
—
—
PWCR22 PWCR21 PWCR20 10-bit
PWM
PWDRL2
PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
—
PWDRU21 PWDRU20
PWCR1
—
—
—
—
—
PWCR12 PWCR11 PWCR10
PWDRU1
—
—
—
—
—
—
PWDRU11 PWDRU10
PWDRL1
PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
PDR1
P17
—
—
P14
P13
—
—
—
PDR3
P37
P36
P35
P34
P33
P32
P31
P30
I/O port
Rev. 1.00 Dec. 19, 2007 Page 425 of 520
REJ09B0409-0100
Section 16 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
PDR4
—
—
—
—
P43
P42
P41
P40
I/O port
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
PDR8
P87
P86
P85
P84
P83
P82
P81
P80
PDR9
—
—
P95
P94
P93
P92
P91
P90
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PUCR1
PUCR17 —
—
PUCR14 PUCR13 —
—
—
PUCR3
PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
PUCR5
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR6
PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
PCR1
PCR17
—
—
PCR14
PCR13
—
—
—
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
PCR30
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
PCR8
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
PMR9
—
—
—
—
—
—
PWM2
PWM1
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
PMRB
—
—
—
—
IRQ1
—
—
—
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
SYSTEM
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
IEGR
—
—
—
IEG4
IEG3
—
IEG1
IEG0
IENR1
IENTA
—
IENWP
IEN4
IEN3
IENEC2
IEN1
IEN0
IENR2
IENDT
IENAD
—
IENTG
IENTFH
IENTFL
IENTC
OSCCR
SUBSTP —
—
—
—
IRQAECF OSCF
—
CPG
Interrupts
IENEC
IRR1
IRRTA
—
—
IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
IRR2
IRRDT
IRRAD
—
IRRTG
IRRTFH
IRRTFL
IRRTC
IRREC
Rev. 1.00 Dec. 19, 2007 Page 426 of 520
REJ09B0409-0100
Interrupts
Section 16 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TMW
—
—
—
—
CKS3
CKS2
CKS1
CKS0
WDT*2
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Interrupts
CKSTPR1
—
—
CKSTPR2
LVDCKSTP —
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP SYSTEM
—
PW2CKSTP
AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Rev. 1.00 Dec. 19, 2007 Page 427 of 520
REJ09B0409-0100
Section 16 List of Registers
16.3
Register States in Each Operating Mode
Register
Abbreviation Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
FLMCR1
—
—
Initialized
Initialized
ROM
Initialized
Initialized
Initialized
FLMCR2
Initialized
—
—
—
—
—
—
FLPWCR
Initialized
—
—
—
—
—
—
EBR
Initialized
—
—
Initialized
Initialized
Initialized
Initialized
FENR
Initialized
—
—
—
—
—
—
LVDCR
Initialized
—
—
—
—
—
—
LVDSR
Initialized
—
—
—
—
—
—
ECPWCRH
Initialized
—
—
—
—
—
—
ECPWCRL
Initialized
—
—
—
—
—
—
Lowvoltage
detect
circuit
AEC*
1
ECPWDRH
Initialized
—
—
—
—
—
—
ECPWDRL
Initialized
—
—
—
—
—
—
WEGR
Initialized
—
—
—
—
—
—
Interrupts
SPCR
Initialized
—
—
—
—
—
—
SCI3
AEGSR
Initialized
—
—
—
—
—
—
AEC*
ECCR
Initialized
—
—
—
—
—
—
ECCSR
Initialized
—
—
—
—
—
—
ECH
Initialized
—
—
—
—
—
—
ECL
Initialized
—
—
—
—
—
—
SMR
Initialized
—
—
Initialized
—
—
Initialized
BRR
Initialized
—
—
Initialized
—
—
Initialized
SCR3
Initialized
—
—
Initialized
—
—
Initialized
TDR
Initialized
—
—
Initialized
—
—
Initialized
SSR
Initialized
—
—
Initialized
—
—
Initialized
RDR
Initialized
—
—
Initialized
—
—
Initialized
TMA
Initialized
—
—
—
—
—
—
TCA
Initialized
—
—
—
—
—
—
TCSRW
Initialized
—
—
—
—
—
—
TCW
Initialized
—
—
—
—
—
—
Rev. 1.00 Dec. 19, 2007 Page 428 of 520
REJ09B0409-0100
1
SCI3
Timer A
2
WDT*
Section 16 List of Registers
Register
Abbreviation Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
TMC
Initialized
—
—
—
—
—
—
Timer C
TCC
Initialized
—
—
—
—
—
—
TLC
Initialized
—
—
—
—
—
—
TCRF
Initialized
—
—
—
—
—
—
TCSRF
Initialized
—
—
—
—
—
—
TCFH
Initialized
—
—
—
—
—
—
TCFL
Initialized
—
—
—
—
—
—
OCRFH
Initialized
—
—
—
—
—
—
OCRFL
Initialized
—
—
—
—
—
—
TMG
Initialized
—
—
—
—
—
—
Timer F
Timer G
ICRGF
Initialized
—
—
—
—
—
—
ICRGR
Initialized
—
—
—
—
—
—
LPCR
Initialized
—
—
—
—
—
—
LCR
Initialized
—
—
—
—
—
—
LCR2
Initialized
—
—
—
—
—
—
LVDCNT
Initialized
—
—
—
—
—
—
Lowvoltage
detect
circuit
ADRRH
—
—
—
—
—
—
—
ADRRL
—
—
—
—
—
—
—
A/D
converter
AMR
Initialized
—
—
—
—
—
—
LCD*
3
ADSR
Initialized
—
—
Initialized
Initialized
Initialized
Initialized
PMR1
Initialized
—
—
—
—
—
—
PMR2
Initialized
—
—
—
—
—
—
PMR3
Initialized
—
—
—
—
—
—
PMR5
Initialized
—
—
—
—
—
—
PWCR2
Initialized
—
—
—
—
—
—
PWDRU2
Initialized
—
—
—
—
—
—
PWDRL2
Initialized
—
—
—
—
—
—
PWCR1
Initialized
—
—
—
—
—
—
PWDRU1
Initialized
—
—
—
—
—
—
PWDRL1
Initialized
—
—
—
—
—
—
I/O port
10-bit
PWM
Rev. 1.00 Dec. 19, 2007 Page 429 of 520
REJ09B0409-0100
Section 16 List of Registers
Register
Abbreviation Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
PDR1
Initialized
—
—
—
—
—
—
I/O port
PDR3
Initialized
—
—
—
—
—
—
PDR4
Initialized
—
—
—
—
—
—
PDR5
Initialized
—
—
—
—
—
—
PDR6
Initialized
—
—
—
—
—
—
PDR7
Initialized
—
—
—
—
—
—
PDR8
Initialized
—
—
—
—
—
—
PDR9
Initialized
—
—
—
—
—
—
PDRA
Initialized
—
—
—
—
—
—
PDRB
Initialized
—
—
—
—
—
—
PUCR1
Initialized
—
—
—
—
—
—
PUCR3
Initialized
—
—
—
—
—
—
PUCR5
Initialized
—
—
—
—
—
—
PUCR6
Initialized
—
—
—
—
—
—
PCR1
Initialized
—
—
—
—
—
—
PCR3
Initialized
—
—
—
—
—
—
PCR4
Initialized
—
—
—
—
—
—
PCR5
Initialized
—
—
—
—
—
—
PCR6
Initialized
—
—
—
—
—
—
PCR7
Initialized
—
—
—
—
—
—
PCR8
Initialized
—
—
—
—
—
—
PMR9
Initialized
—
—
—
—
—
—
PCRA
Initialized
—
—
—
—
—
—
PMRB
Initialized
—
—
—
—
—
—
SYSCR1
Initialized
—
—
—
—
—
—
SYSCR2
Initialized
—
—
—
—
—
—
IEGR
Initialized
—
—
—
—
—
—
IENR1
Initialized
—
—
—
—
—
—
IENR2
Initialized
—
—
—
—
—
—
OSCCR
Initialized
—
—
—
—
—
—
CPG
IRR1
Initialized
—
—
—
—
—
—
Interrupts
IRR2
Initialized
—
—
—
—
—
—
Rev. 1.00 Dec. 19, 2007 Page 430 of 520
REJ09B0409-0100
SYSTEM
Interrupts
Section 16 List of Registers
Register
Abbreviation Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
TMW
Initialized
—
—
—
—
—
—
2
WDT*
IWPR
Initialized

—
—
—
—
—
Interrupts
CKSTPR1
Initialized
—
—
—
—
—
—
SYSTEM
CKSTPR2
Initialized


—
—
—
—
Notes:  is not initialized
1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Rev. 1.00 Dec. 19, 2007 Page 431 of 520
REJ09B0409-0100
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 432 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Section 17 Electrical Characteristics
17.1
Absolute Maximum Ratings (Flash Memory Version and Mask ROM
Version)
Table 17.1 lists the absolute maximum ratings.
Table 17.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*1
CVCC
–0.3 to +4.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
Vin
–0.3 to VCC +0.3
V
V
Other than port B
AVin
–0.3 to AVCC +0.3
Port 9 pin voltage
Port B
VP9
Operating temperature
Topr
–0.3 to VCC +0.3
V
2
°C
–20 to +75*
(regular specifications)
–40 to +85*2
(wide-range temperature
specifications)
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
Rev. 1.00 Dec. 19, 2007 Page 433 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2
Electrical Characteristics (Flash Memory Version and Mask ROM
Version)
17.2.1
Power Supply Voltage and Operating Ranges
(1)
Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator
Selected)
fosc (MHz)
fW (kHz)
20.0
32.768
2.0
2.7
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• All operating modes
fW (kHz)
Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected)
fosc (MHz)
(2)
5.5
VCC (V)
32.768
2.0
0.7
2.7
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 1.00 Dec. 19, 2007 Page 434 of 520
REJ09B0409-0100
2.7
5.5
VCC (V)
• All operating modes
5.5
VCC (V)
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (System Clock Oscillator
Selected)
10.0
φ (MHz)
16.384
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φSUB (kHz)
1.0
8.192
4.096
2.7
5.5
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
1250
φ (kHz)
(3)
15.625
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 1.00 Dec. 19, 2007 Page 435 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
(4)
Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)
φSUB (kHz)
φ (MHz)
16.384
1.0
0.35
2.7
5.5
VCC (V)
φ (kHz)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
125
6.25
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 1.00 Dec. 19, 2007 Page 436 of 520
REJ09B0409-0100
8.192
4.096
2.7
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
5.5
VCC (V)
Section 17 Electrical Characteristics
(5)
Analog Power Supply Voltage and A/D Converter Operating Range (System Clock
Oscillator Selected)
φ (kHz)
φ (MHz)
10.0
1000
500
1.0
2.7
5.5
AVCC (V)
2.7
• Active (high-speed) mode
• Sleep (high-speed) mode
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip
Oscillator Selected)
1.0
φ (kHz)
φ (MHz)
(6)
5.5
AVCC (V)
125
6.25
0.35
2.7
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Rev. 1.00 Dec. 19, 2007 Page 437 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.2
DC Characteristics
Table 17.2 lists the DC characteristics.
Table 17.2
DC Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Min
Typ
Max
Unit
Test Condition
RES,
WKP0 to WKP7,
IRQ0,
IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
VCC × 0.8
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
VCC × 0.9
—
VCC + 0.3
VCC × 0.7
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
VCC × 0.9
—
VCC + 0.3
VCC × 0.7
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
VCC × 0.7
—
AVCC + 0.3
VCC × 0.8
—
AVCC + 0.3
RXD32, UD
OSC1
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
PB0 to PB7
5
IRQAEC, P95*
IRQ1
VCC × 0.8
—
VCC + 0.3
VCC × 0.9
—
VCC + 0.3
VCC × 0.8
—
AVCC + 0.3
VCC × 0.9
—
AVCC + 0.3
Rev. 1.00 Dec. 19, 2007 Page 438 of 520
REJ09B0409-0100
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
Notes
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Input low
voltage
VIL
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
5
IRQAEC, P95* ,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
– 0.3
—
VCC × 0.2
V
VCC = 4.0 V to 5.5 V
– 0.3
—
VCC × 0.1
RXD32, UD
– 0.3
—
VCC × 0.3
– 0.3
—
VCC × 0.2
– 0.3
—
VCC × 0.2
– 0.3
—
VCC × 0.1
– 0.3
—
VCC × 0.3
– 0.3
—
VCC × 0.2
VCC – 1.0
—
—
VCC – 0.5
—
—
OSC1
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
Output
high
voltage
VOH
P13, P14, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
Notes
Other than above
V
VCC = 4.0 V to 5.5 V
V
VCC = 4.0 V to 5.5 V
V
VCC = 4.0 V to 5.5 V
Other than above
Other than above
Other than above
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
VCC – 0.3
—
—
–IOH = 0.1 mA
Rev. 1.00 Dec. 19, 2007 Page 439 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Values
Item
Symbol
Output low VOL
voltage
Applicable Pins
Min
Typ
Max
Unit
Test Condition
P13, P14, P17,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
—
—
0.6
V
—
—
0.5
IOL = 0.4 mA
P30 to P37
—
—
1.0
VCC = 4.0 V to 5.5 V
—
—
0.6
VCC = 4.0 V to 5.5 V
—
—
0.5
IOL = 0.4 mA
—
—
1.5
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
IOL = 10 mA
IOL = 1.6 mA
P90 to P95
IOL = 15 mA
—
—
1.0
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.8
VCC = 4.0 V to 5.5 V
IOL = 8 mA
Input/
output
leakage
current
| IIL |
—
—
1.0
IOL = 5 mA
—
—
0.6
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
RES, P43,
P13, P14, P17,
OSC1, X1,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
PA0 to PA3,
P90 to P95
—
—
1.0
PB0 to PB7
—
—
1.0
Rev. 1.00 Dec. 19, 2007 Page 440 of 520
REJ09B0409-0100
µA
VIN = 0.5 V to VCC –
0.5 V
VIN = 0.5 V to AVCC
– 0.5 V
Notes
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Pull-up
MOS
current
–Ip
P13, P14, P17,
P30 to P37,
P50 to P57,
P60 to P67
20
—
200
µA
VCC = 5.0 V,
VIN = 0.0 V
—
40
—
µA
VCC = 2.7 V,
VIN = 0.0 V
Input
capacitance
Cin
All input pins
except power
supply pin
—
—
15.0
pF
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
Active
mode
supply
current
IOPE1
VCC
—
0.6
—
mA
Active (high-speed)
mode
VCC = 2.7 V,
fOSC = 2 MHz
—
1.0
—
Notes
Reference
value
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.8
—
—
1.5
—
—
1.6
—
—
2.0
—
—
3.3
7.0
—
4.0
7.0
Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
*2 *3 *4
Rev. 1.00 Dec. 19, 2007 Page 441 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
Active
mode
supply
current
IOPE2
VCC
—
0.2
—
mA
Active (mediumspeed) mode
VCC = 2.7 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
—
0.5
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
0.4
—
—
0.8
—
—
0.6
—
—
0.9
—
—
0.9
3.0
—
1.2
3.0
Rev. 1.00 Dec. 19, 2007 Page 442 of 520
REJ09B0409-0100
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 4 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*1 *3 *4
*2 *3 *4
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Sleep
mode
supply
current
ISLEEP
VCC
—
0.3
—
mA
VCC = 2.7 V,
fOSC = 2 MHz
—
0.8
Notes
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
Subactive ISUB
mode
supply
current
VCC
—
0.5
—
—
0.9
—
—
0.9
—
—
1.3
—
—
1.5
5.0
—
2.2
5.0
—
11.3
—
—
12.7
—
—
16.3
50
—
30
50
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
VCC = 5 V,
fOSC = 2 MHz
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
VCC = 5 V,
fOSC = 4 MHz
*2 *3 *4
µA
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/8)
*1 *3 *4
*2 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
Reference
value
*2 *3 *4
Reference
value
*1 *3 *4
*2 *3 *4
Rev. 1.00 Dec. 19, 2007 Page 443 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
Subsleep
mode
supply
current
ISUBSP
VCC
—
4.0
16
µA
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*3 *4
Watch
mode
supply
current
IWATCH
VCC
—
1.4
—
µA
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
*1 *3 *4
Standby
mode
supply
current
—
ISTBY
VCC
1.8
6.0
—
0.3
—
—
—
—
VCC
0.5
0.05
0.6
0.16
µA
—
—
—
—
—
1.0
5.0
2.0
—
—
Rev. 1.00 Dec. 19, 2007 Page 444 of 520
REJ09B0409-0100
—
—
—
RAM data VRAM
retaining
voltage
1.8
V
Reference
value
*2 *3 *4
Reference
value
VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
*3 *4
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*1 *3 *4
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*2 *3 *4
VCC = 2.7 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
*2 *4
VCC = 5.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*2 *3 *4
VCC = 5.0 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
*2 *4
32-kHz crystal
resonator not used
*3 *4
Reference
value
Reference
value
Reference
value
Reference
value
Reference
value
*6
Section 17 Electrical Characteristics
Item
Symbol
Allowable output low
current (per pin)
IOL
Allowable output low
current (total)
∑IOL
Allowable output high –IOH
current (per pin)
Allowable output high ∑–IOH
current (total)
Applicable
Pins
Values
Min
Test
Condition
Typ
Max
Unit
—
Output pins
except ports 3
and 9
—
2.0
mA
Port 3
—
—
10.0
Output pins
except port 9
—
—
0.5
Port 9
—
—
15.0
VCC = 4.0 V to
5.5 V
—
—
5.0
Other than
above
—
Output pins
except ports 3
and 9
—
40.0
Port 3
—
—
80.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
80.0
All output pins —
—
2.0
—
—
0.2
All output pins —
—
15.0
—
—
10.0
Notes
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
Other than
above
mA
VCC = 4.0 V to
5.5 V
Other than
above
VCC start voltage
VCCSTART
VCC
0
—
0.1
V
*2
VCC rising gradient
SVCC
VCC
0.05
—
—
V/ms
*2
Rev. 1.00 Dec. 19, 2007 Page 445 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the flash memory version.
3. Pin states when supply current is measured.
Mode
RES Pin
Internal State
Other Pins
LCD Power
Supply
Active (high-speed)
mode (IOPE1)
VCC
Only CPU operates
VCC
Stops
Oscillator Pins
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
Subactive mode
VCC
Only CPU operates
VCC
Stops
Subsleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
Subclock:
crystal resonator
CPU stops
Watch mode
VCC
Only clock time base
operates
Standby mode
VCC
CPU and timers
both stop
System clock:
crystal resonator
VCC
Stops
VCC
Stops
CPU stops
System clock:
crystal resonator
Subclock:
Pin X1 = GND
4. Except current which flows to the pull-up MOS or output buffer.
5. Used when user mode or boot mode is determined after canceling a reset in the flash
memory version.
6. Voltage maintained in standby mode.
Rev. 1.00 Dec. 19, 2007 Page 446 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.3
AC Characteristics
Table 17.3 lists the control signal timing and table 17.4 lists the serial interface timing.
Table 17.3 Control Signal Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Applicable
Pins
Min
Typ
Max
Unit
System clock
oscillation
frequency
fOSC
OSC1, OSC2
2.0
—
20.0
MHz
0.7
—
2.0
OSC clock (φOSC)
cycle time
tOSC
50.0
—
500
500
—
1429
System clock (φ)
cycle time
OSC1, OSC2
tcyc
Test Condition
On-chip oscillator
selected
ns
Reference
Figure
*2
Figure 17.1
On-chip oscillator
selected
2
—
128
tOSC
—
—
182
µs
Subclock oscillation fW
frequency
X1, X2
—
32.768
—
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5
—
µs
Figure 17.1
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Oscillation
stabilization time
trc
OSC1,
OSC2
—
—
20
ms
trc
X1, X2
—
—
2.0
s
External clock high tCPH
width
OSC1
20
—
—
ns
Figure 17.1
External clock low
width
tCPL
OSC1
20
—
—
ns
Figure 17.1
External clock rise
time
tCPr
OSC1
—
—
5
ns
Figure 17.1
External clock fall
time
tCPf
OSC1
—
—
5
ns
Figure 17.1
RES pin low
width
tREL
RES
10
—
—
tcyc
Figure 17.2
Rev. 1.00 Dec. 19, 2007 Page 447 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Item
Symbol
Input pin high
width
tIH
Input pin low
width
UD pin minimum
transition width
tIL
tUDH
Applicable
Pins
Values
Typ
Max
Unit
IRQ0, IRQ1, 2
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH 0.5
—
—
tOSC
IRQ0, IRQ1, 2
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH 0.5
—
—
tOSC
UD
—
—
tcyc
tsubcyc
tUDL
Min
4
Test Condition
Reference
Figure
Figure 17.3
Figure 17.3
Figure 17.6
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Rev. 1.00 Dec. 19, 2007 Page 448 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Table 17.4
Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input clock Asynchronous
cycle
Clocked synchronous
tscyc
Input clock pulse width
Transmit data delay time
(clocked synchronous)
Min
Typ Max Unit
Test
Condition
Reference
Figure
tcyc or tsubcyc
Figure 17.4
0.6
tscyc
Figure 17.4
1
tcyc or tsubcyc
Figure 17.5
—
ns
Figure 17.5
—
ns
Figure 17.5
4
—
—
6
—
—
tSCKW
0.4
—
tTXD
—
—
Receive data setup time
(clocked synchronous)
tRXS
150.0
—
Receive data hold time
(clocked synchronous)
tRXH
150.0
—
Rev. 1.00 Dec. 19, 2007 Page 449 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.4
A/D Converter Characteristics
Table 17.5 shows the A/D converter characteristics.
Table 17.5
A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Applicable
Pins
Min
Typ
Max
Unit
Analog power supply AVCC
voltage
AVCC
2.7
—
5.5
V
Analog input voltage
AN0 to
AN7
– 0.3
—
AVCC + 0.3 V
Item
Symbol
AVIN
Test
Condition
Reference
Figure
*1
Analog power supply AIOPE
current
AISTOP1
AVCC
—
—
1.5
mA
AVCC
—
600
—
µA
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*3
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
Resolution (data
length)
—
—
10
bit
Nonlinearity error
—
—
±3.5
LSB
—
—
±7.5
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
±2.0
±4.0
LSB
—
±2.0
±8.0
6.2
—
124
Conversion time
AVCC = 5.0 V
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Rev. 1.00 Dec. 19, 2007 Page 450 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.5
LCD Characteristics
Table 17.6 shows the LCD characteristics.
Table 17.6 LCD Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Segment driver
step-down voltage
VDS
Common driver
step-down voltage
VDC
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
Applicable
Pins
Values
Reference
Figure
Min
Typ
Max
Unit
Test Condition
SEG1 to
SEG32
—
—
0.6
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
1.5
3.0
7.0
MΩ
Between V1 and
VSS
2.7
—
5.5
V
V1
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment pin
or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 1.00 Dec. 19, 2007 Page 451 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.6
Flash Memory Characteristics
Table 17.7
Flash Memory Characteristics
Condition:
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of
operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage
when programming/erasing), Ta = –20°C to +75°C (range of operating temperature
when programming/erasing: product with regular specifications, product with widerange temperature specifications)
Values
Item
Symbol
Min
Typ
Max
Unit
Programming time* * *
tP
—
7
200
ms/128 bytes
1 3 5
Erase time* * *
tE
—
1200
ms/block
Reprogramming count
NWEC
1000*
10000*
—
times
Data retain period
tDRP
10
10*
—
—
year
Programming
Wait time after
1
SWE-bit setting*
x
1
—
—
µs
Wait time after
1
PSU-bit setting*
y
50
—
—
µs
1 2 4
100
8
9
Test
Conditions
z1
28
30
32
µs
1≤n≤6
z2
198
200
202
µs
7 ≤ n ≤ 1000
z3
8
10
12
µs
Additional
programming
Wait time after
1
P-bit clear*
α
5
—
—
µs
Wait time after
1
PSU-bit clear*
β
5
—
—
µs
Wait time after
1
PV-bit setting*
γ
4
—
—
µs
Wait time after
1
dummy write*
ε
2
—
—
µs
Wait time after
1
PV-bit clear*
η
2
—
—
µs
Wait time after
1
SWE-bit clear*
θ
100
—
—
µs
Maximum
programming
1 4 5
count* * *
N
—
—
1000
times
Wait time after
1 4
P-bit setting* *
Rev. 1.00 Dec. 19, 2007 Page 452 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Values
Item
Erase
Symbol
Min
Typ
Max
Unit
Wait time after
1
SWE-bit setting*
x
1
—
—
µs
Wait time after
1
ESU-bit setting*
y
100
—
—
µs
Wait time after
1 6
E-bit setting* *
z
10
—
100
ms
Wait time after
1
E-bit clear*
α
10
—
—
µs
Wait time after
1
ESU-bit clear*
β
10
—
—
µs
Wait time after
1
EV-bit setting*
γ
20
—
—
µs
Wait time after
1
dummy write*
ε
2
—
—
µs
Wait time after
1
EV-bit clear*
η
4
—
—
µs
Wait time after
1
SWE-bit clear*
θ
100
—
—
µs
Maximum erase
1 6 7
count* * *
N
—
—
120
times
Test
Conditions
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) × maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2, and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the
number of writes (n) as follows:
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed
range is from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be
performed by this count).
10. This is a data retain characteristic when reprogramming is performed within the
specification range including this minimum value.
Rev. 1.00 Dec. 19, 2007 Page 453 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.7
Power Supply Voltage Detection Circuit Characteristics
Table 17.8
Power Supply Voltage Detection Circuit Characteristics (1)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol
Min
Typ
Max
Unit
LVDR operation drop
voltage*
VLVDRmin
1.0
—
—
V
LVD stabilization time
TLVDON
150
—
—
µs
Standby mode
supply current
ISTBY
—
—
100
µA
Test Conditions
LVDE = 1
VCC = 5.0 V
32 oscillator not
used
Note:
*
Table 17.9
In some cases no reset may occur if the power supply voltage, VCC, drops below
VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for.
Power Supply Voltage Detection Circuit Characteristics (2)
Using on-chip reference voltage and ladder resistor (VREFSEL = VINTDSEL = VINTUSEL = 0)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Power supply drop
detection voltage
Vint(D)*3
3.3
3.7
4.2
V
LVDSEL = 0
Power supply rise
detection voltage
Vint(U)*3
3.6
4.0
4.5
V
LVDSEL = 0
Reset detection voltage
1*1
Vreset1*3 2.0
2.3
2.7
V
LVDSEL = 0
Reset detection voltage
2
2*
Vreset2*3 2.7
3.3
3.9
V
LVDSEL = 1
Notes: 1. The above function should be used in conjunction with the voltage drop/rise detection
function.
2. Low-voltage detection reset should be selected for low-voltage detection reset only.
3. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
Rev. 1.00 Dec. 19, 2007 Page 454 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Table 17.10
Power Supply Voltage Detection Circuit Characteristics (3)
Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL
and VINTUSEL = 1)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
Test Condition
extD/extU interrupt
detection level
Vexd
0.80
1.20
1.60
V
extD/extU pin input
voltage*2
VextD*1
1
VextU*
–0.3
—
VCC + 0.3 or AVCC
+ 0.3, whichever is
lower
V
VCC = 2.7 to 3.3 V
–0.3
—
3.6 or AVCC + 0.3,
whichever is lower
V
VCC = 3.3 to 5.5 V
Notes: 1. The VextD voltage must always be greater than the VextU voltage.
2. The maximum input voltage of the extD and extU pins is 3.6 V.
Rev. 1.00 Dec. 19, 2007 Page 455 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Table 17.11
Power Supply Voltage Detection Circuit Characteristics (4)
Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL =
0)
Rated Values
Typ
Max
Test
Unit Condition
1
Vint(D)* 3.08 * (Vref1 – 0.1)
3.08 * Vref1
3.08 * (Vref1 + 0.1)
V
LVDSEL = 0
Vref1*
—
1.68
V
Vint(D)
1
Vint(U)* 3.33 * (Vref2 – 0.1)
3.33 * Vref2
3.33 * (Vref2 + 0.1)
V
LVDSEL = 0
Vref input voltage
(Vint(U))
Vref2*
—
1.55
V
Vint(U)
Reset detection
voltage 1
Vreset1* 1.91 * (Vref3 – 0.1)
1.91 * Vref3
1.91 * (Vref3 + 0.1)
V
LVDSEL = 0
Vref input voltage
(Vreset1)
Vref3*
—
2.77
V
Vreset1
Reset detection
voltage 2
Vreset2* 2.76 * (Vref4 – 0.1)
2.76 * Vref4
2.76 * (Vref4 + 0.1)
V
LVDSEL = 1
Vref input voltage
(Vreset2)
Vref4*
—
1.89
V
Vreset2
Item
Symbol
Power supply drop
detection voltage
Vref input voltage
(Vint(D))
Power supply rise
detection voltage
Notes:
Min
2
0.98
2
0.91
1
2
0.89
1
2
1.08
1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
2. The Vref input voltage is calculated using the following formula.
2.7 V (= VCC min)
< Vint(D), Vint(U), Vreset2
< 5.5 V (= VCC max)
1.5 V (= RAM retention voltage)
< Vreset1
< 5.5 V (= VCC max)
Vref1: 2.7 < 3.08 * (Vref1 – 0.1), 3.08 * (Vref1 + 0.1) < 5.5 → 0.98 < Vref1 < 1.68
Vref2: 2.7 < 3.33 * (Vref2 – 0.1), 3.33 * (Vref2 + 0.1) < 5.5 → 0.91 < Vref2 < 1.55
Vref3: 1.5 < 1.91 * (Vref3 – 0.1), 1.91 * (Vref3 + 0.1) < 5.5 → 0.89 < Vref3 < 2.77
Vref4: 2.7 < 2.76 * (Vref4 – 0.1), 2.76 * (Vref4 + 0.1) < 5.5 → 1.08 < Vref4 < 1.89
Rev. 1.00 Dec. 19, 2007 Page 456 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Table 17.12
Power Supply Voltage Detection Circuit Characteristics (5)
Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL =
VINTUSEL = 1)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
Comparator detection
accuracy
Vcdl
0.1
—
—
V
extD/extU pin input
voltage
VextD*
VextU*
Vref pin input voltage
Note:
17.2.8
*
Test Condition
| VextU – Vref |
| VextD – Vref |
Vref5
–0.3
—
VCC + 0.3 or
AVCC + 0.3,
whichever is
lower
V
VCC = 2.7 to 3.3 V
–0.3
—
3.6 or AVCC
+ 0.3, whichever
is lower
V
VCC = 3.3 to 5.5 V
0.8
—
2.8
V
VCC = 2.7 to 5.5 V
The VextD voltage must always be greater than the VextU voltage.
Power-On Reset Circuit Characteristics
Table 17.13
Power-On Reset Circuit Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol Min
Typ
Max
Unit
RES pin pull-up
resistance
RRES
65
100
—
kΩ
Power-on reset start
voltage
Vpor
—
—
100
mV
Test Condition
Note: Make sure to drop the power supply voltage, VCC, to below Vpor = 100 mV and then raise it
after the RES pin load had thoroughly dissipated. To drain the load of the RES pin,
attaching a diode to the VCC side is recommended. The power-on reset function may not
work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.
Rev. 1.00 Dec. 19, 2007 Page 457 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.2.9
Watchdog Timer Characteristics
Table 17.14
Watchdog Timer Characteristics
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
On-chip oscillator
overflow time
tOVF
Note:
*
17.3
Applicable
Pins
Rated Values
Min
Typ
Max
Unit
Note
Test
Condition
0.2
0.4
—
s
*
VCC = 5 V
When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the
time remaining until an internal reset is generated.
Operation Timing
Figures 17.1 to 17.6 show timing diagrams.
t OSC , tw
VIH
OSC1
x1
VIL
t CPH
t CPr
t CPL
t CPf
Figure 17.1 Clock Input Timing
Rev. 1.00 Dec. 19, 2007 Page 458 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
RES
VIL
tREL
Figure 17.2 RES Low Width
IRQ0, IRQ1, IRQ3, IRQ4,
TMIC, TMIF, TMIG,
ADTRG, WKP0 to WKP7,
IRQAEC, AEVL, AEVH
VIH
VIL
t IL
t IH
Figure 17.3 Input Timing
t SCKW
SCK 32
t scyc
Figure 17.4 SCK3 Input Clock Timing
Rev. 1.00 Dec. 19, 2007 Page 459 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
t scyc
VIH or VOH*
SCK 32
VIL or VOL*
t TXD
VOH*
VOL*
TXD32
(transmit data)
t RXS
t RXH
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2Vcc + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 17.7.
Figure 17.5 SCI3 Synchronous Mode Input/Output Timing
VIH
UD
VIL
tUDL
tUDH
Figure 17.6 UD Pin Minimum Transition Width Timing
Rev. 1.00 Dec. 19, 2007 Page 460 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.4
Output Load Circuit
VCC
2.4 kΩ
Output pin
30 pF
12 kΩ
Figure 17.7 Output Load Condition
17.5
Resonator Equivalent Circuit
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameters
Frequency
(MHz)
Ceramic Resonator Parameters
Frequency
(MHz)
4
4.193
10
RS (max)
100 Ω
100 Ω
30 Ω
RS (max)
CO (max)
16 pF
16 pF
16 pF
CO (max)
2
4
10
18.3 Ω
6.8 Ω
4.6 Ω
36.94 pF 36.72 pF 32.31 pF
Figure 17.8 Resonator Equivalent Circuit (1)
Rev. 1.00 Dec. 19, 2007 Page 461 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameters
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
4
Manufacturer
RS (max)
100 Ω
Nihon Dempa Kogyo Co., Ltd.
CO (max)
16 pF
Ceramic Resonator Parameters (1)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
2
Manufacturer
RS (max)
18.3 Ω
Murata Manufacturing Co., Ltd.
CO (max)
36.94 pF
Ceramic Resonator Parameters (2)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
10
Manufacturer
RS (max)
4.6 Ω
Murata Manufacturing Co., Ltd.
CO (max)
32.31 pF
Figure 17.9 Resonator Equivalent Circuit (2)
17.6
Usage Note
The flash memory and mask ROM versions satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the flash memory version, the same evaluation
testing should also be conducted for the mask ROM version when changing over to that version.
Rev. 1.00 Dec. 19, 2007 Page 462 of 520
REJ09B0409-0100
Appendix
Appendix
A.
Instruction Set
A.1
Instruction List
Condition Code
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Logical exclusive OR of the operands on both sides
Rev. 1.00 Dec. 19, 2007 Page 463 of 520
REJ09B0409-0100
Appendix
Symbol
Description
¬
NOT (logical complement)
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Symbol
Description
↔
Condition Code Notation (cont)
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
Rev. 1.00 Dec. 19, 2007 Page 464 of 520
REJ09B0409-0100
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Condition Code
MOV.B @(d:16, ERs), Rd
B
4
@(d:16, ERs) → Rd8
— —
MOV.B @(d:24, ERs), Rd
B
8
@(d:24, ERs) → Rd8
— —
MOV.B @ERs+, Rd
B
@ERs → Rd8
ERs32+1 → ERs32
— —
MOV.B @aa:8, Rd
B
2
@aa:8 → Rd8
— —
MOV.B @aa:16, Rd
B
4
@aa:16 → Rd8
— —
MOV.B @aa:24, Rd
B
6
@aa:24 → Rd8
— —
MOV.B Rs, @ERd
B
Rs8 → @ERd
— —
MOV.B Rs, @(d:16, ERd)
B
4
Rs8 → @(d:16, ERd)
— —
MOV.B Rs, @(d:24, ERd)
B
8
Rs8 → @(d:24, ERd)
— —
MOV.B Rs, @–ERd
B
ERd32–1 → ERd32
Rs8 → @ERd
— —
MOV.B Rs, @aa:8
B
2
Rs8 → @aa:8
— —
MOV.B Rs, @aa:16
B
4
Rs8 → @aa:16
— —
MOV.B Rs, @aa:24
B
6
Rs8 → @aa:24
— —
MOV.W #xx:16, Rd
W 4
#xx:16 → Rd16
— —
MOV.W Rs, Rd
W
Rs16 → Rd16
— —
MOV.W @ERs, Rd
W
@ERs → Rd16
— —
2
2
2
2
2
2
MOV.W @(d:16, ERs), Rd W
4
@(d:16, ERs) → Rd16
— —
MOV.W @(d:24, ERs), Rd W
8
@(d:24, ERs) → Rd16
— —
@ERs → Rd16
ERs32+2 → @ERd32
— —
MOV.W @ERs+, Rd
W
MOV.W @aa:16, Rd
W
4
@aa:16 → Rd16
— —
MOV.W @aa:24, Rd
W
6
@aa:24 → Rd16
— —
MOV.W Rs, @ERd
W
Rs16 → @ERd
— —
2
2
MOV.W Rs, @(d:16, ERd) W
4
Rs16 → @(d:16, ERd)
— —
MOV.W Rs, @(d:24, ERd) W
8
Rs16 → @(d:24, ERd)
— —
0 —
0 —
0 —
Advanced
— —
B
↔ ↔ ↔ ↔ ↔ ↔
@ERs → Rd8
MOV.B @ERs, Rd
2
↔ ↔ ↔ ↔ ↔ ↔
— —
B
C
0 —
↔ ↔ ↔ ↔ ↔ ↔ ↔
Rs8 → Rd8
MOV.B Rs, Rd
V
↔ ↔ ↔ ↔ ↔ ↔ ↔
Z
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
I
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
N
— —
↔ ↔ ↔ ↔ ↔
H
#xx:8 → Rd8
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
2
Rn
B
No. of
States*1
↔ ↔ ↔ ↔ ↔
MOV MOV.B #xx:8, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
6
0 —
8
0 —
4
0 —
6
0 —
10
Rev. 1.00 Dec. 19, 2007 Page 465 of 520
REJ09B0409-0100
Appendix
No. of
States*1
Condition Code
— —
@(d:24, ERs) → ERd32
— —
@ERs → ERd32
ERs32+4 → ERs32
— —
6
@aa:16 → ERd32
— —
8
@aa:24 → ERd32
— —
ERs32 → @ERd
— —
ERs32 → @(d:16, ERd)
— —
ERs32 → @(d:24, ERd)
— —
ERd32–4 → ERd32
ERs32 → @ERd
— —
6
ERs32 → @aa:16
— —
8
ERs32 → @aa:24
— —
0 —
0 —
POP POP.W Rn
W
2 @SP → Rn16
SP+2 → SP
— —
POP.L ERn
L
4 @SP → ERn32
SP+4 → SP
— —
0 —
PUSH PUSH.W Rn
W
2 SP–2 → SP
Rn16 → @SP
— —
0 —
PUSH.L ERn
L
4 SP–4 → SP
ERn32 → @SP
— —
0 —
MOVFPE
MOVFPE @aa:16, Rd
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
MOVTPE
MOVTPE Rs, @aa:16
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
W
MOV.W Rs, @aa:16
W
MOV.W Rs, @aa:24
W
MOV.L #xx:32, ERd
L
MOV.L ERs, ERd
L
MOV.L @ERs, ERd
L
MOV.L @(d:16, ERs), ERd
L
6
MOV.L @(d:24, ERs), ERd
L
10
MOV.L @ERs+, ERd
L
MOV.L @aa:16, ERd
L
MOV.L @aa:24, ERd
L
MOV.L ERs, @ERd
L
MOV.L ERs, @(d:16, ERd)
L
6
MOV.L ERs, @(d:24, ERd)
L
10
MOV.L ERs, @–ERd
L
MOV.L ERs, @aa:16
L
MOV.L ERs, @aa:24
L
2
6
2
4
4
4
Rev. 1.00 Dec. 19, 2007 Page 466 of 520
REJ09B0409-0100
4
Advanced
@(d:16, ERs) → ERd32
↔
— —
↔
@ERs → ERd32
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
ERs32 → ERd32
↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔
#xx:32 → ERd32
0 —
↔ ↔ ↔
— —
↔ ↔ ↔
— —
Rs16 → @aa:24
↔
Rs16 → @aa:16
6
C
↔
4
V
↔
Z
↔
I
↔
N
— —
↔
H
ERd32–2 → ERd32
Rs16 → @ERd
0 —
MOV MOV.W Rs, @–ERd
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
6
6
0 —
8
0 —
6
0 —
2
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
6
10
6
10
Appendix
2. Arithmetic Instructions
No. of
States*1
Condition Code
Z
V
C
↔ ↔
— (2)
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
ERd32+ERs32 →
ERd32
— (2)
↔
↔
(3)
↔ ↔
Rd16+Rs16 → Rd16
— (1)
ERd32+#xx:32 →
ERd32
Rd8+#xx:8 +C → Rd8
—
2
B
2
Rd8+Rs8 +C → Rd8
—
ADDS ADDS.L #1, ERd
L
2
ERd32+1 → ERd32
— — — — — —
2
ADDS.L #2, ERd
L
2
ERd32+2 → ERd32
— — — — — —
2
ADDS.L #4, ERd
L
2
ERd32+4 → ERd32
— — — — — —
2
INC.B Rd
B
2
Rd8+1 → Rd8
— —
INC.W #1, Rd
W
2
Rd16+1 → Rd16
— —
INC.W #2, Rd
W
2
Rd16+2 → Rd16
— —
INC.L #1, ERd
L
2
ERd32+1 → ERd32
— —
INC.L #2, ERd
L
2
ERd32+2 → ERd32
— —
DAA
DAA Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
SUB
SUB.B Rs, Rd
B
2
Rd8–Rs8 → Rd8
—
SUB.W #xx:16, Rd
W 4
Rd16–#xx:16 → Rd16
— (1)
SUB.W Rs, Rd
W
Rd16–Rs16 → Rd16
— (1)
SUB.L #xx:32, ERd
L
SUB.L ERs, ERd
L
ADD.W Rs, Rd
W
ADD.L #xx:32, ERd
L
ADD.L ERs, ERd
L
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
6
2
2
(3)
2
4
2
6
2
—
2
—
2
—
2
—
2
—
2
* —
2
Rd8–Rs8–C → Rd8
—
SUBS SUBS.L #1, ERd
L
2
ERd32–1 → ERd32
— — — — — —
2
SUBS.L #2, ERd
L
2
ERd32–2 → ERd32
— — — — — —
2
SUBS.L #4, ERd
L
2
ERd32–4 → ERd32
— — — — — —
2
B
2
Rd8–1 → Rd8
— —
DEC.W #1, Rd
W
2
Rd16–1 → Rd16
— —
DEC.W #2, Rd
W
2
Rd16–2 → Rd16
— —
Rd8–#xx:8–C → Rd8
—
↔ ↔
2
ERd32–ERs32 → ERd32 — (2)
(3)
(3)
↔ ↔ ↔
DEC DEC.B Rd
2
↔ ↔ ↔
SUBX.B Rs, Rd
B
ERd32–#xx:32 → ERd32 — (2)
6
↔ ↔ ↔
2
SUBX SUBX.B #xx:8, Rd
2
↔ ↔ ↔ ↔ ↔ ↔ ↔
2
B
↔ ↔ ↔ ↔ ↔ ↔ ↔
INC
B
2
↔ ↔ ↔ ↔ ↔
W 4
↔ ↔ ↔ ↔ ↔ ↔
ADD.W #xx:16, Rd
2
↔ ↔ ↔ ↔ ↔
B
↔ ↔ ↔ ↔ ↔ ↔ ↔
ADD.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
2
ADD ADD.B #xx:8, Rd
↔
↔ ↔ ↔ ↔ ↔
— (1)
↔ ↔ ↔ ↔ ↔
Rd16+#xx:16 → Rd16
2
↔
—
↔ ↔
Rd8+Rs8 → Rd8
↔
—
Advanced
N
↔ ↔
I
Rd8+#xx:8 → Rd8
Normal
H
↔ ↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
2
@ERn
B
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
4
2
6
2
2
2
—
2
—
2
—
2
Rev. 1.00 Dec. 19, 2007 Page 467 of 520
REJ09B0409-0100
Appendix
No. of
States*1
Condition Code
Advanced
V
C
ERd32–1 → ERd32
— —
L
2
ERd32–2 → ERd32
— —
↔ ↔
—
2
DAS.Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
↔ ↔ ↔
2
DEC.L #2, ERd
↔ ↔ ↔
—
* —
2
B
2
Rd8 × Rs8 → Rd16
(unsigned multiplication)
— — — — — —
14
W
2
Rd16 × Rs16 → ERd32
(unsigned multiplication)
— — — — — —
22
B
4
Rd8 × Rs8 → Rd16
(signed multiplication)
— —
↔
W
4
Rd16 × Rs16 → ERd32
(signed multiplication)
— —
B
2
W
DIVXU DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP CMP.B #xx:8, Rd
16
— —
24
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
— — (6) (7) — —
14
2
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
— — (6) (7) — —
22
B
4
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
— — (8) (7) — —
16
W
4
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
— — (8) (7) — —
24
Rd8–#xx:8
—
Rd8–Rs8
—
Rd16–#xx:16
— (1)
Rd16–Rs16
— (1)
ERd32–#xx:32
— (2)
ERd32–ERs32
— (2)
B
2
CMP.B Rs, Rd
B
CMP.W #xx:16, Rd
W 4
CMP.W Rs, Rd
W
CMP.L #xx:32, ERd
L
CMP.L ERs, ERd
L
2
2
6
2
Rev. 1.00 Dec. 19, 2007 Page 468 of 520
REJ09B0409-0100
↔ ↔ ↔ ↔ ↔ ↔
MULXS. W Rs, ERd
— —
↔ ↔ ↔ ↔ ↔ ↔
MULXS MULXS. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
MULXU. W Rs, ERd
↔ ↔
MULXU MULXU. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
DAS
I
Normal
Z
2
↔
N
L
↔
H
DEC DEC.L #1, ERd
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
4
2
4
2
Appendix
No. of
States*1
Condition Code
W
2
0–Rd16 → Rd16
—
NEG.L ERd
L
2
0–ERd32 → ERd32
—
EXTU EXTU.W Rd
W
2
0 → (<bits 15 to 8>
of Rd16)
— — 0
EXTU.L ERd
L
2
0 → (<bits 31 to 16>
of ERd32)
— — 0
EXTS EXTS.W Rd
W
2
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
— —
EXTS.L ERd
L
2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
— —
Advanced
↔ ↔ ↔
NEG.W Rd
Normal
C
↔ ↔ ↔
—
↔ ↔ ↔
V
↔ ↔ ↔ ↔
0–Rd8 → Rd8
2
0 —
2
↔
2
0 —
2
↔
H
B
0 —
2
↔
Z
↔
I
NEG NEG.B Rd
↔ ↔ ↔
N
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
2
2
2
Rev. 1.00 Dec. 19, 2007 Page 469 of 520
REJ09B0409-0100
Appendix
3. Logic Instructions
AND.B Rs, Rd
B
AND.W #xx:16, Rd
W 4
AND.W Rs, Rd
W
AND.L #xx:32, ERd
L
AND.L ERs, ERd
L
OR.B #xx:8, Rd
B
OR.B Rs, Rd
B
OR.W #xx:16, Rd
W 4
OR.W Rs, Rd
W
OR.L #xx:32, ERd
L
OR.L ERs, ERd
L
XOR.B #xx:8, Rd
B
XOR.B Rs, Rd
B
XOR.W #xx:16, Rd
W 4
XOR.W Rs, Rd
W
XOR.L #xx:32, ERd
L
XOR.L ERs, ERd
L
4
ERd32⊕ERs32 → ERd32 — —
NOT.B Rd
B
2
¬ Rd8 → Rd8
— —
NOT.W Rd
W
2
¬ Rd16 → Rd16
— —
NOT.L ERd
L
2
¬ Rd32 → Rd32
— —
Z
Rd8∧Rs8 → Rd8
— —
Rd16∧#xx:16 → Rd16
— —
Rd16∧Rs16 → Rd16
— —
4
2
2
2
ERd32∧ERs32 → ERd32 — —
Rd8∨#xx:8 → Rd8
— —
Rd8∨Rs8 → Rd8
— —
Rd16∨#xx:16 → Rd16
— —
Rd16∨Rs16 → Rd16
— —
ERd32∨#xx:32 → ERd32 — —
6
4
2
2
2
ERd32∨ERs32 → ERd32 — —
Rd8⊕#xx:8 → Rd8
— —
Rd8⊕Rs8 → Rd8
— —
Rd16⊕#xx:16 → Rd16
— —
Rd16⊕Rs16 → Rd16
— —
ERd32⊕#xx:32 → ERd32 — —
6
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
N
— —
ERd32∧#xx:32 → ERd32 — —
6
Rev. 1.00 Dec. 19, 2007 Page 470 of 520
REJ09B0409-0100
H
Rd8∧#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
NOT
2
@(d, ERn)
2
@ERn
B
Rn
#xx
XOR
Condition Code
Operand Size
OR
No. of
States*1
AND.B #xx:8, Rd
Mnemonic
AND
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
2
Appendix
4. Shift Instructions
W
2
SHAL.L ERd
L
2
SHAR SHAR.B Rd
B
2
SHAR.W Rd
W
2
SHAR.L ERd
L
2
SHLL SHLL.B Rd
B
2
SHLL.W Rd
W
2
SHLL.L ERd
L
2
SHLR SHLR.B Rd
B
2
SHLR.W Rd
W
2
SHLR.L ERd
L
2
ROTXL ROTXL.B Rd
B
2
ROTXL.W Rd
W
2
ROTXL.L ERd
L
2
B
2
ROTXR.W Rd
W
2
ROTXR.L ERd
L
2
ROTL ROTL.B Rd
B
2
ROTL.W Rd
W
2
ROTL.L ERd
L
2
ROTR ROTR.B Rd
B
2
ROTR.W Rd
W
2
ROTR.L ERd
L
2
ROTXR ROTXR.B Rd
0
MSB
LSB
V
C
— —
— —
— —
C
MSB
— —
LSB
— —
— —
0
C
MSB
LSB
— —
— —
— —
0
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advanced
Z
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
I
C
N
↔ ↔ ↔
SHAL.W Rd
H
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Condition Code
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL SHAL.B Rd
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 1.00 Dec. 19, 2007 Page 471 of 520
REJ09B0409-0100
Appendix
5. Bit-Manipulation Instructions
B
BSET #xx:3, @aa:8
B
BSET Rn, Rd
B
BSET Rn, @ERd
B
BSET Rn, @aa:8
B
B
BCLR #xx:3, @ERd
B
BCLR #xx:3, @aa:8
B
BCLR Rn, Rd
B
BCLR Rn, @ERd
B
BCLR Rn, @aa:8
B
BNOT BNOT #xx:3, Rd
B
BNOT #xx:3, @ERd
B
BNOT #xx:3, @aa:8
B
BNOT Rn, Rd
B
BNOT Rn, @ERd
B
BNOT Rn, @aa:8
B
BTST BTST #xx:3, Rd
B
BTST #xx:3, @ERd
B
BTST #xx:3, @aa:8
B
BTST Rn, Rd
B
BTST Rn, @ERd
B
BTST Rn, @aa:8
B
BLD #xx:3, Rd
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
2
Rev. 1.00 Dec. 19, 2007 Page 472 of 520
REJ09B0409-0100
Condition Code
Operation
(#xx:3 of Rd8) ← 1
— — — — — —
2
(#xx:3 of @ERd) ← 1
— — — — — —
8
(#xx:3 of @aa:8) ← 1
— — — — — —
8
(Rn8 of Rd8) ← 1
— — — — — —
2
(Rn8 of @ERd) ← 1
— — — — — —
8
(Rn8 of @aa:8) ← 1
— — — — — —
8
(#xx:3 of Rd8) ← 0
— — — — — —
2
(#xx:3 of @ERd) ← 0
— — — — — —
8
(#xx:3 of @aa:8) ← 0
— — — — — —
8
(Rn8 of Rd8) ← 0
— — — — — —
2
(Rn8 of @ERd) ← 0
— — — — — —
8
(Rn8 of @aa:8) ← 0
— — — — — —
8
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
— — — — — —
2
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
— — — — — —
8
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
— — — — — —
8
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
— — — — — —
2
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
— — — — — —
8
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
— — — — — —
8
¬ (#xx:3 of Rd8) → Z
— — —
¬ (#xx:3 of @ERd) → Z
— — —
¬ (#xx:3 of @aa:8) → Z
— — —
¬ (Rn8 of @Rd8) → Z
— — —
¬ (Rn8 of @ERd) → Z
— — —
¬ (Rn8 of @aa:8) → Z
— — —
(#xx:3 of Rd8) → C
— — — — —
— —
2
— —
6
— —
6
— —
2
— —
6
— —
6
↔
BSET #xx:3, @ERd
BCLR BCLR #xx:3, Rd
BLD
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔
BSET BSET #xx:3, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
Appendix
B
BLD #xx:3, @aa:8
B
BILD BILD #xx:3, Rd
BST
BILD #xx:3, @ERd
B
BILD #xx:3, @aa:8
B
BST #xx:3, Rd
B
BST #xx:3, @ERd
B
BST #xx:3, @aa:8
B
BIST BIST #xx:3, Rd
B
BIST #xx:3, @ERd
B
BIST #xx:3, @aa:8
B
BAND BAND #xx:3, Rd
B
BAND #xx:3, @ERd
B
BAND #xx:3, @aa:8
B
BIAND BIAND #xx:3, Rd
BOR
B
B
BIAND #xx:3, @ERd
B
BIAND #xx:3, @aa:8
B
BOR #xx:3, Rd
B
BOR #xx:3, @ERd
B
BOR #xx:3, @aa:8
B
BIOR BIOR #xx:3, Rd
B
BIOR #xx:3, @ERd
B
BIOR #xx:3, @aa:8
B
BXOR BXOR #xx:3, Rd
B
BXOR #xx:3, @ERd
B
BXOR #xx:3, @aa:8
B
BIXOR BIXOR #xx:3, Rd
B
BIXOR #xx:3, @ERd
B
BIXOR #xx:3, @aa:8
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
(#xx:3 of @ERd) → C
— — — — —
6
(#xx:3 of @aa:8) → C
— — — — —
¬ (#xx:3 of Rd8) → C
— — — — —
¬ (#xx:3 of @ERd) → C
— — — — —
¬ (#xx:3 of @aa:8) → C
— — — — —
C → (#xx:3 of Rd8)
— — — — — —
2
C → (#xx:3 of @ERd24)
— — — — — —
8
C → (#xx:3 of @aa:8)
— — — — — —
8
¬ C → (#xx:3 of Rd8)
— — — — — —
2
¬ C → (#xx:3 of @ERd24)
— — — — — —
8
¬ C → (#xx:3 of @aa:8)
— — — — — —
8
C∧(#xx:3 of Rd8) → C
— — — — —
2
C∧(#xx:3 of @ERd24) → C
— — — — —
C∧(#xx:3 of @aa:8) → C
— — — — —
C∧ ¬ (#xx:3 of Rd8) → C
— — — — —
C∧ ¬ (#xx:3 of @ERd24) → C — — — — —
4
4
2
4
4
2
C∧ ¬ (#xx:3 of @aa:8) → C
— — — — —
C∨(#xx:3 of Rd8) → C
— — — — —
C∨(#xx:3 of @ERd24) → C
— — — — —
C∨(#xx:3 of @aa:8) → C
— — — — —
C∨ ¬ (#xx:3 of Rd8) → C
— — — — —
C∨ ¬ (#xx:3 of @ERd24) → C — — — — —
4
4
2
4
4
2
C∨ ¬ (#xx:3 of @aa:8) → C
— — — — —
C⊕(#xx:3 of Rd8) → C
— — — — —
C⊕(#xx:3 of @ERd24) → C
— — — — —
C⊕(#xx:3 of @aa:8) → C
— — — — —
C⊕ ¬ (#xx:3 of Rd8) → C
— — — — —
C⊕ ¬ (#xx:3 of @ERd24) → C — — — — —
4
4
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
↔ ↔ ↔ ↔ ↔
BLD #xx:3, @ERd
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C⊕ ¬ (#xx:3 of @aa:8) → C
— — — — —
6
2
6
6
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Rev. 1.00 Dec. 19, 2007 Page 473 of 520
REJ09B0409-0100
Appendix
6. Branching Instructions
Bcc
No. of
States*1
Condition Code
BRA d:8 (BT d:8)
—
2
BRA d:16 (BT d:16)
—
4
BRN d:8 (BF d:8)
—
2
BRN d:16 (BF d:16)
—
4
BHI d:8
—
2
BHI d:16
—
4
BLS d:8
—
2
BLS d:16
—
4
BCC d:8 (BHS d:8)
—
2
BCC d:16 (BHS d:16)
—
4
BCS d:8 (BLO d:8)
—
2
BCS d:16 (BLO d:16)
—
4
BNE d:8
—
2
BNE d:16
—
4
BEQ d:8
—
2
BEQ d:16
—
4
BVC d:8
—
2
BVC d:16
—
4
BVS d:8
—
2
BVS d:16
—
4
BPL d:8
—
2
BPL d:16
—
4
BMI d:8
—
2
BMI d:16
—
4
BGE d:8
—
2
BGE d:16
—
4
BLT d:8
—
2
BLT d:16
—
BGT d:8
I
H
N
Z
V
C
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
4
— — — — — —
6
—
2
Z∨ (N⊕V) = 0 — — — — — —
4
BGT d:16
—
4
— — — — — —
6
BLE d:8
—
2
Z∨ (N⊕V) = 1 — — — — — —
4
BLE d:16
—
4
— — — — — —
6
Rev. 1.00 Dec. 19, 2007 Page 474 of 520
REJ09B0409-0100
If condition Always
is true then
PC ← PC+d
Never
else next;
Advanced
Branch
Condition
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C∨ Z = 0
C∨ Z = 1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Appendix
JMP
BSR
JSR
RTS
JMP @ERn
—
JMP @aa:24
—
JMP @@aa:8
—
BSR d:8
—
BSR d:16
—
JSR @ERn
—
JSR @aa:24
—
JSR @@aa:8
—
RTS
—
No. of
States*1
Condition Code
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
PC ← ERn
— — — — — —
PC ← aa:24
— — — — — —
PC ← @aa:8
— — — — — —
8
10
2
PC → @–SP
PC ← PC+d:8
— — — — — —
6
8
4
PC → @–SP
PC ← PC+d:16
— — — — — —
8
10
PC → @–SP
PC ← ERn
— — — — — —
6
8
PC → @–SP
PC ← aa:24
— — — — — —
8
10
PC → @–SP
PC ← @aa:8
— — — — — —
8
12
2 PC ← @SP+
— — — — — —
8
10
2
4
2
2
4
2
4
6
Rev. 1.00 Dec. 19, 2007 Page 475 of 520
REJ09B0409-0100
Appendix
7. System Control Instructions
@(d:24, ERs) → CCR
LDC @ERs+, CCR
W
LDC @aa:16, CCR
W
6
@aa:16 → CCR
LDC @aa:24, CCR
W
8
@aa:24 → CCR
@ERs → CCR
ERs32+2 → ERs32
4
2
↔
↔
↔
↔
Advanced
↔
Normal
↔
↔ ↔ ↔ ↔ ↔
10
↔
W
↔ ↔
LDC @(d:24, ERs), CCR
↔ ↔ ↔ ↔ ↔
@(d:16, ERs) → CCR
↔
6
↔ ↔
W
↔ ↔ ↔ ↔ ↔
LDC @(d:16, ERs), CCR
@ERs → CCR
4
↔
W
10
2
↔ ↔
LDC @ERs, CCR
Rs8 → CCR
2
C
↔ ↔ ↔ ↔ ↔
B
V
↔
B
LDC Rs, CCR
Z
↔ ↔
#xx:8 → CCR
2
LDC #xx:8, CCR
N
↔ ↔ ↔ ↔ ↔
Transition to powerdown state
H
↔ ↔ ↔ ↔ ↔
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
—
I
2
2
6
8
12
8
8
10
CCR → Rd8
2
CCR → @ERd
6
6
CCR → @(d:16, ERd)
8
STC CCR, @(d:24, ERd)
W
10
CCR → @(d:24, ERd)
12
STC CCR, @–ERd
W
ERd32–2 → ERd32
CCR → @ERd
8
STC CCR, @aa:16
W
6
CCR → @aa:16
8
STC CCR, @aa:24
W
8
CCR → @aa:24
10
ANDC ANDC #xx:8, CCR
B
2
CCR∧#xx:8 → CCR
B
2
CCR∨#xx:8 → CCR
B
2
CCR⊕#xx:8 → CCR
ORC
ORC #xx:8, CCR
XORC XORC #xx:8, CCR
NOP
NOP
4
—
Rev. 1.00 Dec. 19, 2007 Page 476 of 520
REJ09B0409-0100
2 PC ← PC+2
↔ ↔ ↔
W
↔ ↔ ↔
STC CCR, @(d:16, ERd)
4
↔ ↔ ↔
W
↔ ↔ ↔
B
STC CCR, @ERd
↔ ↔ ↔
STC CCR, Rd
↔ ↔ ↔
STC
CCR ← @SP+
PC ← @SP+
↔
LDC
—
↔
SLEEP SLEEP
Condition Code
Operation
↔ ↔
RTE
No. of
States*1
↔ ↔
RTE
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
Appendix
8. Block Transfer Instructions
EEPMOV
No. of
States*1
H
N
Z
V
C
Normal
—
@@aa
@(d, PC)
I
EEPMOV. B
—
4 if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
— — — — — — 8+
4n*2
EEPMOV. W
—
4 if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next
— — — — — — 8+
4n*2
Advanced
Condition Code
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases, see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1)
(2)
(3)
(4)
(5)
Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
Retains its previous value when the result is zero; otherwise cleared to 0.
Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 1.00 Dec. 19, 2007 Page 477 of 520
REJ09B0409-0100
REJ09B0409-0100
Rev. 1.00 Dec. 19, 2007 Page 478 of 520
MULXU
5
STC
Table A.2
(2)
LDC
3
SUBX
OR
XOR
AND
MOV
C
D
E
F
BILD
BIST
BLD
BST
TRAPA
BEQ
B
BIAND
BAND
AND
RTE
BNE
CMP
BIXOR
BXOR
XOR
BSR
BCS
A
BIOR
BOR
OR
RTS
BCC
MOV.B
Table A.2
(2)
LDC
7
ADDX
BTST
DIVXU
BLS
AND.B
ANDC
6
9
BCLR
MULXU
BHI
XOR.B
XORC
5
ADD
BNOT
DIVXU
BRN
OR.B
ORC
4
8
7
BSET
BRA
6
2
1
Table A.2 Table A.2 Table A.2 Table A.2
(2)
(2)
(2)
(2)
NOP
4
3
2
1
0
0
MOV
BVS
9
JMP
BPL
BMI
MOV
BSR
CMP
Table A.2 Table A.2
(2)
(2)
BGE
C
MOV
B
Table A.2 Table A.2
(2)
(2)
A
Table A.2 Table A.2
EEPMOV
(2)
(2)
SUB
ADD
Table A.2
(2)
BVC
8
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
E
JSR
BGT
SUBX
ADDX
Table A.2
(3)
BLT
D
BLE
Table A.2
(2)
Table A.2
(2)
F
Table A.2
AL
1st byte 2nd byte
AH AL BH BL
A.2
AH
Instruction code:
Appendix
Operation Code Map
Operation Code Map (1)
MOV
7A
BRA
58
MOV
DAS
1F
79
SUBS
1B
1
ADD
ADD
BRN
NOT
17
DEC
ROTXR
13
1A
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
CMP
CMP
BHI
2
SUB
SUB
BLS
NOT
ROTXR
ROTXL
SHLR
SHLL
3
4
OR
OR
BCC
LDC/STC
1st byte 2nd byte
AH AL BH BL
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
6
BEQ
DEC
EXTU
INC
7
BVC
SUB
NEG
9
BVS
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
BPL
A
MOV
BMI
NEG
CMP
SUB
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A-2 Table A-2
(3)
(3)
ADD
SHAL
B
BGT
E
BLE
DEC
EXTS
INC
Table A-2
(3)
F
Table A.2
BH
AH AL
Instruction code:
Appendix
Operation Code Map (2)
Rev. 1.00 Dec. 19, 2007 Page 479 of 520
REJ09B0409-0100
REJ09B0409-0100
Rev. 1.00 Dec. 19, 2007 Page 480 of 520
DIVXS
3
BSET
7Faa7 * 2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 * 2
BTST
BCLR
7Eaa7 * 2
BNOT
BTST
BSET
7Dr07 * 1
7Eaa6 * 2
BSET
7Dr06 * 1
BTST
BCLR
MULXS
2
7Cr07 * 1
BNOT
DIVXS
1
BTST
MULXS
0
7Cr06 * 1
01F06
01D05
01C05
01406
CL
BIOR
BOR
BIOR
BOR
OR
4
BIXOR
BXOR
BIXOR
BXOR
XOR
5
BIAND
BAND
BIAND
BAND
AND
6
7
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
LDC
STC
F
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Table A.2
AH
ALBH
BLCH
Instruction code:
Appendix
Operation Code Map (3)
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
L=M=N=0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 1.00 Dec. 19, 2007 Page 481 of 520
REJ09B0409-0100
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
Note:
*
1
Depends on which on-chip peripheral module is accessed. See section 16.1, Register
Addresses (Address Order).
Rev. 1.00 Dec. 19, 2007 Page 482 of 520
REJ09B0409-0100
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction
Fetch
I
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W #xx:16, Rd
2
ADD.W Rs, Rd
1
ADD.L #xx:32, ERd
3
ADD.L ERs, ERd
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
1
ADDX Rs, Rd
1
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
AND.W #xx:16, Rd
2
AND.W Rs, Rd
1
AND.L #xx:32, ERd
3
AND
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
AND.L ERs, ERd
2
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @ERd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
Bcc
Word Data
Access
M
Internal
Operation
N
Rev. 1.00 Dec. 19, 2007 Page 483 of 520
REJ09B0409-0100
Appendix
Instruction Mnemonic
Bcc
BCLR
BIAND
BILD
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Stack
Access
Access
Operation
I
J
L
M
N
K
BLT d:8
2
BGT d:8
2
BLE d:8
2
BRA d:16(BT d:16)
2
2
BRN d:16(BF d:16)
2
2
BHI d:16
2
2
BLS d:16
2
2
BCC d:16(BHS d:16)
2
2
BCS d:16(BLO d:16)
2
2
BNE d:16
2
2
BEQ d:16
2
2
BVC d:16
2
2
BVS d:16
2
2
BPL d:16
2
2
BMI d:16
2
2
BGE d:16
2
2
BLT d:16
2
2
BGT d:16
2
2
BLE d:16
2
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @ERd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @ERd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @ERd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @ERd
2
1
BILD #xx:3, @aa:8
2
1
Rev. 1.00 Dec. 19, 2007 Page 484 of 520
REJ09B0409-0100
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
BIOR
BIOR #xx:3, Rd
1
BIOR #xx:3, @ERd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @ERd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @ERd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @ERd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @ERd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @ERd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @ERd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @ERd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @ERd
2
2
BSET Rn, @aa:8
2
2
BSR d:8
2
1
BSR d:16
2
1
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
Stack
K
2
BST #xx:3, Rd
1
BST #xx:3, @ERd
2
2
BST #xx:3, @aa:8
2
2
Rev. 1.00 Dec. 19, 2007 Page 485 of 520
REJ09B0409-0100
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
BTST
BTST #xx:3, Rd
1
BTST #xx:3, @ERd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @ERd
2
1
1
BXOR
CMP
Stack
K
BTST Rn, @aa:8
2
BXOR #xx:3, Rd
1
BXOR #xx:3, @ERd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W #xx:16, Rd
2
CMP.W Rs, Rd
1
CMP.L #xx:32, ERd
3
CMP.L ERs, ERd
1
DAA
DAA Rd
1
DAS
DAS Rd
1
DEC
DEC.B Rd
1
DEC.W #1/2, Rd
1
DEC.L #1/2, ERd
1
DIVXS.B Rs, Rd
2
12
DIVXS.W Rs, ERd
2
20
DIVXU.B Rs, Rd
1
12
DIVXU.W Rs, ERd
1
DUVXS
DIVXU
EEPMOV
EXTS
EXTU
20
1
EEPMOV.B
2
2n+2*
EEPMOV.W
2
2n+2*1
EXTS.W Rd
1
EXTS.L ERd
1
EXTU.W Rd
1
EXTU.L ERd
1
Rev. 1.00 Dec. 19, 2007 Page 486 of 520
REJ09B0409-0100
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
INC
INC.B Rd
1
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8
2
JSR @ERn
2
1
JSR @aa:24
2
1
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
[email protected], CCR
2
1
[email protected](d:16, ERs), CCR
3
1
[email protected](d:24,ERs), CCR
5
1
[email protected]+, CCR
2
1
[email protected]:16, CCR
3
1
[email protected]:24, CCR
4
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd
2
1
MOV.B @(d:24, ERs), Rd
4
1
MOV.B @ERs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @Erd
1
1
MOV.B Rs, @(d:16, ERd)
2
1
MOV.B Rs, @(d:24, ERd)
4
1
MOV.B Rs, @-ERd
1
1
MOV.B Rs, @aa:8
1
1
JMP
JSR
LDC
MOV
Stack
K
2
2
1
1
2
1
2
2
2
Rev. 1.00 Dec. 19, 2007 Page 487 of 520
REJ09B0409-0100
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
MOV
MOV.B Rs, @aa:16
2
1
MOV.B Rs, @aa:24
3
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
1
MOV.W @(d:16,ERs), Rd
2
1
MOV.W @(d:24,ERs), Rd
4
1
MOV.W @ERs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W @aa:24, Rd
3
1
MOV.W Rs, @ERd
1
1
MOV.W Rs, @(d:16,ERd)
2
1
MOV.W Rs, @(d:24,ERd)
4
1
MOV.W Rs, @-ERd
1
1
MOV.W Rs, @aa:16
2
1
MOV.W Rs, @aa:24
3
1
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
2
MOV.L @(d:16,ERs), ERd
3
2
MOV.L @(d:24,ERs), ERd
5
2
MOV.L @ERs+, ERd
2
2
MOV.L @aa:16, ERd
3
2
MOV.L @aa:24, ERd
4
2
MOV.L ERs,@ERd
2
2
MOV.L ERs, @(d:16,ERd)
3
2
MOV.L ERs, @(d:24,ERd)
5
2
MOV.L ERs, @-ERd
2
2
MOV.L ERs, @aa:16
3
2
4
2
MOV
MOV.L ERs, @aa:24
2
Stack
K
MOVFPE
MOVFPE @aa:16, Rd*
2
1
MOVTPE
MOVTPE Rs,@aa:16*2
2
1
Rev. 1.00 Dec. 19, 2007 Page 488 of 520
REJ09B0409-0100
2
2
2
2
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
MULXS
MULXS.B Rs, Rd
2
MULXS.W Rs, ERd
2
20
MULXU
MULXU.B Rs, Rd
1
12
MULXU.W Rs, ERd
1
20
NEG.B Rd
1
NEG.W Rd
1
NEG
NEG.L ERd
1
NOP
NOP
1
NOT
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
OR
Stack
K
12
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
OR.W #xx:16, Rd
2
OR.W Rs, Rd
1
OR.L #xx:32, ERd
3
OR.L ERs, ERd
2
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
1
1
2
POP.L ERn
2
2
2
PUSH.W Rn
1
1
2
PUSH.L ERn
2
2
2
ROTL.B Rd
1
ROTL.W Rd
1
ROTL.L ERd
1
ROTR.B Rd
1
ROTR.W Rd
1
ROTR.L ERd
1
ROTXL.B Rd
1
ROTXL.W Rd
1
ROTXL.L ERd
1
PUSH
ROTL
ROTR
ROTXL
Rev. 1.00 Dec. 19, 2007 Page 489 of 520
REJ09B0409-0100
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
ROTXR
ROTXR.B Rd
1
ROTXR.W Rd
1
ROTXR.L ERd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAL.W Rd
1
SHAL.L ERd
1
SHAR.B Rd
1
SHAR.W Rd
1
SHAR.L ERd
1
SHAR
SHLL
SHLR
SHLL.B Rd
1
SHLL.W Rd
1
SHLL.L ERd
1
SHLR.B Rd
1
SHLR.W Rd
1
Stack
K
SHLR.L ERd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16,ERd)
3
1
STC CCR, @(d:24,ERd)
5
1
STC CCR,@-ERd
2
1
STC CCR, @aa:16
3
1
STC CCR, @aa:24
4
1
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
SUB.L ERs, ERd
1
SUBS #1/2/4, ERd
1
SUB
SUBS
Rev. 1.00 Dec. 19, 2007 Page 490 of 520
REJ09B0409-0100
2
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
SUBX
SUBX #xx:8, Rd
1
SUBX. Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC #xx:8, CCR
1
XOR
XORC
Stack
K
Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1
times respectively.
2. It cannot be used in this LSI.
Rev. 1.00 Dec. 19, 2007 Page 491 of 520
REJ09B0409-0100
Appendix
A.4
Combinations of Instructions and Addressing Modes
Table A.5
Combinations of Instructions and Addressing Modes
—
Arithmetic
operations
BWL BWL
WL BWL
B
B
—
L
— BWL
—
B
— BW
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
MULXS,
DIVXU,
DIVXS
NEG
EXTU, EXTS
Logical
AND, OR, XOR
operations NOT
Shift operations
Bit manipulations
Branching
BCC, BSR
instructions JMP, JSR
System
control
instructions
RTS
RTE
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Block data transfer instructions
—
—
—
—
—
—
—
—
—
—
—
B
—
B
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
BWL BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
WL
BWL
BWL
BWL
B
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
B
—
W
W
—
W
W
—
W
W
—
W
W
—
—
—
—
W
W
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 1.00 Dec. 19, 2007 Page 492 of 520
REJ09B0409-0100
—
—
@@aa:8
B
—
@(d:16.PC)
BWL BWL BWL BWL BWL BWL
—
—
—
—
—
—
—
—
—
—
—
—
@(d:8.PC)
Data
MOV
transfer
POP, PUSH
instructions
MOVFPE,
MOVTPE
@aa:24
@aa:16
@aa:8
@ERn+/@ERn
@(d:24.ERn)
@ERn
Rn
Instructions
#xx
Functions
@(d:16.ERn)
Addressing Mode
—
—
BW
Appendix
B.
I/O Port Block Diagrams
B.1
Block Diagrams of Port 1
SBY (low level during
reset and in standby
mode)
PUCR1n
VCC
PMR1n
P1n
PDR1n
VSS
Internal data bus
VCC
PCR1n
IRQm
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
PUCR1: Port pull-up control register 1
n = 7 and 4
m = 4 and 3
Figure B.1(a) Port 1 Block Diagram (Pins P17 and P14)
Rev. 1.00 Dec. 19, 2007 Page 493 of 520
REJ09B0409-0100
Appendix
SBY
PUCR13
PMR13
PDR13
P13
Internal data bus
VCC
VCC
PCR13
VSS
Timer G
module
TMIG
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
PUCR1: Port pull-up control register 1
Figure B.1(b) Port 1 Block Diagram (Pin P13)
Rev. 1.00 Dec. 19, 2007 Page 494 of 520
REJ09B0409-0100
Appendix
B.2
Block Diagrams of Port 3
SBY
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
Internal data bus
VCC
PCR3n
AEC module
AEVH(P36)
AEVL(P37)
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n = 7 and 6
Figure B.2(a) Port 3 Block Diagram (Pins P37 and P36)
Rev. 1.00 Dec. 19, 2007 Page 495 of 520
REJ09B0409-0100
Appendix
SBY
PUCR35
VCC
PMR25
P35
PDR35
VSS
PDR3:
Port data register 3
PCR3:
Port control register 3
PUCR3:
Port pull-up control register 3
PMR2
Port mode register 2
PCR35
Figure B.2(b) Port 3 Block Diagram (Pin P35)
Rev. 1.00 Dec. 19, 2007 Page 496 of 520
REJ09B0409-0100
Internal data bus
VCC
Appendix
SBY
PUCR3n
VCC
P3n
PDR3n
Internal data bus
VCC
PCR3n
VSS
PDR3: Port data register 3
PCR3: Port control register 3
n = 4 and 3
Figure B.2(c) Port 3 Block Diagram (Pins P34 and P33)
Rev. 1.00 Dec. 19, 2007 Page 497 of 520
REJ09B0409-0100
Appendix
SBY
TMOFH (P32)
TMOFL (P31)
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
PCR3n
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 2 and 1
Figure B.2(d) Port 3 Block Diagram (Pins P32 and P31)
Rev. 1.00 Dec. 19, 2007 Page 498 of 520
REJ09B0409-0100
Internal data bus
VCC
Appendix
SBY
PUCR30
VCC
PMR30
PDR30
P30
Internal data bus
VCC
PCR30
VSS
Timer C
module
UD
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
Figure B.2(e) Port 3 Block Diagram (Pin P30)
Rev. 1.00 Dec. 19, 2007 Page 499 of 520
REJ09B0409-0100
Appendix
B.3
Block Diagrams of Port 4
Internal data bus
PMR20
P43
IRQ0
PMR2: Port mode register 2
Figure B.3(a) Port 4 Block Diagram (Pin P43)
Rev. 1.00 Dec. 19, 2007 Page 500 of 520
REJ09B0409-0100
Appendix
SBY
SCINV3
VCC
SPC32
SCI3 module
TXD32
P42
PCR42
VSS
Internal data bus
PDR42
PDR4: Port data register 4
PCR4: Port control register 4
Figure B.3(b) Port 4 Block Diagram (Pin P42)
Rev. 1.00 Dec. 19, 2007 Page 501 of 520
REJ09B0409-0100
Appendix
SBY
VCC
SCI3 module
RE32
RXD32
P41
PCR41
VSS
SCINV2
PDR4: Port data register 4
PCR4: Port control register 4
Figure B.3(c) Port 4 Block Diagram (Pin P41)
Rev. 1.00 Dec. 19, 2007 Page 502 of 520
REJ09B0409-0100
Internal data bus
PDR41
Appendix
SBY
SCI3 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR40
VSS
Internal data bus
PDR40
PDR4: Port data register 4
PCR4: Port control register 4
Figure B.3(d) Port 4 Block Diagram (Pin P40)
Rev. 1.00 Dec. 19, 2007 Page 503 of 520
REJ09B0409-0100
Appendix
B.4
Block Diagram of Port 5
SBY
PUCR5n
VCC
VCC
P5n
PDR5n
VSS
PCR5n
Internal data bus
PMR5n
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure B.4 Port 5 Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 504 of 520
REJ09B0409-0100
Appendix
B.5
Block Diagram of Port 6
SBY
VCC
PDR6n
VCC
PCR6n
P6n
Internal data bus
PUCR6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure B.5 Port 6 Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 505 of 520
REJ09B0409-0100
Appendix
B.6
Block Diagram of Port 7
SBY
PDR7n
PCR7n
P7n
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure B.6 Port 7 Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 506 of 520
REJ09B0409-0100
Internal data bus
VCC
Appendix
B.7
Block Diagram of Port 8
VCC
PDR8n
PCR8n
P8n
Internal data bus
SBY
VSS
PDR8: Port data register 8
PCR8: Port control register 8
n = 7 to 0
Figure B.7 Port 8 Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 507 of 520
REJ09B0409-0100
Appendix
B.8
Block Diagrams of Port 9
PWM module
PWMn+1
Internal data bus
SBY
PMR9n
P9n
PDR9n
VSS
PDR9: Port data register 9
n = 1 and 0
Figure B.8(a) Port 9 Block Diagram (Pins P91 and P90)
P9n
PDR9n
VSS
PDR9: Port data register 9
n = 5 to 2
Figure B.8(b) Port 9 Block Diagram (Pins P95 to P92)
Rev. 1.00 Dec. 19, 2007 Page 508 of 520
REJ09B0409-0100
Internal data bus
SBY
Appendix
P93
PDR93
Internal data bus
SBY
VSS
LVD module
VREFSEL
Vref
PDR9: Port data register 9
Figure B.8(c) Port 9 Block Diagram (Pins P93)
Rev. 1.00 Dec. 19, 2007 Page 509 of 520
REJ09B0409-0100
Appendix
B.9
Block Diagram of Port A
SBY
VCC
PCRAn
PAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure B.9 Port A Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 510 of 520
REJ09B0409-0100
Internal data bus
PDRAn
Appendix
B.10
Block Diagrams of Port B
Internal
data bus
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 7 to 0
Figure B.10(a) Port B Block Diagram
Rev. 1.00 Dec. 19, 2007 Page 511 of 520
REJ09B0409-0100
Appendix
Internal
data bus
PB0
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTDSEL
extD
Figure B.10(b) Port B Block Diagram (Pin PB0)
Rev. 1.00 Dec. 19, 2007 Page 512 of 520
REJ09B0409-0100
Appendix
Internal
data bus
PB1
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTUSEL
extU
Figure B.10(c) Port B Block Diagram (Pin PB1)
Rev. 1.00 Dec. 19, 2007 Page 513 of 520
REJ09B0409-0100
Appendix
C.
Port States in the Different Processing States
Table C.1
Port
Port States Overview
Reset
Sleep
Subsleep
Standby
Watch
Subactive Active
P17,
High
Retained
P14, P13 impedance
Retained
High
impedance*
Retained
Functions
Functions
P37 to
P30
High
Retained
impedance
Retained
High
impedance*
Retained
Functions
Functions
P43 to
P40
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P57 to
P50
High
Retained
impedance
Retained
High
impedance*
Retained
Functions
Functions
P67 to
P60
High
Retained
impedance
Retained
High
impedance*
Retained
Functions
Functions
P77 to
P70
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P87 to
P80
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P95 to
P90
High
Retained
impedance
Retained
High
impedance*
Retained
Functions
Functions
PA3 to
PA0
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
PB7 to
PB0
High
High
High
High
impedance impedance impedance impedance
Note:
*
High level output when MOS pull-up is in on state.
Rev. 1.00 Dec. 19, 2007 Page 514 of 520
REJ09B0409-0100
High
High
High
impedance impedance impedance
Appendix
D.
List of Product Codes
Table D.1
Product Code Lineup
Product Type
H8/38524
Group
H8/38524
Flash
memory
versions
Regular
specifications
Wide-range
specifications
Mask ROM
versions
Regular
specifications
H8/38522
Mask ROM
versions
Flash
memory
versions
H8/38520
Mask ROM
versions
Mask ROM
versions
HD64F38524H
F38524H
80-pin QFP (FP-80A)
HD64F38524W
F38524W
80-pin TQFP (TFP-80C)
HD64F38524HW
F38524H
80-pin QFP (FP-80A)
HD64F38524WW
F38524W
80-pin TQFP (TFP-80C)
HD64338524H
38524(***)H
80-pin QFP (FP-80A)
HD64338524W
38524(***)W
80-pin TQFP (TFP-80C)
38524(***)H
80-pin QFP (FP-80A)
38524(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64338523H
38523(***)H
80-pin QFP (FP-80A)
HD64338523W
38523(***)W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64338523HW
38523(***)H
80-pin QFP (FP-80A)
Regular
specifications
Regular
specifications
HD64338523WW
38523(***)W
80-pin TQFP (TFP-80C)
HD64F38522H
F38522H
80-pin QFP (FP-80A)
HD64F38522W
F38522W
80-pin TQFP (TFP-80C)
HD64F38522HW
F38522H
80-pin QFP (FP-80A)
HD64F38522WW
F38522W
80-pin TQFP (TFP-80C)
HD64338522H
38522(***)H
80-pin QFP (FP-80A)
HD64338522W
38522(***)W
80-pin TQFP (TFP-80C)
HD64338522HW
38522(***)H
80-pin QFP (FP-80A)
HD64338522WW
38522(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64338521H
38521(***)H
80-pin QFP (FP-80A)
HD64338521W
38521(***)W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64338521HW
38521(***)H
80-pin QFP (FP-80A)
80-pin TQFP (TFP-80C)
Wide-range
specifications
H8/38521
Package
(Package Code)
HD64338524HW
Wide-range
specifications
Mask ROM
versions
Mark Code
HD64338524WW
Wide-range
specifications
H8/38523
Product Code
Regular
specifications
Wide-range
specifications
HD64338521WW
38521(***)W
HD64338520H
38520(***)H
80-pin QFP (FP-80A)
HD64338520W
38520(***)W
80-pin TQFP (TFP-80C)
HD64338520HW
38520(***)H
80-pin QFP (FP-80A)
HD64338520WW
38520(***)W
80-pin TQFP (TFP-80C)
Note: (***) is the ROM code.
Rev. 1.00 Dec. 19, 2007 Page 515 of 520
REJ09B0409-0100
Appendix
E.
Package Dimensions
Dimensional drawings of the packages FP-80A and TFP-80C are shown in figures E.1 and E.2,
below.
JEITA Package Code
P-QFP80-14x14-0.65
RENESAS Code
PRQP0080JB-A
Previous Code
FP-80A/FP-80AV
MASS[Typ.]
1.2g
HD
*1
D
60
41
61
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
40
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
ZE
Min
21
80
1
c
A
F
A2
20
ZD
θ
A1
L
L1
Detail F
e
*3
y
bp
x
M
Figure E.1 FP-80A Package Dimensions
Rev. 1.00 Dec. 19, 2007 Page 516 of 520
REJ09B0409-0100
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
14
14
2.70
16.9 17.2 17.5
16.9 17.2 17.5
3.05
0.00 0.10 0.25
0.24 0.32 0.40
0.30
0.12 0.17 0.22
0.15
0°
8°
0.65
0.12
0.10
0.83
0.83
0.5 0.8 1.1
1.6
Appendix
JEITA Package Code
P-TQFP80-12x12-0.50
RENESAS Code
PTQP0080KC-A
Previous Code
TFP-80C/TFP-80CV
MASS[Typ.]
0.4g
HD
*1
D
60
41
61
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
40
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
ZE
F
c
A2
Index mark
A
20
1
ZD
θ
A1
L
L1
e
*3
y
bp
Detail F
x
M
Nom Max
12
12
1.00
13.8 14.0 14.2
13.8 14.0 14.2
1.20
0.00 0.10 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
0°
8°
0.5
0.10
0.10
1.25
1.25
0.4 0.5 0.6
1.0
Min
21
80
D
E
A2
HD
H1
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Figure E.2 TFP-80C Package Dimensions
Rev. 1.00 Dec. 19, 2007 Page 517 of 520
REJ09B0409-0100
Appendix
Rev. 1.00 Dec. 19, 2007 Page 518 of 520
REJ09B0409-0100
Index
A
I
ADRRH .................................................. 364
ADRRL................................................... 364
ADSR ..................................................... 366
AEGSR ................................................... 285
AMR ....................................................... 364
ICRGF..................................................... 254
ICRGR .................................................... 254
IEGR ......................................................... 59
IENR1 ....................................................... 61
IENR2 ....................................................... 63
IRR1.......................................................... 65
IRR2.......................................................... 67
IWPR ........................................................ 69
B
BRR ........................................................ 317
L
C
CKSTPR1 ........218, 226, 240, 257, 323, 367
CKSTPR2 ................277, 292, 358, 388, 407
E
EBR ........................................................ 134
ECCR...................................................... 287
ECCSR ................................................... 288
ECH ........................................................ 291
ECL......................................................... 292
ECPWCRH............................................. 283
ECPWCRL ............................................. 283
ECPWDRH............................................. 284
ECPWDRL ............................................. 284
LCR......................................................... 384
LCR2....................................................... 386
LPCR ...................................................... 382
LVDCNT ................................................ 407
LVDCR................................................... 402
LVDSR ................................................... 405
O
OCRF ...................................................... 234
OCRFH ................................................... 234
OCRFL.................................................... 234
OSCCR ..................................................... 86
P
F
FENR...................................................... 135
FLMCR1................................................. 130
FLMCR2................................................. 133
FLPWCR ................................................ 134
PCR1....................................................... 166
PCR3....................................................... 173
PCR4....................................................... 180
PCR5....................................................... 184
PCR6....................................................... 189
PCR7....................................................... 193
PCR8....................................................... 196
PCRA ...................................................... 202
PDR1....................................................... 166
Rev. 1.00 Dec. 19, 2007 Page 519 of 520
REJ09B0409-0100
PDR3 ...................................................... 173
PDR4 ...................................................... 180
PDR5 ...................................................... 184
PDR6 ...................................................... 189
PDR7 ...................................................... 193
PDR8 ...................................................... 196
PDR9 ...................................................... 199
PDRA ..................................................... 201
PDRB...................................................... 205
PMR1...................................................... 167
PMR2...............................168, 174, 181, 278
PMR3...................................................... 175
PMR5...................................................... 185
PMR9...................................................... 199
PMRB..................................................... 205
PUCR1.................................................... 166
PUCR3.................................................... 174
PUCR5.................................................... 185
PUCR6.................................................... 190
PWCR1................................................... 355
PWCR2................................................... 355
PWDRL1 ................................................ 355
PWDRL2 ................................................ 355
PWDRU1................................................ 355
PWDRU2................................................ 355
S
SCR3....................................................... 310
SMR........................................................ 307
SPCR .............................................. 209, 324
SSR ......................................................... 314
SYSCR1.................................................. 104
SYSCR2.................................................. 106
T
TCA ........................................................ 218
TCC ........................................................ 225
TCF ......................................................... 233
TCFH ...................................................... 233
TCFL....................................................... 233
TCG ........................................................ 253
TCRF ...................................................... 235
TCSRF .................................................... 237
TCSRW................................................... 272
TCW ....................................................... 275
TDR ........................................................ 306
TLC......................................................... 225
TMA ....................................................... 216
TMC........................................................ 223
TMG ....................................................... 255
TMW....................................................... 276
TSR......................................................... 306
R
RDR........................................................ 305
RSR ........................................................ 305
W
WEGR....................................................... 70
Rev. 1.00 Dec. 19, 2007 Page 520 of 520
REJ09B0409-0100
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/38524 Group
Publication Date: Rev.1.00, Dec. 19, 2007
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.2
H8/38524 Group
Hardware Manual
Similar pages