Exar MP7528LN Cmos dual buffered multiplying 8-bit digital-to-analog converter Datasheet

MP7528
CMOS
Dual Buffered Multiplying 8-Bit
Digital-to-Analog Converter
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
15 V CMOS Compatible
See MP7529A or MP7529B for Improved Performance
Microprocessor Controlled Gain Circuits
Microprocessor Controlled Attenuator Circuits
Microprocessor Controlled Function Generation
Precision AGC Circuits
Bus Structured Instruments
DACA/DACB determines which DAC is to be loaded. The
MP7528’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit
microprocessors.
GENERAL DESCRIPTION
The MP7528 is a dual 8-bit digital/analog converter designed
using EXAR’s proven decoded DAC architecture. It features excellent DAC-to-DAC matching and guaranteed monotonicity.
The device operates from a +5V to +15V power supply with
only 2 mA of current (maximum).
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor
for each DAC.
Data is transferred into either of the two DAC data latches via
a common 8-bit TTL/CMOS compatible input port. Control input
SIMPLIFIED BLOCK AND TIMING DIAGRAM
VDD
VREFA
RFBA
D
Q
LATCH A
E
DB7-DB0
DACA/DACB
IOUTA
DAC A
CS
WR
DGND
CS
WR
RFBB
D
Q
LATCH B
E
DB7-DB0
DACA/DACB
IOUTB
DAC B
AGND
VREFB
Rev. 2.00
1
OUT
MP7528
ORDERING INFORMATION
Package
Type
Temperature
Range
INL
(LSB)
Plastic Dip
–40 to +85°C
MP7528JN
+1
+1
+6
Plastic Dip
–40 to +85°C
MP7528KN
+1/2
+1
+4
Plastic Dip
–40 to +85°C
MP7528LN
+1/4
+1
+3
SOIC
–40 to +85°C
MP7528JS
+1
+1
+6
+4
Part No.
DNL
(LSB)
Gain Error
(LSB)
SOIC
–40 to +85°C
MP7528KS
+1/2
+1
SOIC
–40 to +85°C
MP7528LS
+1/4
+1
+3
PLCC
–40 to +85°C
MP7528JP
+1
+1
+6
PLCC
–40 to +85°C
MP7528KP
+1/2
+1
+4
PLCC
–40 to +85°C
MP7528LP
+1/4
+1
+3
Ceramic Dip
–40 to +85°C
MP7528AD
+1
+1
+6
Ceramic Dip
–40 to +85°C
MP7528BD
+1/2
+1
+4
Ceramic Dip
–40 to +85°C
MP7528CD
+1/4
+1
+3
Ceramic Dip
–55 to +125°C
MP7528SD*
+1
+1
+6
Ceramic Dip
–55 to +125°C
MP7528TD*
+1/2
+1
+4
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
AGND
IOUTA
RFBA
VREFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4
See Packaging Section for Package Dimensions
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
IOUTB
RFBB
VREFB
VDD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
1
20
2
19
3
18
4
5
6
20 Pin CDIP, PDIP (0.300”)
D20, N20
See
Pin Out
at Left
17
16
15
7
14
8
13
9
12
10
11
20 Pin SOIC (Jedec, 0.300”)
S20
Rev. 2.00
2
MP7528
PIN CONFIGURATIONS (CONT’D)
IOUTB
IOUTA
AGND
RFBA
RFBB
3
2
1
20
19
VREFA
4
18
VREFB
DGND
5
17
VDD
6
16
WR
(MSB) DB7
7
15
CS
DB6
8
14
DB0
(LSB)
DACA/DACB
9
10
11
12
13
DB5
DB3
DB1
DB4
DB2
20 Pin PLCC
P20
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
1
AGND
Analog Ground
2
IOUTA
Current Out DAC A
3
RFBA
Feedback Resistor for DAC A
4
VREFA
Reference Input for DAC A
5
DGND
Digital Ground
6
DAC A/
DAC B
DAC Select
7
DB7 (MSB)
Data Input Bit 7
8
DB6
Data Input Bit 6
9
DB5
Data Input Bit 5
10
DB4
Data Input Bit 4
11
DB3
Data Input Bit 3
12
DB2
Data Input Bit 2
13
DB1
Data Input Bit 1
14
DB0 (LSB)
Data Input Bit 0
15
CS
Chip Select
16
WR
Write
17
VDD
Power Supply
18
VREFB
Reference Input for DAC B
19
RFBB
Feedback Resistor for DAC B
20
IOUTB
Current Out DAC B
Rev. 2.00
3
MP7528
ELECTRICAL CHARACTERISTICS
(VDD = + 5 V, VREF = +10 V unless otherwise noted)
Parameter
Symbol
Min
N
8
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J, A, S
K, B, T
L, C
8
Bits
INL
LSB
+1
+1/2
+1/4
+1
+1/2
+1/4
Monotonicity
Differential Non-Linearity
J, A, S
K, B, T
L, C
Gain Error
J, A, S
K, B, T
L, C
End Point Linearity Spec.
Guaranteed over temp
DNL
+1
+1
LSB
All grades monotonic over full
temperature range.
+4
+2
+1
+6
+4
+3
LSB
Using Internal RFB
Digital Inputs = VINH
+70
ppm/°C
∆Gain/∆Temperature
ppm/%
|∆Gain/∆VDD| ∆VDD = + 5%
Digital Inputs = VINH
GE
Gain Temperature Coefficient2
TCGE
Power Supply Rejection Ratio
PSRR
+200
+400
Output Leakage Current (Pin 2)
IOUT1
+50nA
+400nA
nA
Digital Inputs = VINL
Output Leakage Current (Pin 20)
IOUT2
+50nA
+400nA
nA
Digital Inputs = VINH
15
15
kΩ
kΩ
TC = –300 ppm/°C max.
11 kΩ typical
+1
%
Input Resistance
VREFA
VREFB
8
8
15
15
Input Resistance Matching
8
8
+1
DYNAMIC PERFORMANCE2
Harmonic Distortion
Digital Crosstalk
Channel-to-Channel Isolation
AC Feedthrough at IOUT1
Glitch Energy
Propagation Delay
RL=100Ω, CL=13pF
THD
Q
–85
30
CCI
FT
Egl
tPD
–77
–70
160
220
dB
nVs
–65
270
Rev. 2.00
4
dB
dB
nVs
ns
VIN = 6VRMS @ 1 KHz
Measured for code transition
ZS to FSS
VREF = 10kHz, 20 Vp-p, sinewave
ZS to FS Input Change
From digital input to 90%
of final analog output current
MP7528
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
Symbol
Min
VIH
VIL
2.4
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
DIGITAL INPUTS3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance2
Data
Control
ILKG
0.8
+1
2.4
0.8
+10
V
V
µA
CIN
CIN
10
15
10
15
pF
pF
COUTA
COUTA
COUTB
COUTB
120
50
120
50
120
50
120
50
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
V
mA
mA
All digital inputs = 0 V or all = 5 V
All digital inputs = VIL or all = VIH
ANALOG OUTPUTS2
Output Capacitance
POWER SUPPLY5
Functional Voltage Range2
Supply Current
VDD
IDD
4.5
tCS
tCH
tAS
tAH
tDS
tDH
tWR
200
20
200
20
110
0
180
15.75
2
2
4.5
15.75
2
2
SWITCHING
CHARACTERISTICS4
Chip Select to Write Set-Up Time
Chip Select to Write Hold Time
DAC Select to Write Set-Up Time
DAC Select to Write Hold Time
Data Valid to Write Set-Up Time
Data Valid to Write Hold Time
Write Pulse Width
230
30
230
30
130
0
200
ns
ns
ns
ns
ns
ns
NOTES:
1
2
3
4
5
Full Scale Range (FSR) is 10V for unipolar mode.
Guaranteed but not production tested.
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
See timing diagram.
Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
Rev. 2.00
5
MP7528
ELECTRICAL CHARACTERISTICS
(VDD = + 15 V, VREF = +10 V unless otherwise noted)
Parameter
Symbol
Min
N
8
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J, A, S
K, B, T
L, C
8
Bits
INL
LSB
+1
+1/2
+1/4
+1
+1/2
+1/4
Monotonicity
Differential Non-Linearity
J, A, S
K, B, T
L, C
Gain Error
J, A, S
K, B, T
L, C
End Point Linearity Spec.
Guaranteed over temp
DNL
LSB
All grades monotonic over full
temperature range.
LSB
Using Internal RFB
Digital Inputs = VINH
+35
ppm/°C
∆Gain/∆Temperature
ppm/%
|∆Gain/∆VDD| ∆VDD = + 5%
Digital Inputs = VINH
+1
+1
+1
+1
+1
+1
+4
+2
+1
+5
+3
+1
GE
Gain Temperature Coefficient2
TCGE
Power Supply Rejection Ratio
PSRR
+100
+200
Output Leakage Current (Pin 2)
IOUT1
+50nA
+200nA
nA
Digital Inputs = VINL
Output Leakage Current (Pin 20)
IOUT2
+50nA
+200nA
nA
Digital Inputs = VINH
15
15
kΩ
kΩ
TC = –300 ppm/°C max.
11 kΩ typical
+1
%
Input Resistance
VREFA
VREFB
8
8
15
15
Input Resistance Matching
8
8
+1
DYNAMIC PERFORMANCE2
Harmonic Distortion
Digital Crosstalk
Channel-to-Channel Isolation
AC Feedthrough at IOUT1
Glitch Energy
Propagation Delay
RL=100Ω, CL=13pF
THD
Q
–85
60
CCI
FT
Egl
tPD
–77
–70
440
dB
nVs
100
dB
dB
nVs
ns
IILKG
1.5
+1
1.5
+10
V
V
µA
CIN
CIN
10
15
10
15
pF
pF
–65
80
DIGITAL INPUTS3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance2
Data
Control
VIH
VIL
13.5
13.5
Rev. 2.00
6
VIN = 6VRMS @ 1 KHz
Measured for code transition
ZS to FS
VREF = 10kHz, 20 Vp-p, sinewave
ZS to FS Input Change
From 50% of digital input to 90%
of final analog output current
MP7528
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
Symbol
Min
25°C
Typ
Max
Tmin to Tmax
Min
Max
120
50
120
50
120
50
120
50
Units
Test Conditions/Comments
ANALOG OUTPUTS2
Output Capacitance
COUTA
COUTA
COUTB
COUTB
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
V
mA
mA
All digital inputs = 0 V or all = 5 V
All digital inputs = VIL or all = VIH
POWER SUPPLY5
Functional Voltage Range2
Supply Current
VDD
IDD
4.5
tCS
tCH
tAS
tAH
tDS
tDH
tWR
60
10
60
10
30
0
60
15.75
2
2
4.5
15.75
2
2
SWITCHING
CHARACTERISTICS
Chip Select to Write Set-Up Time
Chip Select to Write Hold Time
DAC Select to Write Set-Up Time
DAC Select to Write Hold Time
Data Valid to Write Set-Up Time
Data Valid to Write Hold Time
Write Pulse Width
80
15
80
15
40
0
80
ns
ns
ns
ns
ns
ns
ns
NOTES:
1
2
3
4
5
Full Scale Range (FSR) is 10V for unipolar mode.
Guaranteed but not production tested.
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
See timing diagram.
Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Digital Input Voltage to DGND . . . . . . . . . . . . . –0.5 V, +17 V
VPIN2, VPIN20 to GND . . . . . . . . . . . . . . . . . . . . –0.5 V, +17 V
VREFA, VREFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25
VRFBA, VRFBB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs.) . . . . . . . . . +300°C
Package Power Dissipation Rating to 75°C
CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 900mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
3
GND refers to AGND and DGND.
Rev. 2.00
7
MP7528
Write Mode: When CS and WR are both low the selected
DAC is in the write mode. The input data latches of the selected
DAC are transparent and its analog output responds to activity
on DB0-DB7.
INTERFACE LOGIC INFORMATION
DAC Selection: Both DAC latches share a common 8-bit input port. The control input DACA/DACB selects which DAC can
accept data from the input port.
Hold Mode: The selected DAC latch retains the data which
was present on DB0-DB7 just prior to CS and WR assuming a
high state. Both analog outputs remain at the values corresponding to the data in their respective latches.
Mode Selection: Inputs CS and WR control the operating
mode of the selected DAC. See Mode Selection Table below:
DAC A/DAC B
CS
WR
DAC A
DAC B
L
H
X
X
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
L = LOW state, H = HIGH state, X = Don’t care state
Table 1. Mode Selection Table
tCH
tCS
VDD
CS
0
tAH
tAS
DAC A/DAC B
VDD
0
VDD
tWR
WR
0
tDS
DATA IN
(DB0-DB7)
VIH
VIL
VIH
VIL
tDH
DATA IN
STABLE
NOTES:
1. All input signal rise and fall times measured from 10% to 90% of VDD.
VDD = +5 V, tr = tf = 20 ns
VDD = +15 V, tr = tf = 40 ns
2. Timing measurement reference level is VIH + VIL / 2
Figure 1. Write Cycle Timing Diagram
Rev. 2.00
8
VDD
0
MP7528
MICROPROCESSOR INTERFACE
Address Bus
A0-A15
Address Bus
A8-A15
A*
VMA
CPU
6800
A*
DACA/DACB
Address
Decode
Logic
CS
DAC A
CPU
8085
A+1**
φ2
WR
MP7528
DB0
DB7
D0–D7
DACA/DACB
Address
Decode
Logic
CS
DAC A
A+1**
MP7528
WR
WR
DAC B
ALE
Latch
8212
DB0
DB7
DAC B
Data Bus
AD0–AD7
ADDR/Data Bus
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
NOTE:
8085 instruction SHLD (store H & L direct) can update
both DACS with data from H and L registers
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
Figure 2. MP7528 Dual DAC to 6800
CPU Interface
Figure 3. MP7528 Dual DAC to 8085
CPU Interface
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
5V
Graph 2. Relative Accuracy vs. Digital Code
15 V
Rev. 2.00
9
MP7528
This page left blank
Rev. 2.00
10
MP7528
20 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
D20
S1
See
Note 1
S
11
20
1
10
E1
E
D
Q
Base
Plane
Seating
Plane
A
L
b
INCHES
SYMBOL
A
e
b1
MAX
MIN
MAX
––
0.200
––
5.08
NOTES
––
b
0.014
0.023
0.356
0.584
––
b1
0.038
0.065
0.965
1.65
2
c
0.008
0.015
0.203
0.381
––
D
––
1.060
––
26.92
4
E
0.220
0.310
5.59
7.87
4
E1
0.290
0.320
7.37
8.13
7
e
0.100 BSC
2.54 BSC
5
L
0.125
0.200
3.18
5.08
––
L1
0.150
––
3.81
––
––
Q
0.015
0.070
0.381
1.78
3
S
––
0.080
––
2.03
6
0.005
––
0.13
––
6
0°
15°
0°
15°
––
S1
α
α
NOTES
MILLIMETERS
MIN
c
L1
Rev. 2.00
11
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one and is within the
shaded area shown.
2. The minimum limit for dimension b1 may be 0.023
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating
plane to the base plane.
4. This dimension allows for off-center lid, meniscus and
glass overrun.
5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines.
6. Applies to all four corners.
7. This is measured to outside of lead, not center.
MP7528
20 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
N20
S
20
11
1
10
Q1
E1
E
D
A1
Seating
Plane
A
L
B
e
B1
α
MILLIMETERS
INCHES
SYMBOL
A
MIN
MAX
MIN
MAX
––
0.200
––
5.08
A1
0.015
––
0.38
––
B
0.014
0.023
0.356
0.584
B1 (1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
0.945
1.060
24.0
26.92
E
0.295
0.325
7.49
8.26
E1
0.220
0.310
5.59
7.87
e
0.100 BSC
2.54 BSC
L
0.115
0.150
2.92
3.81
α
0°
15°
0°
15°
Q1
0.055
0.070
1.40
1.78
S
0.040
0.080
1.02
2.03
Note:
(1)
The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
Rev. 2.00
12
C
MP7528
20 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S20
D
20
11
E
H
10
h x 45°
C
A
Seating
Plane
B
e
α
A1
L
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
A
0.097
0.104
2.464
A1
0.0050
0.0115
0.127
0.292
B
0.014
0.019
0.356
0.483
C
0.0091
0.0125
0.231
0.318
D
0.500
0.510
12.70
12.95
E
0.292
0.299
7.42
7.59
e
0.050 BSC
MAX
2.642
1.27 BSC
H
0.400
0.410
10.16
10.41
h
0.010
0.016
0.254
0.406
L
0.016
0.035
0.406
0.889
α
0°
8°
0°
8°
Rev. 2.00
13
MP7528
Notes
Rev. 2.00
14
MP7528
Notes
Rev. 2.00
15
MP7528
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
16
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