TI1 BQ76PL455A 16-cell industrial integrated battery monitor Datasheet

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bq76PL455A
SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016
bq76PL455A 16-Cell Industrial Integrated Battery Monitor with Passive Cell Balancing
1 Features
2 Applications
•
•
•
•
1
•
•
•
Monitors and Balances 6-to-16 Cells per Device
Highly Accurate Monitoring
– High Performance 14-bit Analog-to-Digital
Converter (ADC) With Internal Reference
– All Cells Converted in 2.4 ms (Nominal)
– Eight AUX Inputs for Temperature and Other
Sensors with Input Voltage of 0 V to 5 V
– Internal Precision Reference
Integrated Protector With Separate Vref for
Overvoltage (OV) and Undervoltage (UV)
Comparators and Programmable VCELL Set Points
Engineered for High System Robustness
– Up to 1-Mb/s Stackable Isolated DifferentialUART
– Up to 16 ICs in Daisy-Chain With Twisted Pair
– Passes Bulk Current Injection (BCI) Test
– Designed for Robust Hot-Plug Performance
Passive Balancing with External n-FETs and
Active Balancing with EMB1428Q/EMB1499Q
Energy Storage (ESS) and UPS
E-Bikes, E-Scooters
3 Description
The bq76PL455A device is an integrated 16-cell
battery monitoring and protection device, designed for
high-reliability, high-voltage industrial applications.
The integrated high-speed, differential, capacitorisolated communications interface allows up to
sixteen bq76PL455A devices to communicate with a
host through a single high-speed Universal
Asynchronous
Receiver/Transmitter
(UART)
interface.
The bq76PL455A monitors and detects several
different fault conditions, including: overvoltage,
undervoltage, overtemperature, and communication
faults. Six GPIO ports as well as eight analog AUX
ADC inputs are included for additional monitoring and
programmable functionality. A secondary thermal
shutdown is included for further protection.
The bq76PL455A has features that customers may
find useful to help them meet functional safety
standard requirements. See Safety Manual for
bq76PL455A-Q1 (SLUUB67).
Device Information(1)
PART NUMBER
PACKAGE
bq76PL455A
TQFP (80)
BODY SIZE (NOM)
12.00 mm × 12.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
²
+
All GND connections
are local to this IC. See
text for layout details.
High
Current
Bus
All GND connections
are local to this IC. See
text for layout details.
Cell Balancing Circuits
Low Pass Filters Protection
16
16
Cell Balancing Circuits
Low Pass Filters Protection
VSENSE16
VSENSE1
VSENSE0
EQx
GND
CHP
COMML±
VM
COMML+
COMMH±
CHM
COMMH+
COMML±
OUT2
OUT1
V5VAO
VREF
VSENSE16
VSENSE1
VSENSE0
EQx
CHP
CHM
VM
OUT2
OUT1
V5VAO
VREF
COMML+
COMMH+
COMMH±
To Additional
Battery Monitors
GND
FAULTL±
FAULTH±
FAULTL+
FAULTH+
FAULTH±
FAULTL+
FAULTH+
TOP
VP
NPNB
VDIG
AUX7
GPIO (Out)
GPIO (In)
TX
RX
Texas Instruments
µC
C2000Œ
TMS570Œ
RT
RT
Cell Temperature
Measurement
AUX0
VIO
GPIO0..5
WAKEUP
FAULT_N
TX
RX
TOP
VP
NPNB
VDIG
AUX7
AUX0
VIO
GPIO0..5
WAKEUP
FAULT_N
TX
RX
Differential
Signaling
Daisy-Chain
FAULTL±
VP
I/O Power
Supply
Cell Temperature
Measurement
Highest Cell
(VSENSE16)
Highest Cell
(VSENSE16)
CAN Bus, etc.
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq76PL455A
SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics: Supply Current................. 8
VP 5.3-V Supply Regulation Voltage ........................ 9
VDD18 1.8-V Internal Digital Supply......................... 9
V5VAO Analog Supply .............................................. 9
VM –5-V Integrated Charge Pump .......................... 9
Analog-to-Digital Converter (ADC): Analog Front
End............................................................................. 9
6.11 ADC: VSENSEn Cell Measurement Inputs........... 10
6.12 ADC: VMODULE Input.............................................. 10
6.13 ADC: AUXn General Purpose Inputs .................... 10
6.14 ADC: Internal Temperature Measurement and
Thermal Shutdown (TSD) ........................................ 11
6.15 Passive Balancing Control Outputs ...................... 11
6.16 Digital Input/Output: VIO-Based Single-Ended
I/O ............................................................................ 11
6.17 Digital Input/Output: Daisy Chain Vertical Bus ..... 12
6.18 Digital Input/Output: Wakeup ................................ 12
6.19 EEPROM............................................................... 12
6.20 Secondary Protector – Window Comparators ..... 12
6.21 Power-On-Reset (POR) and FAULT Flag
Thresholds ............................................................... 13
6.22 Miscellaneous ....................................................... 13
6.23 Typical Characteristics .......................................... 14
7
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Command and Response Protocol .........................
Register Maps .........................................................
16
17
17
43
47
62
Application and Implementation ........................ 94
8.1 Application Information............................................ 94
8.2 Typical Application ................................................ 106
8.3 Initialization Set Up .............................................. 111
9
Power Supply Recommendations.................... 113
9.1 NPN LDO Supply .................................................. 113
10 Layout................................................................. 115
10.1 Layout Guidelines ............................................... 115
10.2 Layout Example .................................................. 115
10.3 Board Construction and Accuracy ...................... 116
11 Device and Documentation Support ............... 118
11.1 Device Support ..................................................
11.2 Documentation Support .....................................
11.3 Receiving Notification of Documentation
Updates..................................................................
11.4 Community Resources........................................
11.5 Trademarks .........................................................
11.6 Electrostatic Discharge Caution ..........................
11.7 Glossary ..............................................................
118
119
119
119
119
119
119
12 Mechanical, Packaging, and Orderable
Information ......................................................... 119
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2016) to Revision A
Page
•
Deleted reference to ISO26262 ............................................................................................................................................. 1
•
Changed references of automotive to industrial throughout document.................................................................................. 1
•
Added table notes to ESD Ratings table ................................................................................................................................ 7
•
Added Receiving Notification of Documentation Updates section ..................................................................................... 119
2
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5 Pin Configuration and Functions
OUT2
VR EF
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
68
67
66
65
64
63
62
61
VP
AGND3
NP NB
71
69
AGND2
72
70
AGND1
75
OUT1
NC2
76
73
TOP
77
74
EQ16
VS ENS E16
79
78
EQ15
VS ENS E15
80
PFC Package
80-Pin TQFP
Top View
VSENSE14
1
60
EQ14
2
59
AUX6
AUX7
VSENSE13
3
58
V5VAO
FAULTH+
EQ13
4
57
VSENSE12
5
56
FAULTH-
EQ12
6
55
COMMH+
VSENSE11
7
54
COMMH-
EQ11
8
53
COMML-
VSENSE10
9
52
COMML+
FAULTL-
40
38
TX
FAULT_ N
37
DG ND3
39
36
RX
35
NC1
VIO
DG ND2
41
34
20
33
GPIO5
EQ5
CHM
42
VDIG
19
32
GPIO4
VSENSE5
CHP
GPIO3
43
31
44
18
30
17
EQ6
VM
VSENSE6
29
GPIO2
DGND1
45
VS ENSE0
16
28
GPIO1
EQ7
EQ1
46
27
15
26
GPIO0
VSENSE7
EQ2
CGND
47
VS ENSE1
48
14
25
13
EQ8
24
VSENSE8
VS ENSE2
WAKEUP
23
49
EQ3
12
VS ENSE3
FAULTL+
EQ9
22
50
21
51
11
EQ4
10
VS ENSE4
EQ10
VSENSE9
Pin Functions
NAME
TYPE(1)
DESCRIPTION
PIN
NO.
AGND1
74
P
Analog Ground(2). Connect to ground plane.
AGND2
72
P
Analog Ground(2) for VREF. Internally shorted to AGND3, also make this connection externally in
the printed-circuit board (PCB) layout. Connect to ground plane.
AGND3
69
P
Analog Ground(2) for VREF. Internally shorted to AGND2, also make this connection externally in
the PCB layout. Connect to ground plane.
AUX0
66
AI
Ground referenced general-purpose analog measurement input.
AUX1
65
AI
Ground referenced general-purpose analog measurement input.
AUX2
64
AI
Ground referenced general-purpose analog measurement input.
AUX3
63
AI
Ground referenced general-purpose analog measurement input.
AUX4
62
AI
Ground referenced general-purpose analog measurement input.
AUX5
61
AI
Ground referenced general-purpose analog measurement input.
AUX6
60
AI
Ground referenced general-purpose analog measurement input.
AUX7
59
AI
Ground referenced general-purpose analog measurement input.
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Pin Functions (continued)
NAME
4
TYPE(1)
DESCRIPTION
PIN
NO.
CGND
48
P
Communication ground(2). Connect to ground plane.
CHM
33
P
Charge pump flying capacitor connection. Connect a 22-nF ceramic capacitor(3) between this pin
and CHP.
CHP
32
P
Charge pump flying capacitor connection. Connect a 22-nF ceramic capacitor(3) between this pin
and CHM.
COMMH–
54
DIO
Inverting, high-side differential connection to the COMML– pin of the higher adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
COMMH+
55
DIO
Non-inverting, high-side differential connection to the COMML+ pin of the higher adjacent module in
a daisy chain.
Leave this pin unconnected if not used.
COMML–
53
DIO
Inverting, low-side differential connection to the COMMH– pin of the lower adjacent module in a
daisy chain. Leave this pin unconnected if not used.
COMML+
52
DIO
Non-inverting, low-side differential connection to the COMMH+ pin of the lower adjacent module in a
daisy chain. Leave this pin unconnected if not used.
DGND1
30
P
Digital Ground(2). Connect to ground plane.
DGND2
35
P
Digital Ground(2). Connect to ground plane.
DGND3
37
P
Digital Ground(2). Connect to ground plane.
EQ1
28
DO
Cell Equalization control output used to drive an external N-FET balancing cell 1. May leave this pin
unconnected if not used.
EQ2
26
DO
Cell Equalization control output used to drive an external N-FET balancing cell 2. May leave this pin
unconnected if not used.
EQ3
24
DO
Cell Equalization control output used to drive an external N-FET balancing cell 3. May leave this pin
unconnected if not used.
EQ4
22
DO
Cell Equalization control output used to drive an external N-FET balancing cell 4. May leave this pin
unconnected if not used.
EQ5
20
DO
Cell Equalization control output used to drive an external N-FET balancing cell 5. May leave this pin
unconnected if not used.
EQ6
18
DO
Cell Equalization control output used to drive an external N-FET balancing cell 6. May leave this pin
unconnected if not used.
EQ7
16
DO
Cell Equalization control output used to drive an external N-FET balancing cell 7. May leave this pin
unconnected if not used.
EQ8
14
DO
Cell Equalization control output used to drive an external N-FET balancing cell 8. May leave this pin
unconnected if not used.
EQ9
12
DO
Cell Equalization control output used to drive an external N-FET balancing cell 9. May leave this pin
unconnected if not used.
EQ10
10
DO
Cell Equalization control output used to drive an external N-FET balancing cell 10. May leave this
pin unconnected if not used.
EQ11
8
DO
Cell Equalization control output used to drive an external N-FET balancing cell 11. May leave this
pin unconnected if not used.
EQ12
6
DO
Cell Equalization control output used to drive an external N-FET balancing cell 12. May leave this
pin unconnected if not used.
EQ13
4
DO
Cell Equalization control output used to drive an external N-FET balancing cell 13. May leave this
pin unconnected if not used.
EQ14
2
DO
Cell Equalization control output used to drive an external N-FET balancing cell 14. May leave this
pin unconnected if not used.
EQ15
80
DO
Cell Equalization control output used to drive an external N-FET balancing cell 15. May leave this
pin unconnected if not used.
EQ16
78
DO
Cell Equalization control output used to drive an external N-FET balancing cell 16. May leave this
pin unconnected if not used.
FAULT_N
40
DO
Single-ended active-low fault output. Leave this pin unconnected if not used.
FAULTH–
56
DI
Inverting, high-side differential connection to the FAULTL– pin of the higher adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
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Pin Functions (continued)
NAME
TYPE(1)
DESCRIPTION
57
DI
Non-inverting, high-side differential connection to the FAULTL+ pin of the higher adjacent module in
a daisy chain.
Leave this pin unconnected if not used.
FAULTL–
51
DO
Inverting, low-side differential connection to the FAULTH– pin of the lower adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
FAULTL+
50
DO
Non-inverting, low-side differential connection to the FAULTH+ pin of the lower adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
GPIO0
47
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO1
46
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO2
45
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO3
44
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO4
43
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO5
42
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input.
Do not allow GPIO pins to float when configured as inputs.
NC1
36
NC
Do not connect to this pin. This pin must remain floating for correct operation.
NC2
75
NC
Do not connect to this pin. This pin must remain floating for correct operation.
NPNB
71
AO
Internal voltage regulator controller output pin. Connect to the base of the external NPN transistor.
Leave unconnected if not used.
OUT1
73
AO
Analog multiplexer output. Connect a 390-pF filter capacitor type C0G or NP0 between this pin and
AGND. Connect externally to pin OUT2. Internally tied to pin OUT2.
OUT2
68
AI
ADC input pin. Connect externally to pin OUT1. Internally tied to pin OUT1.
DI
Single-ended UART receive input. This pin must be either:
•
Driven from a UART signal OR
•
Pulled up to VIO
Do not allow this pin to float at any time.
Power supply input and module voltage-measurement pin. Connect to the top cell of the module
through a series resistor. Requires a decoupling capacitor(3) from TOP to the ground plane. See
TOP Pin Connection for details. Locate decoupling capacitor as close to pin as possible. The lowpass filter created by the RC should have a tau similar to the low-pass filter used in the VSENSE
circuits. See VP Regulated Output or Application and Implementation for component selection
details.
PIN
NO.
FAULTH+
RX
39
TOP
76
P
TX
38
DO
V5VAO
58
P
Connection to internal 5-V always-on supply. Decouple with a 4.7-µF capacitor(3) connected to the
ground plane. Locate decoupling capacitor as close to pin as possible. This pin should not be used
to supply external circuitry.
VDIG
34
P
5.3-V Digital Supply input. Always connect VDIG to VP with 1-Ω resistor. Decouple with 4.7-µF and
0.1-µF capacitors(3) in parallel to the ground plane. Locate decoupling capacitors as close to the
VDIG pin as possible.
Single-ended UART transmit output. Leave this pin unconnected if not used.
VIO
41
P
3-V to 5-V power input for IO supply. Connect this pin to the same power supply used to drive the
source/receiver for the GPIO, FAULT_N, RX, and TX pins. Typically, connect this pin to VP/VDIG
for all devices except the base device in the stack. In the base (or single) device, this pin is typically
driven from the same supply as the microcontroller I/O pins.
If VP/VDIG is connected as the power source, this pin should be decoupled with a 0.1-µF
capacitor(3) to the digital ground plane. Place a 1-Ω resistor in series from VP to VIO. Locate the
decoupling capacitor as close to the VIO pin as possible.
If another supply is used, decouple with parallel 10-µF and 0.1-µF capacitors(3).
VM
31
P
Internal –5-V charge pump output. Decouple with 4.7-µF and 0.1-µF capacitors(3) in parallel to the
ground plane. Locate decoupling capacitor as close to pin as possible.
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Pin Functions (continued)
NAME
PIN
NO.
TYPE(1)
DESCRIPTION
VP
70
P
5.3-V regulated analog power supply input/sense pin.
Connect to external NPN transistor's emitter and decouple with a 0.1-µF capacitor(3) to AGND and a
4.7-µF capacitor(3) in series with a 0.390-Ω resistor to GND. Locate decoupling capacitors as close
to the VP pin as possible.
Always connect VDIG to VP with 1-Ω resistor.
VREF
67
P
VREF output filter pin. Decouple with parallel 0.1-µF and 1.8-µF (25 V+) capacitors(3) to the ground
plane. Locate decoupling capacitors as close to the pin as possible. To maintain measurement
fidelity, do not place external loads on this pin.
VSENSE0
29
AI
Connect to the negative pin of the 1st cell.
VSENSE1
27
AI
Channel 1. Connect to the positive pin of the 1st cell.
VSENSE2
25
AI
Channel 2. Connect to the positive pin of the 2nd cell.
VSENSE3
23
AI
Channel 3. Connect to the positive pin of the 3rd cell.
VSENSE4
21
AI
Channel 4. Connect to the positive pin of the 4th cell.
VSENSE5
19
AI
Channel 5. Connect to the positive pin of the 5th cell.
VSENSE6
17
AI
Channel 6. Connect to the positive pin of the 6th cell.
VSENSE7
15
AI
Channel 7. Connect to the positive pin of the 7th cell.
VSENSE8
13
AI
Channel 8. Connect to the positive pin of the 8th cell.
VSENSE9
11
AI
Channel 9. Connect to the positive pin of the 9th cell.
VSENSE10
9
AI
Channel 10. Connect to the positive pin of the 10th cell.
VSENSE11
7
AI
Channel 11. Connect to the positive pin of the 11th cell.
VSENSE12
5
AI
Channel 12.Connect to the positive pin of the 12th cell.
VSENSE13
3
AI
Channel 13. Connect to the positive pin of the 13th cell.
VSENSE14
1
AI
Channel 14. Connect to the positive pin of the 14th cell.
VSENSE15
79
AI
Channel 15. Connect to the positive pin of the 15th cell.
VSENSE16
77
AI
Channel 16. Connect to the positive pin of the 16th cell.
WAKEUP
49
DI
Wakeup input. Pull this pin low or tie to ground if not used. Do not allow this pin to float at any time.
(1) Key: AI = analog input; AO=analog output; DI = digital input; DO= digital output; DIO= digital I/O; P= Power; NC= no connect.
(2) Externally connected pins as common ground or GND in the design. See Grounding for details.
(3) All capacitors are type X7R or better, unless otherwise noted.
6
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6 Specifications
6.1 Absolute Maximum Ratings
over specified Ambient Temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
VP
–0.3
6
V
VDIG
–0.3
6
V
VIO
–0.3
6
V
Lesser of two MAX values
–0.3
6 or (VP + 0.3)
V
Lesser of two MAX values
–0.3
6 or (V5VAO + 0.3)
V
COMMH+, COMMH–, COMML+, COMMH–,
FAULTH+, FAULTH–, FAULTL+, FAULTL–
AC pulse specification (3) for these eight
pins only:
Vpk maximum ≤ 6.5 V for 100 ns or less,
100 kHz ≤ f ≤ 400 MHz
–0.3
6.5
Vpk
GPIO0–5
Lesser of two MAX values
–0.3
6 or (VIO + 0.3)
V
RX
Lesser of two MAX values
–0.3
6 or (VIO + 0.3)
V
–0.3
88
V
(VSENSE16 – 1 V)
(VSENSE16 + 5.5 V)
V
–0.3
0.3
V
n = 1 to 16
–0.3
5.5
n = 1 to 16, 0.1% duty cycle
–0.3
6.5
AUX0–7
TOP
(4)
TOP to VSENSE16 delta (4) (5)
(VSENSE16 + 5.5 V) ≥ TOP ≥
(VSENSE16 – 1 V)
VSENSE0
VSENSEn – VSENSEn–1
V
WAKEUP
–0.3
6
V
Ambient free-air temperature, TA
–40
105
⁰C
Junction temperature, TJ
–40
125
⁰C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise noted, voltages are given with respect to device commons (AGND1–3, DGND1–3, CGND) tied together (device VSS
or GND).
Specified by design, not tested in production.
Must meet all stated conditions for the TOP pin at all times.
Must short the highest-connected cell to the unused VSENSEn inputs above it in configurations that use < 16 cells. For example, a 14cell configuration must short pins VSENSE14, VSENSE15, VSENSE16.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
Charged-device model (CDM),per JEDEC
specification JESD22-C101 (2)
All pins
±2000
All pins except 1, 20, 21, 40, 41, 60, 61,
76, and 80
±500
Pin 76
±450
Corner pins (1, 20, 21, 40, 41, 60, 61,
and 80)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
TA = 25°C and TOP = 57.6 V; Min/Max values stated where TA = –40°C to +85⁰C and TOP = 12 V to 79.2 V (unless
otherwise noted)
MIN
VTOP
Supply voltage
VIO
Digital interface voltage
VTOP_DELTA
Max delta, TOP to highest cell
II/O
Output current, any one pin
GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, TX,
FAULT_N
II/O_T
Output current, sum of
GPIO0 + GPIO1 + GPIO2 + GPIO3 + GPIO4 + GPIO5
+ TX + FAULT_N
(1)
(2)
TOP – GND (VSENSE16 = TOP)
(1) (2)
MAX
UNIT
12
NOM
79.2
V
2.7
5.5
V
300
mV
5
mA
20
mA
VSENSE16 – TOP
0
VSENSE input measurement accuracy is degraded when VTOP_DELTA is exceeded. Delta cannot exceed the limit in the Absolute Maximum
Ratings table.
Must short the highest-connected cell to the unused VSENSEn inputs above it in configurations that use < 16 cells. For example, a 14cell configuration must short pins VSENSE14, VSENSE15, and VSENSE16.
6.4 Thermal Information
bq76PL455A
THERMAL METRIC (1)
TQFP (PFC)
UNIT
80 PINS
RθJA, High K
Junction-to-ambient thermal resistance
44.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
6.4
°C/W
RθJB
Junction-to-board thermal resistance
21.5
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
21
°C/W
RθJC(bottom)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Supply Current (1)
The following applies to all Electrical Characteristics in the following tables, unless otherwise noted: TYP values are stated in
each table where VP = VDIG = 5.3 V, VIO = 5 V, TA = 25°C and VCELL = 3.6 V (VCELL= VSENSEn – VSENSEn–1; n=1 to 16),
TOP = 57.6 V. MIN/MAX values are stated where VP = VDIG = 5.3 V, VIO = 5 V, –40°C ≤ TA ≤ 85⁰C, 1 V < VCELL < 4.95 V,
12 V ≤ TOP < 79.2 V and GND = 0 V.
MIN
TYP
MAX
IIDLE
Total input current from the monitored
cells.
PARAMETER
Power state: IDLE (2)
4
5
7
mA
ITOP_IDLE
Input current into TOP pin, IDLE mode
Power state: IDLE (2)
250
350
450
µA
ISLEEP
Total input current from the monitored
cells into TOP pin
Power state: SHUTDOWN (3)
VP = VDIG = VIO = 0 V, TOP = 57.6
22
50
IACTIVE (4)
Total input current from the monitored
cells while communicating.
Power state: IDLE plus comms (5),
differential comm capacitance 70 pF, no
load on GPIO.
IVIO_IDLE
VIO input current
Power state: IDLE (2)
ISLP_DELTA (4)
Delta ISHUTDOWN between devices in a
stack
TA = 25°C ± 5°C for all devices
(1)
(2)
(3)
(4)
(5)
8
TEST CONDITIONS
UNIT
µA
8
mA
40
µA
4
10
µA
All internal pull-up and pull-down resistors are disabled and their current is not included in parameters listed in this table.
IDLE mode defined as: device awake, ready for communications, and not communicating.
SHUTDOWN mode defined as: test conditions, no communications, no wakeup tone activity, and no FAULT heartbeat.
Specified from characterization data.
ACTIVE mode defined as: UART, differential communications link, and FAULT heartbeat active.
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6.6 VP 5.3-V Supply Regulation Voltage
Characteristics stated using NPN transistor in circuit rated at BVCEO > 100V, β ≥ 100 at 5 mA, Base-Collector C ≤ 35 pF,
ICOLLECTOR > 100 mA, RCOLLECTOR = 400 Ω.
MIN
TYP
MAX
VPVR
Regulated Voltage
PARAMETER
5.1
5.3
5.5
INPNB
External NPN base drive current
0.5
VPSD_DLY
VP/VDIG delay before SHUTDOWN (1)
30
(1)
TEST CONDITIONS
UNIT
V
mA
75
160
ms
Time measured from VP falling below threshold until the part enters SHUTDOWN, or from the part attempting to exit SHUTDOWN
(wakeup) until re-entering SHUTDOWN.
6.7 VDD18 1.8-V Internal Digital Supply (1)
PARAMETER
VDD18VO
(1)
VDD18 Output voltage (1)
TEST CONDITIONS
As measured by internal ADC
MIN
TYP
MAX
1.7
1.8
1.9
UNIT
V
Internal node only, no external access. This parameter is for internal measurement and verification purposes only.
6.8 V5VAO Analog Supply
PARAMETER
TEST CONDITIONS
V5VAOSD
Output Voltage
Power state: SHUTDOWN,
VP = VDIG = VIO = 0 V
V5VAOIDLE
Output Voltage
Power state: IDLE (1), unloaded
(1)
MIN
TYP
MAX
4
4.7
5.3
V
VDIG
V
UNIT
VDIG – 0.5
UNIT
VDIG internally connected to V5VAO in IDLE mode.
6.9 VM –5-V Integrated Charge Pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–5.5
–5
–4.5
VMVM_ON
VM Output Voltage
fCP
Charge pump switching frequency
375
kHz
VMTRIP
VM low-voltage monitor trip point
–3.8
V
VMVO
Measured value read back from ADC VM
monitor
–5.56
–5
V
–4.54
V
6.10 Analog-to-Digital Converter (ADC): Analog Front End
All ADC specifications stated are for the sampling intervals and register settings shown in Table 3. A 390-pF capacitor is on
pin OUT1.
PARAMETER
TEST CONDITIONS
MIN
OUT1RANGE
Pin OUT1 Analog Front End / Level
Shifter output voltage range
0
ROUT_PIN
OUT1 pin internal series resistance
1
TYP
1.2
MAX
UNIT
VP
V
1.35
kΩ
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6.11 ADC: VSENSEn Cell Measurement Inputs
PARAMETER
TEST CONDITIONS
VCELL_VR
Input voltage range
VCELL= VSENSEn – VSENSEn–1, n= 1
to 16
VCHERR25NB
Total Channel Measurement Accuracy at 25°C
VSENSE = 3.6 V
Total Channel Measurment Accuracy,
temperature range of 0°C to 65°C(1)(2)
VCHERR
ISENSE_SEL(3)(4)
TYP
1
MAX
UNIT
4.95
±0.75
V
mV
VSENSE = 1.5 V
–1.50
1.50
VSENSE = 2.0 V
–2.00
2.00
VSENSE = 3.3 V
–3.25
3.25
VSENSE = 3.6 V
–3.50
3.50
VSENSE = 4.2 V
–3.90
3.90
VSENSE = 4.5 V
–4.00
4.00
VSENSE = 1.5 V
–2.85
2.85
VSENSE = 2.0 V
–3.00
3.00
VSENSE = 3.3 V
–4.75
4.75
VSENSE = 3.6 V
–5.00
5.00
VSENSE = 4.2 V
–5.50
5.50
VSENSE = 4.5 V
–5.75
mV
Total Channel Measurment Accuracy,
temperature range of –40°C to 85°C(1)(2)
VCHERR
MIN
mV
VSENSEn input current n = 1 to 16
5.75
VSENSEn–1 pin; on selected channel
2
7.6
µA
ISENSE_NSEL
Channel not selected
< ±100
nA
ISENSE_SD
VSENSEn input current in
SHUTDOWN Mode
< ±100
nA
RSENSE_SEL(4)
VSENSE input resistance
Channel selected for conversion,
measured differentially
[VSENSEn–VSENSE(n–1)]
1
MΩ
OWDSR
Open-wire detection shunt resistance
Open-wire test mode, TSTCONFIG[4]
=1
all odd (CBENBL = 0xAA); or all even
(CBENBL=0x55) cell squeeze resistors
on (alternate resistors only)
LT_DriftVCHAN
Long-term drift (total channel path)
VADC_REF_25
ERRADC_REF_25
4
kΩ
VSENSE = 4.5 V, TA = 65°C(5)
18.47
VSENSE = 4.5 V, TA = 105°C(6)
50.24
ADC reference
ppm/ 1000
hours
2.5
ADC reference error
V
0°C ≤ TA ≤ 65°C
–2.5
2.5
mV
–40°C ≤ TA ≤ 85°C
–3.5
3.5
mV
(1) Error measured with averaging enabled.
(2) User adjustable Gain and Offset registers are provided for further error trim at VSGAIN and VSOFFSET, respectively.
(3) When the bq76PL455A is in IDLE power mode, but not converting any ADC input channel, the part idles the multiplexer on the highest
channel enabled for conversions in the CHAN register.
(4) The current into VSENSEn = ISENSE_SEL + VCELL/RSENSE_SEL.
(5) Computed from the first 500-hour operating life test at a stress temperature of 65°C.
(6) Computed from the first 500-hour operating life test at a stress temperature of 105°C.
6.12 ADC: VMODULE Input
PARAMETER
TEST CONDITIONS
VMODULE_VR
Input voltage range
Measured from TOP to GND (AGND1)
VMODULE_ERR85
Total error from all internal sources
TA = –40°C to 85°C
MIN
TYP
VTOP MIN
MAX
VTOP MAX
UNIT
V
–450
±100
450
mV
MIN
TYP
MAX
UNIT
6.13 ADC: AUXn General Purpose Inputs
PARAMETER
VAUX_VR
VAUXERR65
VAUXERR85
(1)
(2)
10
TEST CONDITIONS
Input voltage range (1)
VP/VDIG = 5.3 V
Total AUX Channel Measurement
Accuracy (2)
VAUX = 0.05 V, 0°C ≤ TA ≤ 65°C
Total AUX Channel Measurement
Accuracy (2)
0
5
V
3
mV
–3
0.1
VAUX = 4.95 V, 0°C ≤ TA ≤ 65°C
–10
0.1
10
mV
VAUX = 0.05 V, –40°C ≤ TA ≤ 85°C
–4.5
0.1
4.5
mV
VAUX = 4.95 V, –40°C ≤ TA ≤ 85°C
–12.5
0.1
12.5
mV
Specified by design, not tested in production.
Calculated and statistically projected worst case from characterization data. Not tested in production.
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ADC: AUXn General Purpose Inputs (continued)
PARAMETER
IDCL_AUX
RIN_AUX
(1)
TEST CONDITIONS
DC Leakage Current
Channel not selected for conversion,
TESTAUXPU = 0
Equivalent input resistance
Channel selected In Acquisition Mode
CAUX (1)
Input capacitance
Channel selected
RAUX_PU
Internal switched pull-up resistor per
AUXn input, supplied from VP pin
TESTAUXPU[n] = 1; n = 0 to 7
MIN
18
TYP
MAX
UNIT
< ±0.1
µA
>3
MΩ
30
pF
26
46
kΩ
6.14 ADC: Internal Temperature Measurement and Thermal Shutdown (TSD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TINT_AD (1)
Internal temperature accuracy of analog
die
–7
3
13
°C
TINT_DD (1)
Internal temperature accuracy of digital
die
–34
8
54
°C
TSDT (2)
Thermal shutdown, junction temperature
both analog and digital dies
(1)
(2)
Increasing temperature
115
140
°C
Specified from characterization data, not tested in production.
Specified by design, not tested in production.
6.15 Passive Balancing Control Outputs
PARAMETER (1)
EQSR_OFF
MIN
TYP
MAX
EQn = 0 (OFF)
TEST CONDITIONS
1.2
1.5
1.8
UNIT
kΩ
EQn = 1 (ON)
1.9
2.3
2.9
kΩ
EQSR_ON
Output resistance, internally in series
with driver
EQVMIN (2)
Cell voltage required for balancing
1.8
V
VS1MIN
VSENSE1 minimum voltage for
balancing (3)
1.8
V
(1)
(2)
(3)
For more functional information, see Passive Balancing .
In the event of an open wire condition, if TSTCONFIG[EQ_SQUEEZE_EN] = 1 and this causes EQVMIN to be violated, it may be
necessary to power down the device to disable the squeeze resistor.
VSENSE1 minimum voltage required for correct operation of any or all EQn outputs. If VSENSE1 falls below this value, any or all other
EQ outputs may fail to assert when requested. The opposite is not true. Outputs will not assert unintentionally when set to the OFF
state.
6.16 Digital Input/Output: VIO-Based Single-Ended I/O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIO – 0.7
VIO
V
DGND
0.7
V
VOH
Logic-level output-voltage high
FAULT_N, TX, GPIO
ILOAD = 5 mA
VOL
Logic-level output-voltage low FAULT_N,
TX, GPIO
ILOAD = 5 mA
VIH
Logic-level input-voltage high RX, GPIO
VIL
Logic-level input-voltage low RX, GPIO
CDIG_IN
Input Capacitance (1) RX, GPIO
RPU
GPIO0..5 pull-up resistor
13
17
25
kΩ
RPD
GPIO0..5 pull-down resistor
16
22
31
kΩ
ILKG
Input leakage source/sink current RX,
GPIOx
RXTXBAUD
RX/TX signaling rate (2) (3)
ERRBAUD_RX
Input Baud rate error (1)
ERRBAUD_TX
Output Baud rate error (1)
tCOMM_BREAK
Communications Clear (Break) (1)
tCOMM_RESET
Communications Reset (1)
(1)
(2)
(3)
VIO – 0.7
V
0.7
V
5
pF
< ±1
µA
125
1000
–3%
3%
–1.5%
1.5%
10
15
Kbaud
bit periods
200
µs
Specified by design, not tested in production.
Defaults: RX = TX = 250 kBd at communications RESET or (factory set) EEPROM setting at POR.
Discrete rates only, not continuously variable.
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6.17 Digital Input/Output: Daisy Chain Vertical Bus
MAX
UNIT
VOH_DCC_TX
Logic level output voltage high
PARAMETER
Single driver loaded, ILOAD = 5 mA
TEST CONDITIONS
VDIG−1
VDIG
V
VOL_DCC_TX
Logic level output voltage low
Single driver loaded, ILOAD = 5 mA
GND
1
V
TPD
Internal propagation delay, COMML to
COMMH (1)
TDCC_BIT_TIME
Diff. Comms. Bit Time (1)
fWAKE_TONE
WAKE TONE frequency (1)
50% duty-cycle WAKE TONE
transmitted on differential pins
COMMH+/COMMH–
tWAKE
WAKE TONE duration (1)
WAKE TONE transmitted on differential
pins COMMH+/COMMH–
(1)
TONE
MIN
TYP
<60
ns
250
ns
100
kHz
1
ms
Specified by design, not tested in production.
6.18 Digital Input/Output: Wakeup
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
WAKEUP high-input voltage
VIL_WAKEUP
WAKEUP low-input voltage
tWAKEUP_HOLD (1)
WAKEUP hold time (high-pulse width)
Pulse driven 0-1-0
tWAKEUP_DLY
Delay between WAKEUP pin assertion and
WAKETONE transmission
Typical application circuit with typical
components as outlined in the Application and
Implementation section.
tWAKE TONE DELAY_DC
Delay (2) between start of WAKETONE received
and WAKETONE transmission
After POR exit condition [VDD18VO > 1.7 V] is
met.
1.2
ms
tWAKEUP_TO_DCOMM
Required delay from WAKETONE transmission
to ready for differential communications (3)
1.1
ms
tWAKEUP_TO_UART
Required delay from WAKETONE transmission
to ready for UART communications (3)
200
µs
(1)
(2)
(3)
2.3
UNIT
VIH_WAKEUP
V
0.7
100
V
µs
1.2
ms
Pulses shorter than 100 µs may wake the device, but must maintain 100 µs to assure start up.
Environmental noise may affect tone detection.
Specified by design, not tested in production.
6.19 EEPROM
over operating free-air temperature range (unless otherwise noted)
PARAMETER
EEPGM
(1)
EEPROM total program time
EECYCLES
Erase / Program cycles
EERETN
Data retention (2) (3)
(1)
(2)
(3)
TEST CONDITIONS
(2)
MIN
No writes to the device are allowed
during the programming cycle
TYP
MAX
UNIT
210
500
ms
(2)
5
10
cycles
years
Program EEPROM temperature (TA ) between 0°C and 30°C.
Specified by design, not tested in production.
Erase / Program cycles not to exceed EECYCLES.
6.20 Secondary Protector – Window Comparators
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OVRANGE
Over-voltage comparator register set-point
limits (1)
UVRANGE
Under-voltage comparator register set-point
limits (1)
OVUVSTEP
Threshold step resolution
ERRCMP_UV
Total UV threshold error (includes
ERRVCOMP_REF_45)
Vin = 0.7 to 3.875 V
ERRCMP_UV_EXT
UV threshold error when range-extend bit is set
COMP_UV[CMP_TST_SHF_UV] = 1
ERRCOMP_OV
Total OV threshold error (includes
ERRVCOMP_REF_45)
ERRCOMP_OV_EXT
OV threshold error when range-extend bit is set
Threshold hysteresis
VCOMP_HYST
(1)
12
MIN
TYP
2
0.7
MAX
UNIT
5.175
V
3.875
25
V
mV
–50
50
mV
–100
100
mV
Vin = 2 to 5.175 V
–50
50
mV
COMP_UV[CMP_TST_SHF_OV] = 1
–60
60
mV
Hysteresis enabled;
DEVCONFIG[COMP_HYST_EN] = 1
50
130
mV
85
Normal range specification. Ranges can be extended by using the COMP_UV[CMP_TST_SHF_UV] and
COMP_OV[CMP_TST_SHF_OV] bits. See register bit description in Table 7 for additional details.
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Secondary Protector – Window Comparators (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TCOMP_UV
UVP Response time
Overdrive = 100 mV
20
µs
TCOMP_OV
OVP Response time
Overdrive = 100 mV
20
µs
VCOMP_REF_45
Comparator reference
Measured by ADC as HREF - HREF_GND
4.5
ERRVCOMP_REF_45
Comparator reference error
V
0°C ≤ TA ≤ 65°C, measured by ADC
–22
–7
9.5
mV
–40°C ≤ TA ≤ 85°C, measured by ADC
–27
–7
15
mV
MIN
TYP
MAX
Falling VP
4.3
4.5
4.7
Rising VP
4.3
4.5
4.7
6.21 Power-On-Reset (POR) and FAULT Flag Thresholds
PARAMETER
TEST CONDITIONS
VPFLT_TRIP
VP_FAULT voltage threshold, analog die
VMFLT_TRIP
VM_FAULT voltage threshold, analog die
DDIEPOR
VP/VDIG POR voltage threshold, digital
die
V5VAOSD
V5VAO SHUTDOWN voltage threshold,
digital die
VIOPOR
VIO POR voltage threshold, digital die
VIOSD_DLY
VIO delay before SHUTDOWN
Falling VM (more negative)
–4.2
–4
–3.8
Rising VM (more positive)
–3.9
–3.8
–3.7
Falling voltage, VP connected to VDIG
3.9
4.15
4.4
Rising voltage, VP connected to VDIG
4.1
4.5
4.7
Falling V5VAO
1.8
2.3
2.8
Rising V5VAO
UNIT
V
V
V
V
2.5
V
Falling VIO
2.1
2.3
2.5
Rising VIO
2.3
2.5
2.7
VIO ≤ VIOPOR
35
57
100
ms
MIN
TYP
MAX
UNIT
48
48.72
MHz
V
6.22 Miscellaneous
PARAMETER
TEST CONDITIONS
fOSC
Main oscillator frequency (±1.5%)
fHBEAT
Fault tone (heartbeat) frequency at pins
FAULTL±
No fault condition present, heartbeat
enabled
10
kHz
HBPULSE
Fault heartbeat pulse width at pins
FAULTL±
No fault condition present, heartbeat
enabled
125
ns
tCKSUM_USER
Time to complete User-space checksum
test (1)
5
ms
tCKSUM_TI
Time to complete TI-space checksum
test (1)
5
ms
tCKSUM_PER
Period for automatic checksum
updates (1)
2
(1)
tADCFullTest
Time to complete full ADC test
tADCTest
Time to complete abbreviated ADC
test (1)
VHREF_GND_FAUL
47.28
µs
450
ms
15
ms
Voltage threshold for 4.5-V reference
ground fault (1)
0.96
V
VHREF_FAULT_OV
Overvoltage threshold for 4.5-V
reference fault (1)
4.75
V
VHREF_FAULT_UV
Undervoltage threshold for 4.5-V
reference fault (1)
4.25
V
T
(1)
Specified by design, not tested in production.
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6.23 Typical Characteristics
The following conditions apply: Typical Operating Circuit, VTOP = 60 V, 16 cells, TA = 25°C (unless otherwise noted)
5
3
1.5 V
4
3.6 V
3
4.5 V
2
1
Error (mV)
Error (mV)
2
1
0
±1
0
±1
±2
±3
±2
±4
±5
±3
±40
±20
0
20
40
60
80
100
120
TA (ƒC)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Cell Voltage (V)
C001
Figure 1. Cell Voltage Measurement Error
Versus Ambient Temperature
5.0
C002
Figure 2. Cell Voltage Measurement Error
Versus Cell Voltage
3
2.0
1.5
2
1
0.5
Error (mV)
Error (mV)
1.0
0.0
±0.5
0
±1
±1.0
0.5 V
±1.5
±2
4.95 V
±2.0
±3
±40
±20
0
20
40
60
80
100
TA (ƒC)
120
1
2
3
4
5
AUX Voltage (V)
C004
Figure 4. AUX Measurement Error Versus AUX Voltage
30
30
28
28
26
26
24
24
Error (mV)
Error (mV)
Figure 3. AUX Measurement Error
Versus Ambient Temperature
22
20
18
22
20
18
16
16
14
14
12
12
10
10
±40
±20
0
20
40
60
80
100
TA (ƒC)
120
±40
±20
0
20
40
60
80
100
TA (ƒC)
C005
Figure 5. Overvoltage Comparator Error
Versus Ambient Temperature
14
0
C003
120
C006
Figure 6. Undervoltage Comparator Error
Versus Ambient Temperature
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Typical Characteristics (continued)
The following conditions apply: Typical Operating Circuit, VTOP = 60 V, 16 cells, TA = 25°C (unless otherwise noted)
30
30
16 V
80 V
Analog Die
Digital Die
20
10
Error (mV)
Error (mV)
10
0
±10
±30
±10
±50
±20
±70
±30
±90
±40
±20
0
20
40
60
80
100
TA (ƒC)
120
±40
±20
0
20
40
60
80
100
120
TA (ƒC)
C007
Figure 7. DIE Temperature Measurement Error
Versus Ambient Temperature
C008
Figure 8. Stack Measurement Error
Versus Ambient Temperature
50
30
40
25
30
20
ISLEEP ( A)
Error (mV)
20
10
0
±10
15
10
±20
±30
5
±40
0
±50
10
20
30
40
50
60
70
VSTACK (V)
80
±40
0
20
5
2.5012
4
2.5011
TA = 105°C
2.5013
2
60
80
100
120
C010
Figure 10. SLEEP Current Versus Ambient Temperature
6
3
40
TA (ƒC)
Figure 9. Stack Measurement Error Versus Stack Voltage
IACTIVE (mA)
±20
C009
2.501
2.5009
1
2.5008
0
±40
±20
0
20
40
TA (ƒC)
60
80
100
120
2.5007
0
C011
Figure 11. ACTIVE Current Versus Ambient Temperature
100
200
300
Time (hrs)
400
500
600
D001
Figure 12. ADC VREF Long Term Drift at 105°C
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7 Detailed Description
7.1 Overview
The bq76PL455A is an integrated 16-cell monitor, protector, and cell balancer designed for high-reliability
industrial applications with many built-in self-diagnostic features.
Up to 16 bq76PL455A devices can be connected in series using the high-speed differential communications
interface, which has been evaluated for compliance with Bulk Current Injection (BCI) standards. This capacitorisolated communications link provides effective common-mode noise rejection. The bq76PL455A communicates
with the host through a high-speed UART interface. The bq76PL455A provides up to six general-purpose,
programmable, digital I/O ports, as well as eight AUX ADC inputs, typically used to monitor externally supplied
temperature sensors. Configuration of the digital I/O ports can be set to generate faults based on conditions set
in register GP_FLT_IN. Further configuration of these faults can be for an indication of a fault on the FAULT_N
output pin.
Designed for high-reliability industrial applications, the bq76PL455A includes many functional blocks and selfdiagnostic test features covering defined single-fault conditions in analog and digital blocks. The host
microcontroller receives fault notifications through a separate communications path. The device contains userselectable self-test features to diagnose functional blocks within the device, such as automatic shutdown in the
event of overtemperature, calibration integrity, and so forth. The Safety Manual for bq76PL455A-Q1 (SLUUB67)
is available upon request for reference to aid the user in the evaluation of the built-in test features of the
bq76PL455A.
A provided built-in secondary protection block, with two dedicated programmable comparators per cell input,
separately senses and reports overvoltage and undervoltage conditions. The comparators utilize a second
separate testable internal band gap reference.
The bq76PL455A provides pins for direct drive of external N-FETs for passive cell balancing with power
resistors. The balancing function configuration responds to on or off commands or specified to run for a specific
time.
The device is powered from the stack of cells to which it is connected and all required voltages are generated
internally.
16
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VREF
OUT2
V5VAO
OUT1
Charge
Pump
NPN PROTECT
VDIG
VP CLAMP
CHP
VM
VP
TOP
NPNB
HIGHEST
CELL
CHM
7.2 Functional Block Diagram
VREG1.8
2.5V
VREF
5.3 V REF
NPN Regulator
5V
ALWAYS
ON
10 V ALWAYS ON
VTOP
WinComp
Squeeze
Resistors
OV
Stack
Monitor
AGND
OSC
ADC
MUX
Temp
Sensor
VSENSE16
UV
ADC
POR
EQ16
VP POR
VP
OV
1k
VSENSE15
VDIG
VDIG POR
VIO
VIO POR
VDD18
1.8V POR
V5VAO
V5VAO POR
UV
Temp
Sensor
OV
AUX0
AFE
VSENSE2
AUX7
MUX
UV
AUX Pullup
EQ2
Control
AUXPUEN
OV
EEPROM
VSENSE1
V5VAO
UV
RX
EEC Decoder
EQ1
VSENSE0
TX
VDD18
EQ
Control
!
4.5V
VREF
Registers
V5VAO
TSD
VDIG
TX / RX
COMMH+
COMMH-
TX / RX
COMML+
COMML-
NPN PROTECT
OV DAC
UV DAC
!
WAKE
TSD
Threshold Set
POR
VM POR
VM
VDIG
VDIG POR
VP
Wakeup
Control
FAULTH+
FAULTHFAULTL+
FAULTL-
Digital
Comparators
WAKE
Checksum
Engine
WAKEUP
Control
WAKEUP
Comms
Interface
Registers
Registers
VP POR
LPF
I/O
WAKEUP
RX
GPIO5
GPIO0
FAULT_N
VIO
CGND
DGND
AGND3
AGND2
ANALOG DIE
AGND1
TX
DIGITAL DIE
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7.3 Feature Description
7.3.1 Block Descriptions
7.3.1.1 Power
The bq76PL455A operates from internally generated regulated voltages. The group of cells monitoring the device
is the source for the internal regulators. Power comes from the most-positive and most-negative pins of the
series-connected cells to minimize the likelihood of cell unbalancing. In most applications, the bq76PL455A
operates using its internal supplies.
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Feature Description (continued)
12 to 79.2 V
NPNB
VDIG
VP
VIO
V10VAO
PRE-REGULATOR
(-) 8-16 CELL MODULE (+)
VP
REGULATOR
V5VAO
LDO
5.3 V VP RAIL
TOP
RX / TX
GPIO
FAULT_N
ANALOG DIE TSD
5.3 V VDIG RAIL
16 V EEPROM
CHARGE PUMP
VDIG_OK
V5VAO
DIGITAL DIE TSD
OSC
CHP
VREF
1.8 V
LDO
4.5 V
REF2
PROGRAM
2.5 V
VREF
VREF
VM
CHARGE PUMP
CHM
AFE
ADC
:,1'2: &203¶6
VM
DIGITAL CORE
LOGIC
GND
WAKEUP CIRCUITS
VBUS DRIVERS
VBUS RECEIVERS
DIGITAL DIE TSD
OSC
AFE
:,1'2: &203¶6
- ANALOG DIE
- DIGITAL DIE
EEPROM
:,1'2: &203¶6
OSC
ADC
1.8 V LDO
Partial diagram, some components omitted for clarity.
Inter-die connections not shown for clarity.
Refer to complete schematics (available from TI) for details.
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Figure 13. Power Flow Diagram
18
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VDD18
VIO
VDIG
VP
VP Power Domain
V5VAO
Feature Description (continued)
POR
TSENSE
AUX[0..7]
VDIG
MUX
OUT2
ADC
VDD18
V5VAO
LDO
V5VAO (bypass cap)
VREF
(bypass cap)
VREF
VP
TSD
Level Shifters
VDIG
1.8 V LDO
VDD18
Power Domain
VDD18
OSC
V5VAO
POR OK
I/O
FAULTH
TX/
RX
FAULTL
TX/
RX
COMMH
TX/
RX
COMML
Level Shifters
Digital Control Logic
EEPROM
HVGEN
VDIG
Power
Domain
TX/
RX
Power-Up
Control
ANALOG die I/O
EEPROM
Programming
Voltage
+10 V (from ANALOG die)
LPR
WAKEUP
V5VAO
Power Domain
I/O
I/O
I/O
Low-Power
Receiver
KEY:
VP
GPIO
VIO Power Domain
VDIG
VDD18
VIO
GPIO[0..5]
FAULT_N
RX
TX
V5VAO
VIO
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Figure 14. Digital Die Power Domains
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NPNB
VP
VDIG
CHM
CHP
VM
Feature Description (continued)
TOP
VP Power Domain
VSENSEn
VSENSEn-1
VMODULE
Measurement
VSENSE ...
Balancing
Control
Circuits
TOP
REF2
Cell
AFE/
Mux
VM
Power Domain
VM Monitor
Window Comparators
VM
VP
TSENSE
Control
Registers
VDIG
TOP
V10VAO
VDIG
CELLS 1-16
KEY:
LDO
TSD
V10VAO
Power Domain
VDIG Power Domain
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Figure 15. Analog Die Power Domains
7.3.1.1.1 TOP Pin Connection
The bq76PL455A has a connection from the top of the cell-module battery stack to the TOP pin, typically through
an external-series resistor and capacitor to GND forming a low-pass filter. The low-pass filter design typically has
a similar time constant to the VSENSE input pins. The minimum recommended values are 100 Ω and 0.1 µF.
See the Application and Implementation section for details.
7.3.1.1.2 V10VAO
V10VAO is an internal-only, always on, pre-regulator supplied from the TOP pin. It supplies the power to the
V5VAO block, Analog Die TSD block, and VP control and regulator circuits. It is not externally accessible.
7.3.1.1.3 V5VAO
V5VAO is the always-on power supply that ensures power is supplied to the differential communications circuits
(COMML+/–) and the WAKEUP input at all times. This ensures that the IC always detects the WAKEUP signal
and the differential communications receive the WAKE tone. The V5VAO is supplied by a combination of an
internal regulator and the VDIG supply. If VDIG falls below the normal operating voltage (during startup), the
internal regulator supplies V5VAO. Once VDIG reaches regulation, V5VAO is supplied directly from VDIG.
20
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Feature Description (continued)
NOTE
V5VAO can only supply enough power to meet internal IC requirements; it should not
connect to external circuitry.
7.3.1.1.4 VP Regulated Output
The bq76PL455A power comes directly from the cells to which it is connected. Current draw is from the top and
bottom of the n-cell battery assembly, so that current through each cell is the same. An integrated linear
regulator utilizes an external NPN transistor (Zetex ZXTN4004K or similar) to generate a nominal 5.3-V rail on
pin VP. VP is both a power input and the sense node for this supply. The NPNB pin controls the external NPN
transistor of the regulator. A capacitor or resistor-capacitor combination must connect externally from VP to GND,
see Pin Configuration and Functions for details. VP must connect externally to VDIG and can optionally connect
to VIO. Both of these connections are through series 1-Ω resistors and separately decoupled. This regulator is
OFF in SHUTDOWN mode.
Table 1. Recommended NPN Transistor Characteristics
PARAMETER
BVCEO
DESCRIPTION
Collector-Emitter voltage
Beta β
Gain
CCB
Collector-Base capacitance
P
IC
(1)
(2)
Power handling
TEST CONDITION
TYPICAL VALUE
UNIT
100
V
at 5 mA
> 100
(1)
(2)
See the following text for
collector resistor details.
Collector current rating
≤ 35
pF
500
mW
> 100
mA
Choose this value with respect to the locally supplied maximum-cell voltage and derate appropriately for operating conditions and
temperature.
Derate this value appropriately for operating conditions and temperature.
Add a collector resistor between the NPN collector and the TOP pin to reduce power dissipation in the NPN
under normal and system fault conditions. The value of this resistor is chosen based on the minimum batterystack voltage, the bq76PL455A VP/VDIG total load current, and the load current of any external I/O circuitry
powered directly or indirectly by VP/VDIG. Also, the recommendation is to add a 1-µF decoupling capacitor
directly from the collector to AGND.
7.3.1.1.5 VDIG Power Input
VDIG is the digital voltage supply input. Always connect it to the VP pin, which normally receives power from the
NPN. Optionally, an external supply may drive VDIG, but still must be connected to VP. This applies in all
operating modes. The VDIG source is from VP through a 1-Ω resistor. Decouple VDIG with a separate capacitor
at the pin.
7.3.1.1.6 VDD18 Regulator
A provided internal regulator generates a 1.8-V digital supply for internal device use only. The 1.8-V supply does
not require an external capacitor, and there is no pin or external connection. Faults on VDD18 that cause the
voltage to drop below its regulation may cause UART communication errors. If the fault is caused by LDO_TEST,
reset or shutdown/wakeup the device to regain functionality.
7.3.1.1.7 VIO Power Input
VIO is the voltage supply input used to power the digital I/O pins TX, RX, FAULT_N, and GPIOn. VIO may
connect to an externally regulated-supply rail, which is common to an I/O device such as a microcontroller.
Alternately, the source for VIO may be from VP through a 1-Ω resistor. Decouple VIO with a separate capacitor
at the pin.
If VIO does not have power, the part holds in reset and enters shutdown after a short delay. This gives a very
good reset mechanism for non-stacked systems. Upon power up from a SHUTDOWN, the
SHDN_STS[GTSD_PD_STAT] bit will be set. This flag bit is the logical <OR> of this condition or triggering the
thermal shutdown of the digital die in a die overtemperature situation.
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7.3.1.1.8 VM Charge Pump
The included internal-charge pump is for biasing the Analog Front End (AFE) and other analog circuits. It
requires an external flying capacitor connected between the CHP and CHM pins plus a storage capacitor on pin
VM to generate a rail of –5 V for internal use. The charge pump (VM) is always on in IDLE and off in
SHUTDOWN. VM requires the oscillator to be running and stable and does not start until the other supplies are
above their POR thresholds. The VM charge pump will start ramping at the start of the WAKEUP tone on COMH.
7.3.2 Analog Front End (AFE)/Level Shifter
The bq76PL455A AFE allows monitoring of up to 16 cells. Provided for this purpose are seventeen VSENSE
inputs, labeled VSENSE0 through VSENSE16. The programming for bq76PL455A can be set to sample all, or a
subset, of the connected cells. Sampling always begins at the highest-selected cell and finishes with the lowestselected cell. During measurement, the AFE selects the cell addressed by the logic block and level-shift the
sensed cell voltage with a gain of 1 down to the ground-referred OUT1 pin. The output of the AFE (OUT1) has a
See section '' for component selection.
The analog output of the AFE connects to OUT1 through an internal 1.2-kΩ series resistor. Connect OUT1
externally to OUT2. At this external connection between the AFE and the ADC, the requirement is to place an
external filter capacitor to form an RC filter to reduce noise bandwidth. A filter capacitor will increase the settling
time of the signal presented to the ADC input. A trade-off can be made between ADC sample time, filtering, and
accuracy. The AFE output must settle to within < 1/4 of the ADC LSB for best measurement accuracy.
7.3.3 ADC
The ADC in the bq76PL455A is a 14-bit Successive Approximation Register (SAR) ADC. It has a fixed
conversion (hold) time of 3.44 µs, with a user-selectable sample interval or period between conversions. The
user-selectable sample interval determines the acquisition (tracking) settling time between conversions, used
mostly to allow the input capacitor on OUT1 to settle between conversions, and to allow for internal settling.
The ADC input mux on the digital die allows it to connect to the following:
• The AFE (analog die) mux output on OUT1 which measures:
– Up to 16 cell voltage channels
– The VMODULE voltage
– The internal temperature of the analog die
– The REF2 analog die reference
– The VM (–5V) charge pump generated voltage supply on the analog die
• Measurement channels on the digital die:
– The 8 AUX input channels
– The VDD18 1.8-V voltage supply on the digital die
– The internal temperature of the digital die
The ADC can be set up to take single samples or multiple samples in one of two averaging modes. This
selection is made using OVERSMPL[CMD_OVS_CYCLE].
7.3.3.1 Channel Selection Registers
Program channels for measurement by setting bits in the CHANNELS and NCHAN registers. Each channel can
be set up for measurement individually. User programmable correction factors are available for cell and AUX
channels. Conversion times are individually user programmable for different types of inputs (that is, cells, AUX,
and internal measurements).
The NCHAN register sets the number of VSENSE channels (cell inputs) for use by the device. Unused channels
are dropped consecutively starting from channel 16. Set this register for the number of cells used, that is, for 14
cells, program 0x0E. This register also sets mask cell overvoltage and undervoltage faults for unused channels,
and turns off the UV and OV comparators associated with the channel. The idle channel (the channel the mux
rests on between sample intervals) is set to the value in this register. This allows the OUT1 pin to hold the filter
capacitor at the voltage, which will be sampled first on the next cycle.
22
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7.3.3.2 Averaging
The oversampling for the ADC average measurements is programmable to 2, 4, 8, 16, or 32 times. Individual
samples are arithmetically averaged by the bq76PL455A, which then outputs a single 16-bit (14 bits + 2
additional bits created by the averaging process) average measurement. The individual samples used to create
the average value are not available.
As shown in Figure 16, the ADC averages any selected cell voltages first, then any selected AUX input channels,
and then any remaining channels selected in the CHANNELS register in the order listed. Depending on the state
of the CMD_OVS_CYCLE bit in the OVERSMPL register, oversampling of the Voltage and AUX channels follows
one of the following procedures:
• Sampling each channel once and cycling through all channels before oversampling again in the case of
CMD_OVS_CYCLE = 1 (cycled averaging) OR
• Sampling multiple times on a single channel before changing channel in the case of CMD_OVS_CYCLE = 0
(non-cycled averaging).
Figure 16 shows these on the left and right, respectively.
When oversampling, Table 2 shows the oversample periods for each channel after the first sample. The first
sample can have a different period programmed (see Table 2), followed by all subsequent samples at different
period shown in Table 3. The first sample and subsequent sample periods are separate of each other.
1
CMD_OVS_CYCLE = ?
0
Averaging?
VSENSE16
VSENSE16
Averaging?
VSENSE15
Averaging?
VSENSE15
Averaging?
VSENSE1
VSENSE1
AUX7
AUX7
Averaging?
Averaging?
Averaging?
AUX0
AUX0
Digital Die Temperature
Averaging is not available
for this node
Averaging?
Analog Die Temperature
Averaging?
Digital Die VDD18
Averaging?
Analog Die REF2
Averaging?
Analog Die REF2 GND
Averaging?
Analog Die VMODULE
(2 samples averaged per iteration)
Averaging?
Analog Die VM
Figure 16. Sampling/Oversampling (Averaging) Sequence
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Table 2. Channel Sample Period Settings
CHANNEL
(1)
(2)
OTHER SAMPLES (AVERAGING)
FIRST SAMPLE
CMD_OVS_CYCLE=0
CMD_OVS_CYCLE=1
VSENSEn (n=1..16)
ADC_PERIOD_VOL
CMD_OVS_HPER
ADC_PERIOD_VOL
AUXn (n=0..7)
ADC_PERIOD_AUXn
CMD_OVS_GPER
ADC_PERIOD_AUXn
DIGITAL DIE TEMP (1)
Approximately 50 µs
n/a
n/a
ANALOG DIE TEMP
ADC_PERIOD_TEMP
CMD_OVS_HPER
CMD_OVS_HPER
VDD18
Approximately 30 µs
CMD_OVS_GPER
CMD_OVS_GPER
ANALOG DIE VREF
ADC_PERIOD_REF
CMD_OVS_HPER
CMD_OVS_HPER
MODULE MONITOR (2)
ADC_PERIOD_MON
CMD_OVS_HPER
CMD_OVS_HPER
VM
ADC_PERIOD_VM
CMD_OVS_HPER
CMD_OVS_HPER
Oversampling (averaging) is not available for this measurement.
TSTCONFIG[MODULE_MON_EN] determines whether 2 conversions or 1 conversion takes place.
The ADC_PERIOD_VOL bits set the period between ADC samples for the indicated channels whether
oversampling or not. When CMD_OVS_CYCLE = 1, the oversampling period of the Cell and AUX channels
remains
fixed
at
the
single
sample
period
of
CELL_SPER[ADC_PERIOD_VOL]
and
AUX_SPER[ADC_PERIOD_AUX], respectively. Otherwise, if CMD_OVS_CYCLE = 0, then the oversample
period for the Cell channels is set by bits CMD_OVS_HPER and for the AUX channels is CMD_OVS_GPER.
CMD_OVS_HPER must be programmed to 12.6 µs and CMD_OVS_GPER can be programmed between 4.13
µs and 12.6 µs in the OVERSMPL register.
After the initial sample period performed per a single sample, oversampling on all other channels are at the
CMD_OVS_GPER and CMD_OVS_HPER period settings as indicated in Table 2.
Writing to the CMD register is used to start the voltage sampling process. This is usually done with a
BROADCAST Write_With_Response_Command sent to the CMD register. Using the BROADCAST version of
the synchronously sample channels command will result in all devices in the stack sampling at the same time.
That is, all devices begin sampling their respective cells, then AUX, and so on, simultaneously.
7.3.3.3 Recommended Sample Periods
Refer to Table 3 for initial recommended settings. Other settings are possible; see the Application and
Implementation section for additional information.
Table 3. ADC Recommended Sample Periods and Setup
MEASURED
PARAMETER
(2)
(3)
24
(1)
PERIOD REGISTER (2)
1 SAMPLE
SAMPLES 2–8
NAME
VCELL
60 µs
12.6 µs
CELL_SPER
0xBC
VAUX
12.6 µs
12.6 µs
AUX_SPER
0x44444444
VMODULE
1000 µs
12.6 µs
TEST_SPER
0xF999
Die Temp (ANL)
100 µs
12.6 µs
CELL_SPER
0xBC
Die Temp (DIG)
(1)
PERIOD
st
50 µs
(3)
AS SHIPPED
N/A
N/A
N/A
VM
30 µs
12.6 µs
TEST_SPER
0xF999
VDD18
30 µs
12.6 µs
N/A
N/A
REF2
30 µs
12.6 µs
TEST_SPER
0xF999
Sampling periods and averaging mode will affect device accuracy. Device accuracy and register settings (including the sampling period)
used to achieve stated device accuracy are specified under "Electrical Characteristics, ADC" in Analog-to-Digital Converter (ADC):
Analog Front End. Other settings are possible. Device accuracy is not assured at settings other than those specified in the Electrical
Characteristics tables.
Other register settings used: OVERSMPL = 0x7B; PWRCONFIG = 0x80
This is not a programmable parameter. No averaging is performed, but there is an inherent delay in the design for the ADC
measurement of the die temperature.
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7.3.3.4 VSENSE Input Channels
The VSENSE input channels measure the voltages of individual cells in the range of 1 V-to-4.95 V. Each input
should connect to an external low-pass filter (LPF) to reduce noise at the input, and a Zener diode to provide
protection to the device during random hot-plug cell connection. Typical values for the LPF range from 100 Ω to
1 kΩ, and 0.1 µF to 1 µF. Values outside this range may degrade accuracy due to system-level noise or from
excessive IR loss in the series resistor.
Tie up unused inputs to the highest-connected cell. For example, in a 14-cell system, tied to VSENSE14 are
unused inputs VSENSE15 and VSENSE16. Channels are used from lowest to highest, with VSENSE0
connected to the (–) terminal of the bottom cell.
The values returned from an ADC conversion for these channels convert to volts by:
VCELL = [(2 × VREF) / 65535] × READ_ADC_VALUE
(1)
A number of factors affect total channel measurement accuracy, including, but not limited to, variations due to IR
reflow, board-level stresses, any current leakage in external components, and the method of sampling. It is highly
recommended that the end user perform GAIN and OFFSET calibration as described in the Application and
Implementation section.
7.3.3.5 AUXn Input Channels
The AUXn input channels are used to measure external analog voltages from approximately 0 V to 5 V. A typical
use for these channels is to measure temperature using thermistors. These channels require a simple external
low-pass filter to reduce high frequency noise for best operation. The RC values correspond to the user's
application requirements.
The values returned from an ADC conversion for these channels convert to volts by:
VAUX = [(2 × VREF) / 65535] × READ_ADC_VALUE
(2)
7.3.3.6 VMODULE Measurement Result Conversion to Voltage
VMODULE is the voltage measured from the TOP pin to GND. The value scales by 25 with an internal resistor
voltage divider. Setting TSTCONFIG[MODULE_MON_EN] enables measuring of VMODULE voltage. Enable or
disable the measurement to aid with self-testing. When set to 0, the channel should measure close to 0 V.
The values returned from an ADC conversion for this channel converts to volts by:
VMODULE = ([(2 × VREF) / 65535] × READ_ADC_VALUE) × 25
(3)
7.3.3.7 Digital Die Temperature Measurement
The temperature of the digital die may be measured as a part of the normal ADC measurement sequence by
setting bit CHANNELS[CMD_TSEL]. The reported result is the voltage from the temperature sensor, not the
actual temperature.
No averaging is ever performed on this channel, but the timing will appear as if the requested oversampling was
performed.
FAULT_SYS[INT_TEMP_FAULT] is continuously updated based on the currently stored measurement result and
threshold. To allow clearing of the fault, sample the temperature within a normal operating range.
Conversion formula:
Internal Digital Die Temperature °C = (VADC – 2.287) × 131.944
(4)
7.3.3.7.1 Automatic Temperature Sampling
After initialization is complete, an internal timer will cause the digital-die temperature sensor sampling to be
scheduled once per second. No oversampling is performed. If a command cycle occurs that samples the digital
die temperature sensor, the timer resets. A command will interrupt an automatic temperature sample, but if the
command does not sample the digital die temperature, the automatic temperature sample will occur as soon as
the command completes. This can cause sample values to appear to change without a sample request.
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7.3.3.8 Analog Die Temperature Measurement
The temperature measurement of the analog die is programmable as part of the normal ADC measurement
sequence by setting bit CHANNELS[CMD_HTSEL]. The reported result is the voltage from the temperature
sensor, not the actual temperature.
There is no internal threshold checking for this value. For self-testing purposes, the expectation is that the
microcontroller compares this value with the converted temperature from the digital die and decides if they are
reporting the same temperature. The analog die temperature measurement is more accurate than the digital-die
temperature measurement. Therefore, the digital die temperature measurement should be considered only a
rough estimation of the temperature measured by the analog die temperature monitor. The host firmware must
account for any offset between the two measurements.
Conversion formula:
Internal Analog Die Temperature °C = (VADC – 1.8078) × 147.514
where
•
VADC=[(2 × VREF) / 65535] × READ_ADC_VALUE
(5)
7.3.3.9 VM Measurement Result Conversion to Voltage
There is no internal threshold checking of this value. The expectation is that the microcontroller checks that the
value is within the appropriate range.
The value returned from an ADC conversion for this channel converts to volts by:
VVM = –2 × [(2 × VREF) / 65535] × READ_ADC_VALUE
(6)
7.3.3.10 V5VAO, VDIG, VDD18 Measurement Result Conversion to Voltage
The value returned from an ADC conversion for these channels converts to volts by:
VADC = [(2 × VREF) / 65535] × READ_ADC_VALUE
(7)
There is no internal threshold checking of these values. The expectation is that the microcontroller checks that
the values are within the appropriate ranges.
7.3.4 Thermal Shutdown
Thermal shutdown occurs when either one or both of the Thermal Shutdown (TSD) sensors on either die sense
an overtemperature condition. The sensors operate separately without interaction and are separate from the
analog and digital die sensors. Each has a separate register-status indicator flag. When a TSD fault occurs, the
part immediately enters the SHUTDOWN state. To awake the part, follow the normal WAKEUP procedure. The
bq76PL455A does not exit SHUTDOWN automatically. It cannot be awakened until the temperature falls below
the
TSD
threshold.
Upon
waking
up,
either
SHDN_STS[GTSD_PD_STAT]
or
(SHDN_STS[ANALOG_PD_STAT]&& SHDN_STS[HTSD_PD_STAT]) bits will be set.
7.3.5 Voltage Reference (ADC)
The VREF pin receives a precise internal voltage reference for the ADC. Two parallel X7R or better filter
capacitors between pins VREF and AGND are required for the reference; see Application and Implementation for
recommended values and PCB layout considerations.
7.3.6 Voltage Reference (REF2)
The window comparators have a 4.5-V internal voltage reference provided. It does not go out to an external pin.
To check the reference, select it with the CHANNELS[CMD_REFSEL] bit.
7.3.7 Passive Balancing
Sixteen internal drivers control individual cell balancing through the pins labeled EQ1…EQ16. When the device
issues a balance command through register CBENBL, the bq76PL455A asserts the EQ(N) output, switches to
the VSENSE(N) rail and turns on QBAL. With a de-asserted register bit, the EQn bit switches to the VSENSEn–1
rail, turns off QBAL, and reduces the balancing current to zero. The squeeze (OWD) function must be disabled for
correct balancing operation by setting TSTCONFIG[EQ_SQUEEZE_EN] = 0.
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If CBCONFIG[BAL_CONTINUE] is set to '0', then when there is a FAULT the bq76PL455A disables balancing.
The CBENBL register bits clear to indicate this event. However, there is one exception. The USER checksum
fault indicated by FALUT_DEV[USER_CKSUM_FLT] does not disable balancing. The following describes the
scenarios:
• BAL_CONTINUE = 0: CBENBL is set to 0 and balancing is disabled until the fault and fault status bits are
cleared. Information about what was being balanced is discarded. No change is made to the BAL_TIME bits
in CBCONFIG. The CBENBL register must then be rewritten with the desired balancing action.
• BAL_CONTINUE = 1: There is no effect on CBENBL and CBCONFIG and any balancing in progress
continues.
Changing the CBENBL register will create a checksum fault and cause FAULT_DEV[USER_CKSUM_ERR] to be
set. This may be a result of setting bits to enable balancing for cells, or the register being reset, because of a
fault or CBTIME expiring.
The internal balancing control circuitry only powers up when any bit in CBENBL is set. See Passive Cell
Balancing Circuit section for details on selecting the external passive balancing components.
7.3.8 General Purpose Input-Outputs (GPIO)
There are six GPIO pins available in the bq76PL455A. Registers GPIO_xxx, located at addresses 0x78–7D,
control GPIO behavior. Each can be programmed to be an input or output pin.
Each GPIO pin can have an internal pull-up or pull-down resistor enabled to keep the pin in a known state when
power is not on for external circuitry. Configuration for pull-up or pull-down resistors is in the GPIO_PU and
GPIO_PD registers. The pull-up/down resistors have internal connections to supply VIO. The resistor values are
in the Digital Input/Output: Wakeup section of the Electrical Characteristics tables.
The GPIOs can also trigger a FAULT condition. Programmed GPIOs trigger a FAULT indication by setting bits in
register GPIO_FLT_IN.
The FAULT_GPI register and the DEVCONFIG[UNLATCHED_FAULT] bit controls the behavior of the device in
response to a FAULT triggered by an enabled GPIO pin. The usual pin configuration is to be an input in the
GPIO_DIR register when used to trigger faults.
7.3.9 UART Interface to Host Microcontroller
The UART follows the standard serial protocol of 8-N-1, where it sends information as a START bit, followed by
eight data bits, and then followed by one STOP bit. In all, 10 bits comprise a character time. Received data bits
are oversampled by 16 times to improve communication reliability.
The UART sends data on the TX pin and receives data on the RX pin. When the transmitter is idling (not sending
data), TX = 1. The RX input pin idles in the same state, RX = 1. Hold the RX line high using a pull-up to VIO, if
not used (that is, non-base device in the daisy chain). Do not allow the RX pin to float when VIO is present.
7.3.9.1 UART Transmitter
The transmitter can be configured to wait a specified amount of time after the last bit reception and start of
transmission using the TX_HOLDOFF register. The TX_HOLDOFF register specifies the number of bit periods
that the bq76PL455A will wait to allow time for the microcontroller to switch the bus direction at the end of its
transmission.
7.3.9.2 UART Receiver
The UART interface design works in half-duplex. As a result, while the device is transmitting data on the TX pin,
it ignores RX. To avoid collisions when sending data up the daisy-chain interface, the host microcontroller should
wait until it receives all bytes of a transmission from the device to the microcontroller before attempting to send
data or commands up the daisy-chain interface. If the microcontroller starts a transaction without waiting to
receive the preceding transaction's response, the communication might hang up and the microcontroller may
need to send Communication Clear (see Communication Clear (Break) Detection) or Communication Reset (see
Communication Reset Detection) to restore normal communications.
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7.3.9.3 Baud Rate Selection
The baud rate of the communications channel to the microcontroller is set in the COMCONFIG[BAUD] register
for 125k-250k-500k-1M baud rates. The default rate after a communications reset is 250k. The default rate after
a POR is the rate selected by the value stored in EEPROM for the COMCONFIG[BAUD] register.
When the value in this register changes, the new rate takes effect after the complete reception of a valid packet
containing the new setting including the CRC. This should send the next packet at the new baud rate and all
packets transmitted by the device will be at the new rate. It is possible to change the baud rate at any time and,
optionally, store the new baud rate in the EEPROM as a new POR default. After changing the baud rate, observe
a minimum wait period of 10 µs before sending the first packet at the new baud rate.
The value in the COMCONFIG[BAUD] register only affects the baud rate used in microcontroller communications
on the TX and RX pins. The daisy-chain vertical communication bus rate is at a higher fixed rate and not user
modifiable. All devices in the stack must have the same baud rate setting as the base device to read data from
stacked devices.
7.3.9.4 Communication Clear (Break) Detection
Use communications clear to reset the receiver to re-synchronize looking for the start of frame.
The receiver continuously monitors the RX line for a break (<BRK>) condition. A <BRK> is detected when the
RX line is held low for at least tCOMM_BREAKmin bit periods (approximately 1 character times). Sending for more
than tCOMM_BREAKmax bit periods may result in recognition of a communication reset instead of the intended
communication clear. When detected, a <BRK> will set the STATUS[COMM_CLEAR] flag.
7.3.9.5 Communication Reset Detection
Detection of a communication reset occurs when the RX line is held low for more than approximately
tCOMM_RESETmin. The primary purpose of sending a communications reset is to recover the device in the event the
baud rate is inadvertently changed or unknown. The baud rate resets unconditionally to the FACTORY default
value of 250 kb/s, REGARDLESS of the value stored in the EEPROM COMCONFIG register. This sets the baud
rate to a known, fixed rate (250k baud), and the STATUS[COMM_RESET] flag.
7.3.9.6 Communication Timeouts
Programming is available for two timeout values based on the absence of a valid packet from either UART or
differential stack communications. The times are set in the two-bit fields of the Communications Timeout (CTO)
register. A valid packet definition is any packet with a valid CRC.
7.3.9.6.1 Communications Timeout Fault
Register CTO[COMM_TMOUT_PER] sets the period with no valid communications from either communications
interface before sensing a COMM_TIMEOUT fault.
Always set CTO[COMM_TMOUT_PER] to be set less than the CTO[COMM_PD_PER] to get a communications
timeout fault before SHUTDOWN occurs.
7.3.9.6.2 Communications Timeout Power-Down (SHUTDOWN)
CTO[COMM_PD_PER] forces the part to shut down when this time is exceeded without a valid communication
from either the UART or the differential stack communications.
7.3.10 Stacked Daisy-Chain Communications
In the stacked configuration, the main microcontroller first communicates through a bq76PL455A device using
the UART communications interface, see Figure 17. Communication is then relayed up the chain of connected
slave bq76PL455A devices using a proprietary differential communications protocol over AC-coupled differential
links interconnected by the COMMH+/– and COMML+/– pins.
Each device in the daisy chain buffers the signal drive levels. The signal is not re-clocked or filtered; it passes
through the device without change and the entire stack sees all data sequencing regardless of the target device.
The packet is not validated before being transmitted to the next device in the daisy chain. The uniquely
addressed or group addressed device acts on the command (that is, begins an ADC conversion of the inputs) as
soon as it receives and validates the packet for correct address, message contents, and CRC.
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FAULTHt
FAULTH+
COMMHt
SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016
COMMH+
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WAKEUP
WAKEUP
FAULTHt
FAULTLt
FAULT_N
FAULTH+
FAULTL+
FAULT_N
COMMHt
COMMLt
FAULTLt
COMML+
COMMH+
COMML+
FAULTL+
TX
TX
VIO
RX
COMMLt
VP
TWISTED PAIR WIRING
VP
RX
VIO
TWO CAPACITORS FOR
ENHANCED SAFETY
COMMH+
COMMHt
FAULTH+
FAULTHt
COMML+
COMMLt
FAULTL+
FAULTLt
DC BLOCKING CAPACITORS
(ISOLATION)
3.3 V / 5 V
LDO
WAKEUP
TMS-570
MICROCONTROLLER
GPIO_1
TX
RX
VDD
FAULT_N
RX
TX
VIO
GPIO_0
VP
Figure 17. Simplified Stack Communications Connectivity
7.3.10.1 Differential Communications
The bq76PL455A uses two differential communications links, which perform different tasks. The hardware used
for the transmitters and receivers are similar. The communications link used for data and commands (the vertical
bus or VBUS) on the COMML+/– and COMMH+/– pairs is bidirectional, while the FAULTH+/– pins are receivers
only, and the FAULTL+/– are transmitters only.
NOTE
The UART receiver (RX), COMMH+/– transmitters, and COMML+/– receivers cannot be
disabled.
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The base device sends and receives data through UART at variable baud rates from 125 kb/s to 1 Mb/s. The
VBUS daisy chain operates at a fixed, nominal, data rate of 4 Mb/s using a proprietary asynchronous protocol.
Each byte is sent as 10 bits at 250 ns/bit or 2.5 µs/byte. The bottom device retransmits data from/to the
differential serial interface on the single-ended interface connected to the host system at the baud rate selected
for the single-ended serial interface. All bq76PL455As in the daisy-chain should be set to the same baud rate to
align timing between the devices.
The VBUS interface uses a modified version of the UART protocol so it can easily translate to/from the UART
protocol. Transmission of a bit requires 250 ns, including both half-bits. It is effectively a 4-MHz signal that is
phase-shift keyed, so the resulting transmission will have both 4-MHz and 2-MHz components. See Figure 18 for
additional information.
7.3.10.2 Protocol Description
The differential VBUS uses an asynchronous byte-transfer protocol with one start bit, eight data bits, and an
optional framing bit. The start bit is always a zero. Duplication of the LSB-first data occurs so that the
transmission has no DC content. A zero is transmitted as one half-bit period low followed by one half-bit period
high. Transmission of a one is as one half-bit period high followed by one half-bit period low. A framing bit of one
will cause the byte to be discarded and the byte abort flag (FAULT_COM[ABORT_H or ABORT_L]) to be set.
Since the data transmit on the differential interface as it is being received from the single-ended UART interface,
this is used to indicate that an erroneous stop bit was detected.
Each time the bq76PL455A detects a byte with a framing bit of zero, it is interpreted as a frame-initialization byte.
If the prior frame was not completed, FAULT_COM[FRAM_ERR] is set.
If detection of the start bit occurs, the receiver samples the input on the fourth clock edge to produce the bit.
Since a bit is always immediately followed by its complement, the two will be compared and the complement
error flag (FAULT_COM[COMP_ERR_H or COMP_ERR_L]) is set if they are not opposites. The first time such
an error occurs during a frame, the assumption is that the first sampling of the bit (not the complement) is the
correct one. (If this choice is incorrect, it should detect it as a CRC failure.) If such an error occurs more than
once during a frame, the fatal-complement error flag (FAULT_COM[COMP_FLT_H or COMP_FLT_L]) is set and
the frame ignored. Since the device ignores the remainder of the frame, a FRAM_ERR occurs when the next
frame arrives.
While receiving a byte, the receiver will resynchronize on every falling edge. A falling edge is expected at least
once every 3 bits. If the expected sampling point of the fourth bit does not detect a falling edge, the edge error
flag (FAULT_COM[EDGE_ERR_H or EDGE_ERR_L]) will be set and the receiver will return to idle, discarding
the frame.
If the bq76PL455A device detects eight consecutive edge errors on the low-side interface (COMM_L+/–) with no
valid bytes being received, the block will be reset in the same manner as SOFT_RESET. This allows a wakeup
tone from the chip below in the stack to cause the part to reset.
125 ns
250 ns
COMM+
COMM–
rec_in
start
0
1
1
1
0
0
1
0
framing
Figure 18. VBUS Data Example, 0x4E Sent
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7.3.11 Register and EEPROM
7.3.11.1 Error Check and Correct (ECC) EEPROM
Register values for selected registers are permanently stored in EEPROM. All registers also exist as volatile
storage locations at the same addresses, referred to as shadow registers. The volatile registers are for reading,
writing, and device control. For a list of registers included in the EEPROM, see Table 7.
At wakeup, the bq76PL455A first loads all shadow registers with default values from Register Summary. Then
the bq76PL455A loads the registers conditionally with EEPROM contents from the results of the Error Check and
Correct (ECC) evaluation of the EEPROM.
The EEPROM is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct
(ECC) value stored. The ECC detects a single bit (Single-Error-Correction) or double bit (Double-Error-Detection)
changes in EEPROM stored data.
The ECC is calculated for each block, individually. Single-bit errors are corrected, double-bit errors are only
detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and either
FAULT_DEV[USER_ECC_COR] or FAULT_DEV[FACT_ECC_COR] bit is set to flag the corrected error event.
The block is loaded to shadow registers after the single-bit error correction. Since the evaluation is on a block-byblock basis, it is possible for multiple blocks to have a single-correctable error per block and still be loaded
correctly. Multiple bit errors can exist with full correction, as long as they are limited to a single error per block.
A block with a bad ECC comparison (two bit errors in one block) is not loaded and the
FAULT_DEV[USER_ECC_ERR] or FAULT_DEV[FACT_ECC_ERR] bit is set to flag the failed bit-error event.
The default value remains in the register. This allows some blocks to be loaded correctly (no fail or single bit
corrected value) and some blocks not to load. Any time either of the FAULT_DEV[*_ECC_ERR] is set, and the
condition is not cleared by a soft reset, the device has failed and should not be used.
7.3.12 FAULT Sensing and Signaling
A dedicated differential FAULT link allows each bq76PL455A in a stack of devices to signal the presence of any
monitored and active/latched fault condition to the main microcontroller separately from the UART link. The
FAULTH+/– and FAULTL+/– pins implement an AC-coupled differential-signaling scheme similar to
communication pins COMML+/– and COMMH+/–, but using only a simple heartbeat signal to indicate normal or
fault conditions by the presence or absence of a repetitive pulse, respectively. The low duty-cycle heartbeat
stops anytime it senses a fault and the fault condition sets a bit in one of the FAULT_* registers. Masked faults
have no effect on the heartbeat generation.
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7.3.12.1 Fault Flow Schematics
FAULT MASKING
FAULT SOURCES
FAULT STATUS
MASK_COM[]
FAULT_COM[]
COMP_ERR_H_MSK
1
COMP_ERR_H_S
COMP_ERR_L_MSK
1
COMP_FLT_H_MSK
1
COMP_ERR_L_S
COMP_FLT_H_S
COMP_FLT_L_MSK
1
EDGE_ERR_H_MSK
1
COMP_FLT_L_S
EDGE_ERR_H_S
EDGE_ERR_L_MSK
1
ABORT_H_MSK
1
EDGE_ERR_L_S
&
COMP_ERR_H
&
COMP_ERR_L
&
COMP_FLT_H
&
COMP_FLT_L
&
EDGE_ERR_H
&
EDGE_ERR_L
&
ABORT_H
&
ABORT_L
&
CRC_FAULT_H
&
CRC_FAULT_L
&
FRAM_ERR
&
STOP_ERR
&
STK_FAULT_ERR
COMM_FAULT_ANY
ABORT_H_S
ABORT_L_MSK
1
CRC_FAULT_H_MSK
1
ABORT_L_S
CRC_FAULT_H_S
CRC_FAULT_L_MSK
1
FRAM_ERR_MSK
1
CRC_FAULT_L_S
FRAM_ERR_S
STOP_ERR_MSK
1
STK_FAULT_ERR_MSK
1
STOP_ERR_S
STK_FAULT_ERR_S
FAULT MASKING
FAULT SOURCES
H1
FAULT STATUS
MASK_DEV[]
FAULT_DEV[]
USER_CKSUM_MSK
1
USER_CKSUM_ERR_S
FACT_CKSUM_MSK
1
ANALOG_FERR_MSK
1
FACT_CKSUM_ERR_S
ANALOG_FAULT_ERR_S
&
USER_CKSUM_ERR
&
FACT_CKSUM_ERR
&
ANALOG_FAULT_ERR
HREF_FAULT_S
HREF_FAULT
HREF_GND_FAULT_S
HREF_GND_FAULT
CHIP_FAULT_ANY
H1
These faults are only
created on
command. They do
ADC_CAL_ERR_S
ADC_CAL_ERR
USER_ECC_COR_S
USER_ECC_COR
USER_ECC_ERR_S
USER_ECC_ERR
FACT_ECC_COR_S
FACT_ECC_COR
FACT_ECC_ERR_S
FACT_ECC_ERR
not require masks.
Legend
H1
PINx
X_ERR
<OR>
&
Internal Source
1
<AND>
External Source (pin)
<NOT>
P
H1
<NOR>
=1
<XNOR>
P<Q
COMPARATOR
Q
Figure 19. Digital Faults
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COMP_UV[]
DAC
COMP_UV_THRESH[7:1]
REF2
FAULT SOURCES
FAULT MASKING
VSENSEn
FAULT STATUS
FAULT _2UV[]
V_CELL < COMP_UV_THRESH
UV COMP
VSENSEn-1
NCHAN[]
COMP_CONFIG < 1
&
COMP_UV_FAULT[15:0]
16
COMP_UV_FAULT _ANY
≥1
SYSFLT_ANL_ANY
≥1
&
UNLATCHED_FAULT
FAULT _2OV[]
V_CELL > COMP_OV_THRESH
OV COMP
NCHAN[]
COMP_CONFIG < 2
&
COMP_OV_FAULT [15:0]
COMP_OV_FAULT _ANY
≥1
These UV and OV window comparator (WINCOMP) faults
only clear automatically when UNLATCHED _FAULT is set
and NO OTHER analog die based fault exists. This is true
even for faults that are masked.
COMP_OV[]
DAC
COMP_OV_THRESH[7:1]
Analog die faults include FAULT_SYS[3:0] or any bit in
registers FAULT _2UV[] or FAULT _2OV[].
REF2
FAULT SOURCES
FAULT MASKING
CELL_UV[]
VSENSEn
ADC
16
CELLn ADC RESULT [15 :0]
FAULT STATUS
FAULT _UV[]
P
VSENSEn-1
P< Q
UV_THRESH_CELL[15:0 ]
CELLn_UV_FAULT
UV_FAULT [15:0]
16
UV_FAULT _ANY
Q
≥1
UNLATCHED_FAULT
NCHAN[]
CELL0_OV[]
16
FAULT _UV[]
P
P> Q
OV_THRESH_CELL[15: 0]
CELLn_OV_FAULT
OV_FAULT[15:0]
16
OV_FAULT _ANY
Q
≥1
UNLATCHED_FAULT
NCHAN[]
Figure 20. Analog Faults
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FAULT SOURCES (8)
AUXn
ADC
www.ti.com
FAULT MASKING
FAULT STATUS
AUX0_UV[]
FAULT_AUX[]
16
AUXn ADC RESULT [15:0]
P
P<Q
n = 0:7
AUXn_UV_FAULT
AUX_UV_FAULT [n]
Q
UV_THRESH_AUXn[15:0]
≥1
AUXUV_FLT_ANY
AUX0_OV[]
16
P
P>Q
AUXn_OV_FAULT
AUX_OV_FAULT [n]
Q
OV_THRESH_AUXn[15:0]
≥1
AUXOV_FLT_ANY
UNLATCHED _FAULT
FAULT SOURCES (6)
FAULT MASKING
FAULT STATUS
GPIO_IN[5:0]
GP_FLT_IN[]
FAULT_GPI[5:0]
GPIOn
GPIO_IN [n]
=1
n = 0:5
GPI_FLT_SENSE
&
GPI_FAULT [n ]
GPI_FLT_CONFIG[n]
≥1
GPI_FLT_ANY
UNLATCHED _FAULT
Figure 21. AUX and GPIO Pin Faults
FAULT MASKING
MASK_SYS[]
FAULT SOURCES
FAULT STATUS
FAULT_SYS[]
SYS_RESET_MSK
1
COMM _TIMEOUT_MSK
1
SYS _RESET_S
COMM_TIMEOUT_S
&
SYS_RESET
&
COMM _TIMEOUT
VDIG_WAKE_FAULT_S
INT_TEMP_FAULT _MSK
1
INT_TEMP_FAULT_S
VDIG_WAKE_FAULT
&
INT_TEMP_FAULT
SYS_FAULT _ANY
≥1
UNLATCHED_FAULT
VDIG_FAULT _MSK
1
VM_FAULT_MSK
1
VP_FAULT _MSK
1
VP_CLAMP_<SK
1
VDIG_FAULT_S
VM_FAULT_S
VP_FAULT_S
VP_CLAMP_S
&
VDIG_FAULT
&
VM_FAULT
&
VP_FAULT
&
VP_CLAMP
≥1
SYSFLT_ANL_ANY
Figure 22. System Faults
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FAULT SOURCES
FAULT SUMMARY
FAULT _SUM[]
UV_FAULT_ANY
UV_FAULT _SUM
OV_FAULT_ANY
OV_FAULT _SUM
AUXUV_FAULT_ANY
AUXUV_FAULT _SUM
AUXOV_FAULT_ANY
AUXOV_FAULT _SUM
CMPUV_FAULT_ANY
CMPUV_FAULT _SUM
CMPOV_FAULT_ANY
CMPOV_FAULT _SUM
COMM _FAULT_ANY
COMM_FAULT _SUM
FAULT SUMMARY - Top Level
STATUS[]
≥1
SYS _FAULT_ANY
SYS_FAULT _SUM
CHIP_FAULT_ANY
CHIP_FAULT _SUM
GPI _FAULT_ANY
GPI_FAULT _SUM
FAULT _CONDITION
Bit not latched
STACK_FAULT _DET
Latched bit
FAULTH±
10kHZ TONE
DETECT
TONE_PRESENT
&
STACK _FAULT
Bit not latched
COM_CONFIG[]
Enables High Side
Diff RX (COMMH±)
FAULT _HIGH_EN
Enables Lo Side
Diff TX (COMML±)
DIFF_FAULT _EN
&
FAULT MASKING
FO_CTRL[]
10kHz TONE
GENERATOR
FAULTL ±
FAULT SOURCES
UV_FAULT _OUT
UV_FAULT_ANY
OV_FAULT _OUT
OV_FAULT_ANY
AUXUV_FAULT _OUT
AUXUV_FAULT_ANY
AUXOV_FAULT _OUT
AUXOV_FAULT_ANY
CMPUV_FAULT_OUT
CMPUV_FAULT_ANY
CMPOV_FAULT_OUT
CMPOV_FAULT_ANY
COMM_FAULT _OUT
COMM _FAULT_ANY
SYS_FAULT _OUT
SYS _FAULT_ANY
CHIP_FAULT _OUT
CHIP_FAULT_ANY
GPI_FAULT_OUT
GPI _FAULT_ANY
&
&
&
&
&
≥1
FAULT _N
&
&
&
&
&
Figure 23. Fault Hierarchy Top-Level
7.3.12.2 FAULT Signaling
The FAULT bus transmits a simple heartbeat pulse at a fixed frequency when enabled and unmasked faults are
not present. Masking a fault does not clear a pre-existing fault condition. A device sensing a fault condition stops
transmitting the heartbeat to the ICs in the chain below. The ICs sense this condition in the stack below and then
assert the FAULT_N pins if configured to sense the lack of tone in COMCONFIG. FAULT_N only asserts if the
UART_EN bit in COMCONFIG is set.
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The differential signal lines are isolated between ICs by a DC blocking capacitor similar to the differential
communications VBUS daisy chain. The capacitor typical rating is at a minimum of two times the stack voltage to
provide plenty of standoff margins to handle system faults that expose the device to local hazardous voltages.
One capacitor is sufficient for the normal operation of the device. The system designer may elect to use two
capacitors, one at each end of the cable or PCB wiring, for an additional safety factor. In this case, use double
the capacitor value from the normal requirement, so that the two capacitors in series result in the same value in
the signal path.
The heartbeat derivation comes from the device main oscillator and is generated separately out of each device in
the stack. The device does not copy or re-transmit the value from the device above it. The
FAULT_COM[STK_FAULT_ERR] that indicates a problem with the fault heartbeat is sensed individually by each
device in the stack and may be tripped in some devices and not in others under some fault conditions.
The FAULT_N pin signals faults from both internal sources and from ICs above in the stack, if enabled. Internal
faults are on FAULT_N depending on the enabled sources in the FO_CTRL register. Faults from stacked devices
above it are signaled on the FAULT_N pin when enabled by COMCONFIG[FAULT_HIGH_EN]. The FAULT_N
pin always outputs a low signal in reset or shutdown.
7.3.12.3 Fault Sensing
Masking of fault sources may be in registers MASK_COMM, MASK_SYS, and MASK_DEV. Masking a fault will
prevent the flag from being set at a future time, but it will not clear an already set fault flag.
Any time an unmasked fault condition is triggered, the device sets a bit in the appropriate FAULT_* register at
addresses 0x52–63.
When a device senses an unmasked fault or, with enabled fault communications, when the heartbeat from the
device above stops, the FAULT_N pin asserts low to signal the fault to a user circuit or microcontroller. Each
device in the stack that sees one of these conditions asserts the FAULT_N pin if the UART_EN bit in
COMCONFIG is set. The heartbeat stop and FAULT_N pin assertions occur simultaneously.
Normally, after RESET, POR, or normal wakeup, user firmware must clear FAULT_SYS[SYS_RESET] to start
the heartbeat. If there is an enabled stack communications interface, the heartbeat will start after clearing
SYS_RESET and receiving four cycles of the heartbeat on the north-interface FAULTH pins. This typically
requires a little more than approximately 400 µs and results in clearing the STATUS[STACK_FAULT] flag.
Faults propagate down the stack through the FAULTL pins. The lower of two adjacent bq76PL455A devices
monitors its FAULTH pins for the propagated faults from the device above it in the stack.
When COMCONFIG[FAULT_HIGH_EN] = 1, the logic will monitor the receiver for falling edges. Under-frequency
conditions will set the STATUS[STACK_FAULT_DET] and STATUS[STACK_FAULT] flags. Note that this allows
every other pulse to be lost without reporting an error.
Over-frequency conditions will set the FAULT_COM[STK_FAULT_ERR] flag. Once proper signaling resumes on
the high-side fault pin, it will again be possible to clear this fault.
The fault heartbeat stops and FAULT_N asserts during any of the following conditions:
• The fault heartbeat stops on the high-side fault interface FAULTH pins (if not configured to ignore it)
• Some automatic feature in the device detects a fault; that is, the secondary protector VSENSE comparators,
checksum failure, automatic internal temperature sampling, and so forth
• A command to sample returned a value that was out of range and caused a fault
• An internal self-test fails
NOTE
The STK_FAULT_ERR may not be clearable under some conditions.
1. If a STK_FAULT_ERR is detected and then no more edges appear on the high-side fault pins
(as would be the case if the chip above had a fault condition), it may be impossible to clear the
STK_FAULT_ERR flag.
2. A masked STK_FAULT_ERR does not clear during initialization. As a result, there is an
approximately 4.5-µs window at startup during which, if the high-side fault receiver detects more
than four falling edges, STK_FAULT_ERR will be set even though it is masked.
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7.3.12.3.1 Fault Output Control
FO_CTRL allows groups of enabled faults to drive the pin when the appropriate bit is set. When the register bit is
set, any fault of the indicated type will cause the assertion of the fault outputs (FAULTL, FAULT_N) if they are
enabled—that is, FAULT_N will be driven low and the tone on FAULTL pins will be stopped.
The following groups of faults are enabled in this register (see FO_CTRL 0x6E–6F (110–111) Fault Output
Control for bit position details):
• Any UV fault (VSENSE inputs)
• Any OV fault (VSENSE inputs)
• Any UV fault (AUX inputs)
• Any OV fault (AUX inputs)
• Any UV fault (window comparators)
• Any OV fault (window comparators)
• Any communications fault (see FAULT_COM)
• Any system fault (see FAULT_SYS)
• Any device fault (see FAULT_DEV)
• Any GPIO fault (see FAULT_GPI)
7.3.12.3.2 Fault Masking
The following registers can enable or mask fault sources individually or in groups. Masking a fault prevents it
from being set, but does not clear an existing fault bit.
• MASK_COMM—Communications related faults
• MASK_SYS—System faults in power supplies, over temperature, and so on
• MASK_DEV—Internal register-checksum faults, and so on
• GP_FLT_IN—GPIO input level faults
• NCHAN—Masks faults for unused channels, turns off window comparators for unused channels
7.3.12.4 Fault Latching
When UNLATCHED_FAULT is set, the bits in some of the fault registers (see the following text and Register
Details for included registers) will automatically clear when the fault condition goes away. Continuously set faults
will clear when the condition goes away. Faults set by an event will clear when the event occurs (such as a
sampled channel will clear when that channel is sampled). In this mode, writing to the included fault registers will
have no effect. Unlatched faults, when detected and cleared, can result in creating transient behavior for the
associated flag bits, FAULT_N, and FAULTL.
Changes to the DEVCONFIG[UNLATCHED_FAULT] bit should only occur while no fault bits are set. The
latched/unlatched status of fault bits is undefined when the UNLATCHED_FAULT bit changes while a fault
bit = 1.
Fault bits in the following registers are unaffected by the DEVCONFIG[UNLATCHED_FAULT] bit and are always
latched:
• FAULT_COM—All bits
• FAULT_SYS—All bits, except INT_TEMP_FAULT
• FAULT_DEV—All bits
The DEVCONFIG[UNLATCHED_FAULT] bit, when set, prevents the latching of fault bits in the following
registers:
• FAULT_UV—Undervoltage VSENSE ADC limit exceeded
• FAULT_OV—Overvoltage VSENSE ADC limit exceeded
• FAULT_AUX—Programmable AUX threshold in AUXn_UV or AUXn_OV exceeded
• FAULT_2UV—Undervoltage VSENSE secondary protection comparator limit exceeded
• FAULT_2OV—Overvoltage VSENSE secondary protection comparator limit exceeded
• FAULT_SYS—INT_TEMP_FAULT bit only
• FAULT_GPI—GPIO (programmable) logic input level triggered a fault
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7.3.12.4.1 Special Considerations in Unlatched Fault Mode
In unlatched mode, when the FAULT_2UV and FAULT_2OV registers sense and record secondary protector
(window comparator) faults and one or more other analog die faults (that is, VP_FAULT, VDIG_FAULT, or
VM_FAULT) are present, none of the mentioned faults will clear until all have been cleared, even if the cause of
the fault has gone away. That is, they may appear latched until all these faults are clear.
If these faults (FAULT_SYS[VP_FAULT, VP_CLAMP, VM_FAULT, or VDIG_FAULT]) are present, it is
reasonable to assume that the comparators may not be functioning properly and/or may have stopped reporting
a fault because they stopped functioning rather than the fault condition having gone away.
7.3.12.5 Fault Status and Fault Reset
The following registers can read or reset the fault status individually or in groups:
• STATUS—Sum of all faults plus stack fault conditions are in this register, some fault information bits are reset
here. This register is at the top of the fault hierarchy.
• FAULT_SUM—Groups of faults are summarized by single flags in this register and may be either read or
reset here. This is level 2 of the fault hierarchy.
• FAULT_UV—Undervoltage VSENSE ADC limit exceeded. This is level 3 of the fault hierarchy.
• FAULT_OV—Overvoltage VSENSE ADC limit exceeded. This is level 3 of the fault hierarchy.
• FAULT_AUX—Programmable AUX threshold in AUXn_UV or AUXn_OV exceeded. This is level 3 of the fault
hierarchy.
• FAULT_2UV—Undervoltage VSENSE secondary protection comparator limit exceeded. This is level 3 of the
fault hierarchy.
• FAULT_2OV—Overvoltage VSENSE secondary protection comparator limit exceeded. This is level 3 of the
fault hierarchy.
• FAULT_SYS—System level faults: power supplies, over temperature, communications timeout, and reset.
This is level 3 of the fault hierarchy.
• FAULT_GPI—GPIO (programmable) logic input level triggered a fault. This is level 3 of the fault hierarchy.
• FAULT_COM—Communication faults. This is level 3 of the fault hierarchy.
• FAULT_DEV—Device faults. This is level 3 of the fault hierarchy.
7.3.12.6 Checksum Faults
To discover changes to registers, the bq76PL455A constantly runs a background check on their contents by
computing a checksum and comparing it to a stored value. The bq76PL455A detects changes approximately
every two microseconds. The changes can be intentional (that is, a change written by the microcontroller),
unintentional (due to an unexpected device or system fault), or, in some cases, the result of an automated
operation (expiration of the balancing timer). The test runs against the registers in both a TI space and USER
space. This includes most registers with changes that come from the microcontroller; consult Register Summary
for an exact list of included locations.
The CSUM_RSLT register holds the currently computed checksum value. It compares this value against the
stored checksum value in register CSUM. To update the stored value, read the current value in CSUM_RSLT
and write it back to the CSUM register or compute the value as shown in Computing User Checksum. A
checksum saves to CSUM in EEPROM by setting MAGIC1 and MAGIC2 appropriately, then setting
DEV_CTRL[WRITE_EEPROM]. The appropriate values for MAGIC1 and MAGIC2 definitions are in the Register
Details section of this document in the bit description field for the WRITE_EEPROM bit.
When CSUM and CSUM_RSLT do not match, the FAULT_DEV[USER_CKSUM_ERR] flag will be set until the
condition is corrected. This fault flag is unlatched and will self-clear when a mismatch no longer occurs.
Continuous monitoring of the TI EEPROM space occurs in a similar fashion, concurrently with the monitoring of
the USER space. If a register change is detected, the FAULT_DEV[FACT_CKSUM_ERR] flag is set. If this ever
occurs, the user firmware should perform a soft RESET of the part. This fault flag is not self-clearing. Write a 1 to
the bit to clear it. If a soft reset does not correct the issue, do not use the device.
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7.3.12.6.1 Checksum Testing
Each of the checksums (TI, USER spaces) has a test mode that causes each input bit in the checksum
calculation (that is, the register bits that are part of the checksum calculation) to flip twice (once per clock) and
the TEST_CSUM register contains the count for the number of toggles on the checksums fault output. This helps
to ensure that the background checksum testing described previously correctly discovers any bit that might be in
the wrong state.
The user's firmware, usually as a part of self-testing and validation, can initiate the tests. The
TESTCTRL[CKSUM_TEST_RUN] bits are set to begin the test on either the TI or USER space registers. See
TESTCTRL 0x20–21 (32–33) Test Control for details of the bit settings.
NOTE
Other faults may be set in the process of running this procedure, but ignore those.
7.3.12.6.1.1 Computing User Checksum
The user checksum is a 32-bit value computed using all the data values in the user data space. The computation
is a simple 32 bit add of registers and constants concatenated into 32-bit values. The computation, shown below,
consists of the data at the address specified or 0:
cust_cksum_calc =
{0, 0, 0, a3} +
{a4, a5, a6, a7} +
{0, 0, a10, a11} +
{0, a13, a14, a15} +
{a16, a17, a18, a19} +
{a20, a21, 0, 0} +
{0, 0, a30, a31}+
{0, 0, a34, a35}+
{a36, a37, 0, 0} +
{a40, 0, 0, 0}+
{0, 0,a50, a51}+
{a52, a53, a54, a55} +
{0, a61, a62, a63} +
{a64, a65, a66, a67} +
{a68, 0, 0, 0}+
{a104, a105, a106, a107} +
{a108, 0, a110, a111} +
{a120, a121, a122, a123} +
{0, a125, 0, 0}+
{a140, a141, a142, a143} +
{a144, a145, a146, a147} +
{a148, a149, a150, a151} +
{a152, a153, a154, a155} +
{a156, a157, a158, a159} +
{a160, a161, a162, a163} +
{a164, a165, a166, a167} +
{a168, a169, a170, a171} +
{a172, a173, a174, a175} +
{a176, a177, 0, 0} +
{a200, a201, a202, a203} +
{a204, a205, a206, a207} +
{0, 0, a210, a211} +
{a212, a213, a214, a215} +
{a216, a217, a218, a219} +
{a220, a221, a222, a223} +
{a224, a225, a226, a227};
NOTE
In the example code, a_
refers to register address
number. For example: a3 =
register address 0x03.
7.3.12.7 AUXn OV/UV Threshold Faults
The AUXn input pins can trigger a fault indication. The OV and UV thresholds for each AUXn input can be set
separately in the AUXn_OV and AUXn_UV registers. The result of each AUXn channel conversion is compared
to these values. When the threshold is exceeded (less-than AUXn_UV, greater-than AUXn[OV]), the FAULT_N
and FAULTL pins are asserted, if enabled. To stop unwanted FAULT pin assertions from one or more channels
(but other channels are desired), set the threshold voltage settings for the undesired channels to their minimum
and maximum values or only convert the desired channels.
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FAULT_AUX[AUX_UV_FAULT, AUX_OV_FAULT] will be continually set based on the currently stored ADC
result and threshold. This allows testing of the threshold and fault by changing the threshold without having to
sample the channel.
Example:
The design requires AUX0 and AUX1 undervoltage threshold at 1 V and AUX0 and AUX1 overvoltage
threshold at 3 V. The design requires that no FAULT pin activation result from AUX UV or OV conditions on
AUX2…AUX7. Set the following conditions:
AUX0_UV = 1 V, AUX0_OV = 3 V
AUX1_UV = 1 V, AUX1_OV = 3 V
AUX2_UV = 0 V, AUX2_OV = 5 V
AUX3_UV = 0 V, AUX3_OV = 5 V
AUX4_UV = 0 V, AUX4_OV = 5 V
AUX5_UV = 0 V, AUX5_OV = 5 V
AUX6_UV = 0 V, AUX6_OV = 5 V
AUX7_UV = 0 V, AUX7_OV = 5 V
7.3.12.8 Secondary Protectors: Analog Window Comparators for Cell UV/OV
Thirty-two analog comparators, connected in pairs as window comparators for the 16 channels, provide cellvoltage monitoring that is separate from the main acquisition path and work in parallel with the main ADC route.
Configuration of the faults sensed by the analog window comparators is by the number of channels enabled in
the NCHAN register. In case of malfunction of the AFE or ADC, the analog comparators will still be able to flag
the crossing of the (register selectable) undervoltage and overvoltage comparator thresholds.
To avoid undesired comparator faults, two internal DACs set the separate overvoltage (COMP_OV) and
undervoltage (COMP_UV) thresholds. The DACs use the REF2 (4.5 V) reference, which is a separate circuit
from the 2.5 V (VREF) ADC reference. The OV threshold can range from 2 V to 5.175 V in steps of 25 mV. The
UV threshold can range from 0.7 V to 3.875 V in steps of 25 mV.
NOTE
When the cell voltage is very close to the comparator thresholds, enabling or disabling cell
balancing may result in transient comparator faults.
Use the DEVCONFIG[COMP_CONFIG] register to enable OV and UV faults, OV-only faults, or no faults.
Enabling UV-only faults is not possible.
NOTE
If the comparators are disabled then re-enabled during normal operation (such as after
startup has occurred), the OV faults are signaled and must be manually cleared.
7.3.12.8.1 Window Comparator Special Considerations
As shown in Figure 24, there are resistors of approximately 100 Ω in series with each VSENSE pin that isolate
the connections to the AFE from the secondary-protector circuits (window comparators). This isolator allows
detection of common-cause failures affecting both the AFE and secondary-protector circuits.
A Squeeze function in the device helps to detect open-sense wire (to the monitored cell) conditions. When the
Squeeze function turns on, it places an approximately 5-kΩ resistance across adjacent VSENSE inputs, and
creates an additional voltage drop through the approximately 100-Ω series resistors. This causes the apparent
increase in the voltage applied to the window-comparator blocks immediately above, and below, the inputs that
have the Squeeze resistor applied. Only the comparators can see the increased voltage not the AFE. This in turn
may cause the OV comparator fault to trip, even if the external sense-pin voltage measurement says otherwise,
depending on the OV threshold.
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CAUTION
Using the Squeeze function under open wire conditions and with a broken connection
to the external Zener may cause internal device damage to occur.
It is highly recommended to run all diagnostic tests on the bq76PL455A after correction of the open wire
condition. Pay special attention to the validation of the window comparator accuracy against the AFE accuracy to
ensure parametric compliance. In the event of non-compliance, remove the affected bq76PL455A device from
service immediately.
In the example in Figure 24, the Squeeze resistor is enabled for (across) VSENSEn-1 to VSENSEn. This will
cause the apparent voltage seen by the comparators for cell n–1 and cell n+1 to increase. For the cell voltage of
cell n, which in this example is approximately 3.6 V, there will be an additional drop on the internal lines going to
the window-comparator block (but not to the AFE) of (3.6 V / 5K × 100 × 2) = approximately 144 mV. This will
also show up as an increase of approximately 72 mV on the cells above and below the cell being squeezed.
Larger input resistors, such as 1 kΩ, will dominate this error source and may result in unexpected trips of the
window comparators, depending on the threshold settings, and will change the manner in which the calculations
suggested in this example are made.
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~100 Ÿ
+
AFE LVL
SHIFT
±
VSENSEn+1
100 Ÿ
1 µF
~100 Ÿ
~5k
+
WINDOW
COMP
±
SQUEEZE
~100 Ÿ
+
AFE LVL
SHIFT
±
VSENSEn
100 Ÿ
1 µF
~100 Ÿ
~5N Ÿ
+
WINDOW
COMP
±
SQUEEZE
~100 Ÿ
+
AFE LVL
SHIFT
±
VSENSEn-1
1 µF
~100 Ÿ
GND
100 Ÿ
LOW PASS
FILTER
+
WINDOW
COMP
±
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Figure 24. Window Comparator Input Configuration Overview
7.3.12.9 Communications Faults
During the course of normal data communications, noise may induce errors in the bit stream. The errors may
assert faults depending on the mask settings in the MASK_COMM and MASK_SYS registers.
• UART communications faults details are in UART Interface to Host Microcontroller
• Differential (VBUS) communications faults description is a part of the protocol description in Protocol
Description
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7.3.12.10 Communications Timeout Counters
Check the communication timeout counters by setting and reading the 24 most-significant bits of the timeout
counter using COMM_TIM_CNT. A 4-kHz clock source drives the timeout counter. To aid this testing,
CCNT_RST_OFF may be set so the communication sent to either set or monitor the counter does not reset the
counter. The counter value may be set using COMM_TIM_CNT to enable faster testing of long periods. The bits
that are not accessible are set to '1' by writing to this register, to test the counter rollovers quickly.
7.3.13 Built-in-Test Functions
To access the built-in-test functions, set bits in the various registers. The identification of these bits are in the
descriptions of the appropriate registers and their bits in Register Details.
7.3.13.1 Safety Manual and FMEDA
The Safety Manual for bq76PL455A-Q1 (SLUUB67) is available on ti.com. Please contact your TI Sales
Associate or Applications Engineer for the bq76PL455A-Q1 FMEDA (SLUUB93).
7.4 Device Functional Modes
The bq76PL455A device has three power states (modes):
• SHUTDOWN (sleep)—The lowest power state used for long periods of inactivity to extend battery life.
• IDLE—The default condition when awake and ready to receive and execute commands.
• ACTIVE—The highest power state while communicating; that is, IDLE + communications activity.
7.4.1 SHUTDOWN
SHUTDOWN is the lowest power state available in the part. In this state, power is off and monitoring disabled for
most internal blocks. Typically, SHUTDOWN is for long periods of inactivity when the battery is not being
charged or discharged. The part must receive a high signal on the WAKEUP pin or a WAKEUP tone through the
vertical communications bus to transition to the IDLE state.
To enter SHUTDOWN, remove external voltage sources of VP, VDIG, and all input voltage sources to AUX pins
and other I/O pins. VIO can remain while in SHUTDOWN mode and GPIO can remain if based on VIO. While in
SHUTDOWN mode, VP and VDIG must remain off or be disabled to avoid back powering the bq76PL455A
through internal ESD structures. When VIO is lowered, the bq76PL455A will immediately go into reset. Holding
VIO for longer than VIOSD_DLY MAX will cause the device to enter SHUTDOWN mode.
The WAKEUP pin must be held in the low state to allow the device to enter and remain in the SHUTDOWN state
(setting the pin low does not place the device in SHUTDOWN). If the WAKEUP pin remains in the high state, the
device will cycle off and immediately back on. Operation is unpredictable if the WAKEUP pin floats, so take care
to keep this pin in a defined state. This is not harmful to the device, but may not provide the expected behavior in
the system.
If the NPN circuit is not used (external supply), VP and VDIG should turn off immediately after entering shutdown
mode. Lowering VP and VDIG will also put the device in SHUTDOWN mode.
The part will enter SHUTDOWN when any of the following conditions occur:
• The user requested SHUTDOWN through a command by asserting DEV_CTRL[PWRDN], usually with a
broadcast form of the command. The WAKEUP pin on the base bq76PL455A must remain in the low state.
• There was a communications timeout caused by the timer set in register CTO[COMM_PD_PER] due to:
– No valid frames (packets) received in the set period, <OR>
– TSTCONFIG[CCNT_RST_OFF] is set and the timer expired whether valid frames were received or not,
usually as a part of BIST.
• TSTCONFIG[VDIG_TEST] was set at some time since the last SHUTDOWN <AND> VDIG dropped below its
SHUTDOWN threshold (DDIEPOR). Once set, subsequently clearing TSTCONFIG[VDIG_TEST] will not
disable this control even though the bit will read 0. It will not disable until the device enters shutdown.
• One of the two thermal shutdown (TSD) circuits sensed an overtemperature condition (there is one sensor on
each die that operates separately, with separate register flag indicators).
• VIO was below its VIOPOR threshold for longer than VIOSD_DLY.
• V5VAO was below the V5VAOSD POR threshold.
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Device Functional Modes (continued)
•
Internal VP regulator is on and attempting to drive the NPNB signal, but VP remains below the internal VP
POR threshold for longer than VPSD_DLY.
NOTE
Once in the SHUTDOWN state, the part must be re-awakened to continue normal
operations. See Wakeup Behavior from SHUTDOWN.
7.4.2 Wakeup
The bq76PL455A device will wake up and enter the IDLE state when either of the following conditions occurs:
• WAKEUP pin is high
• COMML pins receive the WAKE tone
7.4.3 Wakeup Behavior from SHUTDOWN
The WAKEUP pin can bring the part from the SHUTDOWN state to the IDLE state. It can do this in any stack
position. However, typically only the base device uses it when driven from a microcontroller. The pin is level
sensitive and is normally at a low (logic-zero) level. When the part is in SHUTDOWN and the WAKEUP pin
becomes high, the part will transition from SHUTDOWN to IDLE. After applying the high signal, the WAKEUP pin
must de-assert and then return to the low state to allow the part to enter SHUTDOWN again. Upon changing
state, the bq76PL455A will briefly transmit a differential wakeup tone on its COMMH+ and COMMH– pins to the
next higher bq76PL455A, where that device's COMML+ and COMML– pins receives it.
NOTE
The WAKEUP pin is usually kept in the de-asserted (low) state. If the pin is asserted
(high) and then the device is commanded to SHUTDOWN, it will immediately reawaken
and become IDLE. To prevent unexpected state transitions, this pin must not be floating.
Make sure that the pin does not float if the device driving the pin has no power.
The bottom (southernmost) device in the stack sends the wakeup tone out of the COMMH pins in response to
the WAKEUP pin assertion. The next device to the north receives the WAKEUP tone on its COMML pins. It
awakens, which in turn sends the WAKEUP tone to the next device above it. The WAKEUP tone propagates up
the stack in this way to wake all devices in the stack. While the part is in SHUTDOWN, the COMML pins are in
receive mode, and no transmission will occur.
7.4.4 Power-On Reset (POR) or Wakeup
The IC's state machine fully resets at wakeup. Wakeup causes the VP/VDIG output to come up, which in turn
brings up VDD18, providing power to portions of the analog circuits and to all of the core logic, including the
registers and the EEPROM. This is effectively a POR of the part. All registers are loaded with values stored in
EEPROM. Registers that are not loaded from EEPROM reset to their default values indicated in Table 7.
NOTE
Immediately following a reset for any reason, some faults are not valid (=0) until a sample
is taken. All fault bits in registers FAULT_UV, FAULT_OV, and FAULT_AUX are invalid. In
addition, bits FAULT_DEV[HREF_FAULT, HREF_GND_FAULT] are also invalid. Reading
a fault register will not cause the taking of a sample or updating of the bits. A command
must be sent to the device to sample all channels to update the above listed fault bits,
making them valid.
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Device Functional Modes (continued)
Note that this sequence is the same regardless of the reset source—POR, soft reset, wake tone received from
the part below.
1. External NPN regulator circuit turns on. VP, VDIG, (and VIO if connected to VP) begin to ramp up. If VIO is
supplied by an external source (such as the microcontroller I/O power supply), then VIO must be stable and
greater than its POR threshold.
2. Once VDIG reaches its POR threshold, the internal 1.8 V (internal digital supply VDD) regulator begins to
ramp up. Once VDIG reaches the POR threshold, VREF and the internal 1.8 V supply (VDD18) start up. The
reference for the VDD (1.8 V) supply is VREF, so it will not reach its final operating voltage until VREF
reaches its final voltage.
3. Once VP, VDIG, VIO, and VDD all reach their POR thresholds, the oscillator starts.
4. Once the oscillator is running, the Finite State Machine (FSM) starts up and begins sending the wake tone
out of the high-side interface (COMMH±).
5. The FSM in turn waits approximately 10 µs for the EEPROM to be ready.
6. All system registers will be loaded from EEPROM.
7. Relevant information will be propagated to the Analog die registers, except regulator power down.
8. If GPIO addressing is enabled (DEVCONFIG[ADDR_SEL] = 0), the GPIO[4:0] pins are sampled to determine
the device's communication address and recorded in ADDR.
9. Sample the internal Digital-die temperature channel. This pre-loads the value, so temperature-based
calibration will function properly. No other channels will be sampled during initialization and faults will not be
generated from them until after they are sampled.
10. Clear any masked faults that could have occurred. This includes clearing threshold-based faults that are
masked by their threshold.
11. Begin monitoring for UART communications.
12. Initialize Analog die faults. (Continue sequencing in parallel; do not wait for the following sub-sequence to
complete.)
(a) Wait until no VM fault is reported from Analog die or the user writes '1' to STATUS[SYS_INIT].
(b) Enable all Analog die fault registers.
(c) Set STATUS[SYS_INIT] = 0.
13. Wait for wakeup tone to complete.
14. Begin monitoring for differential communications.
15. Once the FAULT_SYS[SYS_RESET] fault is cleared by the host microcontroller, turn off the external NPNregulator circuit if the regulator is disabled (that is, DEVCONFIG[REG_DISABLE] = 1).
While the system initialization sequence above is in progress (while SYS_INIT reads '1'), many faults will not
report properly and sampling commands may not function properly. Also, note that aborting the initialization
sequence (by writing '1' to SYS_INIT) may cause the reporting of erroneous faults and sampling of Analog
channels to report invalid results until the VM voltage is up and stable.
Additionally, there is a delay associated with the enabling of the UART communications and a delay associated
with the completion of the initialization process once the VM fault clears (or the user aborts the initialization
sequence).
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Device Functional Modes (continued)
7.4.5 Calculating Wakeup Timing
The following sequence assumes that the microcontroller power circuit provides the VIO supply. The host
microcontroller initiates the sequence and the VIO is up and stable. (The sequence does not change if VIO is tied
to the regulator. However, if some other source is providing WAKEUP, but the microcontroller provides the VIO
supply, the VIO supply needs to clear the POR threshold within VIOSD_DLY of WAKEUP or the part will go back
into shutdown.)
1. The user asserts the WAKEUP pin on the bottom board's base device.
2. At this point, the VP regulator will turn on and ramp the VP/VDIG supplies. The time required to reach the
POR thresholds for VP/VDIG varies and is dependent on the designer's component selection. (Note that
VP/VDIG/VIO must all reach their respective POR thresholds.) Once VP reaches its POR threshold, VREF
will also need to ramp to its operating voltage.
3. The time from reaching the POR thresholds to the start of the wakeup tone being transmitted from the highside interface is specified as tWAKEUP_DLY.
4. The time from the start of the wakeup tone being transmitted until communications are allowed to this part is
specified as tWAKEUP_TO_UART.
NOTE
It is acceptable to begin communicating with the part at this point, if it is the only part in
the stack. If there are additional parts in the stack, you can still begin communicating with
the bottom part at this point. However, this may cause communications error flags to get
set in bq76PL455A parts positioned higher in the stack.
5. The time from the wakeup tone transmission from the high side of the device below (end of step 3), until the
regulator turns on the current board, is (tWAKE_TONE_DLY_DC – tWAKEUP_DLY).
6. The regulator turns on and ramps the VP/VDIG/VREF/VIO supplies. As with the bottom device, this time is
board dependent.
7. The time from reaching the POR thresholds to the start of the wakeup tone being transmitted from the highside interface to the next device up the stack is specified as tWAKEUP_DLY. Note that for calculation purposes to
group #5 and #7 together as tWAKE_TONE_DLY_DC.
8. The time from the wakeup tone being transmitted from the high-side interface until you are allowed to
communicate with this part is specified as tWAKEUP_TO_DCOMM.
If there are additional parts in the stack, apply steps 5–8 accordingly.
To compute the total time from assertion of WAKEUP to the stack being ready for communications, we will
define:
• tBOT_RAMP as the time needed for the supply ramp on the bottom board. The above steps must be used to
determine the wakeup time for the bottom board.
• tSTACK_RAMP as the time needed for the supply ramp on all stacked boards
• nSTACK_BOARDS as the number of stacked boards (not including the bottom board)
If there is only one device, then the required delay from WAKEUP until it is acceptable to begin communicating
will be:
tBOT_RAMP + tWAKEUP_DLY + tWAKEUP_TO_UART
(8)
Else, if there is more than one board in the stack, the delay from WAKEUP until it is acceptable to begin
communicating will be:
tBOT_RAMP + tWAKEUP_DLY + nSTACK_BOARDS * (tSTACK_RAMP + tWAKE_TONE_DLY_DC) + tWAKEUP_TO_DCOMM
(9)
It is generally acceptable to start communicating with the stack once the bottom UART interface is ready for
communications. However, parts above in the stack may not respond until their required times. It is also possible
to cause communication error flags to be set in the parts above by doing this. As mentioned previously, the
fastest way to get the stack talking (assuming all parts have the EEPROM burned for their stack location and
configuration) may be to continuously send a read request to the top device until it responds and then clear all
communications errors that occur because of this.
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Device Functional Modes (continued)
If you try to send communications to the bottom device before the UART interface is ready, it can get out of sync.
To fix this, send a comm_clear. This is not necessary for parts on the differential interface, since they will resynchronize to the bottom chip on every frame. Therefore, only the bottom chip can lose synchronization.
7.4.6 Soft Reset
Setting the SOFT_RESET bit in the DEV_CTRL register will not power down the device, but it will fully reset and
restart the state machine per the sequence in Power-On Reset (POR) or Wakeup. All ICs in the stack above the
reset part will wake up if in SHUTDOWN and reset if awake.
7.4.7 Wakeup Behavior in IDLE Mode
When the bq76PL455A device receives a WAKEUP tone while it is already awake, it performs a reset. The
device requires a series of pulses of the received WAKEUP tone to begin the reset process. Sending the tone
will wake the device if asleep or reset it if idle. The result is that sending the wakeup tone to parts in the stack
can be used to reset them and cause all to enter the IDLE state whether they were previously in SHUTDOWN or
IDLE. This is another method to reset the state of all devices in the stack.
The device will generate a wakeup tone to the other devices north in the chain as a part of the reset sequence.
As a result, each device above the device receiving the wake tone will in turn reset.
7.5 Command and Response Protocol
This protocol enables a single host, such as a microcontroller, to communicate with one or more bq76PL455A
devices. The host initiates every transaction between the host and one or more bq76PL455A devices. The
bq76PL455A will never send data to the host without first receiving a command frame from the host.
NOTE
After each command frame is transmitted, the initiator should always wait for all expected
responses to be returned (or a timeout in case of error) before initiating a new command
frame.
The phrases Write without Response and Write or write are equivalent and synonymous,
unless otherwise noted.
The phrases Write with Response and Read or read are equivalent and synonymous,
unless otherwise noted.
7.5.1 Transaction Frame Description
The transaction frame format includes both Command Frames and Response Frames. There are five field types
used within a transaction frame:
1. Frame Initialization
2. Device Address or Group ID
3. Register Address
4. Data
5. Cyclic Redundancy Check (CRC)
Note that not all byte types are part of every transaction frame.
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Command and Response Protocol (continued)
7.5.1.1 Frame Initialization Byte
The Frame Initialization Byte is always the first byte of the frame. In all cases, the length of the frame can be
determined from this initial byte. Note that bit 7 identifies each frame as either a command frame or a response
frame. The initialization byte is defined as follows for each of the two Frame Init types:
7
6
Command Frame Init
FRM_TYPE = 1
Response Frame Init
FRM_TYPE = 0
5
4
REQ_TYPE
3
2
ADDR_SIZE
1
0
DATA_SIZE
RESP_BYTES-1
The descriptions for the fields shown in the frame initialization bytes are in Table 4.
Table 4. Frame Initialization Byte Fields
VALUE (BINARY)
FRM_TYPE
REQ_TYPE
ADDR_SIZE(1)
DATA_SIZE(2)
RESP_BYTES-1
DESCRIPTION
0
Response Frame
1
Command Frame
000
Single Device Write with Response
001
Single Device Write without Response
010
Group Write with Response
011
Group Write without Response
100
Reserved
101
Reserved
110
Broadcast Write with Response
111
Broadcast Write without Response
0
8-bit Register Address
1
16-bit Register Address
000
0 bytes
001
1 byte
010
2 bytes
011
3 bytes
100
4 bytes
101
5 bytes
110
6 bytes
111
8 bytes
Number of data bytes contained in response frame minus 1
(1) ADDR_SIZE = 0 is recommended. All USER registers are addressable using an 8-bit register address.
(2) Data size of 7 bytes is not supported.
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7.5.1.2 Device Address/Group ID Byte
The Device Address or Group ID Byte identifies the device or group of devices targeted by the command. Only
those devices that contain a matching value in their Device Address Register (register address 10) or Group ID
Register (register address 11) will respond to the command. The REQ_TYPE field in the command frame will
determine how to interpret this byte.
NOTE
Device Address/Group ID Byte is not present in a Broadcast command frame.
7
Device Address or Group ID
6
5
4
3
2
1
0
Identifier of device(s) receiving communication (always one byte)
7.5.1.3 Register Address Byte(s)
Register addresses can be one or two bytes in length. For single byte addresses (ADDR_SIZE = 0), the MSB is
not transmitted and is assumed to be 0.
7
6
5
Register Address (MSB)
4
3
2
1
0
Register being targeted
Register Address (LSB)
7.5.1.4 Data Bytes
The basis of data byte interpretation is from the type of command frame being sent and the target register
specified in the command frame.
For command frames targeted at the Command Register (address 2), the data contains the command, highest
responding device address and, optionally, new data for the Command Channel Select Register (address 3–6)
and Averaging Register (address 7).
For command frames targeted at other registers:
•
•
If REQ_TYPE is Write without Response, the data bytes contain the values to be written to the registers
If REQ_TYPE is Write with Response, the data bytes contain the values returned from the registers
7
Data[0]
…
Data[n]
6
5
4
3
2
1
0
Data Bytes (the number of bytes should match the DATA_SIZE field in the Frame
Initialization byte)
NOTE
Transactions with seven data bytes are not possible.
7.5.1.5 CRC Bytes
7
CRC (MSB)
CRC(LSB)
6
5
4
3
2
1
0
16-bit CRC (CRC-16-IBM—See CRC Description)
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7.5.2 CRC Description
The standard CRC-16-IBM algorithm uses the following CRC generator polynomial:
X16 + X15 + X2 + 1
In general, a CRC (cyclic redundancy check) represents the remainder of a process analogous to polynomial
long division, where the frame being checked is divided by the generator. The CRC appended to the frame is the
remainder. Because of this process, when the device receives a frame, the CRC calculated by the receiver
across the entire frame including the transmitted CRC will be zero, indicating a correct transmission and
reception. A non-zero result indicates a communication error.
The CRC calculation by the transmitter is in bit-stream order across the entire transmission frame (except for the
CRC, of course). When determining bit-stream order for implementing the CRC algorithm, it is important to note
that protocol bytes transmit serially, least-significant bit first.
An efficient, 8-bit parallel C function that can be utilized directly is included at the end of this section. The
following pseudo-code algorithm is a more easily described bitwise implementation of the CRC algorithm utilizing
the CRC-16-IBM generator polynomial:
CRC='0000_0000_0000_0000'
DIN={(frame in bit-stream order), '0000_0000_0000_0000'};
for n=0 to length_in_bits(DIN)-1{
CRC15:0=[(CRC0^DINn), CRC15, (CRC14^CRC0), CRC13:2, (CRC1CRC0)};
};
In this notation, subscripts represent zero-based bit selection from either the frame-data bit stream or the 16-bit
CRC (as it is being calculated); strings in single quotes (') represent binary constants; the caret (^) denotes a
single-bit exclusive-or operation; and the curly-brace – comma ({a, b, … c}) expressions denote bitwise
concatenation. Underscores (_) are only to enhance readability and can be ignored.
The 16-bit CRC is initialized to all 0-bits. DIN is the frame to be transmitted or received in bit-stream order, with
sixteen 0-bits appended to the end. The expression length_in_bits(DIN) will equal the length of the input in bytes
× 8 + 2. The for loop is intended to iterate over DIN one-bit at a time in bit-stream order. CRC15:0 is the 16-bit
CRC for transmittal (or checked in the case of a received frame). Note that the bitwise concatenation on the
right-hand side of the CRC equation is also 16-bits in total length.
The bit numbers in the equation for the CRC (inside the for loop) have been chosen so that X16 in a formal
mathematical description (such as the specification of the CRC-16-IBM generator polynomial) corresponds with
bit 0 in the subscript notation in the pseudo-code. In the pseudo-code, bit 0 is the least-significant bit and is on
the right-hand side of the concatenation. Bit0 is the first bit transmitted on the wire using serial communication.
An artifact of this notation and algorithmic choice is that the final CRC of the algorithm is byte-reversed with
respect to how the device will store the values in memory. Specifically, the byte labeled CRC (MSB) in the frame
descriptions throughout this document is the low order byte of the CRC generated by both the pseudo-code and
the C function, and the byte labeled CRC (LSB) is the high order-generated byte. The advantage of arranging the
generated CRC word in this way is that no bit-level reversal is needed.
The following example will be useful to an algorithm implementer to verify that the final implementation is correct.
In this example, an initiator (microcontroller) is generating a CRC for a command frame. The following is a
sample frame for use:
7
Command Frame Init
50
1
6
5
4
3
001 (binary)
0
Device Address
03
Register Address
07
Data
05
CRC (MSB)
1E
CRC (LSB)
CF
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1
0
001 (binary)
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For this example, by the time the for loop in the pseudo-code previously described is executed, CRC is 0 and
DIN (in hex bytes) is 91, 03, 07, 05, 00, 00. In bit-stream order, this becomes:
DIN = '1000_1001_1100_0000_1110_0000_1010_0000_0000_0000_0000_0000'
As the for loop executes, the CRC value, based on each subsequent bit of DIN, progresses as follows:
n
DINn
CRC15:0
n
DINn
CRC15:0
n
DINn
CRC15:0
0
1
1000 0000 0000 0000
16
1
0010 0001 1100 1001
32
0
0100 1010 0001 0101
1
0
0100 0000 0000 0000
17
1
0011 0000 1110 0101
33
0
1000 0101 0000 1011
2
0
0010 0000 0000 0000
18
1
0011 1000 0111 0011
34
0
1110 0010 1000 0100
3
0
0001 0000 0000 0000
19
0
1011 1100 0011 1000
45
0
0111 0001 0100 0010
4
1
1000 1000 0000 0000
20
0
0101 1110 0001 1100
36
0
0011 1000 1010 0001
5
0
0100 0100 0000 0000
21
0
0010 1111 0000 1110
37
0
1011 1100 0101 0001
6
0
0010 0010 0000 0000
22
0
0001 0111 1000 0111
38
0
1111 1110 0010 1001
7
1
1001 0001 0000 0000
23
0
1010 1011 1100 0010
39
0
1101 1111 0001 0101
8
1
1100 1000 1000 0000
24
1
1101 0101 1110 0001
40
0
1100 1111 1000 1011
9
1
1110 0100 0100 0000
25
0
1100 1010 1111 0001
41
0
1100 0111 1100 0100
10
0
0111 0010 0010 0000
26
1
0100 0101 0111 1001
42
0
0110 0011 1110 0010
11
0
0011 1001 0001 0000
27
0
1000 0010 1011 1101
43
0
0011 0001 1111 0001
12
0
0001 1100 1000 1000
28
0
1110 0001 0101 1111
44
0
1011 1000 1111 1001
13
0
0000 1110 0100 0100
29
0
1101 0000 1010 1110
45
0
1111 1100 0111 1101
14
0
0000 0111 0010 0010
30
0
0110 1000 0101 0111
46
0
1101 1110 0011 1111
15
0
0000 0011 1001 0001
31
0
1001 0100 0010 1010
47
0
1100 1111 0001 1110
The computed CRC value is '1100_1111_0001_1110'. The 16-bit CRC consists of two bytes, which this algorithm
produces in reverse order. The correct ordering of these two bytes in the command frame is MSB first, LSB last
(that is, '0001_1110' followed by '1100_1111' or in hex, 1E, CF). The intention is for these two bytes to transmit
serially starting with the least-significant bit of each.
Take great care when implementing the CRC algorithm to ensure that the bit ordering convention is consistent in
the entire frame including the CRC. The implementer should check several examples from this document against
the data generated by the algorithm for use to ensure that the implementation is correct. The final command
frame as it passes to a UART is:
COMMAND FRAME BYTES
Command Frame Init
91
Device Address
03
Register Address
07
Data
05
CRC (MSB)
1E
CRC (LSB)
CF
The algorithm for checking a frame is similar. As an example, to check this frame, one possible implementation
would be to simply calculate the CRC the first four bytes (excluding the CRC) and compare it with the received
CRC value. Another option would be to take advantage of the cyclic nature of the CRC algorithm, passing all six
bytes through, and then verifying that the result is 0. In this case, the initial zero padding of DIN with sixteen
zeroes will not be necessary. The resulting calculation would progress as follows, resulting in a final CRC value
of 0, indicating a successful check:
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n
DINn
CRC15:0
n
DINn
CRC15:0
n
DINn
CRC15:0
0
1
1000_0000_0000_0000
16
1
0010_0001_1100_1001
32
0
0100_1010_0001_0101
1
0
0100_0000_0000_0000
17
1
0011_0000_1110_0101
33
1
0000_0101_0000_1011
2
0
0010_0000_0000_0000
18
1
0011_1000_0111_0011
34
1
0010_0010_1000_0100
3
0
0001_0000_0000_0000
19
0
1011_1100_0011_1000
45
1
1001_0001_0100_0010
4
1
1000_1000_0000_0000
20
0
0101_1110_0001_1100
36
1
1100_1000_1010_0001
5
0
0100_0100_0000_0000
21
0
0010_1111_0000_1110
37
0
1100_0100_0101_0001
6
0
0010_0010_0000_0000
22
0
0001_0111_1000_0111
38
0
1100_0010_0010_1001
7
1
1001_0001_0000_0000
23
0
1010_1011_1100_0010
39
0
1100_0001_0001_0101
8
1
1100_1000_1000_0000
24
1
1101_0101_1110_0001
40
1
0100_0000_1000_1011
9
1
1110_0100_0100_0000
25
0
1100_1010_1111_0001
41
1
0000_0000_0100_0100
10
0
0111_0010_0010_0000
26
1
0100_0101_0111_1001
42
1
1000_0000_0010_0010
11
0
0011_1001_0001_0000
27
0
1000_0010_1011_1101
43
1
1100_0000_0001_0001
12
0
0001_1100_1000_1000
28
0
1110_0001_0101_1111
44
0
1100_0000_0000_1001
13
0
0000_1110_0100_0100
29
0
1101_0000_1010_1110
45
0
1100_0000_0000_0101
14
0
0000_0111_0010_0010
30
0
0110_1000_0101_0111
46
1
0100_0000_0000_0011
15
0
0000_0011_1001_0001
31
0
1001_0100_0010_1010
47
1
0000_0000_0000_0000
There are many good sources for algorithms and efficient techniques for generating and checking CRCs
available on the Internet. The following byte-oriented C language routine has been developed and verified as a
reference. The only complication needed to take into account using this function is that the low byte of the CRC
value returned is the CRC (MSB) and the high byte is the CRC (LSB).
Uint16 crc_16_ibm(uint8 *buf, uint16 len) {
uint16 crc = 0;
uint16 j;
while (len--) {
crc ^= *buf++;
for (j = 0; j < 8 8; j++)
crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0);
}
return crc;
}
7.5.3 Transaction Frame Examples
To illustrate the various Command and Response formats, examples of representative transaction-frame types
are presented in the following paragraphs. All numeric values are in hexadecimal unless otherwise noted. The
CRC values in the examples are correct and the implementer can use them to verify the CRC algorithm. Unless
specifically noted otherwise, all examples use 8-bit register addressing.
Additional communication examples with matched command and response frames are in the bq76PL455A-Q1
Software Design Reference (SLVA617).
Command Frames fall into two general categories:
1. Command frames that generate one or more response frames
2. Command frames that do not generate response frames
The REQ_TYPE field in the Frame Initialization byte determines the category to which a command frame
belongs. Category 1 contains the Single Device Write with Response, Group Write with Response, and
Broadcast Write with Response request types. Category 2 contains the Single Device Write without Response,
Group Write without Response, and Broadcast Write without Response request types.
Command frames that generate response frames, may generate more than one response frame. This depends
on the specific command frame and the number of devices addressed by the command frame. In the case where
more than one response frame is received in response to a single command frame, each response frame will be
a complete frame containing the Frame Initialization, Data, and CRC bytes. A single device will not respond with
more than a single-response frame in response to any single-command frame.
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Special care should be taken when addressing the Command Register (address 2). When sending command
frames that generate response frames to this register, the length of a response frame is dependent on the
content of the Command Channel Select Register (address 3–6). When addressing multiple devices, the
response from each device may vary in length depending on the configuration of the addressed device.
Additionally, there may be a delay in the expected response(s) depending on the configuration information stored
in the Voltage and Internal Temperature Sampling Period Register (address 62), AUX Sampling Period Register
(address 63-66), and Test Sampling Period Register (address 67-68). All of the aforementioned registers affect
the channel sampling period.
7.5.3.1 Single Device Write with Response Command Frame
Interpretation of the Data field in a Single Device Write with Response frame depends on the target register of
the command.
If the target register is the Command Register (address 2), then the data bytes may contain the command, new
content for the Command Channel Select Register, and new content for the Averaging Register. If the data for
the Command Channel Register and Averaging Register are omitted from the Single Device Write with
Response Command Frame, then the previously configured values in those registers will be used. If the data are
included in the command frame, then these values will be written into the respective registers and used for the
requested sampling.
If the target register is not the Command Register, then the interpretation of the data bytes will be as the number
of bytes being requested from the bq76PL455A minus one, starting at the register address provided in the
Register Address byte of the command frame.
The DATA_SIZE field in the Frame Initialization byte should be written with the number of data bytes in the
command frame.
7.5.3.1.1 Single Device Write with Response to Command Register (Address 2)
The value of the DATA_SIZE field in the Frame Initialization byte for this case is typically 001 (1 byte), 101 (5
bytes) or 110 (six bytes). These variations correspond to commands which:
1. Send only the sample command request and expect the bq76PL455A to use the preprogrammed sampling
values in the registers that control sampling.
2. Send the sample command request and the value for the Channel Select Register (address 3–6), but expect
the bq76PL455A to use the preprogrammed value in the Averaging Register (address 7). The data bytes
from the command frame will overwrite the Channel Select Register.
3. Send the sample command request and the values for the Channel Select Register (address 3–6) and
Averaging Register (address 7). The data bytes from the command frame will overwrite the respective
register for both the Channel Select Register and the Averaging Register.
The size of the response frame in response to a command frame of this type is directly related to the number of
channels selected by either the preprogrammed data in the Channel Select Register (address 3–6) or the data
passed to the bq76PL455A in the command frame.
Three examples follow. All three examples target the device at Device Address 00, which is typically the address
of a single device or the address of the lowest device in a stack of devices.
7.5.3.1.1.1 Data Contains Command Only
For the purpose of this example, assume the following start conditions:
1. Content of Channel Select Register before command: 0FFF5500
2. Content of Averaging Register before command: 00
7
Command Frame Init
1
6
5
4
3
000 (binary)
0
Device Address
00
Register Address
02
Data (Command)
00
CRC (MSB)
29
CRC (LSB)
5C
2
1
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001 (binary)
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Notice that the DATA_SIZE field in the Frame Initialization byte is 001. This means this Command Frame
contains one data byte. This one data byte contains the Command for the Command Register (in this case 00).
For more details regarding the Command Register, refer to the Command Register in Register Details.
The expected response frame to this example command frame would contain 35 bytes: one Frame Initialization
byte, 32 data bytes (two bytes for each of the sixteen-selected channels), and two-CRC bytes.
The content of the CHANNELS register and of the OVERSMPL register will remain unchanged.
7.5.3.1.1.2 Data Contains Command and Channel Selection
For the purpose of this example (Table 5), assume the following start conditions:
1. Content of Channel Select Register before command: 0FFF5500
2. Content of Averaging Register before command: 00
Table 5. Command and Channel Selection Example
7
Command Frame Init
6
1
5
4
3
000 (binary)
2
0
Device Address
00
Register Address
02
Data (Command)
00
Data (Channel Select MSB)
FF
Data (Channel Select)
FF
Data (Channel Select)
01
Data (Channel Select LSB)
00
CRC (MSB)
C8
CRC (LSB)
09
1
0
101 (binary)
Notice that the DATA_SIZE field in the Frame Initialization byte is 5 (b'101). This means that the Command
Frame contains five data bytes. The first data byte contains the Command for the Command Register (in this
case 00). The second through fifth data bytes contain the channel selection data, which the device writes to the
Channel Select Register as part of this command. For more details on register usage, refer to Register Details
for details.
The expected response frame to this example command frame would contain 37 bytes: one Frame Initialization
byte, 34 data bytes (two bytes for each of the seventeen-selected channels), and two CRC bytes.
The content of the Channel Select Register will change. Resulting register content will be as follows:
1. Content of Channel Select Register after command: FFFF0100
2. Content of Averaging Register after command: 00
7.5.3.1.1.3 Data Contains Command, Channel Selection, and Averaging Selection
For the purpose of this example, assume the following start conditions:
1. Content of Channel Select Register before command: 0FFF5500
2. Content of Averaging Register before command: 00
Table 6. Command, Channel Selection, and Averaging Selection Example
7
Command Frame Init
54
1
6
5
4
3
000 (binary)
0
Device Address
00
Register Address
02
Data (Command)
00
Data (Channel Select MSB)
FF
Data (Channel Select)
FF
Data (Channel Select)
0F
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1
0
110 (binary)
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Table 6. Command, Channel Selection, and Averaging Selection Example (continued)
7
6
5
4
Data (Channel Select LSB)
3
2
1
0
00
Data (Averaging Select)
7B
CRC (MSB)
3D
CRC (LSB)
86
Notice that the DATA_SIZE field in the Frame Initialization byte is 6 (b'110). This means this Command Frame
contains six data bytes. The first data byte contains the Command for the Command Register (in this case 00).
The second through fifth data bytes contain the channel selection data, which the bq76PL455A device writes to
the Channel Select Register as part of this command. The sixth data byte contains the averaging configuration
data, which the device writes to the Averaging Register as part of this command. For more details on register
usage, refer to Register Details for details.
The expected response frame to this example command frame would contain 43 bytes: one Frame Initialization
byte, 40 data bytes (two bytes for each of the twenty selected channels), and two CRC bytes.
The content of the Channel Select Register and the Averaging Register will change. Resulting register content
will be as follows:
1. Content of Channel Select Register after command: FFFF0F00
2. Content of Averaging Register after command: 7B
7.5.3.1.2 Single Device Write with Response to Register(s) Other than Command Register
The value of the DATA_SIZE field in the Framing Initialization byte for this case is typically 001 (1 byte). The
interpretation of this value will be as the number of expected data bytes in the response frame minus one. For
instance, if the expectation were to be to read the four bytes contained in the Channel Select Register, the data
byte would contain 03 (four minus one).
Two examples follow. All examples in this section target the device at Device Address 00, which is typically the
address of a single device or the address of the lowest device in a stack of devices.
7.5.3.1.2.1 Requesting Four Bytes of Data from a Single Register
This command example requests four bytes of data, all from a single register. In the case of this example, the
four bytes will come from the Channel Select Register at address 3–6. The most-significant byte of the four-byte
register will be the first data byte in the response frame.
7
Command Frame Init
1
6
5
4
3
000 (binary)
0
Device Address
00
Register Address
03
Data (Desired Number of Bytes – 1)
03
CRC (MSB)
68
CRC (LSB)
CD
2
1
0
001 (binary)
Notice that the DATA_SIZE field in the Frame Initialization byte is 001. This means this Command Frame
contains one data byte. This data byte contains the desired number of response bytes minus one.
The response frame will contain seven bytes: one Frame Initialization byte, four data bytes, and two CRC bytes.
7.5.3.1.2.2 Requesting Multiple Bytes across Register Boundaries
It is possible to request data from multiple registers across register boundaries. When performing this type of
read, Reserved Register Addresses can also be in the block of registers being read. Reads of Reserved Register
Addresses will always return zero and one must count these bytes in the requested number of data bytes. In this
example, the request is for the data from three registers [the Channel Select Register (address 3–6), Averaging
Register (address 7), and Device Address Register (address 10)]. These registers contain six bytes of data;
however, two Reserved Register Addresses (addresses 8 and 9) lie between the Averaging Register (address 7)
and the Device Address Register (address 10), so the request must be for eight bytes of data.
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6
1
5
4
3
000 (binary)
2
0
Device Address
01
Register Address
03
Data (Desired Number of Bytes - 1)
07
CRC (MSB)
38
CRC (LSB)
CE
1
0
001 (binary)
NOTE
The DATA_SIZE field in the Frame Initialization byte is 1, indicating that this command
frame contains a single data byte. This data byte indicates the number of desired bytes in
the response (minus one).
The response frame will contain eleven bytes: one Frame Initialization byte, eight data
bytes, and two CRC bytes.
7.5.3.2 Single Device Write without Response Command Frame
A Single Device Write without Response command is indicated when FRM_TYPE = 1 and REQ_TYPE = 1. In
this example, the register address size is 8-bits (ADDR_SIZE = 0) and the data length written is 1 byte
(DATA_SIZE). No Response Frame is expected to be returned.
The command in the example writes a single byte value to the Averaging Register (address 7).
For the purpose of this example, assume the following start conditions:
1. Content of Averaging Register before command: 00
7
Command Frame Init
1
6
5
4
3
001 (binary)
0
Device Address
03
Register Address
07
Data (New Data for Target Register)
05
CRC (MSB)
1E
CRC (LSB)
CF
2
1
0
001 (binary)
The content of the Averaging Register will change. Resulting Averaging Register content will be: 05.
To write more than one byte to the bq76PL455A, the DATA_SIZE field in the Frame Initialization byte should be
updated and additional data bytes added to the command frame. A single command frame of this type can write
up to eight, data bytes.
7.5.3.3 Group_Write_With_Response Command Frame
There are several different ways to format the Group Write with Response command frame, and the
interpretation of the data bytes will be different depending on the command frame configuration.
The Group Write with Response, which targets the Command register (address 2), has several different
configurations. These configurations also differ from the two configurations of the Group Write with Response
when it is targeted to a register other than the Command register. Primary examples of these different
configurations are in the following sections.
It is important to note that devices in defined Groups must consist of devices with consecutive addresses. The
device with the lowest address should be located closest to the host (that is, higher addresses should be located
higher in the stack). Devices will respond to Group Write with Response command frames in order of decreasing
address. If an address does not exist, the device will stop the responses. The recommendation is to have a
group in which devices only have contiguous addresses. To establish Group IDs, program the Group ID Register
(address 11) of all devices in a specific group to the same value.
56
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NOTE
For the following configuration examples, assume a daisy chain of four devices with
addresses 00–03 in which devices at address 01 and address 02 belong to Group ID 01,
and the devices at address 00 and address 03 belong to Group ID 00.
7.5.3.3.1 Configuration 1: Group Write with Response to Command Register with Sampling Parameters Included in
Command Frame
In response to the command frame in this example, each bq76PL455A in the specified group will write the new
sample parameters into the CHANNELS and OVERSMPL registers, sample the channels identified in the data
parameters, store the results, and send a response frame containing the sample data. In this example, the user
expects two complete response frames, since there are two devices in the addressed group.
7
Command Frame Init
6
1
5
4
3
010 (binary)
0
Group ID
01
Register Address
02
Data (Command)
02
Data (Channel Select MSB)
FF
Data (Channel Select)
FF
Data (Channel Select)
55
Data (Channel Select LSB)
00
Data (Averaging Setting)
00
CRC (MSB)
04
CRC (LSB)
59
2
1
0
110 (binary)
For details on how to read the response, refer to Register Details. A simplified overview of the meaning of the
data bytes in this example is in the following table.
BYTE (HEX)
BYTE (BINARY)
DESCRIPTION
A6
1 010 0 110
Command frame, Group Write with Response = REQ_TYPE, 8-bit Register Addressing, 6 data
bytes = DATA_SIZE
01
00000001
Target is Group ID = 01
02
00000010
Target Register = 02 (Command Register)
02
000 00010
Upper three bits define Command sent to Command register, lower 5 bits is address of
highest device in group to respond
FF
11111111
Select Channels 16 to 9
FF
11111111
Select Channels 8 to 1
55
01010101
Select AUX6, AUX4, AUX2 and AUX0
00
00000000
Do not select temperature or additional channels
00
00000000
No averaging
04
00000100
CRC
59
01011001
CRC
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7.5.3.3.2 Configuration 2: Group Write with Response to Command Register without Sampling Parameters Included
in Command Frame
NOTE
Sampling parameters come from values already stored in the CHANNELS and
OVERSMPL registers.
In response to the sample command frame in this example, each bq76PL455A in the specified group will sample
the channels identified by the values currently stored in the Command Channel Select register (address 3–6) and
sample them using the averaging setting currently set in the Averaging register (address 7).
7
Command Frame Init
6
1
5
4
3
010 (binary)
2
0
Group ID
01
Register Address
02
Data (Command)
02
CRC (MSB)
F2
CRC (LSB)
9D
1
0
001 (binary)
For details on how to interpret the response, refer to Register Details. A simplified overview of the meaning of the
data bytes in this example is in the following table.
BYTE
(HEX)
BYTE (BINARY)
DESCRIPTION
A1
1 010 0 001
Command frame, Group Write with Response = REQ_TYPE, 8-bit Register Addressing, 1 data byte =
DATA_SIZE
01
00000001
Target is Group ID = 01
02
00000010
Target Register = 02 (Command Register)
02
000 00010
Upper three bits define Command sent to Command register, lower 5 bits is address of highest device
in group to respond
F2
11110010
CRC
9D
10011101
CRC
7.5.3.3.3 Configuration 3: Group Write with Response to non-Command Register
NOTE
This configuration uses two bytes for addressing and response size.
The sample command frame in this example will read the data currently stored in the Command Channel Select
(address 3–6) register. Interpretation of the data bytes is in the left-hand column of the following table. The
DATA_SIZE field in the Frame Initialization byte indicates the number of data bytes in the command frame.
7
Command Frame Init
1
6
5
4
3
010 (binary)
0
Group ID
01
Register Address
03
Data (Address of Highest Device in Group to
Respond)
02
Data (Expected Number of Response Data
Bytes – 1)
03
CRC (MSB)
49
CRC (LSB)
44
58
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1
0
010 (binary)
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For details on how to interpret the response, refer to Register Details. A simplified overview of the meaning of the
data bytes in this example is in the following table.
BYTE (HEX)
BYTE (BINARY)
DESCRIPTION
A2
1 010 0 001
Command frame, Group Write with Response = REQ_TYPE, 8-bit Register Addressing, 2
data bytes = DATA_SIZE
01
00000001
Target is Group ID = 01
03
00000011
Target Register = 03 (Command Channel Select Register)
02
00000010
Address of highest device in target group
03
00000011
Number of Data Bytes – 1 expected in response (4 bytes in this example)
49
01001001
CRC
44
01000100
CRC
The command frame in this example will generate a response frame from each of the two devices targeted by
the command frame. Each response frame will contain data stored in the Command Channel Select register of
the responding bq76PL455A. The response frame from the bq76PL455A at the highest address in the addressed
group will arrive first. If the stored data were FFFF8000 (hex) for the device at Device Address 02 in Group 01
and the data were FFFF0100 (hex) for the device at Device Address 01 in Group ID 01, then the response
frames would be as in the following table.
7
Response Frame Init
6
5
4
0
3
FF
Data
FF
Data
80
Data
00
CRC (MSB)
25
CRC (LSB)
E4
Response Frame Init
1
0
2
1
0
0000011 (binary)
Data
7
2
6
5
0
4
3
0000011 (binary)
Data
FF
Data
FF
Data
01
Data
00
CRC (MSB)
45
CRC (LSB)
B4
The second of the two response frames will arrive immediately after the first response frame, so the response
will typically appear to be one continuous response. Therefore, it is important to remember that each responding
device will respond with a complete response frame with its own Frame Initialization byte, data bytes, and CRC
bytes.
7.5.3.3.4 Configuration 4: Group Write with Response to Non-Command Register
NOTE
This configuration uses one byte for addressing and response size.
As in the example for Configuration 3, the sample command frame in this example will read the value currently
stored in the Command Channel Select (address 3–6) register, but the message to do so is one byte shorter.
The expected response frames would be the same as in the example for Configuration 3.
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6
1
5
4
3
010 (binary)
2
0
Group ID
01
Register Address
03
Data (Address of Highest Device in Group to
Respond)
62
CRC (MSB)
F3
CRC (LSB)
25
1
0
001 (binary)
For details on how to interpret the data, refer to Register Details. A simplified overview of the meaning of the
data bytes in this example is in the following table.
BYTE (HEX)
BYTE (BINARY)
DESCRIPTION
Command frame, Group Write with Response = REQ_TYPE, 8-bit Register Addressing, 1
data byte = DATA_SIZE
A1
1 010 0 001
01
00000001
Target is Group ID = 01
03
00000011
Target Register = 03 (Command Channel Select Register)
62
011 00010
Upper three bits are Number of Data Bytes – 1 expected in response, lower 5 bits is
address of highest device in group to respond
F3
11110011
CRC (MSB)
25
00100101
CRC (LSB)
NOTE
Although not recommended, each of the configurations can also use 16-bit register
addressing, which would add another byte for the MSB of the register address to the
command frame.
7.5.3.4 Group Write without Response Command Frame
A Group Write without Response command is indicated when FRM_TYPE = 1 and REQ_TYPE = 3 (011 binary).
In this example, the register address size is 8-bits (ADDR_SIZE = 0) and the data length written is 1 byte
(DATA_SIZE). No Response Frame is expected to be returned.
In response to this example command frame, each bq76PL455A in the target group will write the value in the
data byte to the target register (the Averaging Register in this example). For more information on the effect of this
example command frame, see Register Details.
7
Command Frame Init
1
6
5
4
3
011 (binary)
Group ID
0
2
1
0
001 (binary)
01
Register Address
07
Data
7B
CRC (MSB)
34
CRC (LSB)
EF
7.5.3.5 Broadcast Write with Response Command Frame
As with the Single Write and Group Write with Response command frames, the interpretation of the Broadcast
Write with Response command frame bytes will be different when the target register is the Command Register
(address 2) compared to when the target is another register. Determination of response frame lengths when the
command frame targets the Command Register will be by the content of the Channel Select Register of each
targeted bq76PL455A device.
Broadcast Write command frames do not contain a Device Address/Group ID byte. This is the primary deviation
from the examples already provided in the Group Write with Response section.
60
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With the exception described previously, formation of the Broadcast Write with Response command frames can
be in a similar fashion to the various configuration examples in the Group Write with Response,
Group_Write_With_Response Command Frame.
As with the Group Write with Response commands frames, Broadcast Write with Response command frames
can utilize one of two formats to indicate the address of the highest device to respond and the number of bytes
expected in response from each targeted device. One format uses one byte to specify both the address of the
highest board in the response chain and the number of desired response bytes. The other format uses two bytes
to specify the address of the highest responding device and the desired number of response bytes separately
(first the address, then the number of bytes-1).
The two command frames that follow provide an example of each format.
An example of the two-byte method (to read the Communication Configuration register):
7
Command Frame Init
6
1
5
4
3
110 (binary)
2
0
Register Address
10
Data (Address of highest responder)
03
Data (Number of response data bytes – 1)
01
CRC (MSB)
F6
CRC (LSB)
8D
1
0
010 (binary)
For further details on how to interpret the data, refer to Register Details. A simplified overview of the meaning of
the data bytes in this example is in the following table.
BYTE (HEX)
BYTE (BINARY)
DESCRIPTION
E2
11100010
Command frame, Broadcast Write with Response = REQ_TYPE, 8-bit Register
Addressing, 2 data bytes = DATA_SIZE
10
00010000
Target Register Address (Communication Configuration Register)
03
00000011
Address of highest (first) device to respond
01
00000001
Number of data bytes –1 expected in response (that is, 2 bytes)
F6
11110110
CRC (MSB)
8D
10001101
CRC (LSB)
An example of the one-byte method (to read the Communication Configuration register):
7
Command Frame Init
1
6
5
4
3
110 (binary)
2
0
Register Address
10
Data (Data Size and Address of highest
responder)
22
CRC (MSB)
DC
CRC (LSB)
1F
1
0
001 (binary)
For further details on how to interpret the data, refer to Register Details. A simplified overview of the meaning of
the data bytes in this example is in the following table.
BYTE (HEX)
BYTE (BINARY)
DESCRIPTION
11100001
Command frame, Broadcast Write with Response = REQ_TYPE, 8-bit Register
Addressing, 1 data byte = DATA_SIZE
10
00010000
Target Register Address (Communication Configuration Register)
22
001 00010
Upper three bits are Number of Data Bytes – 1 expected in response, lower 5 bits is
address of highest device to respond
DD
11011101
CRC
EF
11101111
CRC
E1
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7.5.3.6 Broadcast Write without Response Command Frame
A Broadcast Write without Response command is indicated when FRM_TYPE = 1 and REQ_TYPE = 7 (111
binary).
In this example, the register address size is 8-bits (ADDR_SIZE = 0) and the data length written is 1 byte
(DATA_SIZE). Note that since this command is for all devices, there is no Device Address/Group ID byte in the
command frame.
No Response Frame is expected to be returned.
7
Command Frame Init
6
1
5
4
3
111 (binary)
2
0
Register Address
C8
Data
12
CRC (MSB)
86
CRC (LSB)
3E
1
0
001 (binary)
This example writes 12 (hex) into one of the Scratchpad Register bytes at address 200 (C8 hex) on all targeted
devices. See Register Details for further information on the effects of changing register values.
7.5.4 Response Frame
A Response Frame is indicated when FRM_TYPE = 0. Note that bits 6 through 0 in the Frame Initialization byte
use a different format from the Command Frame format, as described in Frame Initialization Byte.
In this example, the response data length is 3 bytes (RESP_BYTES – 1 = 2). There is support for data lengths
from 1 through 128 bytes. Since the protocol described here is for a single initiator (microcontroller) system, the
initiator is always the intended target of a Response Frame.
If a command frame targets more than one device, responses go back to the initiator first from the device at the
highest address in the targeted group, then the next highest address, and so forth until all devices in the targeted
group have responded. Each device will respond with a complete response frame, which includes a Frame
Initialization byte, one or more data bytes, and two CRC bytes.
If the command frame targets more than one device and the target register of that command frame is the
Command Register, then there may be a delay in the responses. This delay is due to the time required for the
targeted bq76PL455A devices to sample, store, and respond with their newly sampled data. The delay in the
responses will be dependent on the sampling period and channel selection configuration of each targeted device.
7
Response Frame Init
6
5
0
(binary)
4
3
2
1
0
0000010 (binary)
Data
9B
Data
8C
Data
7D
CRC (MSB)
D4
CRC (LSB)
B6
7.6 Register Maps
7.6.1 Conventions and Notations
The following conventions are in use throughout the document.
• Keywords that refer to specific software registers are in ALL CAPITALS.
• Each byte in a multi-byte register can be addressed individually. The format is big endian with the mostsignificant byte stored in the lowest physical address. Data are returned in lowest-to-highest address order.
• Locations marked "RESERVED" should not be written to, and always return 0.
• Bits marked "RESERVED" or "reserved" should be written as 0, unless otherwise specified.
62
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Register Maps (continued)
NOTE
Failure to comply with the preceding two statements may result in unexpected device
behavior.
7.6.1.1 Register Usage
All registers, except the Command Register (CMD), operate in the same manner. For all registers except CMD,
reading will return the value stored in the addressed register, and writing will store a new value into the
addressed register.
The Command Register (CMD) is a special register that accepts commands. A value written to CMD causes the
bq76PL455A to carry out a specific action and this may include the generation of a response from the
bq76PL455A. For example, a Synchronous Sample command written to CMD causes a response that contains
the conversion values for any selected channels.
NOTE
New commands should not be written until the current command is complete and any
requested response has been received in its entirety, or a timeout has occurred.
All unused bits in the registers should always be written as 0, unless otherwise noted.
The register space is byte-addressable. Reads or writes can cover any number of bytes. Multi-byte registers (16bit or 32-bit, and so forth) can read them as individual bytes, one at a time, or as a single register. The mostsignificant byte of multi-byte registers is stored at the lower address.
User firmware should not write to register addresses shown as "RESERVED" and addresses not shown in
Register Summary. Reserved Register Addresses will return zero if read, unless otherwise noted.
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Register Maps (continued)
7.6.2 Register Summary
KEY: ADDR = Address; R = Read; W = Write; R/W = Read/Write;EE = EEPROM: NA = value is volatile storage
only and not included in the EEPROM; '-' indicates the location is reserved for future use; (hex value) indicates
the default value programmed into the EEPROM location, that will be copied to the associated volatile register
upon successful reset initialization; CSUM = Checksum: Y = value included in checksum calculation; N = value
not included in calculation.
Table 7. Register Summary
ADDR
DECIMAL
BITS
NAME
00–01
0–1
16
SREV
Silicon Revision
02
2
8
CMD
Command
03–06
3–6
DESCRIPTION
32
CHANNELS
Command channel select
R/W
CSUM(3)
N/A
R
N
N/A
W
N
0000
0000
FFFF
0000
R/W
Y
RAM(1)
EE(2)
0806
00
07
7
8
OVERSMPL
Command averaging (oversampling)
00
7B
R/W
Y
08–09
8–9
16
RESERVED
Reserved for future use
00
—
R/W
N
0A
10
8
ADDR
Device address
00
00
R/W
Y
0B
11
8
GROUP_ID
(Device) Group Identifier
00
00
R/W
Y
0C
12
8
DEV_CTRL
Device control
20
N/A
R/W
N
0D
13
8
NCHAN
Number of channels enabled for conversion
00
10
R/W
Y
0E
14
8
DEVCONFIG
Device configuration
00
10
R/W
Y
0F
15
8
PWRCONFIG
Power configuration
10–11
16–17
16
COMCONFIG
Communications configuration
12
18
8
TXHOLDOFF
13
19
8
CBCONFIG
14–15
20–21
16
CBENBL
16–1D
22–29
64
1E–1F
30–31
20–21
32–33
22–24
34–36
25
37
26–27
38–39
00
80
R/W
Y
1000
1080
R/W
Y
UART Transmitter holdoff
00
00
R/W
Y
Cell balancing (equalization) configuration
00
00
R/W
Y
Cell balancing enables
0000
N/A
R/W
Y
RESERVED
Reserved for future use
00
—
R/W
N
16
TSTCONFIG
Built-In Self-Test (BIST) configuration
0000
N/A
R/W
Y
16
TESTCTRL
BIST control
0000
N/A
R/W
N
24
TEST_ADC
ADC BIST control
0000
N/A
R/W
Y
8
TESTAUXPU
Test control—AUX pull-up resistors
00
N/A
R/W
Y
16
RESERVED
Reserved for future use
00
—
R/W
N
28
40
8
CTO
29–2B
41–43
24
CTO_CNT
00
DC
R/W
Y
Communications time-out counter
0000
N/A
R/W
N
2C–31
44–49
40
RESERVED
32
50
8
Reserved for future use
0000
—
R/W
N
00
0
R/W
33–36
51–54
Y
32
0000
0000
R/W
37
Y
55
8
00
00
R/W
Y
38–3C
56–60
40
RESERVED
Reserved for future use
0000
—
R/W
N
3D
61
8
SMPL_DLY1
Initial sampling delay
00
0
R/W
Y
3E
62
8
CELL_SPER
Cell and die temperature measurement period
00
BC
R/W
Y
3F–42
63–66
32
AUX_SPER
AUX channels sampling period
0000
0000
4444
4444
R/W
Y
Communications time-out
0000
F999
R/W
Y
00
—
R/W
N
00
N/A
R
N
81(4)
N/A
R/W
N
0100
(4)
N/A
R/W
N
(4)
43–44
67–68
16
TEST_SPER
ADC test sampling period
45–4F
69–79
88
RESERVED
Reserved for future use
50
80
8
SHDN_STS
Shutdown recovery status
51
81
8
STATUS
52–53
82–83
16
FAULT_SUM
Device status
Fault summary
54–55
84–85
16
FAULT_UV
Undervoltage faults
0000
N/A
R/W
N
56–57
86–87
16
FAULT_OV
Overvoltage faults
0000(4)
N/A
R/W
N
58–59
88–89
16
FAULT_AUX
AUX threshold exceeded faults
0000(4)
N/A
R/W
N
(4)
N/A
R/W
N
5A–5B
64
DEFAULT (HEX)
ADDR
HEX
90–91
16
FAULT_2UV
Comparator UV faults
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Register Maps (continued)
Table 7. Register Summary (continued)
DEFAULT (HEX)
ADDR
HEX
ADDR
DECIMAL
BITS
5C–5D
92–93
16
FAULT_2OV
5E–5F
94–95
16
FAULT_COM
NAME
DESCRIPTION
R/W
CSUM(3)
N/A
R/W
N
N/A
R/W
N
RAM(1)
EE(2)
Comparator OV faults
0000(4)
Communication faults
(4)
60
96
8
FAULT_SYS
System fault
61–62
97–98
16
FAULT_DEV
Device fault
63
99
8
FAULT_GPI
General purpose input (GPIO) fault
64–67
100–103
32
RESERVED
Reserved for future use
68–69
104–105
16
MASK_COMM
6A
106
8
MASK_SYS
System FAULT mask register
6B–6C
107–108
16
MASK_DEV
Chip FAULT mask register
6D
109
8
RESERVED
Reserved for future use
6E–6F
110–111
16
FO_CTRL
70–77
112–119
64
RESERVED
78
120
8
79
121
8
7A
122
8
7B
123
7C
124
Communications FAULT mask register
FAULT output control
0000
(4)
N/A
R/W
N
0000(4)
N/A
R/W
N
00(4)
N/A
R/W
N
80
00
—
R/W
N
0000
0000
R/W
Y
0
00
R/W
Y
0000
0000
R/W
Y
0
—
R/W
N
0000
FFC0
R/W
Y
Reserved for future use
0
—
R/W
N
GPIO_DIR
GPIO direction control
00
00
R/W
Y
GPIO_OUT
GPIO output control
00
00
R/W
Y
GPIO_PU
GPIO pull-up resistor control
00
00
R/W
Y
8
GPIO_PD
GPIO pull-down resistor control
00
00
R/W
Y
8
GPIO_IN
GPIO input value
00
N/A
R
N
7D
125
8
GP_FLT_IN
GPIO input 0/1 FAULT assertion state
00
00
R/W
Y
7.00E–81
126–129
32
RESERVED
Reserved for future use
00
—
R/W
N
82–85
130–133
32
MAGIC1
0000
0000
N/A
W
N
86–8B
134–139
48
RESERVED
Reserved for future use
00
—
R/W
N
8C
140
8
COMP_UV
Comparator undervoltage threshold
00
00
R/W
Y
8D
141
8
COMP_OV
Comparator overvoltage threshold
00
FE
R/W
Y
8E–8F
142–143
16
CELL_UV
Cell undervoltage threshold
0000
0000
R/W
Y
90–91
144–145
16
CELL_OV
Cell overvoltage threshold
0000
FFFC
R/W
Y
92–93
146–147
16
AUX0_UV
AUX0 undervoltage threshold
0000
0000
R/W
Y
94–95
148–149
16
AUX0_OV
AUX0 overvoltage threshold
0000
FFFC
R/W
Y
96–97
150–151
16
AUX1_UV
AUX1 undervoltage threshold
0000
0000
R/W
Y
98–99
152–153
16
AUX1_OV
AUX1 overvoltage threshold
0000
FFFC
R/W
Y
9A–9B
154–155
16
AUX2_UV
AUX2 undervoltage threshold
0000
0000
R/W
Y
9C–9D
156–157
16
AUX2_OV
AUX2 overvoltage threshold
0000
FFFC
R/W
Y
9E–9F
158–159
16
AUX3_UV
AUX3 undervoltage threshold
0000
0000
R/W
Y
A0–A1
160–161
16
AUX3_OV
AUX3 overvoltage threshold
0000
FFFC
R/W
Y
A2–A3
162–163
16
AUX4_UV
AUX4 undervoltage threshold
0000
0000
R/W
Y
A4–A5
164–165
16
AUX4_OV
AUX4 overvoltage threshold
0000
FFFC
R/W
Y
A6–A7
166–167
16
AUX5_UV
AUX5 undervoltage threshold
0000
0000
R/W
Y
A8–A9
168–169
16
AUX5_OV
AUX5 overvoltage threshold
0000
FFFC
R/W
Y
AA–AB
170–171
16
AUX6_UV
AUX6 undervoltage threshold
0000
00000
R/W
Y
AC–AD
172–173
16
AUX6_OV
AUX6 overvoltage threshold
0000
FFFC
R/W
Y
AE–AF
174–175
16
AUX7_UV
AUX7 undervoltage threshold
0000
00000
R/W
Y
AUX7 overvoltage threshold
0000
FFFC
R/W
Y
Reserved for future use
0000
—
R/W
N
"Magic" value enables EEPROM write
B0–B1
176–177
16
AUX7_OV
B2–BD
178–189
96
RESERVED
BE–C5
190–197
64
LOT_NUM
Device Lot Number
00…
Factory(5)
R
N
C6–C7
198–199
16
SER_NUM
Device Serial Number
00…
Factory(5)
R
N
C8–CF
200–207
64
SCRATCH
User-defined data
00…
00…
R/W
Y
D0-D1
208–209
16
RESERVED
Reserved for future use
00
—
R/W
N
D2
210
8
VSOFFSET
ADC voltage offset correction
00
00
R/W
Y
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Register Maps (continued)
Table 7. Register Summary (continued)
ADDR
HEX
ADDR
DECIMAL
DEFAULT (HEX)
BITS
NAME
DESCRIPTION
RAM(1)
EE(2)
R/W
CSUM(3)
D3
211
8
VSGAIN
ADC voltage gain correction
00
00
R/W
Y
D4-D5
212–213
16
AX0OFFSET
AUX0 ADC offset correction
0000
0000
R/W
Y
D6-D7
214–215
16
AX1OFFSET
AUX1 ADC offset correction
0000
0000
R/W
Y
D8-D9
216–217
16
AX2OFFSET
AUX2 ADC offset correction
0000
0000
R/W
Y
DA-DB
218–219
16
AX3OFFSET
AUX3 ADC offset correction
0000
0000
R/W
Y
DC-DD
220–221
16
AX4OFFSET
AUX4 ADC offset correction
0000
0000
R/W
Y
DE-DF
222–223
16
AX5OFFSET
AUX5 ADC offset correction
0000
0000
R/W
Y
E0–E1
224–225
16
AX6OFFSET
AUX6 ADC offset correction
0000
0000
R/W
Y
E2–E3
226–227
16
AX7OFFSET
AUX7 ADC offset correction
0000
0000
R/W
Y
E4–E5
228–229
16
RESERVED
Reserved for future use
00
—
R/W
N
E6–ED
230–237
64
TSTR_ECC
ECC Test Results
00…
N/A
R
N
EE–EF
238–239
16
RESERVED
Reserved for future use
0
—
R/W
N
Saved checksum value
1234
5678
C9B0
12F7
R/W
N
Checksum Readout
C9B0
12F7
N/A
R
N
Checksum Test Result
F0–F3
240–243
32
CSUM
F4–F7
244–247
32
CSUM_RSLT(6)
F8–F9
248–249
16
TEST_CSUM
FA
250
8
EE_BURN
FB
251
8
RESERVED
FC–FF
252–255
32
MAGIC2
0000
N/A
R
N
EEPROM Burn Count; up-counter
FA
Y
R
N
Reserved for future use
00
—
R/W
N
0000
0000
N/A
W
N
"Magic" value enables EEPROM write
(1) Initial value loaded at device RESET or POR.
(2) Value stored in EEPROM from factory may be overwritten by the user. This value is loaded after initial RESET or POR value (see note
(1)
) only if the ECC is valid or correctable for the block.
(3) CSUM: This register is included ('Y') or not included ('N") in the USER checksum calculation.
(4) Value shown after wakeup and only the FAULT_SYS[SYS_RESET] fault conditions exist.
(5) Factory programmed values will vary from device to device.
(6) This register value is set indirectly by the contents of all register values included in the checksum. The value updates after any register
change for registers included in the checksum.
Table 8. Registers in Alphabetical Order
NAME
ADDR
ADDR HEX
ADDR DECIMAL
0A
10
AUX channels sampling period
3F–42
63–66
AUX0_OV
AUX0 overvoltage threshold
94–95
148–149
AUX0_UV
AUX0 undervoltage threshold
92–93
146–147
AUX1_OV
AUX1 overvoltage threshold
98–99
152–153
AUX_SPER
66
DESCRIPTION
Device address
AUX1_UV
AUX1 undervoltage threshold
96–97
150–151
AUX2_OV
AUX2 overvoltage threshold
9C–9D
156–157
AUX2_UV
AUX2 undervoltage threshold
9A–9B
154–155
AUX3_OV
AUX3 overvoltage threshold
A0–A1
160–161
AUX3_UV
AUX3 undervoltage threshold
9E–9F
158–159
AUX4_OV
AUX4 overvoltage threshold
A4–A5
164–165
AUX4_UV
AUX4 undervoltage threshold
A2–A3
162–163
AUX5_OV
AUX5 overvoltage threshold
A8–A9
168–169
AUX5_UV
AUX5 undervoltage threshold
A6–A7
166–167
AUX6_OV
AUX6 overvoltage threshold
AC–AD
172–173
AUX6_UV
AUX6 undervoltage threshold
AA–AB
170–171
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Table 8. Registers in Alphabetical Order (continued)
ADDR HEX
ADDR DECIMAL
AUX7_OV
NAME
AUX7 overvoltage threshold
DESCRIPTION
B0–B1
176–177
AUX7_UV
AUX7 undervoltage threshold
AE–AF
174–175
AX0OFFSET
AUX0 ADC offset correction
D4–D5
212–213
AX1OFFSET
AUX1 ADC offset correction
D6–D7
214–215
AX2OFFSET
AUX2 ADC offset correction
D8–D9
216–217
AX3OFFSET
AUX3 ADC offset correction
DA–DB
218–219
AX4OFFSET
AUX4 ADC offset correction
DC–DD
220–221
AX5OFFSET
AUX5 ADC offset correction
DE–DF
222–223
AX6OFFSET
AUX6 ADC offset correction
E0-E1
224–225
AX7OFFSET
AUX7 ADC offset correction
E2-E3
226–227
CBCONFIG
Cell balancing (equalization) configuration
13
19
CBENBL
Cell balancing enables
14–15
20–21
CELL_OV
Cell overvoltage threshold
90–91
144–145
3E
62
Cell undervoltage threshold
8E–8F
142–143
Command channel select
03–06
3-6
02
2
CELL_SPER
CELL_UV
CHANNELS
CMD
COMCONFIG
Cell and die temperature measurement period
Command
10–11
16–17
COMP_OV
Comparator overvoltage threshold
8D
141
COMP_UV
Comparator undervoltage threshold
8C
140
Saved checksum value
F0–F3
240–243
Checksum Readout
F4–F7
244–247
CSUM
CSUM_RSLT
CTO
Communications configuration
Communications time-out
28
40
29–2B
41–43
12
CTO_CNT
Communications time-out counter
DEV_CTRL
Device control
0C
Device configuration
0E
14
EEPROM Burn Count; up-counter
FA
250
DEVCONFIG
EE_BURN
FAULT_AUX
AUX threshold exceeded faults
58–59
88–89
FAULT_COM
Communication faults
5E–5F
94–95
FAULT_2OV
Comparator OV faults
5C–5D
92–93
FAULT_2UV
Comparator UV faults
5A–5B
90–91
FAULT_DEV
Device fault
61–62
97–98
FAULT_GPI
General purpose input (GPIO) fault
FAULT_OV
63
99
Overvoltage faults
56–57
86–87
FAULT_SUM
Fault summary
52–53
82–83
FAULT_SYS
System fault
FAULT_UV
FO_CTRL
60
96
Undervoltage faults
54–55
84–85
FAULT output control
6E–6F
110–111
GP_FLT_IN
GPIO input 0/1 FAULT assertion state
7D
125
GPIO_DIR
GPIO direction control
78
120
GPIO input value
7C
124
GPIO_IN
GPIO_OUT
GPIO output control
79
121
GPIO_PD
GPIO pull-down resistor control
7B
123
GPIO_PU
GPIO pull-up resistor control
7A
122
GROUP_ID
(Device) Group Identifier
0B
11
LOT_NUM
Die Lot Identifier
BE–C5
190–197
"Magic" value enables EEPROM write
82–85
130–133
MAGIC1
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Table 8. Registers in Alphabetical Order (continued)
NAME
"Magic" value enables EEPROM write
MASK_COMM
ADDR HEX
ADDR DECIMAL
FC–FF
252–255
Communications FAULT mask register
68–69
104–105
MASK_DEV
Chip FAULT mask register
6B–6C
107–108
MASK_SYS
System FAULT mask register
6A
106
Number of channels enabled for conversion
0D
13
Command averaging (oversampling)
07
7
Power configuration
0F
15
NCHAN
OVERSMPL
PWRCONFIG
RESERVED
Reserved for future use
08-09
9-Aug
RESERVED
Reserved for future use
16–1D
22–29
RESERVED
Reserved for future use
26–27
38–39
RESERVED
Reserved for future use
2C–31
44–49
RESERVED
Reserved for future use
32
50
RESERVED
Reserved for future use
33–36
51–54
RESERVED
Reserved for future use
37
55
RESERVED
Reserved for future use
38–3C
56–60
RESERVED
Reserved for future use
45–4F
69–79
RESERVED
Reserved for future use
64–67
100–103
RESERVED
Reserved for future use
6D
109
RESERVED
Reserved for future use
70–77
112–119
RESERVED
Reserved for future use
7.00E–81
126–129
RESERVED
Reserved for future use
86–8B
134–139
RESERVED
Reserved for future use
B2–BD
178–189
RESERVED
Reserved for future use
D0–D1
208–209
RESERVED
Reserved for future use
E4-E5
228–229
RESERVED
Reserved for future use
EE-EF
238–239
RESERVED
Reserved for future use
FB
251
SCRATCH
User-defined data
C8–CF
200–207
SER_NUM
Device serial number
C6–C7
198–199
SHDN_STS
Shutdown recovery status
50
80
SMPL_DLY1
Initial sampling delay
3D
61
00–01
0–1
SREV
STATUS
Silicon Revision
51
81
ADC BIST control
22–24
34–36
TEST_CSUM
Checksum Test Result
F8–F9
248–249
TEST_SPER
ADC test sampling period
43–44
67–68
TESTAUXPU
Test control—AUX pull-up resistors
TEST_ADC
Device status
25
37
32–33
TESTCTRL
BIST control
20–21
TSTCONFIG
Built-In Self-Test (BIST) configuration
1E–1F
30–31
TSTR_ECC
ECC Test Results
E6-ED
230–237
TXHOLDOFF
68
DESCRIPTION
MAGIC2
UART Transmitter holdoff
12
18
VSGAIN
ADC voltage gain correction
D3
211
VSOFFSET
ADC voltage offset correction
D2
210
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7.6.3 Register Details
NOTE
The terms "Write without Response", "Write", and "write" are equivalent and synonymous.
The words "Read" and "read" are equivalent to "Write with Response".
7.6.3.1 SREV 0x00-01 (0-1) Device Version
This register provides the digital and analog die revisions used in the bq76PL455A device.
BIT
NAME
DESCRIPTION
[15:8]
DDIE_VER
Digital die version number (byte address 0)
[7:0]
ADIE_VER
Analog die version number (byte address 1)
7.6.3.2 CMD 0x02 (2) Command
Write_With_Response requests directly targeted to this register cause the specified command to execute and the
corresponding results to return a response. The number of bytes returned will be based on the bits selected in
the CHANNELS register. Some bits in the CHANNELS register have more than one value returned, refer to their
descriptions under the CHANNELS register.
NOTE
This transaction will return results from the command, not a read of register values.
It is not possible to read the last value written to this register. Indirect reads of this register produce an undefined
value for this register.
A command sent to this register without writing the CHANNELS or OVERSMPL registers in the same frame uses
the values currently in those registers. If a command writes the CHANNELS or OVERSMPL registers in the same
frame then sends the command to the register, the new register values will overwrite the current register values
and the execution of the command uses the new values.
Requested values return MSB first in the order that they exist in the CHANNELS register, starting with the MSB
(Cell 16, Cell 15 …). No values return for bits not selected in the CHANNELS register.
BIT
NAME
DESCRIPTION
[7:6]
Reserved
Write these bits as 0.
[4:0]
resp_addr
If set by a Broadcast_Write_With_Response or Group_Write_With_Response request, devices will respond
in successive order. These bits set the address of the highest device in the group/set to respond. This
value has no effect for other transaction types.
7.6.3.3 CHANNELS 0x03–06 (3–6) Channel Select
When the indicated bit is set, the named channel is included when a CMD (COMMAND) is executed in the
Command register.
BIT
NAME
DESCRIPTION
This bitmask determines which battery cell voltages are used when a COMMAND is executed.
CMD_VSEL[0] (bit 16) corresponds to cell 1, bit 31 corresponds to cell 16.
[31:16]
CMD_VSEL
For each bit in this field:
0 = Do not include this cell voltage.
1 = Include this cell voltage.
This bitmask determines which auxiliary channels are used when a COMMAND is executed.
CMD_ASEL[0] (bit 8) corresponds to AUX0.
[15:8]
[7]
CMD_ASEL
For each bit in this field:
0 = Do not include this AUX channel.
1 = include this AUX channel.
CMD_GTSEL
Digital die temperature. Usually used as part of self-testing.
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BIT
NAME
[6]
CMD_HTSEL
Analog die temperature. Usually used as part of self-testing.
DESCRIPTION
[5]
CMD_V18SEL
VDD18 internal digital supply. Usually used as part of self-testing.
[4]
RSVD
Reserved — Always write a 0.
[3]
RSVD
Reserved — Always write a 0.
[2]
CMD_REFSEL
4.5-V analog die reference (window comparator ref) is included when a COMMAND is executed. This bit
selects both the 4.5-V reference and the ground output from the reference MUX. Sampling and reporting
will be 4.5 V and then ground. This command is generally used for self-testing purposes.
[1]
CMD_MODULESEL
Sum-of-cells (VMODULE) monitor is included when a COMMAND is executed. Two conversions are
performed to get this value, but only the average of the two is stored and reported.
TSTCONFIG[MODULE_MON_EN] is used to enable the MODULE measurement. When
TSTCONFIG[MODULE_MON_EN] = 0, but CMD_MODULESEL = 1, then ground will be measured. This
selection is generally used for self-testing purposes.
[0]
CMD_VMMONSEL
VM (negative supply charge pump) voltage monitor. TST_CONFIG[VM_MON_EN] is used to enable the
measurement. This selection is generally used for self-testing purposes.
7.6.3.4 OVERSMPL 0x07 (7) Command Oversampling
BIT
NAME
DESCRIPTION
This bit only applies to voltage and AUX averaging (oversampling).
[7]
[6:5]
=0
Average channels by sampling multiple times on the same channel
before changing channel. The initial sample period for the first sample
on each channel is made per the respective ADC_PERIOD_VOL and
ADC_PERIOD_AUXx time period settings, and then each subsequent
average occurs at the respective CMD_OVS_HPER and
CMD_OVS_GPER period settings.
=1
Average channels by cycling through all channels one sample per
channel before resampling. All voltage averages are completed before
any AUX sampling begins and then all AUX are completed before
anything else. The settling time before voltage sampling is set by
ADC_PERIOD_VOL and the settling time before AUX sampling is set
by ADC_PERIOD_AUXx.
=3
CMD_OVS_HPER sets the averaging period for the:
CMD_OVS_CYCLE
•
•
•
•
CMD_OVS_HPER
Internal temperature measurement of the analog die
4.5-V voltage reference of the analog die
VM monitor
Sum-of-cells (VMODULE) monitor
When CMD_OVS_CYCLE = 0, this value also sets the period for the averaging on all
the cell voltage channels.
These bits must be set to 3 (0b11), which selects 12.6 µs as the average period. Other
settings are Reserved and should not be used.
CMD_OVS_GPER sets the averaging period for:
•
•
[4:3]
CMD_OVS_GPER
When CMD_OVS_CYCLE = 0, this value also sets the period for the averaging on all
the auxiliary channels.
=0
=1
=2
=3
70
Internal temperature measurement of the digital die. Note that
although CMD_OVS_GPER bits set the timing for the internal
temperature measurement of the digital die, averaging is not used
for this measurement.
VDD18
4.13 µs
5.96 µs
8.02 µs
12.6 µs: This setting is recommended for best accuracy in most
designs. See the Application and Implementation section for detailed
information on using other settings.
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BIT
NAME
DESCRIPTION
These bits set the number of times each ADC converted value will be averaged before
being stored. Each converted signal will be sampled the requested number of times,
averaged, and the results convergent rounded to 16 bits.
[2:0]
=0
=1
=2
=3
=4
=5
= 6–7
CMD_OVSMP
Single sample (no averaging)
2 samples are averaged.
4 samples are averaged.
8 samples are averaged.
16 samples are averaged.
32 samples are averaged.
Reserved, do not use this value.
7.6.3.5 ADDR 0x0A (10) Device Address
BIT
NAME
DESCRIPTION
[7:5]
RSVD
Reserved — always write as zero.
[4:0]
DEV_ADDR
These bits set the device address that the device will respond. These bits can only be written when
AUTO_ADDRESS is set to 1. Otherwise, writes to these bits are ignored. The address may also be stored
and loaded from EEPROM or using GPIO bits. See text for details.
7.6.3.6 GROUP_ID 0x0B (11) Group ID
BIT
NAME
DESCRIPTION
[7:4]
RSVD
Reserved — always write as zero.
[3:0]
GROUP_ID
These bits set the lower 4 bits of the group identifier that the device will respond to for Group Broadcast
requests. The upper 4 bits of the group identifier are fixed at 0 and cannot be changed.
7.6.3.7 DEV_CTRL 0x0C (12) Device Control
BIT
NAME
DESCRIPTION
[7]
SOFT_RESET
Writing a '1' will return the device to its reset state, causing it to rerun its initialization sequence. This bit is
self-clearing and will always return '0' when read.
[6]
PWRDN
Writing a '1' will cause the device to shut down. This is usually broadcast to the entire stack of ICs to shut
down all of the bq76PL455A devices at the same time.
Writing a '1' will cause a wakeup tone to be sent from the high-side communication interface to the next
device up the stack.
[5]
STACK_WAKE
Note that setting this bit blocks communication to devices higher in the stack until the wakeup tone
sequence is complete. The time it takes to complete the stack wake sequence is dependent on the state
and number of devices in the stack.
This bit is self-clearing and will return '1' while a wakeup tone is in process, and '0' after it has completed.
Writing a '1' while MAGIC1 is set to 0x8C2DB194 and MAGIC2 is set to 0xA375E60F causes the EEPROM
to save (be programmed with) the current register values.
This bit is self-clearing and will return '1' while the programming cycle is in progress, and '0' after the
programming cycle is complete. This bit should not be written while a programming cycle is in progress.
[4]
WRITE_EEPROM
Normal EEPROM burns require COMM_PD_PER >= 3. For COMM_PD_PER settings smaller than this,
the user should have the device perform the following steps:
1. Set CCNT_RST_OFF = 1
2. Set COMM_TIM_CNT = 0x1000
3. Burn as normal
Do not write to registers while a programming cycle is in progress.
Do not shut down the device while a programming cycle is in progress.
If ADDR_SEL = 0, writing a '1' will cause the device to sample the GPIO pins and store the resulting value
in DEV_ADDR.
[3]
AUTO_ADDRESS
If ADDR_SEL = 1, writing a '1' will cause the device to enter auto addressing mode.
When ADDR_SEL = 1, this bit is self-clearing and will be set to '0' after the next frame is received, even if
that frame does not set DEV_ADDR.
When ADDR_SEL = 0 this bit is self-clearing and will always read 0.
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BIT
[2:0]
NAME
RSVD
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DESCRIPTION
Reserved — always write as zero
7.6.3.8 NCHAN 0x0D (13) Number of Channels
BIT
[7:5]
NAME
RSVD
DESCRIPTION
Reserved — always write as zero.
This register sets the number of VSENSE channels (battery inputs) that will be used by the device. Unused
channels are dropped consecutively starting from channel 16.
The idle channel (the channel the MUX "rests" on between sample intervals) is set to this value.
[4:0]
NUM_CHAN
A setting of 0 is not recommended. If 0 is set, the idle channel = VSENSE1.
This value masks cell overvoltage and undervoltage faults for unused channels and turns off the
comparators associated with the channel.
Values greater than 16 are reserved and should not be used.
7.6.3.9 DEVCONFIG 0x0E (14) Device Configuration
BIT
[7:6]
NAME
Reserved
DESCRIPTION
These bits must always be set to 0.
0 = Internal regulator (NPN drive for VP/VDIG) is enabled. This is the normal operating mode.
[5]
REG_DISABLE
1 = Internal regulator (NPN drive) is disabled. In this case, the bq76PL455A VP, VDIG, and VIO must be
externally supplied. REG_DISABLE = 1 is typically used only for some system diagnostic tests.
Regardless of the state of this bit, the regulator will always be enabled while FAULT_SYS[SYS_RESET]
= 1.
0 = Address will be set using the GPIO inputs.
[4]
ADDR_SEL
1 = Address will be set using auto addressing.
Note: Changing this bit will not change the current device address.
0 = Overvoltage (OV) and undervoltage (UV) comparators are enabled.
[3:2]
COMP_CONFIG
1 = OV comparators are enabled, UV comparators are disabled.
2 = Comparators are disabled.
3 = Reserved
[1]
COMP_HYST_EN
0 = Comparator hysteresis is disabled.
1 = Comparator hysteresis is enabled.
0 = Faults are latched and write fault register to clear.
1 = Faults are unlatched and clear automatically.
[0]
UNLATCHED_FAULT This setting only applies to some fault registers. See individual fault register descriptions for details.
The UNLATCHED_FAULT bit should only be changed while no fault bits are set (= 1). The
latched/unlatched status of fault bits is undefined when the UNLATCHED_FAULT bit is changed while a
fault bit = 1.
7.6.3.10 PWRCONFIG (0x0F) (15) Power Configuration
BIT
NAME
DESCRIPTION
It is strongly recommended this bit be set to 1.
[7]
AFE_PCTL
Cell voltage sampling will be delayed by 100 µs every time sampling is requested, regardless of whether
or not the AFE was already powered up. This provides time for the AFE to power up and ensures that
the sampling synchronization is maintained between multiple devices.
Changes to this register may not take effect until after the next AFE sample is taken.
[6:0]
RSVD
Reserved — always write as zero.
7.6.3.11 COMCONFIG 0x10–11 (16–17) Communications Configuration
BIT
[15:14]
72
NAME
RSVD
DESCRIPTION
Reserved — always write/read as zero.
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BIT
NAME
DESCRIPTION
[13:12]
BAUD
0 = 125 Kbaud
1 = 250 Kbaud
2 = 500 Kbaud
3 = 1 Mbaud
This register will be reset to 250 Kbaud by a communication reset.
[11:8]
RSVD
Reserved — always write/read as zero.
[7]
UART_EN
0 = Disable single-ended transmitter and FAULT_N outputs. When disabled, TX will drive high and
FAULT_N will drive low. Signals do not tri-state.
1 = Enable single-ended transmitter interface
[6]
COMM_HIGH_EN
0 = Disable high-side differential receiver interface
1 = Enable high-side differential receiver interface
[5]
DIFF_COMM_EN
0 = Disable differential low-side transmission interface
1 = Enable differential low-side transmission interface
[4]
FAULT_HIGH_EN
0 = Disable high-side fault differential receiver interface
1 = Enable high-side fault differential receiver interface
[3]
DIFF_FAULT_EN
0 = Disable differential fault output heartbeat
1 = Enable differential fault output heartbeat
RSVD
Reserved—Always write/read as zero.
[2:0]
7.6.3.12
TXHOLDOFF 0x12 (18) UART Transmitter Holdoff
BIT
NAME
[7:0]
TX_HOLDOFF
DESCRIPTION
This sets how many bit periods after a received stop bit the transmitter needs to wait before it starts to
transmit response data.
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7.6.3.13
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CBCONFIG 0x13 (19) Balance Configuration
BIT
NAME
DESCRIPTION
This sets the time that balancing will be enabled before it is automatically disabled. This is separate
from the communication timeout counter and is not reset by communication. The counter is reset any
time the BALANCE_EN register is written with a non-zero value.
[7:4]
0 = Until stopped (timer disabled)
1 = 1 second
2 = 1 minute
3 = 2 minutes
4 = 5 minutes
5 = 10 minutes
6 = 15 minutes
7 = 20 minutes
8 = 30 minutes
9 = 60 minutes
10–15 = Reserved
BAL_TIME
This controls how CBENBL[BALANCE_EN] bits are handled when faults occur.
[3]
[2:0]
BAL_CONTINUE
RSVD
0 = CBENBL is set to 0 when any fault bit is set, except CUST_CKSUM_ERR, which is ignored.
1 = CBENBL is not changed if a fault occurs.
Reserved — always write/read as zero.
7.6.3.14 CBENBL 0x14–15 (20–21) Balancing Enable
BIT
NAME
DESCRIPTION
When EQ_SQUEEZE_EN = 0, these bits control the channels which are balancing. When
EQ_SQUEEZE_EN = 1, these bits control the squeeze resistors used in open-wire-detection (OWD).
BALANCE_EN[0] controls pin EQ1 for balancing cell1, bit1 controls EQ2, and so forth.
For each bit:
[15:0]
BALANCE_EN
0 = Balancing (or squeeze) is disabled on this channel.
1 = Balancing (or squeeze) is enabled on this channel.
If BAL_CONTINUE = 0, all bits in this register will be set to '0' and writes will be ignored if any fault bit
(except CUST_CKSUM_ERR) is set. CUST_CKSUM_ERR is ignored.
If BAL_CONTINUE = 1, fault bits have no effect on this register.
7.6.3.15 TSTCONFIG 0x1E–1F (30–31) Test Configuration
BIT
NAME
DESCRIPTION
[15:12]
RSVD
Reserved — always write/read as zero.
[11:8]
LDO_TEST
These bits directly control the VDD18 LDO test. Set to 0 for normal operation. For additional
information, contact a representative at Texas Instruments.
When this bit is set, the communication counter does not reset when a valid communications packet is
received, allowing the communications timeout counters to be tested.
[7]
74
CCNT_RST_OFF
[6]
VDIG_TEST
[5]
RSVD
Do not change COMM_PD_PER while this bit is set:
•
If COMM_PD_PER is inadvertently set to a value less than COMM_TIM_CNT while this bit is set,
the communications timeout may be missed and not occur for up to 70 min after loss of
communications.
•
If COMM_PD_PER is inadvertently written while this bit is set, writing a new value to
COMM_TIM_CNT (new value before the timeout should occur) will avoid the issue.
This bit is used to cause the device to enter SHUTDOWN when the VDIGDDIEPOR is tripped as part of a
suite of self-test functions.
Note: Once set, subsequently clearing this bit will not disable this control even though the bit will read 0.
It will not be disabled until the device enters shutdown.
Reserved — always write as zero.
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BIT
NAME
DESCRIPTION
[4]
EQ_SQUEEZE_EN (1)
This bit is used to control the internal resistors connected across the VSENSE inputs, and changes the
behavior of the CBENBL register. In the event of a broken wire, applying the resistor should cause any
stored charge on the VSENSEn capacitor to bleed off.
This bit is normally used for system testing purposes. When using this feature,
CBCONFIG[BAL_CONTINUE] is typically set to '1'.
[3]
RSVD
Reserved — always write as zero
0 = Disable VM (–5 V charge pump) monitor so the monitor ground can be measured using
CMD_VMMONSEL.
[2]
VM_MON_EN
[1]
RSVD
1 = Enable VM monitor so it can be measured using CMD_VMMONSEL.
This bit is normally used for self-testing purposes.
Reserved — always write as zero.
0 = Disable VMODULE monitor so the monitor ground can be measured using CMD_MODULESEL.
[0]
MODULE_MON_EN
1 = Enable VMODULE monitor so it can be measured using CMD_MODULESEL.
This bit is normally used for self-testing purposes.
(1)
Please see Section Window Comparator Special Considerations for additional considerations for the use of this function.
7.6.3.16 TESTCTRL 0x20–21 (32–33) Test Control
CAUTION
Do NOT run more than one test simultaneously.
BIT
[15:10]
[7:5]
[4]
[3]
[2]
[1]
NAME
DESCRIPTION
RSVD
Reserved — always write/read as zero.
ECC_TEST
0 = Do nothing.
1 = Load USER space register correctable error to ECC_TEST_RSLT(x).
2 = Load USER space register uncorrectable error to ECC_TEST_RSLT(x).
3 = Load TI space register correctable error ECC_TEST_RSLT(x).
4 = Load TI space register uncorrectable error to ECC_TEST_RSLT(x).
5–7 = Reserved
This bit is normally used for self-testing purposes.
ADC_FCAL_TEST
This test can be used to confirm the ADC is functioning properly. Test pass or fail is reported in register
FAULT_DEV[ADC_CAL_ERR] (0x61[4]).
0 = Do nothing.
1 = Perform a full calibration test of the ADC.
This bit is self-clearing and will return '1' while the test is running and '0' when it is complete.
Note: If written to '1' when ADC_PCAL_TEST is set, the device will stop the partial calibration and start
a full calibration. The ADC_PCAL_TEST bit will be cleared.
ADC_PCAL_TEST
This test can be used to confirm the ADC is functioning properly by running an abbreviated calibration
cycle and comparing the results to those stored during TI factory testing. The original results are not
overwritten.
0 = Do nothing
1 = Perform a partial calibration test of the ADC.
This bit is self-clearing and will return '1' while the test is running and '0' when it is complete.
Note: If written to ‘1’ when ADC_FCAL_TEST is set, the device will ignore the command and the
ADC_PCAL_TEST bit will be cleared.
GTSD_TRIP
This bit directly forces the thermal shutdown of the digital die to trip. Setting this bit to 1 will cause the
device to reset:
0 = Normal operation
1 = Simulate over temperature (triggers thermal shutdown)
This bit is normally used for self-testing purposes.
HTSD_TRIP
This bit directly forces the thermal shutdown of the analog die to trip. Setting this bit to 1 will cause the
device to reset:
0 = Normal operation
1 = Simulate over temperature (triggers thermal shutdown)
This bit is normally used for self-testing purposes.
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BIT
NAME
[0]
NPN_OC_TRIP
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DESCRIPTION
0 = Normal operation, no NPN protection check is triggered
1 = Simulate NPN protection check (triggers power-down)
Setting this bit will cause the device to reset.
This bit is normally used for self-testing purposes.
7.6.3.17 TEST_ADC 0x22–24 (34–36) ADC Output Test
BIT
NAME
[23]
ADC_OUTTST_EN
DESCRIPTION
When this bit is set, the ADC conversion will be run, but the ADC_TEST_OUT value will be substituted
for the ADC output value.
This test is normally used for self-testing purposes.
[22:20]
RSVD
Reserved — always write as zero.
[19:14]
RSVD
Reserved — always read/write as zero.
ADC_TEST_OUT
These 14 bits in two's complement format set the false ADC output value that will be used when
enabled. The default value of 0x0000 represents middle range (nominally 2.5000 V). The maximum
positive value (nominally 4.9997 V) is 0x1FFF and the maximum negative value is 0x2000 (nominally
0.0000 V). It should be noted that channel trim values will still be applied to the value programmed here.
[13:0]
7.6.3.18 TESTAUXPU 0x25 (37) AUX Pull-up Test Control
BIT
[7:0]
NAME
AUX_PULLUP_EN
DESCRIPTION
These bits enable pull-ups on the AUX inputs for self-test or system configuration purposes. Bit zero
corresponds to AUX0. Setting a bit (1) enables the resistor. Clearing the bit (0) disables the resistor.
7.6.3.19 CTO 0x28 (40) Communication Timeout
BIT
NAME
DESCRIPTION
This register sets the period at which the system will automatically power-down if no valid
communication frames have been received.
[7:4]
COMM_PD_PER
0 = Communication power-down disabled
1 = 0.1 second
2 = 0.5 second
3 = 1 second
4 = 2 seconds
5 = 5 seconds
6 = 10 seconds
7 = 30 seconds
8 = 1 minute
9 = 2 minutes
10 = 5 minutes
11 = 10 minutes
12 = 30 minutes
13 = 1 hour
14–15 = Reserved
Note: This setting should be greater than the COMM_TMOUTPER setting (below), if it is necessary to
trigger a fault, and code has the time to address it before the device enters SHUTDOWN.
76
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BIT
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NAME
DESCRIPTION
This register sets the period after which the system will set the FAULT_SYS[COMM_TIMEOUT] fault if
no valid communication frames have been received.
[3:0]
COMM_TMOUTPER
0 = Communication timeout fault disabled
1 = 0.1 second
2 = 0.5 second
3 = 1 second
4 = 2 seconds
5 = 5 seconds
6 = 10 seconds
7 = 30 seconds
8 = 1 minutes
9 = 2 minutes
10 = 5 minutes
11 = 10 minutes
12 = 30 minutes
13 = 1 hour
14–15 = Reserved
Note: This setting should be less than the COMM_PD_PER setting, if it is necessary to trigger a fault,
and code has the time to address it before the device enters SHUTDOWN as a part of testing.
7.6.3.20 CTO_CNT 0x29–2B (41–43) Communication Timeout Counter
BIT
[23:0]
NAME
COMM_TIM_CNT
DESCRIPTION
This register sets and reports the current value of the communication timeout up-counter running from a
4-kHz clock source. This is the counter used for both COMM_PD_PER and COMM_TMOUTPER.
Writing these bits sets the current value of the communication timeout counter. Reads of this register
are only useful when CCNT_RST_OFF is set.
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7.6.3.21 SMPL_SLY1 0x3D (61) Initial Sampling Delay
BIT
[7]
NAME
RSVD
DESCRIPTION
Reserved — always write/read as zero.
This value specifies the delay from changing the MUX to the first cell voltage until the channel is
sampled. This delay is applied only once per sample request, even if oversampling is used.
0 = no delay (Recommended (1))*
1 = 2 µs
2 = 5 µs
3 = 10 µs
[6:4]
4 = 20 µs
INIT_VOL_DLY
5 = 50 µs
6 = 100 µs
7 = 200 µs
This value is useful when all the cell voltages should return values that are nearly the same, as it
allows one settling delay and shorter channel-to-channel delays.
See the Application and Implementation section for using non-zero settings in accordance with specific
design criteria requirements.
[3]
RSVD
Reserved — always write/read as zero
This value specifies the delay from changing the MUX to the first auxiliary channel until the channel is
sampled. This delay is applied only once per sample request, even if oversampling is used.
0 = no delay (Recommended (1))*
1 = 2 µs
2 = 5 µs
3 = 10 µs
[2:0]
4 = 20 µs
INIT_AUX_DLY
5 = 50 µs
6 = 100 µs
7 = 200 µs
This value is useful when all the AUX voltages should return values that are nearly the same, as it
allows one settling delay and shorter channel-to-channel delays.
See the Application and Implementation section for using non-zero settings in accordance with specific
design criteria requirements.
(1)
Recommended setting: 0x00
7.6.3.22 Cell_CSPER 0x3E (62) Cell Voltage and Internal Temperature Sampling Interval
BIT
78
NAME
DESCRIPTION
[7:4]
ADC_PERIOD_VOL
This value sets the ADC sampling interval that will be used for the cell voltages.
[3:0]
ADC_PERIOD_HTEMP
This value sets the ADC sampling interval that will be used for the analog die internal temperature
channel. See Table 9 for settings.
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Table 9. ADC Sample Intervals, Registers 62–68
SAMPLING (1)
PERIOD
(1)
(1)
µs
NOTE
ADC_PERIOD_*
4.13
0
5.96
1
Not Recommended for
Analog Die Channels
8.02
2
10.0
3
12.6
4
OK
14.9
5
OK
17.4
6
OK
19.9
7
OK
24.9
8
OK
30.0
9
OK
40.1
A
OK
60.0
B
OK
100
C
OK
200
D
OK
500
E
OK
1000
F
OK
Sampling interval and averaging mode will affect device accuracy.
7.6.3.23 AUX_SPER 0x3F–42 (63–66) AUX Sampling Period
BIT
NAME
[31:28]
ADC_PERIOD_AUX0
[27:24]
ADC_PERIOD_AUX1
[23:20]
ADC_PERIOD_AUX2
[19:16]
ADC_PERIOD_AUX3
[15:12]
ADC_PERIOD_AUX4
[11:8]
ADC_PERIOD_AUX5
[7:4]
ADC_PERIOD_AUX6
[3:0]
ADC_PERIOD_AUX7
DESCRIPTION
This value sets the ADC sampling interval that will be used for the specified AUX channel. See
Table 9 for settings.
7.6.3.24 TEST_SPER 0x43–44 (67–68) Test Sampling Periods
BIT
NAME
DESCRIPTION
[15:12]
ADC_PERIOD_MOD
This value sets the ADC sampling interval that will be used for the Module monitor.
See Table 9 for settings.
[11:8]
RSVD
Reserved — to maintain compatibility with default configuration, the user should program these bits
to "1001" (binary).
[7:4]
ADC_PERIOD_REF
This value sets the ADC sampling interval that will be used for the 4.5-V ANALOG reference.
See Table 9 for settings.
[3:0]
ADC_PERIOD_VM
This value sets the ADC sampling interval for the VM monitor to use.
See Table 9 for settings.
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7.6.3.25 SHDN_STS 0x50 (80) Shutdown Recovery Status
The SHDN_STS register is for design debug only. The application software must not use information in this
register for system actions.
BIT
NAME
DESCRIPTION
[7]
GCL_PD_STAT
This bit is set after a control logic power down event. It indicates that shutdown was requested by
the controller. This is caused by writing the DEV_CTRL[PWRDN] = 1 bit or the communication
power down timeout expiring.
[6]
GTSD_PD_STAT
This bit indicates that shutdown was caused by the Digital TSD (Thermal Shut Down) or by VIO
being held low long enough to cause shutdown.
[5]
V5VAO_PD_STAT
This bit is set by a falling V5VAO reaching the V5VAO POR voltage V5VAOSD. This usually
indicates that voltage from the TOP pin was removed and reapplied.
[4]
ANALOG_PD_STAT
This bit is set due to the analog die requesting shutdown. See the details for bits 0:1 (below) for
the specific cause.
In proper operation, if this bit is set either NPN_PD_STAT bit [1] or HTSD_PD_STAT, bit [0]
should also be set.
RSVD
Reserved — always read as zero.
[1]
NPN_PD_STAT
This bit is set any time the (VP regulator circuit) external NPN took too long to get VP into proper
operating range.
This bit is only valid when ANALOG_PD_STAT is set; otherwise, it should be ignored.
[0]
HTSD_PD_STAT
This bit is set when the Analog die TSD occurs.
This bit is only valid when ANALOG_PD_STAT is set; otherwise, it should be ignored.
[3:2]
7.6.3.26 STATUS 0x51 (81) Device Status
BIT
[7]
NAME
FAULT_CONDITION
DESCRIPTION
Write '1': No effect
Write '0': No effect
Read '1': A fault bit is currently set in one or more of the fault registers. This does not include bits
in this register even if they do affect the fault output.
Write '1': No effect
Write '0': No effect
[6]
STACK_FAULT
Read '1': A fault is currently detected on the differential fault input.
The state of this bit is always included in the fault output. This fault is masked if
COMCONFIG[FAULT_HIGH_EN] == 0. This fault is self-clearing when the fault condition goes
away.
Write '1': Reset the bit to zero.
Write '0': No effect
Read '1': A fault was detected on the differential fault input.
[5]
STACK_FAULT_DET
This is a latched version of STACK_FAULT and indicates that some stack fault has been seen
since the last time this bit was reset.
The state of this bit does not affect the fault output. It is provided for informational purposes and
for debugging transient faults. This fault is masked if
COMCONFIG[FAULT_HIGH_EN] == 0.
[4]
COMM_CLEAR
Write '1': Reset the bit to zero.
Write '0': No effect
Read '1': A communication clear has been detected.
The state of this bit does not affect the fault output.
[3]
COMM_RESET
Write '1': Reset the bit to zero.
Write '0': No effect
Read '1': A communication reset has been detected.
The state of this bit does not affect the fault output.
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BIT
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NAME
DESCRIPTION
This read-only bit indicates ADC conversion data are available when set. Writing to the bit has no
effect.
The bit is reset by reading any conversion result (sample) data.
[1]
NEW_DATA
This can be used to tell if some new data have been collected since the last COMMAND to report
sample data. This only indicates if some sample has been collected since the last report. It does
not track what channel was reported or collected. This bit will not be set by the automatic internal
temperature sampling or initialization sampling.
Write '1': Stop waiting for VM and continue with initialization.
Write '0': No effect
Read '0': System initialization is complete.
Read '1': System initialization is in progress.
[0]
SYS_INIT
This can be useful to speed up the wakeup sequence. Device accuracy may be impaired and is
not specified until VM is in the correct range.
This is useful when waking the device quickly for self-testing purposes or performing tests that will
cause shutdown or reset. Setting this bit allows code to perform other functions while waiting for
VM to ramp up.
7.6.3.27 FAULT_SUM 0x52–53 (82–83) Fault Summary
BIT
NAME
[15]
UV_FAULT_SUM
[14]
OV_FAULT_SUM
[13]
AUXUV_FAULT_SUM
[12]
AUXOV_FAULT_SUM
[11]
CMPUV_FAULT_SUM
[10]
CMPOV_FAULT_SUM
[9]
COMM_FAULT_SUM
[8]
SYS_FAULT_SUM
[7]
CHIP_FAULT_SUM
[6]
GPI_FAULT_SUM
[5:0]
RSVD
DESCRIPTION
For each of these bits:
Write '1': Reset all fault conditions of this type.
Write '0': No effect
Read '1': One or more of the individual fault bits of this type are currently set.
These bits always reflect the state of the underlying bits in the other fault registers, which may be
latched or not, depending on the setting of the DEVCONFIG[UNLATCHED_FAULT] bit.
Reserved — always read as zero.
7.6.3.28 FAULT_UV 0x54–55 (84–85) Cell Undervoltage Fault
BIT
[15:0]
NAME
DESCRIPTION
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': The stored result for the corresponding battery channel is less than UV_THRES_CELL.
UV_FAULT[0] corresponds to cell 1.
If UNLATCHED_FAULT is set, this register is self-clearing.
UV_FAULT
7.6.3.29 FAULT_OV 0x56–57 (86–87) Cell Overvoltage Fault
BIT
[15:0]
NAME
OV_FAULT
DESCRIPTION
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': The stored result for the corresponding battery channel is greater than
OV_THRES_CELL. OV_FAULT[0] corresponds to cell 1.
If UNLATCHED_FAULT is set, this register is self-clearing.
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7.6.3.30 FAULT_AUX 0x58–59 (88–89) Auxiliary Under/Over-Threshold Fault
BIT
[15:8]
[7:0]
NAME
DESCRIPTION
AUX_UV_FAULT
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': The stored result for the corresponding auxiliary channel is less than
UV_THRES_AUX*. AUX_UV_FAULT[0] corresponds to AUX0.
If UNLATCHED_FAULT is set, this register is self-clearing.
AUX_OV_FAULT
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': The stored result for the corresponding auxiliary channel is greater than
OV_THRES_AUX*. AUX_OV_FAULT[0] corresponds to AUX0.
If UNLATCHED_FAULT is set, this register is self-clearing.
7.6.3.31 FAULT_2UV 0x5A–5B (90–91) Comparator Undervoltage Fault
BIT
[15:0]
NAME
CMPUV_FAULT
DESCRIPTION
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': Corresponding battery cell comparator has detected an undervoltage condition.
CMPUV_FAULT[0] corresponds to cell 1.
When UNLATCHED_FAULT is set, these comparator faults only automatically clear if no other
Analog die based fault exists. This is true even for faults that are masked.
Analog die faults include FAULT_SYS[0:3] or any bit in registers FAULT_2UV or FAULT_2OV.
7.6.3.32 FAULT_2OV 0x5C–5D (92–93) Comparator Overvoltage Fault
BIT
[15:0]
NAME
CMPOV_FAULT
DESCRIPTION
For each bit in this bitmask:
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': Corresponding battery cell comparator has detected an overvoltage condition.
CMPOV_FAULT[0] corresponds to cell 1.
When UNLATCHED_FAULT is set, these comparator faults only automatically clear if no other
Analog die based fault exists. This is true even for faults that are masked.
Analog die faults include FAULT_SYS[0:3] or any bit in registers FAULT_2UV or FAULT_2OV.
7.6.3.33 FAULT_COM 0x5E–5F (94–95) Communications Fault
BIT
NAME
DESCRIPTION
[15]
COMP_ERR_H
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A bit on the high-side interface failed to compare with its complement. This is notification
only; the frame is processed by the communications interface logic.
[14]
COMP_ERR_L
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A bit on the low-side interface failed to compare with its complement. This is notification
only; the frame is processed by the communications interface logic.
COMP_FLT_H
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A frame on the high-side interface (COMMH) was stopped due to two or more
complement errors (COMP_ERR_H).
COMP_FLT_L
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A frame on the low-side interface (COMML) was stopped due to two or more
complement errors (COMP_ERR_L).
[13]
[12]
82
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BIT
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NAME
DESCRIPTION
[11]
EDGE_ERR_H
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A falling edge was not detected on the high-side interface by the 4th bit.
[10]
EDGE_ERR_L
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A falling edge was not detected on the low-side interface by the 4th bit.
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A framing bit with value "1" was detected on the high-side differential interface.
[9]
ABORT_H
A data byte was stopped and ignored. If this occurs on the high-side interface, it is always due to a
communication problem. Sending COMM_RESET or COMM_CLEAR to the UART interface on the
bottom chip will cause this fault on the low-side interface.
When it occurs on the high side, it may have caused this chip to fail to return its frame in a
broadcast or group response (although the microcontroller should already have detected this
before this bit was read).
[8]
ABORT_L (1)
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A framing bit with value "1" was detected on the low-side differential interface.
A data byte was stopped and ignored. ABORT_L also reads "1" on devices in a stack when a
COMM_RESET or COMM_CLEAR is sent to the UART interface on the base device of a stack.
CRC_FAULT_H
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A CRC fault has been detected on the high-side interface.
The frame was discarded. If it occurs on the high side, it may have caused this chip to fail to return
its frame in a broadcast or group response.
CRC_FAULT_L
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A CRC fault has been detected on the low-side interface (either single-ended UART or
differential VBUS).
The frame was discarded.
[5]
FRAME_ERR
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': A framing error has been detected.
This indicates that the chip received a start of frame on the differential communications interface
before it had completed the prior frame.
[4]
RSVD
Reserved — always read as zero
[7]
[6]
[3]
STOP_ERR (1)
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': The UART receiver detected an invalid stop bit on the single-ended low-side interface.
This error only appears on chips using the UART interface. COMM_CLEAR and COMM_RESET
will also cause this fault.
This error is specific to the UART interface.
[2:1] RSVD
Reserved — always read as zero
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': Stack fault input (FAULTH±) is too noisy or is running at the wrong frequency.
[0]
STK_FAULT_ERR
Note: The STK_FAULT_ERR flag may not be clearable under some conditions. If a
STK_FAULT_ERR is detected, and then no more edges appear on the high-side fault pins (as
would be the case if the chip above had a fault condition), it may be impossible to clear the
STK_FAULT_ERR flag. Once proper signaling resumes on the high-side fault pin, it will again be
possible to clear this fault.
Masked STK_FAULT_ERR is not cleared during initialization. As a result, there is a approximately
5-µs window at startup where, if the high-side fault receiver detects more than four falling edges,
the STK_FAULT_ERR will be set even though it is masked.
(1)
COMM_CLEAR causes STOP_ERR and COMM_CLEAR on base device and ABORT_L on the chips higher in the stack.
COMP_ERR_L, COMP_FLT_L, and EDGE_ERR_L faults do not occur on the base device in a stack configuration. See Protocol
Description section for more details.
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7.6.3.34 FAULT_SYS 0x60 (96) System Fault
BIT
NAME
DESCRIPTION
Write '1': Reset the bit to zero.
[7]
SYS_RESET
Write '0': No effect
Read '1': A system reset has been detected.
Write '1': Reset the fault condition.
[6]
COMM_TIMEOUT
Write '0': No effect
Read '1': Communications timeout has been detected.
Write '1': Reset the fault condition.
Write '0': No effect
[5]
VDIG_WAKE_FAULT
Read '1': VDIG supply was already high on wakeup. This could happen if the NPN transistor
were leaking and preventing VDIG from going away when VP/VDIG shuts down. It could also
occur if the chip is reset (in which case the VDIG supply remained on) or if it was shut down too
briefly to allow the supply time to ramp down. This bit is provided to allow detection of leakage
current into the supply during shutdown.
This bit is checked only set by the device during the device initialization sequence. Once
cleared, it will not set again until the block is reset.
Write '1': Reset the fault condition.
[4]
INT_TEMP_FAULT
Write '0': No effect
Read '1': Overtemperature condition in the digital die
If UNLATCHED_FAULT is set, this bit is self-clearing.
Write '1': Reset the fault condition.
[3]
VDIG_FAULT
Write '0': No effect
Read '1': VDIG supply failure detected in the analog die.
Write '1': Reset the fault condition.
[2]
VM_FAULT
Write '0': No effect
Read '1': VM supply failure detected in analog die.
Write '1': Reset the fault condition.
[1]
VP_FAULT
Write '0': No effect
Read '1': VP supply failure detected in analog die.
Write '1': Reset the fault condition.
[0]
VP_CLAMP
Write '0': No effect
Read '1': NPNB pin is monitored and clamped to keep the NPNB pin from going over voltage.
7.6.3.35 FAULT_DEV 0x61–62 (97–98) Chip Fault
BIT
NAME
DESCRIPTION
Write '1': No effect
[15]
USER_CKSUM_ERR
Write '0': No effect
Read '1': A checksum error was detected in the registers. This fault is self-clearing when the
condition goes away.
Write '1': Reset the fault condition.
[14]
FACT_CKSUM_ERR
Write '0': No effect
Read '1': A checksum error was detected in the factory registers.
Write '1': Reset the fault condition.
Write '0': No effect
[13]
ANALOG_FAULT_ERR
[12]
HREF_FAULT
Read '1': The analog die is reporting an error, but it cannot tell what the error is (no error
condition has been detected). This may be caused by a single event upset, or possibly the
device has failed. If this occurs consistently, the device should be removed from service.
Write '1': Reset the fault condition.
Write '0': No effect
Read '1': Analog die 4.5-V reference measurement was out of range.
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BIT
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NAME
DESCRIPTION
Write '1': Reset the fault condition.
[11]
HREF_GND_FAULT
Write '0': No effect
Read '1': Analog-die reference ground measurement was out of range.
[10:5]
RSVD
Reserved — always read as zero
Write '1': Reset the fault condition.
[4]
ADC_CAL_ERR
Write '0': No effect
Read '1': An ADC test (ADC_FCAL_TEST or ADC_PCAL_TEST) failed.
Write '1': Reset the fault condition.
[3]
USER_ECC_COR
Write '0': No effect
Read '1': A ECC fault was corrected while loading user space from EEPROM.
Write '1': Reset the fault condition.
[2]
USER_ECC_ERR
Write '0': No effect
Read '1': An uncorrectable ECC fault was detected while loading from EEPROM. Registers in
the block (not all registers) have been loaded with their default values.
Write '1': Reset the fault condition.
[1]
FACT_ECC_COR
Write '0': No effect
Read '1': A ECC fault was corrected while loading factory space from EEPROM.
Write '1': Reset the fault condition.
Write '0': No effect
[0]
FACT_ECC_ERR
Read '1': An uncorrectable ECC fault was detected while loading from factory registers.
Registers in the block (not all registers) have been loaded with their default values. The device
is operating abnormally and has probably failed. Functionality, behavior, and results are suspect
and should not be relied upon.
7.6.3.36 FAULT_GPI 0x63 (99) GPI Fault
BIT
[7:6]
NAME
RSVD
DESCRIPTION
Reserved — always read as zero.
Write '1': Reset the fault condition.
Write '0': No effect
[5:0]
GPI_FAULT
Read '1': A GPIO input, configured as a fault input in GPI_FAULT_CONFIG, has signaled a
fault condition.
If UNLATCHED_FAULT is set, this register is self-clearing.
7.6.3.37 MASK_COMM 0x68–69 (104–105) Communications Fault Masks
BIT
NAME
[15]
COMP_ERR_H_MSK
[14]
COMP_ERR_L_MSK
[13]
COMP_FLT_H_MSK
[12]
COMP_FLT_L_MSK
[11]
EDGE_ERR_H_MSK
[10]
EDGE_ERR_L_MSK
[9]
ABORT_H_MSK
[8]
ABORT_L_MSK
[7]
CRC_FAULT_H_MSK
[6]
CRC_FAULT_L_MSK
[5]
FRAM_ERR_MSK
[4]
RSVD
[3]
STOP_ERR_MSK
DESCRIPTION
For each of these bits:
0 = Do not mask this fault.
1 = Mask this fault.
Reserved — always write/read as zero
0 = Do not mask this fault.
1 = Mask this fault.
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BIT
[2:1]
NAME
www.ti.com
DESCRIPTION
RSVD
Reserved — always write/read as zero
0 = Do not mask this fault.
1 = Mask this fault.
[0]
STK_FAULT_ERR_MSK
Masked STK_FAULT_ERR is not cleared during initialization. As a result, there is an
approximately 5-µs window at startup where, if the high-side fault receiver detects more than
four falling edges, STK_FAULT_ERR will be set even though it is masked.
7.6.3.38 MASK_SYS 0x6A (106) System Fault Masks
BIT
(1)
NAME
DESCRIPTION
(1)
[7]
SYS_RESET_MSK
[6]
COMM_TIMEOUTMSK
For each of these bits:
0 = Do not mask this fault.
1 = Mask this fault.
[5]
RSVD
Reserved — always write/read as zero
[4]
INT_TEMP_FAULT_MSK
[3]
VDIG_FAULT_MSK
[2]
VM_FAULT_MSK
[1]
VP_FAULT_MSK
[0]
VP_CLAMP_MSK
For each of these bits:
0 = Do not mask this fault.
1 = Mask this fault.
If the SYS_RESET_MSK is set to 1, this setting should be burned to EEPROM in order to provide useful information.
7.6.3.39 MASK_DEV 0x6B–6C (107–108) Chip Fault Masks
BIT
NAME
DESCRIPTION
[15]
USER_CKSUM_MSK
[14]
FACT_CKSUM_MSK
[13]
ANALOG_FERR_MSK
For each of these bits:
0 = Do not mask this fault.
1 = Mask this fault.
RSVD
Reserved — always write/read as zero
[12:0]
7.6.3.40 FO_CTRL 0x6E–6F (110–111) Fault Output Control
BIT
[15]
UV_FAULT_OUT
[14]
OV_FAULT_OUT
[13]
AUXUV_FAULT_OUT
[12]
AUXOV_FAULT_OUT
[11]
CMPUV_FAULT_OUT
[10]
CMPOV_FAULT_OUT
[9]
COMM_FAULT_OUT
[8]
SYS_FAULT_OUT
[7]
CHIP_FAULT_OUT
[6]
GPI_FAULT_OUT
[5:0]
86
NAME
RSVD
DESCRIPTION
For each of these bits:
0 = Do not include these faults in the fault output.
1 = Include these faults in the fault output.
Reserved — always write/read as zero
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7.6.3.41 GPIO_DIR 0x78 (120) General Purpose IO Direction
BIT
[7:6]
NAME
RSVD
DESCRIPTION
Reserved — always write/read as zero
This bitmask enables the GPIO pins to behave as GPI or GPO:
[5:0]
GPO_EN
0: Input
1: Output
GPO_EN[0] corresponds to GPIO0.
7.6.3.42 GPIO_OUT 0x79 (121) General Purpose Output
BIT
[7:6]
NAME
RSVD
DESCRIPTION
Reserved — always write/read as zero
This bitmask sets the output state for each GPIO pin when the corresponding bit of GPO_EN = 1. GPO[0]
corresponds to GPIO0.
[5:0]
GPO
0: the GPIO output is 0.
1: the GPIO output is 1.
7.6.3.43 GPIO_PU 0x7A (122) General Purpose Pull-Up
BIT
NAME
DESCRIPTION
[7:6]
RSVD
Reserved — always write/read as zero
[5:0]
GPO_PU
Setting any bit to 1 turns the respective GPIO pull-up on.
Note: Care should be taken not to turn on a bit at same time as the corresponding GPO_PD bit in
register GPIO_PD.
7.6.3.44 GPIO_PD 0x7B (123) General Purpose Pull-Down
BIT
NAME
DESCRIPTION
[7:6]
RSVD
Reserved — always write/read as zero
[5:0]
GPO_PD
Setting any bit to 1 turns the respective GPIO pull-down on.
Note: Care should be taken not to turn on a bit at same time as the corresponding GPO_PU bit in
register GPIO_PU.
7.6.3.45 GPIO_IN 0x7C (124) General Purpose Input
[7:6]
RSVD
Reserved — always read as zero
[5:0]
GPI
Reports the current value of the GPIO pin. GPI[0] corresponds to GPIO0.
7.6.3.46 GP_FLT_IN 0x7D (125) General Purpose Fault Input
BIT
NAME
DESCRIPTION
[7]
RSVD
Reserved — always read as zero
[6]
GPI_FAULT_SENSE
0 = GPIO fault inputs will create a fault if low.
1 = GPIO fault inputs will create a fault if high.
[5:0]
GPI_FAULT_CONFIG
This bitmask sets which of the GPIO pins are treated as fault inputs.
Note that this setting does not prevent the I/O pin from being driven by the device. This feature may be
used as a part of self-test.
7.6.3.47 MAGIC1 0x82–85 (130–133) Magic1
BIT
[31:0]
NAME
MAGIC1
DESCRIPTION
Magic value to enable EEPROM programming. This value must be written in a single frame. Reads
always return zero.
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7.6.3.48 COMP_UV 0x8C (140) Comparator Undervoltage Threshold
BIT
NAME
[7:1]
[0]
DESCRIPTION
CMP_UV_THRES
These bits set the comparator undervoltage-threshold value in 25-mV steps. The range is determined
by the CMP_TST_SHF_UV bit.
CMP_TST_SHF_UV
This bit sets the operating range for the undervoltage comparators.
0 = Normal range of 0.7 V to 3.875 V
1= Shifted range of 2.0 V to 5.175 V (used for self-test purposes)
7.6.3.49 COMP_OV 0x8D (141) Comparator Overvoltage Threshold
BIT
NAME
[7:1]
[0]
DESCRIPTION
CMP_OV_THRES
These bits set the comparator overvoltage-threshold value in 25-mV steps. The range is determined
by the CMP_TST_SHF_OV bit.
CMP_TST_SHF_OV
This bit sets the operating range for the undervoltage comparators.
0 = Normal range of 2.0 V to 5.175 V
1= Shifted range of 0.7 V to 3.875 V (used for self-test purposes).
7.6.3.50 CELL_UV 0x8E–8F (142–143) Cell Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_CELL
This register sets the upper 14 bits of the 16-bit undervoltage threshold value that will be used for all
of the ADC cell voltage measurements. This is a scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.51 CELL_OV 0x90–91 (144–145) Cell Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_CELL
This register sets the overvoltage threshold value that will be used for all of the ADC cell voltage
measurements. This is a scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.52 AUX0_UV 0x92–93 (146–147) AUX0 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX0
This register contains the undervoltage threshold that will be used for the AUX0 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.53 AUX0_OV 0x94–95 (148–149) AUX0 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX0
This register contains the overvoltage threshold that will be used for the AUX0 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.54 AUX1_UV 0x96–97 (150–151) AUX1 Undervoltage Threshold
BIT
88
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX1
This register contains the undervoltage threshold that will be used for the AUX1 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
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7.6.3.55 AUX1_OV 0x98–99 (152–153) AUX1 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX1
This register contains the overvoltage threshold that will be used for the AUX1 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.56 AUX2_UV 0x9A–9B (154–155) AUX2 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX2
This register contains the undervoltage threshold that will be used for the AUX2 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.57 AUX2_OV 0x9C–9D (156–157) AUX2 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX2
This register contains the overvoltage threshold that will be used for the AUX2 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.58 AUX3_UV 0x9E–9F (158–159) AUX3 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX3
This register contains the undervoltage threshold that will be used for the AUX3 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.59 AUX3_OV 0xA0–A1 (160–161) AUX3 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX3
This register contains the overvoltage threshold that will be used for the AUX3 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.60 AUX4_UV 0xA2–A3 (162–163) AUX4 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX4
This register contains the undervoltage threshold that will be used for the AUX4 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.61 AUX4_OV 0xA4–A5 (164–165) AUX4 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX4
This register contains the overvoltage threshold that will be used for the AUX4 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.62 AUX5_UV 0xA6–A7 (166–167) AUX5 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX5
This register contains the undervoltage threshold that will be used for the AUX5 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
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7.6.3.63 AUX5_OV 0xA8–A9 (168–169) AUX5 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX5
This register contains the overvoltage threshold that will be used for the AUX5 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.64 AUX6_UV 0xAA–AB (170–171) AUX6 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX6
This register contains the undervoltage threshold that will be used for the AUX6 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.65 AUX6_OV 0xAC–AD (172–173) AUX6 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX6
This register contains the overvoltage threshold that will be used for the AUX6 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.66 AUX7_UV 0xAE–AFB (174–175) AUX7 Undervoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
UV_THRES_AUX7
This register contains the undervoltage threshold that will be used for the AUX7 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.67 AUX7_OV 0xB0–B1 (176–177) AUX7 Overvoltage Threshold
BIT
NAME
DESCRIPTION
[15:2]
OV_THRES_AUX7
This register contains the overvoltage threshold that will be used for the AUX7 samples. This is a
scaled offset-binary value from 0 V to 5 V.
[1:0]
RSVD
Reserved — always write/read as zero
7.6.3.68 LOT_NUM 0xBE–C5 (190–197) Device Lot Number
BIT
NAME
[63:0]
LOT_NUM(x)
DESCRIPTION
Device lot number
7.6.3.69 SER_NUM 0xC6–C7 (198–199) Device Serial Number
BIT
NAME
[15:0]
SERIAL_NUM
DESCRIPTION
Device serial number
7.6.3.70 SCRATCH 0xC8–CF (200–207) Scratch Registers
BIT
NAME
[63:0]
90
SCRATCH(x)
DESCRIPTION
This register contains user-defined data (for example, post-assembly calibration coefficients) that can
be written and read by the host microcontroller.
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7.6.3.71 VSOFFSET 0xD2 (210) Cell Offset Correction
BIT
[7:0]
NAME
CCOFFSET
DESCRIPTION
User offset-adjustment register for VSENSE cell voltage channels. This 2's complement value will be
added to all cell voltage channels. The range is approximately –9.77 mV to 9.69 mV in 255 steps.
The offset is approximately equal to (5 V × CCOFFSET / 216). It can be used to compensate for
offsets induced by the user design or PCB mounting.
7.6.3.72 VSGAIN 0xD3 (211) Cell Gain Correction
BIT
[7:0]
NAME
DESCRIPTION
User gain-adjustment register for VSENSE cell voltage channels. This is a 2's complement value
where positive values represent a gain > 1.0 and negative values represent a gain < 1.0, and is
applied to all cell voltage channels.
CCGAIN
The range is approximately –9.77 mV to 9.69 mV full scale in 255 steps. The gain correction is
approximately equal to (input value × (1 + CCGAIN / 216)). It can be used to compensate for gain
error induced by the user design (such as larger values of input resistor) or PCB mounting.
7.6.3.73 AX0OFFSET 0xD4–D5 (212–213) AUX0 Offset Correction
BIT
[15:10]
[9:0]
NAME
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET0
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET0 / 216). See Section AUX Channel Post-Assembly
Calibration Adjustment for details. It can be used to compensate for offsets induced by the user
design or PCB mounting.
7.6.3.74 AX1OFFSET 0xD6–D7 (214–215) AUX1 Offset Correction
BIT
[15:10]
[9:0]
NAME
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET1
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET1 / 216). See Section AUX Channel Post-Assembly
Calibration Adjustment for details. It can be used to compensate for offsets induced by the user
design or PCB mounting.
7.6.3.75 AX2OFFSET 0xD8–D9 (216–217) AUX2 Offset Correction
BIT
[15:10]
[9:0]
NAME
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET2
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET2 / 216). See Section AUX Channel Post-Assembly
Calibration Adjustment for details. It can be used to compensate for offsets induced by the user
design or PCB mounting.
7.6.3.76 AX3OFFSET 0xDA–DB (218–219) AUX3 Offset Correction
BIT
[15:10]
[9:0]
NAME
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET3
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET3 / 216). See Section AUX Channel Post-Assembly
Calibration Adjustment for details. It can be used to compensate for offsets induced by the user
design or PCB mounting.
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7.6.3.77 AX4OFFSET 0xDC–DD (220–221) AUX4 Offset Correction
BIT
NAME
[15:10]
[9:0]
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET4
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET4 / 216). See Section AUX Channel Post-Assembly
Calibration Adjustment for details. It can be used to compensate for offsets induced by the user
design or PCB mounting.
7.6.3.78 AX5OFFSET 0xDE–DF (222–223) AUX5 Offset Correction
BIT
NAME
[15:10]
[9:0]
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET5
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET5 / 216). See text for details. It can be used to
compensate for offsets induced by the user design or PCB mounting.
7.6.3.79 AX6OFFSET 0xE0-E1 (224–225) AUX6 Offset Correction
BIT
NAME
[15:10]
[9:0]
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET6
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET6 / 216). See text for details. It can be used to
compensate for offsets induced by the user design or PCB mounting.
7.6.3.80 AX7OFFSET 0xE2-E3 (226–227) AUX7 Offset Correction
BIT
NAME
[15:10]
[9:0]
DESCRIPTION
RSVD
Reserved — always write/read as zero
AUX_COFFSET7
User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX
channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is
approximately equal to (5 V × AUXCOFFSET7 / 216). See text for details. It can be used to
compensate for offsets induced by the user design or PCB mounting.
7.6.3.81 TSTR_ECC 0xE6-ED (230–237) ECC Test Result[1:0]
BIT
NAME
[31:0]
ECC_TEST_RSLT(x)
DESCRIPTION
These values display the test result from running an ECC test using the TEST_CTRL[ECC_TEST]
bits.
Expected output for Correctable User ECC Test 0x18C3 FF8A 68A9 8069.
Expected output for Correctable Factory ECC Test 0xCC72 D182 80BA 9767.
Expected output for non-correctable User and Factory ECC tests is 0x0000 0000 0000 0000.
7.6.3.82 CSUM 0xF0–F3 (240–243) Checksum
BIT
NAME
[31:0]
USER_CKSUM
DESCRIPTION
This register contains the programmed checksum for the registers. See Table 7, column "CS" for
included registers. The FAULT_DEV[USER_CKSUM_ERR] flag will be set when this value does not
match the internally calculated value shown in CSUM_RSLT 0xF4–F7(244–247) Checksum Readout.
7.6.3.83 CSUM_RSLT 0xF4–F7(244–247) Checksum Readout
BIT
NAME
[31:0]
92
USER_CKSUM_RD
DESCRIPTION
This register contains the current internally calculated checksum for the registers.
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7.6.3.84 TEST_CSUM 0xF8–F9 (248–249) Checksum Test Result
BIT
[15:0]
NAME
CKSUM_TEST
DESCRIPTION
This register contains the most recent test result, from either a User or TI space checksum test.
TESTCTRL[CKSUM_TEST_RUN] triggers the test for which the results will appear in the
CKSUM_TEST register. Expected results are provided in the CKSUM_TEST_RUN bit description.
7.6.3.85 EE_BURN 0xFA (250) EEPROM Burn Count
BIT
NAME
[7:0]
EE_BURN_CNT
DESCRIPTION
This register contains the EEPROM burn count. It is incremented every time the EEPROM is
programmed.
7.6.3.86 MAGIC2 0xFC–FF (252–255) Magic2
BIT
[31:0]
NAME
MAGIC2
DESCRIPTION
Magic value to enable EEPROM programming. This value must be written in a single frame. Reads
always return zero.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Special Pin Considerations
8.1.1.1 Unused VSENSE Inputs (Designs with Less Than 16 Cells)
VSENSE inputs start with VSENSE0 and continue to VSENSE16. Inputs must be used in ascending order, with
all unused inputs connected together with the input to the highest used VSENSE_ input. For example, in a
13-cell design, inputs VSENSE14, VSENSE15, and VSENSE16 are not used. These VSENSE inputs must be
connected together with VSENSE13 for proper operation. The highest used VSENSE, which is connected to a
cell through the resistor of the input low-pass filter. As an example, VSENSE13 is connected to cell 13 through a
100-Ω resistor; pins VSENSE14, VSENSE15, and VSENSE16 are then connected to pin VSENSE13.
A 100-Ω resistor is used here as an example only, all inputs should use the same resistor as chosen by the
designer to meet filter requirements for their circuit implementation. Figure 25 illustrates the proper connection for
unused VSENSE inputs.
Q1
NPNB
C1
1 µF
C2
0.1 µF
RCOL
TOP
R1
100 Ÿ
D1
VSENSE16
D2
VSENSE15
VSENSE14
RIN
100 Ÿ
CELL13
R2
100Ÿ
VSENSE13
C3
1 µF
Z2
6.2 V
VSENSE12
To
CELL12
C4
1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Example Connection for Less than 16 Cells (Some Components Omitted for Clarity)
8.1.1.2 Unused AUX Inputs
Unused AUX inputs can be allowed to float, be tied to VSS, or pulled up to VP/VDIG through a nominal 10-kΩ to
1-MΩ resistor. To pull up the AUX input to VP, enable the TESTAUXPU register, which uses an internally
supplied resistor.
94
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Application Information (continued)
8.1.1.3 TOP and VSENSE16 Pins
To ensure that the voltage between TOP and VSENSE16 does not violate the Absolute Maximum Ratings and
Recommended Operating Conditions during hot-plug or other unusual conditions, connect the VSENSE16 input
(and any unused SENSE inputs) to the TOP pin using two back-to-back signal diodes. Select diodes with a high
enough current rating to withstand the continuous currents during a wire disconnect and the inrush currents
during hot plug. Use diodes that have a higher Vf, such as an ultra-fast or fast diode. Low Vf diodes, such as
Schottkey diodes, must not be used because noise on the TOP pin may couple onto the VSENSE16 pin (or
highest-sense line used).
The TOP input must also include a low-pass filter using a 0.1-µF capacitor and a 100-Ω to 300-Ω resistor to
avoid voltage stress during cell connection (hot-plug). Figure 26 illustrates the correct VSENSE-TOP connection.
Additionally, connect a transient suppression diode (TVS) to TOP to clamp the voltage to below 88 V and prevent
an overvoltage condition on TOP during hot-plug and other transient events.
TOP
100 Ÿ
0.1 µF
Back-to-back
signal diodes
VSENSE16
100 Ÿ
1 µF
CELL16
90 V
6.2 V
VSENSE15
100 Ÿ
To CELL15
1 µF
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Figure 26. Connecting the TOP and VSENSE16 Pins
8.1.1.4 AGND1 and VSENSE0 Pins
To ensure that the voltage between VSENSE0 and AGND1 does not violate the Absolute Maximum Ratings and
Recommended Operating Conditions during hot-plug or other unusual conditions, connect the VSENSE0 input to
the AGND1 pin using two back-to-back signal diodes. Select diodes with high enough current rating to withstand
the continuous currents during a wire disconnect and the inrush currents during hot plug. Use diodes that have a
higher Vf, such as an ultra-fast or fast diode. Low Vf diodes, such as Schottkey diodes, must not be used
because noise on AGND may couple onto the VSENSE0 input. Additionally, connect a 1-µF capacitor between
VSENSE0 and AGND1. Figure 27 illustrates the correct VSENSE0-to-AGND1 connection.
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Application Information (continued)
To CELL2
RIN
100 Ÿ
VSENSE1
C1
1 µF
Z1
6.2 V
CELL1
VSENSE0
R1
100 Ÿ
Back-to-back
signal diodes
D1
C2
1 µF
D2
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Connecting the AGND1 and VSENSE0 Pins
8.1.1.5 VSENSE to VSENSE Connections
To ensure that the voltage between the VSENSE_ inputs (VSENSE0 to VSENSE1, VSENSE1 to VSENSE2, and
so forth) does not violate the Absolute Maximum Ratings and Recommended Operating Conditions during hotplug or other unusual conditions, zener diodes must be connected between the VSENSE input pins, as close as
possible to the inputs. One zener across every input is advised. The zener diodes provide overvoltage protection
and a path for inrush current during a hotplug event. Figure 28 illustrates the correct VSENSE-to-VSENSE
connection.
R69
BAT16S_F
VSENSE16
100 Ÿ
2
3
C16
1 F
100 V
BAT0
1
Q16
60 V
R88
Z16
6.2 V
2
1
R16
75 Ÿ
EQ16
2 NŸ
R70
100 k
R76
BAT15_F
VSENSE15
Z15
6.2 V
2
3
C15
1 F
100 V
BAT0
2
R15
75 Ÿ
1
100 Ÿ
BAT14_F
1
R89
Q15
60 V
2 NŸ
EQ15
R22
100 NŸ
R24
VSENSE14
100 Ÿ
Copyright © 2016, Texas Instruments Incorporated
BAT0S is the sense point to the negative terminal of CELL1. BAT0 is the power plane for the negative terminal of the
cell stack.
Figure 28. Cell Voltage Sense Circuit
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Application Information (continued)
Select zener diodes that meet the following conditions:
1. The bq76PL455 inputs are protected from input voltage transients greater than 5.5 V. Any transients greater
than 5.5 V must be clamped to less than 6.5 V for an accumulative time duration not to exceed 0.1% of the
device 10-year lifetime.
2. The zener maximum reverse current (Iz) at normal battery-cell voltage levels are as low as possible to keep
the quiescent system-current draw low. Additionally, any leakage through the zener diode affects the total
channel accuracy measurements as it adds to the voltage drop across the filter resistor.
3. The zener must be capable of withstanding instantaneous or continuous currents that the bq76PL455A
experiences during fault events. These events can include cable connect/disconnect, inrush, or reverse
battery voltage. Depending on the fault and the direction of current flow, the maximum power dissipation for
the zener diode must not be exceeded to stay within maximum operating conditions.
Additionally, a series resistor and bypass capacitor are required for each of the VSENSE inputs. The series
resistor (R132 and R138 in Figure 28) serves two functions:
1. They protect the AFE inputs from in-rush currents during hot plug-in. This requirement limits the input series
R to a minimum of 100 Ω. Keep this resistance as low as possible to minimize input voltage offset, which is
also subject to drift over temperature. These requirements limit the maximum value to 1 kΩ. Error due to
input bias currents, on the front end of the AFE, is directly proportional to the value of the resistors. The
voltage measurement error can be calculated as:
voltage measurement error = 2 × R × ISENSE
(10)
2. The resistor and capacitor (R132 and C61 in Figure 28) provide an RC filter for high-frequency noise on the
AFE inputs. The tuning of this filter cutoff is adjustable and depends on the expected frequency of noise in
the system. Select a minimum 0.1-µF capacitor connected from the VSENSE input to the battery pack GND
(BAT0 in Figure 28). Calculate the cutoff frequency using Equation 11:
B? =
1
*V
2è41%1
(11)
3. Ensure that the RC-filter components are as close to the device as possible. The capacitor location is
extremely important and must be given priority for optimum performance.
4. For applications that require a very low filter cutoff frequency, connect a differential capacitor between the
VSENSE lines to provide the bulk of the AFE input filtering. The bias voltage on these differential capacitors
are the same (or very close), therefore, anti-aliasing is improved.
Additional components are necessary to improve EMC performance of bq76PL455A in applications with
electrically noisy environments.
• Use ferrite beads or small inductors in series with the cell inputs between the cell output and the series
resistor to the VSENSE input. The bead and small capacitor must be located near each other.
• Add a 0.0033-µF capacitor from each cell input to the battery pack (BAT0 in Figure 29). Adjust the value of
capacitance to satisfy the PCB layout and field conditions for the application.
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Application Information (continued)
+
BAT16S L1
BAT16S_F
C30
500 ohm
L2
BAT15_F
C43
500 ohm
L3
BAT14_F
C45
500 ohm
L4
BAT13_F
C46
500 ohm
L5
BAT12_F
C47
500 ohm
L6
BAT11_F
C48
500 ohm
L7
BAT10_F
C49
500 ohm
L8
BAT9_F
C50
500 ohm
L9
BAT8_F
C51
500 ohm
L10
BAT7_F
C52
500 ohm
L11
BAT6_F
C53
500 ohm
L12
BAT0
BAT0
BAT0
BAT0
BAT0
BAT0
BAT0
BAT0
BAT0
BAT5_F
BAT0
500 ohm
L13
BAT4_F
C55
500 ohm
L14
500 ohm
L15
BAT0
BAT3_F
C56
BAT2_F
C57
500 ohm
L16
BAT1_F
500 ohm C58
BAT0
BAT0
BAT0
BAT0
BAT0S L17 BAT0S_F
±
BAT0
500 ohm
BAT0
C61
3300 pF BAT0
BAT0S is the sense point to the negative
terminal of CELL1. BAT0 is the power
plane for the negative terminal of the cell
stack.
Figure 29. EMC Filter on Cell Inputs
The AUX_ inputs are single ended, which makes them vulnerable to noisy environments. In order to achieve
more accurate results in extremely noisy environments, it is recommended to use to AUX_ inputs to form a
pseudo-differential measurement. One example is shown in . In this example, AUX1 is used to measure the high
side of the connection, while AUX0 is used to measure the low-side of the connection. The AUX0 measurement
is then subtracted from the AUX1 measurement in order to get a differential measurement that is more accurate.
98
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Application Information (continued)
VP
R1
1k&
AUX1
!
10&
C1
1)F
R2
1k&
C2
1)F
AUX0
Figure 30. Differential AUX_ Example
8.1.1.6 AUX_Connections
VAUX connections require a series resistor and bypass capacitor for filtering to ensure best results. Connect a
1-kΩ resistor from the measure point to the VAUX input and bypass VAUX to GND with a 1-µF capacitor. See
Figure 31 for connection example.
AUX1
AUX2
R1
1 NŸ
R2
1 NŸ
AUX1
C1
1 µF
AUX0
C2
1 µF
Figure 31. AUX_ Filter Components
8.1.2 Communication Buses
8.1.2.1 Single-Ended Communication (UART)
Communication with the bq76PL455A from a host controller is performed utilizing a UART communication
protocol. The UART interface requires the following configuration:
1. COMML- is connected by 100-kΩ pull-down to DGND.
2. COMML+ is connected by 100-kΩ pull-up to V5VAO.
3. FAULT_N has a 50k pull-down to make sure a faults are generated when VIO is not present. The pull-down
on the FAULT_N notifies the host controller in the case of an inadvertent shutdowns.
4. TX and RX are pulled-up to VIO through a 100-kΩ resistor. Do not leave TX and RX unconnected. The TX
must be pulled high to prevent triggering an invalid communications frame during the idle state when TX is
high. When using a serial cable to connect to the host controller, connect the TX pull-up on the host side and
the RX pull-up on the bq76PL455A side.
8.1.2.2 Daisy-Chain Communication Differential Communications
For applications that require multiple bq76PL455A devices, a back-side differential communication bus is
provided that allows the host controller to interface with up to 16 devices, while utilizing only one UART interface.
In this configuration, the bq76PL455A devices are daisy-chained. For the devices that are higher in the stack (not
using the UART interface, differential communications only), the following is the required configuration.
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1. FAULT_N has a 50-kΩ pull-down resistor to make sure a fault is generated when VIO is not present.
2. TX and RX should be pulled-up to VIO through a 100-kΩ resistor. Do not leave TX and RX unconnected.
8.1.2.2.1 Stacked Devices on Same PCB
When multiple, daisy-chained bq76PL455A devices are located on the same PCB, use the circuit in Figure 32 to
ensure best performance of the backside communication.
COMML+
COMMH+
TVS Diode (2)
10 Ÿ
1 nF
10 Ÿ
10 Ÿ
1 nF
10 Ÿ
TVS Diode (2)
COMMH-
COMML-
UP-STACK, HIGHER VOLTAGE
Figure 32. Components Required for Daisy-Chain Communication between Devices on Same PCB
8.1.2.2.2 Stacked Devices Separated by Cables
Many applications require multiple, daisy-chained bq76PL455A devices that are separated by cables. The cable
introduces additional challenges to the application. The recommended circuit is as defined in Figure 33 and
Figure 34.
PCB#1
Common-mode
Choke
Tw. Pair Cable
PCB#2
Common-mode
Choke
COMML+
COMMH+
TVS Diode(2)
1 nF
1 nF
10 Ÿ
100 µH
COMMH-
~100 Ÿ
1 nF
1 nF
UP- STACK, HIGHER VOLTAGE
10 Ÿ
10 Ÿ
TVS Diode(2)
100 µH
COMML10 Ÿ
Figure 33. Components Required for Daisy-Chain Communication between PCBs
PCB#1
Tw. Pair Cable
PCB#2
Common-mode
Choke
Common-mode
Choke
COMMH+
COMML+
TVS Diode(2)
10 Ÿ
470 µH
COMMH-
100 µH
100 µH
~100 Ÿ
10 Ÿ
10 Ÿ
1 nF
1 nF
1 nF
1 nF
470 µH
TVS Diode(2)
COMML10 Ÿ
UP-STACK, HIGHER VOLTAGE
Figure 34. Components Required for Daisy-Chain Communication between PCBs in Noisy Environments
8.1.2.2.3 Daisy-Chain Communication Cables
Select and design the communication cables such that the total sum of capacitance on any COMML±, COMMH±
or FAULT_N± lines (between ICs) is no greater than 140 pF to support the maximum number of stacked ICs.
The capacitance of the cable is calculated using Equation 12:
100
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Application Information (continued)
QJODEAH@A@ PSEOPA@ L=EN ?=>HA % =
2.2Ý
1.3&
p
log l
B×@
where
•
•
•
•
•
C = mutual capacitance, pF/ft
Ɛ = insulation dielectric constant (for example: PVC = 5)
f = stranding factor (for example: 1 strand = 1, 7 strands = 0.939, 19 strands = 0.97, 37 strands = 0.98)
D = diameter over the insulation, inches
d = diameter of the conductor, inches
(12)
The unshielded twisted cable used for bench testing (Alpha Wire 3050 series, Digi-Key part number +A2015W1000-ND) has the following specifications:
Ɛ = 5 (PVC)
f = 0.939 (7 strand)
D = 0.056”
d = 0.024” (0.056” – 2 x 0.016” insulation thickness)
conductor DCR = 25 Ω/1000 ft
∴ (therefore) resulting in capacitance of ≈21.6 pF/ft.
The best choice of differential cable is an automotive-grade, unshielded, twisted cable designed for CAN, such
as the Waytek SAE J1939/15 CAN data bus cable. The capacitance for this cable is approximately 17 pF/ft.
The input capacitance presented by the common-mode filter (see Common-Mode Filter) must also be included in
the total capacitance budget. Only one TVS diode is used as they are connected to both sides of the differential
pair. The allowable cable length is calculated using Equation 13:
140L( F 2 × ?KIIKJ IK@A BEHPAN F 1 × 685 @EK@A ?=L=?EP=J?A
=HHKS=>HA ?=>HA HAJCPD EJ BP =
?=>HA ?=L=?EP=J?A/BP
(13)
8.1.2.2.4 TVS Diodes
TVS diodes are required on the differential I/Os for protection of the communication interface signals during hotplug events and also for absorption of high-voltage transients in operation. Select the TVS diodes for the lowest
possible capacitance as any capacitance as any capacitance on the lines affects the rise-time of the
communication signal. The NXP PESD5V0U1UA is used on the reference design, which has a maximum Cd of
2.6 pF.
8.1.2.2.5 Resistance
The total resistance of each COMML±, COMMH± or FAULT_N± lines must be less than 20 Ω (10 Ω on each end
of the signal connection between bq76PL455A devices). This series resistance is required to limit in-rush current
in a hot-plug event.
8.1.2.2.6 Common-Mode Filter
TI recommends to use a 50–100 µH common-mode filter minimum for proper operation. To achieve the best
performance in noisy environments, use dual common-mode filters (100 µH and 470 µH).
For single common-mode filter applications, the TDK 51-µH, 2.8-kΩ choke (part number ACT45B-510-2P-TL003)
is recommended. This device has an input capacitance of approximately 18 pF.
For dual common-mode filter applications, the TDK 100-µH, 5.8-kΩ choke (part number ACT45B-101-2P-TL003)
and Wurth 470-µH, 2.2-kΩ (part number 744242471) are recommended. The total capacitance is approximately
40 pF.
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Application Information (continued)
8.1.2.2.7 Isolation Capacitor
The differential signal lines are isolated between ICs by a DC blocking capacitor. The capacitor must be rated
with a high enough voltage to provide standoff margin in the event of a fault in the system that exposes the
device to a local hazardous voltage. Selecting a capacitor rated at a minimum of 2 times the stack the voltage is
the recommended practice. One capacitor is sufficient for the normal operation of the device. However, two
capacitors are used (one at each end of the cable or PCB wiring) for an additional safety factor. In these
applications, the capacitor must be doubled from the typical requirement to maintain the required capacitance in
the signal path. Connect a minimum of 1 nF, with ±10% or better tolerance and the appropriate voltage rating for
the application. In noisy environments, 2 nF is recommended.
8.1.2.2.8 Unused Differential Communications Pins
Unused stack communications pins (COMMH+/–, COMML+/–, FAULTH+/–, FAULTL+/–) have internal
terminations; no external pull-up or pull-down resistors are required on these pins, if not used. If not used, leave
the unused pins unconnected. The COMMH drivers cannot be disabled.
8.1.3 ADC
8.1.3.1 Idle (Parking) Channel Errors
Between acquisition cycles, the multiplexer idles on the highest VSENSE channel enabled for conversion by the
CHANNELS register for sampling first on the next cycle.
Parking introduces a very small error to the idle channel due to the input impedance of the device causing a
small IR drop through the external resistor, which is part of the LP filter. The error is increased when using
VSENSE series resistors greater than 100 Ω. Setting the AFE_CTL bit = 1 in this application provides the
greatest error improvement. When AFE_PCTL is set, every time cell voltage sampling requests occur, cell
voltage sampling delays by 100 µs, regardless of the power status of the AFE. This maintains sampling
synchronization between multiple chips. Changes to this bit do not take effect until after the next AFE sample
occurs.
8.1.3.2 VSENSE Channel Post-Assembly Calibration Adjustment
Use of post-assembly calibration adjustment can improve device accuracy further after exposure to soldering
and/or bake cycles in the manufacturing process. ADC gain and offset-correction factors are programmable in
the bq76PL455A to allow for post-assembly calibration. The total range of adjustment limitation for both factors is
from –9.77 mV to 9.69 mV.
Application of these gain and offset corrections is global to all VSENSE channels. The AUX channels do not
receive these corrections. Application of the corrections is to the raw ADC values after application of the factorystored offset and gain corrections.
Perform the correction procedures at room temperature (RT) using a stable, high-accuracy DC source and / or
voltmeter. The registers contain signed 2's complement values. A zero value in either register indicates no
correction. Measurement of two voltage points, VIN1 and VIN2, occurs for each correction. The expected
minimum and maximum values for the cell can be used; however, ensure the lowest VINMIN value is greater than
or equal to 2.0 V and the highest VINMAXis less than or equal to 4.5 V.
For best results in most designs, both VIN1 and VIN2 use the average voltage measured by each channel
VSENSE1–16 after correcting for any errors in the stimulus (source) voltages at each input.
8.1.3.2.1 Gain Error Correction
Gain Error Correction: –9.77 mV to 9.69 mV in 255 steps (8 bits) in register VSGAIN
Procedure:
1. Apply voltage VIN1, read back from ADC VOUT1, and record both.
2. Apply voltage VIN2, read back from ADC VOUT2, and record both.
3. Calculate slope m = (VOUT2–VOUT1) / (VIN2–VIN1).
4. Find the gain error correction (GEC) at 5 V in 16-bit LSB (5 V is used regardless of VINx value).
102
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Application Information (continued)
ææ 1 ö ö
5
æ1
ö
= ç ç ÷ - 1÷ * 216
GEC = ç - 1÷ *
è m ø æ 5 ö èè m ø ø
ç 16 ÷
è2 ø
(14)
NOTE
The final GEC should be an 8-bit 2's-complement value in the range –128 to +127
after discarding the upper 8 bits of the 16-bit value. Values exceeding this are suspect
and probably indicate an error. If using such a value, saturate (–128 or +127) the
resulting 8-bit value and correct the sign as necessary.
This gain adjustment is input dependent—A correction of 9 mV at full-scale input,
results in a correction of 4.5 mV at half-scale input.
5. Write the 8-bit value to the VSGAIN register.
6. Perform the steps in Offset Error Correction.
8.1.3.2.2 Offset Error Correction
Offset Error Correction: –9.77 mV to 9.69 mV in 255 steps (8 bits) in register VSOFFSET
Procedure: (Use m, VIN1, and VOUT1 from the Gain Error Correction procedure.)
1. Find the offset error correction (OEC).
æ1ö
VIN1 - ç ÷ * VOUT1
æ
ö 216
æ1ö
èmø
OEC =
= ç VIN1 - ç ÷ * VOUT1÷ *
5
èmø
è
ø 5
216
(15)
NOTE
The final OEC should be an 8-bit 2's-complement value in the range –128 to +127 after
discarding the upper 8-bits of the 16-bit value. Values exceeding this are suspect and
probably indicate an error. If such a value must be used, the resulting 8-bit value should
be saturated (–128 or +127) and sign corrected as necessary.
2. Write the 8-bit value to the VSOFFSET register.
3. Save the new values to EEPROM by setting DEV_CTRL[WRITE_EEPROM], after setting the appropriate
values for MAGIC1 and MAGIC2. The EEPROM checksum will also require re-calculation and saving due to
this (or any) change.
8.1.3.3 AUX Channel Post-Assembly Calibration Adjustment
Using post-assembly calibration adjustment can also improve the AUX channel accuracy further after exposure
to soldering and/or bake cycles in the manufacturing process. The process is similar to the steps for the
VSENSE channel correction, with three differences:
• AUX channels only have offset correction, there is no gain correction.
• Each AUX channel has an individual offset correction register, rather than a single global correction.
• The correction range has an extension from –39.06 mV to 38.99 mV in 1023 steps (10 bits).
Perform the correction procedures at room temperature (RT) using a stable, high-accuracy DC source and / or
voltmeter. The registers contain 10-bit, signed, 2's-complement values. A zero value in any register indicates no
correction. Each correction measures two voltage points. The procedure can use the expected minimum and
maximum values for the cell. However, the lowest VINMIN value should be greater than or equal to 2.0 V and the
highest VINMAX should be less than or equal to 4.5 V.
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Application Information (continued)
Although the bq76PL455A does not provide AUX gain error correction, the host microcontroller can perform the
required correction using the slope value calculated as part of the GEC for the VSENSE channels. The
procedure can use the value stored in VSGAIN or a different value stored separately in one of the SCRATCH
registers of the bq76PL455A. If the procedure uses a value stored in the bq76PL455A, this permits the value to
follow the device in distributed systems. Optionally, the microcontroller memory can store the value. Because
gain error corrections are primarily correcting for VREF errors, a single-gain error correction for the AUX
channels is sufficient.
AUX Offset Error Correction: –39.06 mV to 38.99 mV in 1023 steps (10 bits) in registers AX0OFFSET through
AX7OFFSET, one 16-bit register per AUX input channel.
Procedure: (use m from the VSENSE Gain Error Correction procedure, or recalculate separately using any AUX
channel, as desired)
1. Apply voltage VINn, read back from ADC VOUTn, where 'n' is the AUX channel number. Record both values.
2. Find the AUX offset correction (AOC). This is the same formula used for the VSENSE offset correction
(OEC,) but a larger adjustment range is possible.
æ1ö
VINn - ç ÷ * VOUTn
æ
ö 216
æ1ö
èmø
AOCn =
= ç VINn - ç ÷ * VOUTn ÷ *
5
èmø
è
ø 5
(16)
216
NOTE
The final AOC should be a 10-bit 2's-complement value in the range –512 to +511 after
discarding the upper 6-bits of the 16-bit value. Values exceeding this are suspect and
probably indicate an error. If such a value must be used, the resulting 10-bit value should
be saturated (–512 or +511) and sign corrected as necessary.
3. Write the 10-bit value to the 16-b AXnOFFSET register, where n is the AUX channel number.
4. Repeat steps 1–3 for each AUX channel 0–7.
5. Save the new values to EEPROM by setting DEV_CTRL[WRITE_EEPROM], after setting the appropriate
values for MAGIC1 and MAGIC2. The EEPROM checksum will also require re-calculation and saving due to
this (or any) change.
8.1.4 Device Addressing
8.1.4.1 Using a Stored Address
As part of the reset process, the EEPROM restores the value in ADDR. If DEVCONFIG[ADDR_SEL] ==0, this
value is overridden by the value sampled from the GPIOs.
8.1.4.2 GPIO Addressing
When DEVCONFIG[ADDR_SEL] ==0, the device uses the address sampled from GPIO[4:0] to set ADDR. The
address is sampled as part of the reset process or by setting DEV_CTRL[AUTO_ADDRESS].
8.1.4.3 Auto Addressing
Prior to using the Auto-Addressing function in a stack, all devices must be awake and ready for communication.
The steps necessary for this state are detailed elsewhere in this document, but typically require a few
milliseconds per device.
Very simple stacks consisting of a single device may use address 0x00 (or any other valid address) for the
device. The first device in stacks of more than one device may also use Address 0x00.
104
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When DEVCONFIG[ADDR_SEL] ==1 and DEV_CTRL[AUTO_ADDRESS] ==1, then the device enters automatic
addressing mode. In this mode, the device turns off the high-side communications transmitters for one frame (so
the next frame received is not driven out the high-side differential interface) and enables writes to
ADDR[DEV_ADDR]. The expectation is that the next frame will set the address of the part. Normally, the address
is not writeable, so the device can use a Broadcast write transaction and will only affect the one part waiting for
an address. After receiving the frame, writes to ADDR[DEV_ADDR] are again disabled and the high-side
transmitter is re-enabled.
To auto-address the stack of bq76PL455A devices, the microcontroller should:
1. Broadcast write DEV_CTRL[AUTO_ADDRESS] = 1
2. Broadcast write consecutive addresses to ADDR[DEV_ADDR] until all parts have been assigned a valid
address.
Good practice dictates that all devices be checked by reading back their address registers, at a minimum, to
establish that the addressing functions worked properly. Subsequent reading and writing depend on correctly
addressed devices in the stack or executing any user-initiated tests, such as the checksum test.
8.1.5 Balancing
If the part is configured to disable balancing on a fault condition and any fault occurs while balancing is occurring
(CBCONFIG[BAL_CONTINUE] = 1 && CBENBL ≠ 0), there is a window approximately 2 µs where writes to the
part are blocked immediately after the fault occurs. If the user attempts a write in this window, the write will not
occur. In general, the user should verify that any commands have been properly processed.
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8.2 Typical Application
TOPCELL
R69
R49
VSENSE16
1 µF
R16
75
3
C8
R8
75
CELL8
1 µF
EQ16
2k
R70
100 k
Q8
60V
Z8
6.2 V
R96
1
1
2
Q16
60V
Z16
6.2 V
R88
2
CELL16
VSENSE8
100 :
C16
3
100 :
EQ8
2k
R57
100 k
R58
R76
VSENSE15
1 µF
R15
75
3
R7
75
CELL7
EQ15
2k
R22
100 k
R24
Q7
60V
C7
1 µF
Z7
6.2 V
R97
1
R89
1
2
Q15
60V
Z15
6.2 V
2
CELL15
VSENSE7
100 :
C15
3
100 :
EQ7
2k
R60
100 k
R61
VSENSE14
100 :
3
1 µF
R6
75
CELL6
EQ14
2
2k
R26
100 k
R27
Q6
60V
C6
1 µF
Z6
6.2 V
R98
1
R90
1
2
Q14
60V
Z14
6.2 V
3
R14
75
CELL14
VSENSE6
100 :
C14
EQ6
2k
R63
100 k
R64
VSENSE13
R13
75
1 µF
Z13
6.2 V
Q5
60V
Z5
6.2 V
R99
1
2
Q13
60V
EQ13
2k
R29
100 k
C5
1 µF
R5
75
CELL5
R91
1
2
VSENSE5
100 :
3
C13
3
CELL13
100 :
EQ5
2k
R66
100 k
R67
R30
VSENSE12
Z12
6.2 V
EQ12
2k
R32
100 k
R33
Q4
60V
C4
1 µF
R4
75
CELL4
Z4
6.2 V
R100
1
3
1
2
Q12
60V
1 µF
R92
2
R12
75
CELL12
VSENSE4
100 :
C12
3
100 :
EQ4
2k
R73
100 k
R74
VSENSE11
Z11
6.2 V
1 µF
R3
75
CELL3
3
3
1
2
Q11
60V
1 µF
C3
R93
EQ11
2k
R35
100 k
R36
Q3
60V
Z3
6.2 V
R101
1
R11
75
CELL11
VSENSE3
100 :
C11
2
100 :
EQ3
2k
R77
100 k
R79
VSENSE10
R10
75
1 µF
Z10
6.2 V
R2
75
CELL2
EQ10
2k
R45
100 k
R46
Q2
60V
C2
1 µF
Z2
6.2 V
R102
1
R94
2
1
2
Q10
60V
VSENSE2
100 :
3
C10
3
CELL10
100 :
EQ2
2k
R83
100 k
R84
VSENSE9
Z9
6.2 V
R95
EQ9
2k
R48
100 k
Q1
60V
C1
1 µF
R1
75
CELL1
3
3
1
2
Q9
60V
1 µF
Z1
6.2 V
R103
1
R9
75
CELL9
VSENSE1
100 :
C9
2
100 :
EQ1
2k
R86
100 k
R87
VSENSE0
100 :
BAT0
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Figure 35. Cell Connections
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D6
VSENSE15
VSENSE14
VSENSE13
VSENSE12
VSENSE11
VSENSE10
VSENSE9
VSENSE8
VSENSE7
VSENSE6
VSENSE5
VSENSE4
VSENSE3
VSENSE2
VSENSE1
VSENSE0
D4
C30
1 µF
FAULTH-
VIO
C29
0.1 µF
C28
1 µF
VM
V5VAO
C25
4.7 µF
D3
C20
1 µF
Z20
5V
VDIG
C31
0.1 µF
VSENSE16
VSENSE15
VSENSE14
VSENSE13
VSENSE12
VSENSE11
VSENSE10
VSENSE9
VSENSE8
VSENSE7
VSENSE6
VSENSE5
VSENSE4
VSENSE3
VSENSE2
VSENSE1
VSENSE0
C26
0.1 µF
C27
4.7 µF
VREF
GND
COMML+
COMMLFAULTL+
FAULTL-
AUX7
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
AUX0
C23
0.1µF
C24
1.8 µF
VIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
WAKEUP
FAULT_N
AGND1
AGND2
AGND3
AUX7
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
AUX0
C22
390 pF
DGND1
DGND2
DGND3
EQ16
EQ15
EQ14
EQ13
EQ12
EQ11
EQ10
EQ9
EQ8
EQ7
EQ6
EQ5
EQ4
EQ3
EQ2
EQ1
CHP
EQ16
EQ15
EQ14
EQ13
EQ12
EQ11
EQ10
EQ9
EQ8
EQ7
EQ6
EQ5
EQ4
EQ3
EQ2
EQ1
OUT1
OUT2
CHM
D5
R111
10 Ÿ
R106
1Ÿ
FAULTH+
NPNB
C19
0.1 F
VSENSE16
R110
10 Ÿ
C18
1 F
Q8
TOP
TOPCELL
C32
1000 pF
Z19
5V
COMMH-
C17
1 F
R120
100 Ÿ
R109
10 Ÿ
C34
1000 pF
Z18
5V
VP
R105
200 Ÿ
C33
1000 pF
C35
1000 pF
COMMH+
R104
T2
T1
R108
10 Ÿ
Z17
5V
200 Ÿ
FAULTL
on next device
ACT45B-101
Only needed when an
additional device is used in
daisy chain applications
COMML
on next device
ACT45B-101
Typical Application (continued)
RX
TX
Texas
Instruments
µC
C2000Œ
TMS570Œ
GPIO (Out)
GPIO (In)
TX
RX
CAN Bus, etc.
C21
0.022 µF
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Figure 36. Main Device
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Typical Application (continued)
Only needed when an
additional device is used in
daisy chain applications
T3
C27
1000 pF
D6
VSENSE0
FAULTH-
VDIG
C47
1 µF
VIO
C44
0.1 µF
C45
1 µF
VM
V5VAO
C43
0.1 µF
C41
4.7 µF
D8
C43
4.7 µF
VREF
GND
AUX7
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
AUX0
C33
0.022 µF
C39
0.1µF
C40
1.8 µF
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
WAKEUP
FAULT_N
Z28
5V
R121
10
COMML+
COMMLFAULTL+
FAULTL-
AUX7
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
AUX0
C38
390 pF
AGND1
AGND2
AGND3
EQ16
EQ15
EQ14
EQ13
EQ12
EQ11
EQ10
EQ9
EQ8
EQ7
EQ6
EQ5
EQ4
EQ3
EQ2
EQ1
CHP
EQ16
EQ15
EQ14
EQ13
EQ12
EQ11
EQ10
EQ9
EQ8
EQ7
EQ6
EQ5
EQ4
EQ3
EQ2
EQ1
OUT1
OUT2
DGND1
DGND2
DGND3
D7
C32
1 µF
R115
1Ÿ
C46
0.1 µF
VSENSE16
VSENSE15
VSENSE14
VSENSE13
VSENSE12
VSENSE11
VSENSE10
VSENSE9
VSENSE8
VSENSE7
VSENSE6
VSENSE5
VSENSE4
VSENSE3
VSENSE2
VSENSE1
VSENSE0
VSENSE15
VSENSE14
VSENSE13
VSENSE12
VSENSE11
VSENSE10
VSENSE9
VSENSE8
VSENSE7
VSENSE6
VSENSE5
VSENSE4
VSENSE3
VSENSE2
VSENSE1
CHM
D5
VSENSE16
FAULTH+
TOP
C21
0.1 F
Z24
5V
R114
1Ÿ
COMMH-
R120
100 Ÿ
C26
1 F
Q9
VP
C25
1 F
TOPCELL
R19
10 Ÿ
Z23
5V
COMMH+
R113
200 Ÿ
R17
10 Ÿ
C30
1000 pF
C34
1000 pF
R18
10 Ÿ
Z22
5V
NPNB
R112
200 Ÿ
T4
C29
1000 pF
R16
10 Ÿ
Z30
5V
FAULTL
on next device
ACT45B-101
ACT45B-101
COMML
on next device
Z27
5V
C34
1000 pF
RX
TX
R122
10
C35
1000 pF
COMMH Network
on Previous Device
Z26
5V
Z25
5V
R124
10
R123
10
C36
1000 pF
C37
1000 pF
FAULTH Network
on Previous Device
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Figure 37. Additional Device
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Typical Application (continued)
8.2.1 Design Requirements
In order to extract the best performance from the bq76PL455A, it is imperative to take care with the choice of
external components and the design of the PCB to which the device and the associated components are
mounted.
8.2.2 Detailed Design Procedure
The following sections have a more detailed discussion of design considerations that should be made.
8.2.2.1 Voltage Reference
A decoupling capacitor (sum of C60 and C39 in schematic in or ) of no greater than 2 µF, with minimum
temperature stability rating of X7R (COG/NPO provide better performance).
8.2.2.2 OUT1 Capacitor Selection
To determine the value of the OUT1 capacitor, use the averaging mode, sampling period, and averaging sample
interval.
8.2.2.2.1 For OVERSMPL[CMD_OVS_CYCLE] = 0
When OVERSMPL[CMD_OVS_CYCLE] = 0, each channel is sampled n times before proceeding to the next
channel. This bit only affects the VSENSE and AUX channels. The typical recommended OUT1 capacitor value
is 390 pF, type C0G/NP0 or better.
8.2.2.2.2 For OVERSMPL[CMD_OVS_CYCLE] = 1
When OVERSMPL[CMD_OVS_CYCLE] = 1, all channels are sampled in order, then the cycle repeats until the
number of additional oversamples has been taken. This bit only affects the VSENSE and AUX channels. For a
brief discussion of proper OUT1 capacitor selection and the default configuration, please see Out Filter Selection
section in bq76PL455EVM and GUI User's Guide (SLUUAT2).
8.2.2.3 Passive Cell Balancing Circuit
Figure 38 shows the balancing circuit for two cells in the stack. All cells require this circuit for passive balancing.
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Typical Application (continued)
R69
BAT16S_F
VSENSE16
100 Ÿ
2
3
C16
1 F
100 V
BAT0
1
Q16
60 V
R88
Z16
6.2 V
2
1
R16
75 Ÿ
EQ16
2 NŸ
R70
100 k
R76
BAT15_F
VSENSE15
Z15
6.2 V
2
3
C15
1 F
100 V
BAT0
2
R15
75 Ÿ
1
100 Ÿ
BAT14_F
1
R89
Q15
60 V
2 NŸ
EQ15
R22
100 NŸ
R24
VSENSE14
100 Ÿ
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Cell Balancing Circuit
8.2.2.4 Balance FET
Select the Balance FET (Q15 and Q16) based on the following criteria:
1. The VDS must be selected based on derating requirements determined by the stack voltage.
2. VGS must be as large as possible and preferably have ESD protection from gate to source. This protects the
part during hot plug.
3. The VGS threshold is of concern only if the discharge resistors are going to be turned on at low-battery
voltages.
The 2V7002K is recommended because of its 60 VDS, ± 20 VGS, and the gate is ESD protected with an internal
zener diode.
RDS value is of little consideration with the discharge currents for this application.
Power dissipation of the FET will be a function of discharge current selected and the resistance value of FET at
that worst-case condition, usually at hot temperature. I2R will be the power dissipated. Take care in selecting size
if using very small packages.
The VGS resistor (R77 and R85) ensures that the gate of the FET is turned off and does not float into a linear or
on state causing excessive leakage currents on that cell in case of FET failure or PCB open.
A series resistor between the EQ pin and the FET gate limits current going into the FET during hot plug or other
transient events.
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Typical Application (continued)
8.2.2.5 Balance Resistor
The balance resistor (R15 and R16) sets the required balance current. If used, the resistors in series with the cell
connections (top and bottom, in front of the zener diode) must be included in this calculation. These resistors
must be sized appropriately to handle the thermal dissipation of continuous cell balancing.
8.2.2.6 WAKEUP Pin
The WAKEUP pin input requires a pull-down to ensure it is not left unconnected and cause an unintended
wakeup (active high).
8.3 Initialization Set Up
8.3.1 Factory Configuration Summary
When the bq76PL455A leaves the factory, its EEPROM memory holds a configuration suitable for many
applications, but may need some adjustment for your design.
From the factory (see Register Summary):
1. The address is set to 0x00.
2. All digital and communications faults are enabled.
3. All analog faults (OV, UV) are disabled (masked).
4. Any fault that occurs and is not masked will control the FAULT_N and FAULTL± outputs.
5. Sampling is set for 8-sample averaging, 60 µs for the first sample, and 12.6 µs for the other samples (7).
This setup requires a 390-pF capacitor on pin OUT1.
6. All sixteen VSENSE inputs and no AUX channels are enabled for conversions.
7. No user-settable gain or offset corrections are applied to the VSENSE or AUX ADC channels – these allow
post-assembly or end-of-line corrections to ADC results.
8. The UART interface is enabled at 250 Kbaud.
9. GPIO pins are all programmed as inputs, no pull-up or pull-down resistor is enabled, leaving the inputs
floating. The pins should be reprogrammed to become outputs, or inputs with a pull-up/down enabled if none
are provided externally. The pins should not be allowed to remain as floating inputs, because unpredictable
operation is possible accompanied by excess current draw.
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Initialization Set Up (continued)
8.3.2 Device Setup/User Configuration Summary
An abbreviated version of starting up a stack of devices is described. Many more details are available in the
bq76PL455A-Q1 Software Design Reference (SLVA617), including validated communications sequences.
1. Set an address for each device in the stack, using GPIO pins or Auto-Addressing.
(a) Make sure all devices are awake and are ready to receive the Auto-Address Enable command.
(b) Turn on the downstream communications drivers on all devices in the chain.
(c) Place all devices into Auto-Address learn mode.
(d) Send out new addresses to all possible bq76PL455A device addresses, in incrementing order starting at
zero.
(e) Read back the value stored in the Device Address register from each newly addressed device, starting at
address zero and proceeding sequentially. The last bq76PL455A to respond successfully is the last
device in the serial chain. Steps d and e may be shortened if the range of possible devices is known in
advance. Limit the number addressed to the expected quantity.
(f) Turn off the high-side communications receiver on the last (top-most) device in the chain.
(g) Turn off the single-ended transmitter on all but the lowest device in the chain.
(h) Starting at the top of the stack of devices, clear all existing faults. It is important to start clearing faults
from the top of the stack to prevent faults from higher units from re-enabling faults as they propagate
down the stack.
2. Configure the AFE (Channel Selections and Fault Thresholds)
Prior to reading voltages from daisy-chain networked devices, the AFE on each of the stacked devices
should be properly configured to scan the desired channels at the desired timing. Once each device has
been properly configured, reading voltages from each device can begin.
The following listed steps should be performed as a group for each stacked device, starting from the top
device, continuing through, and ending with the bottom-most device of the stack. Generally, this configuration
is done in advance during factory initialization and test and the desired configuration parameters are stored
in EEPROM on each device.
(a) Configure GPIO pins as required by your design
(b) Configure the initial sampling delay
(c) Configure voltage and internal sample intervals/periods
(d) Configure the oversampling rate
(e) Select number of cells and desired channels to sample
(f) Set overvoltage and undervoltage thresholds
(g) Check and clear faults, which may have occurred because of the configuration.
3. Reading Voltages from Daisy-Chain Networked Devices
When bq76PL455A devices are networked, wherein each device monitors a section of a stack of cells, it is
important to try to capture the voltages of each sub-stack as synchronously as possible. This snapshot can
be obtained if all devices in the stack are sampling in parallel.
Summary of Steps for Reading Voltages from Daisy-Chain Networked Devices
Broadcast a Sample and Send command to all devices in the network: this causes all devices to start
sampling in parallel, and, once the sampling is complete, the devices will respond in sequence, starting
at the highest address with the sampled data. Alternatively, the following two-step process could be
employed to similar effect:
(a) Broadcast a trigger to all devices in the network to start sampling the selected cell and auxiliary channels
and temperature.
(b) Query each device individually in sequence for the data collected during the last snapshot read.
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9 Power Supply Recommendations
The bq76PL455A is powered from the same cells it monitors. The bq76PL455A generates the additional VP and
VDIG supplies used in operation from this input. For best performance, use the following guidelines for
component selection.
9.1 NPN LDO Supply
VP1 is the input for the external LDO supply for the bq76PL455A. Figure 39 shows the typical circuit.
BAT16
R163
2512
200
R164
2512
200
4
C40
1 µF
GND
Q17
ZXTN4004KTC
150 V
3
NPN_BASE
1
VP1
C36
4.7 µF
50 V
R78
1.00
VDIG
R23
0.39
R80
1.00
VIO
VP1
GND
Figure 39. Power Supply Schematic
Select the NPN Transistor based on the following criteria:
1. Collector-Emitter Breakdown Voltage (BVCEO) > 100 V (or the module voltage plus any derating)
2. DC gain (β or approximately equal to hfe (AC gain)) > 100 at the expected load current
3. Collector-base capacitance < 35 pF at typical base-voltage range
4. Power handling > 500 mW (this assumes a 1-kΩ resistance in series with the collector)
5. Current handling > 100 mA
The series resistors R163 and R164 in Figure 39 serve several purposes:
1. Limit the current in the event of a fault
2. Shift some constant power dissipation in the regulator away from the transistor onto the resistor
3. Combine with the input capacitor on the transistor collector to serve as a filter
To calculate the required resistance, use Equation 17:
where
•
•
•
VCE(SAT) = VCE min at VBE(on), from transistor datasheet.
31mA is the bq79PL455A maximum inrush current at startup.
ILOAD is the expected current for any non-bq76PL455A external loads applied to the VP pin.
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NPN LDO Supply (continued)
Allowing for the lowest possible module voltage (VBAT min) of 12 V, using VP max = 5.5 V, VCE_SAT = 0.25 V
(from transistor datasheet) and maximum load current (bq76PL455A IACTIVE max + any additional load connected
to VP) ≈7 mA, results in R max ≈1.464 kΩ.
The R78 and R80 series resistors in the VDIG and VIO supplies (respectively) isolate large load capacitance
from the voltage regulator to help with loop stability.
Connect a filter on the VP supply (R23 and C36) for stability. Use R23 = 390 mΩ and C36 = 4.7 µF.
9.1.1 External Supply
The bq76PL455A also supports using an external supply for VDIG and VIO. Connect the external supply to these
inputs and disable the internal regulator by setting REG_DISABLE = 1 in DEVCONFIG register (address 14).
9.1.2 Handling of Supplies in Shutdown Mode
If the NPN circuit is not used (external supply), VP and VDIG should be turned off immediately after entering
SHUTDOWN mode. Removing the VP and VDIG supplies places the device in SHUTDOWN mode.
While in SHUTDOWN mode, VIO and any other external supply indirectly connected to the communication, fault,
GPIO and AUX inputs must be turned off or disabled to avoid back powering the device through internal ESD
structures. The bq76PL455A immediately enters reset when VIO is removed.
9.1.3 AFE Output RC Filter
The bq76PL455A AFE output requires an RC-filter circuit comprised of a 1-kΩ series resistor (internal to the
device) and an external capacitor on OUT1 (C44). OUT1 and OUT2 must be connected together externally. The
simple first-order RC filter provides a limited amount of noise filtering before the signal is converted by the
integrated ADC. Each input channel is converted sequentially according to the channel conversion time. For
example: ADC_PERIOD_VOL, programmed in register 62, see Register Maps, and the OUT1 and OUT2 voltage
must change quickly and settle to the new measured channel value within this time. The RC filter, while reducing
noise, slows the settling speed of the OUT1 and OUT2 voltage to the ADC and must be selected as a tradeoff
between noise cancellation and accuracy degradation. Selecting too much capacitance prevents OUT1 from
settling to the required accuracy within the programmed-channel conversion period.
Ideally, to maximize measurement accuracy, the AFE output must settle to within < 1/2 of the ADC LSB. The
worst case condition is one where the AFE output has to move the full range that is possible in the system. For
example, when an extreme imbalance condition exists or if there is a broken cell sense connection, the swing
may exceed 4.2 V. In typical conditions, where cell-to-cell variation is within 100 mV, the AFE output does not
need the extreme settling time when the new channel is selected. Select the capacitor value based on the
maximum channel-to-channel voltage transition and the actual available settling time, which is dependent on the
conversion period of the programmed channel and oversampling mode, if oversampling is programmed.
A value of 390 pF provides best accuracy with a 60-µS ADC conversion period and 8× oversampling (on the
same channel before changing channels – CMD_OVS_CYCLE = 0).
For help in selecting C44 for other sampling periods and modes or when it is desired to sample a mixture of
channel types (for example: temperature, internal test voltages as well as external cells), please contact Texas
Instruments through your FAE.
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10 Layout
10.1 Layout Guidelines
Since the bq76PL455A measures small changes in voltage, care must be taken in the layout of signals to and
from the device to avoid coupling noise onto sensitive inputs. The layout of ground and power connections, as
well as communication signals should also be made carefully.
10.1.1 Grounding
The bq76PL455A has three analog ground pins: AGND1, AGND2, and AGND3. AGND1 is a general-purpose
analog ground associated with the integrated linear regulator controller VP, while AGND2 and AGND3 are quiet
analog grounds for the 2.5-V reference, ADC, AFE, and Secondary Protector (window comparators) circuitry. The
bq76PL455A device also has three DGND pins for the digital core and one CGND pin for the differential
communications I/Os.
Creation of a good ground plane in the layout is crucial to getting optimal performance from the part. A good
ground plane on a dedicated layer will improve measurement accuracy, reduce noise, and provide the necessary
ESD, EMI, and EMC performance. There is a strong recommendation to have a minimum of four layers in the
PCB, with one fully dedicated as an unbroken VSS plane (except thermal reliefs). Avoid placing tracks on this
layer to maintain the unbroken integrity of the plane structure.
All seven device grounds should connect to the ground plane with as short as possible track sections to minimize
the effects of stray inductance on noise performance.
If more than one bq76PL455A is included on a single PCB assembly, each will require its own plane in the area
surrounding the device. This is required because each device has its own VSS reference, often separated by
more than 60 V from VSS-to-VSS of adjacent ICs in the stack. These can exist on the same physical layer, with
correct separation to meet creepage and clearance requirements.
Although the plane is employed as a solid GND reference with all grounds connected to it, good layout practice
still requires locating any decoupling capacitors as close to the pin they are associated with as possible. This
reduces inductance and keeps the loop area as small as possible, which in turn keeps the capacitors as effective
as possible in reducing noise.
In this document, the reference term for combined grounds connected to the ground plane is ground or GND.
10.1.2 Differential Communications
The bq76PL455A uses two differential communications links to transmit signals between ICs in a stack.
Employing differential links provides superior noise immunity. The base device then translates the differential
signals back to a single-ended signal.
It is important to maintain the signal integrity of each differential pair to maximize immunity to interfering signals
from external sources.
1. Keep wires and PCB traces as short as possible. Do not exceed datasheet recommendations.
2. For any single-signal pair between two nodes (ICs), individual wires and traces should have the same length.
3. Unshielded, twisted-pair wiring is required for any cable runs.
4. Run PCB traces in parallel, on the same layer, without any other traces or planes in between. Long runs
should avoid noisy traces and/or be stitched at intervals similar to twisted-pair wire.
5. Use high-quality capacitors for voltage isolation between ICs and place in close physical proximity to each
other as part of the parallel-track layout.
10.2 Layout Example
To ensure the best possible accuracy performance, TI recommends to follow some basic layout guidelines for
the bq76PL455A to provide best EMI and BCI performance. The isolation caps must be placed close to the edge
of the board. The Common Mode Chokes must be close to the daisy-chain cable connector to provide a highimpedance path to common-mode noise as it enters the board. Place the series resistors and TVS diodes next to
the bq76PL455A.
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Layout Example (continued)
An unbroken ground plane layer as part of a four or more layer board is recommended, with all AGND, DGND,
and CGND connections made directly to the plane. The common GND planes are star connected directly to
BAT0. There should also be a keep-out area on plane area adjacent to the isolation capacitors if daisy-chain
communication is implemented. The following is a list of grounds.
• AGND1 – Power section (noisy GND)
• AGND2 – GND for Front end output
• AGND3 – GND for ADC input
• DGND1, DGND2, DGND3 – Digital GND
• CGND – Communications digital GND
Keep all signal Traces on
Top and Bottom Layers
Middle Layers
Isolation
Keepout
AGND1
AGND2
AGND3
COMML
COMML
COMML
DGND2
DGND1
DGND3
DGND2
COMMH
CGND
CGND
DGND1
COMMH
DGND3
AGND1
COMMH
AGND2
AGND3
GND
GND
BAT0
BAT0
Figure 40. Simplified Layout Guideline
10.3 Board Construction and Accuracy
The accuracy numbers provided in are based on the following board stack. Results may vary with board
thickness, layout, solder profile, and so forth.
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Board Construction and Accuracy (continued)
Figure 41. Board Stack for Board Level Accuracy Measurements
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
An evaluation module (EVM), with an associated PC-based Graphical User Interface (GUI) program, is available.
Please see Related Documentation for the reference numbers for the evaluation module and its associated
interface software.
11.1.2 Device-Specific Terminology
AFE
Analog front-end. A set of analog signal-conditioning circuitry that uses operational amplifiers and
filters to provide a configurable and flexible-electronics functional block, which is needed to
interface a variety of sensors to a microcontroller or an analog-to-digital converter.
Battery
A collection of series and parallel connected cells with a single set of high voltage (+) and (–)
outputs, which power the vehicle.
BIST
Built-in-Self-Test. A feature of the part allowing testing of critical and other blocks for correct
operation. Testing is user controlled and may include external components. Built-In Self Tests can
be used optionally as a diagnostic check of defined internal functions of the bq76PL455A-Q1.
BMS
Battery Monitor System (or battery management system), a system of bq76PL455A-Q1s connected
together and then to a microcontroller (µC) for measuring, monitoring, and controlling a stacked
series of cells forming a battery pack.
Cell
An individual cell or group of cells connected in parallel. Cells are connected to VSENSE inputs and
connected in series to form modules and stacks of cells to form a battery.
Daisy-Chain A series-connected string of monitoring devices, that is, bq76PL455A-Q1 devices communicating
to a base device by passing the communications signals through DC blocking devices and the
bq76PL455A-Q1 integrated circuits (ICs) in the string. In the case of the bq76PL455A-Q1, a
suitably rated capacitor is used as the DC block. A differential communications link is used to form
the daisy-chain of the bq76PL455A-Q1. “Daisy-chain” usually refers to just the communications
links, but is sometimes used to refer to the collection of devices and cells.
Differential-Signaling Differential signaling sends a digital signal and its complement simultaneously over a
pair of wires. The receiver is sensitive to the difference of the two signals, not the absolute
amplitude of either signal by itself. The wire pair is usually twisted so that any interfering signal
affects both equally as a common-mode signal. The result is that differential signaling offers much
higher common-mode rejection ratios (CMRR) than single-ended signals and results in much better
noise rejection.
LPF
Low Pass Filter made up of one or more R/C combinations where the resistor is in series with the
signal and the capacitor is on the load side and connected to “ground”. Each R/C element
contributes one time constant or tau.
Module
A collection of cells connected in series monitored by one bq76PL455A-Q1. This is typically 16
cells, but may be fewer as needed. Modules may be connected in series to form stacks and
complete battery packs. The bq76PL455A-Q1s are also typically connected in a series daisy-chain
to facilitate communications to a microcontroller.
Stack
A collection of modules of cells. Stack and battery are synonymous in most applications.
VCELL
The voltage from one cell or group of parallel connected cells, which is measured across two
VSENSE pins, for example, VSENSEn and VSENSEn-1.
VMODULE
The voltage from a collection of series connected cells forming a module. The voltage is measured
by the device from the TOP pin to GND.
VSTACK
The voltage from a collection of series connected cells forming a stack or battery pack. This is often
a high voltage. The voltage is not measured directly by the bq76PL455A-Q1, but may be calculated
by adding all of the individual cell voltages in the stack or by adding together all of the VMODULE
voltages in the stack. These should produce approximately the same value.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• bq76PL455A-Q1 Software Design Reference (SLVA617)
• bq76PL455EVM and GUI User Guide (SLUUBA7)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
• JEDEC Standard JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions - Natural
Convection (Still Air)
• JEDEC Standard JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages
• JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions - Junction-toBoard
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data are subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
For packaging and ordering information, please contact your TI representative.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: bq76PL455A
119
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ76PL455APFCR
ACTIVE
TQFP
PFC
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
76PL455APFC
BQ76PL455APFCT
ACTIVE
TQFP
PFC
80
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
76PL455APFC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF BQ76PL455A :
• Automotive: BQ76PL455A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ76PL455APFCR
TQFP
PFC
80
1000
330.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
BQ76PL455APFCT
TQFP
PFC
80
250
180.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ76PL455APFCR
TQFP
PFC
80
1000
367.0
367.0
45.0
BQ76PL455APFCT
TQFP
PFC
80
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996
PFC (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
0,08 M
41
61
40
80
21
1
0,13 NOM
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
0,25
14,20
SQ
13,80
0,05 MIN
0°– 7°
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4073177 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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