54LS169/DM54LS169A/DM74LS169A Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs all change at the same time when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four master-slave flip-flops on the rising edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset either high or low. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count-enable inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input. When the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up, and approximately equal to the low portion of the QA output when counting down. This low-level overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, up/ down), which modify the operating mode, have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Features Y Y Y Y Y Fully synchronous operation for counting and programming. Internal look-ahead for fast counting. Carry output for n-bit cascading. Fully independent clock circuit Alternate Military/Aerospace device (54LS169) is available. Contact a National Semiconductor Sales Office/Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6401 – 1 Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB, DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN See NS Package Number E20A, J16A, M16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6401 RRD-B30M105/Printed in U. S. A. 54LS169/DM54LS169A/DM74LS169A Synchronous 4-Bit Up/Down Binary Counter June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM54LS169A Parameter DM74LS169A Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 V 0.7 0.8 V mA VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b 0.4 b 0.4 IOL Low Level Output Current 4 8 mA fCLK Clock Frequency (Note 1) 0 25 MHz 0 20 MHz 2 2 0 25 20 Clock Frequency (Note 2) 0 tW Clock Pulse Width (Note 3) 25 25 tSU Setup Time (Note 3) Data 20 20 Enable T or P 20 20 Load 25 25 U/D 30 30 tH Hold Time (Note 3) TA Free Air Operating Temperature V ns ns 0 0 b 55 125 ns 0 70 §C Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: TA e 25§ C and VCC e 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 4) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.5 V VI Input Clamp Voltage VOH High Level Output Voltage VCC e Min, II e b18 mA VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 Input Current @ Max Input Voltage VCC e Max VI e 7V Enable T 0.2 Others 0.1 High Level Input Current VCC e Max VI e 2.7V Enable T 40 Others 20 Low Level Input Current VCC e Max VI e 0.4V Enable T b 0.8 Others b 0.4 Short Circuit Output Current VCC e Max (Note 5) DM54 b 20 b 100 DM74 b 20 b 100 Supply Current VCC e Max (Note 6) VOL II IIH IIL IOS ICC 20 V 0.4 34 Note 4: All typicals are at VCC e 5V and TA e 25§ C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: ICC is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs open. 2 V mA mA mA mA mA Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX Symbol Parameter From (Input) To (Output) CL e 15 pF Min Max CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Ripple Carry 35 39 ns tPHL Propagation Delay Time High to Low Level Output Clock to Ripple Carry 35 44 ns tPLH Propagation Delay Time Low to High Level Output Clock to Any Q 20 24 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q 23 32 ns tPLH Propagation Delay Time Low to High Level Output Enable T to Ripple Carry 18 24 ns tPHL Propagation Delay Time High to Low Level Output Enable T to Ripple Carry 18 28 ns tPLH Propagation Delay Time Low to High Level Output Up/Down to Ripple Carry (Note 1) 25 30 ns tPHL Propagation Delay Time High to Low Level Output Up/Down to Ripple Carry (Note 1) 29 38 ns 25 20 MHz Note 1: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase. 3 Logic Diagram LS169A Binary Counter TL/F/6401 – 2 4 Timing Diagram LS169A Binary Counters Typical Load, Count, and Inhibit Sequences TL/F/6401 – 3 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS169LMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS169DMQB or DM54LS169AJ NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS169AM NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS169AN NS Package Number N16E 7 54LS169/DM54LS169A/DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS169FMQB or DM54LS169AW NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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