Power APU3037MP 8-pin synchronous pwm controller Datasheet

Technology Licensed from International Rectifier
APU3037 / APU3037A
8-PIN SYNCHRONOUS PWM CONTROLLER
DESCRIPTION
FEATURES
Synchronous Controller in 8-Pin Package
Operating with single 5V or 12V supply voltage
Internal 200KHz Oscillator
(400KHz for APU3037A)
Soft-Start Function
Fixed Frequency Voltage Mode
500mA Peak Output Drive Capability
Protects the output when control FET is shorted
RoHS Compliant
The APU3037 controller IC is designed to provide a low
cost synchronous Buck regulator for on-board DC to DC
converter applications. With the migration of today’s ASIC
products requiring low supply voltages such as 1.8V and
lower, together with currents in excess of 3A, traditional
linear regulators are simply too lossy to be used when
input supply is 5V or even in some cases with 3.3V
input supply. The APU3037 together with dual N-channel
MOSFETs such as AP60T03, provide a low cost solution
for such applications. This device features an internal
200KHz oscillator (400KHz for "A" version), under-voltage lockout for both Vcc and Vc supplies, an external
programmable soft-start function as well as output under-voltage detection that latches off the device when an
output short is detected.
APPLICATIONS
DDR memory source sink Vtt application
Low cost on-board DC to DC such as 5V to 3.3V,
2.5V or 1.8V
Graphic Card
Hard Disk Drive
TYPICAL APPLICATION
5V
12V
C3
0.1uF
L1
C2
10TPB100M,
100uF, 55mV
C4
1uF
Vcc
SS/SD
C9
2200pF
C1
47uF
Vc
Q1
AP60T03GH
HDrv
C8
0.1uF
1uH
U1
APU3037
Comp
L2
1.5V/5A
1N4148
5.6uH, 5.3A
Q2
AP60T03GH
LDrv
C7
2x 6TPC150M,
150uF, 40mV
R3
Fb
249, 1%
Gnd
R4
24k
R5
1.24K, 1%
Figure 1 - Typical application of APU3037 or APU3037A.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
0 To 70
0 To 70
0 To 70
DEVICE
APU3037O
APU3037M/MP
APU3037AO
APU3037AM/AMP
Data and specifications subject to change without notice.
PACKAGE
FREQUENCY
8-Pin Plastic TSSOP (O)
200KHz
8-Pin Plastic SOIC NB (M/MP)
200KHz
8-Pin Plastic TSSOP (O)
400KHz
8-Pin Plastic SOIC NB (M/MP)
400KHz
200507075-1/18
APU3037 / APU3037A
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage ..................................................
Vc Supply Voltage ......................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
25V
30V (not rated for inductive load)
-65°C To 150°C
0°C To 125°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
8-PIN PLASTIC TSSOP (O)
Fb 1
8 SS/SD
Vcc 2
7 Comp
8-PIN PLASTIC SOIC (M/MP)
Fb 1
Vcc 2
8 SS/SD
7 Comp
LDrv 3
6 Vc
LDrv 3
6 Vc
Gnd 4
5 HDrv
Gnd 4
5 HDrv
θJA=124°C/W
θJA=160°C/W without exposed pad (M)
θJA=80°C/W with exposed pad (MP)
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Reference Voltage
Fb Voltage
Fb Voltage Line Regulation
UVLO
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - Vc
UVLO Hysteresis - Vc
UVLO Threshold - Fb
SYM
MIN
TYP
MAX
UNITS
APU3037
APU3037A
5<Vcc<12
1.225
0.784
1.250
0.800
0.2
1.275
0.816
0.35
V
%
UVLO Vcc Supply Ramping Up
4.0
4.4
UVLO Vc Supply Ramping Up
3.1
UVLO Fb Fb Ramping Down (APU3037)
0.4
0.3
4.2
0.25
3.3
0.2
0.6
0.4
0.1
V FB
LREG
TEST CONDITION
(APU3037A)
UVLO Hysteresis - Fb
Supply Current
Vcc Dynamic Supply Current
Vc Dynamic Supply Current
Vcc Static Supply Current
Vc Static Supply Current
Soft-Start Section
Charge Current
Dyn Icc
Dyn Ic
ICCQ
ICQ
SSIB
3.5
0.8
0.5
V
V
V
V
V
V
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
SS=0V
SS=0V
2
2
1
0.5
5
7
3.3
1
8
10
6
4.5
mA
mA
mA
mA
SS=0V
-10
-20
-30
mA
2/18
APU3037 / APU3037A
PARAMETER
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
Transconductance
Oscillator
Frequency
SYM
Ramp-Amplitude Voltage
Output Drivers
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
V RAMP
IFB1
IFB2
TEST CONDITION
Tr
Tf
APU3037
APU3037A
TON
MAX
UNITS
450
-0.1
-64
600
750
mA
mA
mmho
180
360
1.225
200
400
1.25
220
440
1.275
KHz
50
85
0
50
50
150
90
0
100
100
250
95
ns
ns
ns
%
%
CL=1500pF
CL=1500pF
TDB
TOFF
TYP
SS=3V, Fb=1V
SS=0V, Fb=1V
gm
Freq
MIN
Fb=1V, Freq=200KHz
Fb=1.5V
V
PIN DESCRIPTIONS
PIN#
1
PIN SYMBOL
PIN DESCRIPTION
Fb
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
2
Vcc
This pin provides biasing for the internal blocks of the IC as well as power for the low side
driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
3
LDrv
Output driver for the synchronous power MOSFET.
4
Gnd
This pin serves as the ground pin and must be connected directly to the ground plane. A
high frequency capacitor (0.1 to 1mF) must be connected from V5 and V12 pins to this pin
for noise free operation.
5
HDrv
Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,
from this pin to ground for the application when the inductor current goes negative (Source/
Sink), soft-start at no load and for the fast load transient from full load to no load.
6
Vc
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1mF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
7
Comp
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
8
SS / SD
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin below 0.5V.
3/18
APU3037 / APU3037A
BLOCK DIAGRAM
Vcc
3V
Bias
Generator
1.25V
0.2V
POR
4.0V
3V
0.2V
Vc
20uA
3.5V
6 Vc
64uA Max
SS/SD 8
Oscillator
5 HDrv
Ct
POR
S
1.25V
Q
Error Comp
25K
Error Amp
R
2 Vcc
Reset Dom
25K
Fb 1
3 LDrv
FbLo Comp
0.5V
4 Gnd
Comp 7
POR
Figure 2 - Simplified block diagram of the APU3037.
THEORY OF OPERATION
Introduction
The APU3037 is a fixed frequency, voltage mode synchronous controller and consists of a precision reference voltage, an error amplifier, an internal oscillator, a
PWM comparator, 0.5A peak gate driver, soft-start and
shutdown circuits (see Block Diagram).
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier; this is
the amplified error signal from the sensed output voltage
and the reference voltage.
This voltage is compared to a fixed frequency linear
sawtooth ramp and generates fixed frequency pulses of
variable duty-cycle, which drives the two N-channel external MOSFETs.The timing of the IC is provided through
an internal oscillator circuit which uses on-chip capacitor to set the oscillation frequency to 200 KHz (400 KHz
for “A” version).
Soft-Start
The APU3037 has a programmable soft-start to control
the output voltage rise and limit the current surge at the
start-up. To ensure correct start-up, the soft-start sequence initiates when the Vc and Vcc rise above their
threshold (3.3V and 4.2V respectively) and generates
the Power On Reset (POR) signal. Soft-start function
operates by sourcing an internal current to charge an
external capacitor to about 3V. Initially, the soft-start function clamps the E/A’s output of the PWM converter. As
the charging voltage of the external capacitor ramps up,
the PWM signals increase from zero to the point the
feedback loop takes control.
Short-Circuit Protection
The outputs are protected against the short-circuit. The
APU3037 protects the circuit for shorted output by sensing the output voltage (through the external resistor divider). The APU3037 shuts down the PWM signals, when
the Fb voltage drops below 0.6V (0.4V for APU3037A).
The APU3037 also protects the output from over-voltaging
when the control FET is shorted. This is done by turning
on the sync FET with the maximum duty cycle.
Under-Voltage Lockout
The under-voltage lockout circuit assures that the
MOSFET driver outputs remain in the off state whenever
the supply voltage drops below set parameters. Lockout
occurs if Vc and Vcc fall below 3.3V and 4.2V respectively. Normal operation resumes once Vc and Vcc rise
above the set values.
4/18
APU3037 / APU3037A
APPLICATION INFORMATION
Design Example:
The following example is a typical application for APU3037,
the schematic is Figure 18 on page 14.
VIN = 5V
VOUT = 3.3V
IOUT = 4A
DVOUT = 100mV
fS = 200KHz
tSTART = 753Css (ms)
(
R6
1+
R5
)
---(1)
When an external resistor divider is connected to the
output as shown in Figure 3.
VOUT
APU3037
R6
Fb
R5
Figure 3 - Typical application of the APU3037 for
programming the output voltage.
Equation (1) can be rewritten as:
R6 = R5 3
( VV
---(2)
Where:
CSS is the soft-start capacitor (mF)
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input
of the error amplifier, which is internally referenced to
1.25V (0.8V for APU3037A). The divider is ratioed to provide 1.25V at the Fb pin when the output is at its desired
value. The output voltage is defined by using the following equation:
VOUT = VREF 3
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft start capacitance value. The start up time of the
converter can be calculated by using:
OUT
REF
)
For a start-up time of 7.5ms, the soft-start capacitor will
be 0.1mF. Choose a ceramic capacitor at 0.1mF.
Shutdown
The converter can be shutdown by pulling the soft-start
pin below 0.5V. The control MOSFET turns off and the
synchronous MOSFET turns on during shutdown.
Boost Supply Vc
To drive the high-side switch it is necessary to supply a
gate voltage at least 4V greater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 18. The capacitor is charged up to
approximately twice the bus voltage. A capacitor in the
range of 0.1mF to 1mF is generally adequate for most
applications. In application, when a separate voltage
source is available the boost circuit can be avoided as
shown in Figure 1.
Input Capacitor Selection
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
larger capacitor, the less ripple expected but consider
should be taken for the higher surge current during the
power-up. The APU3037 provides the soft-start function
which controls and limits the current surge. The value of
the input capacitor can be calculated by the following
formula:
-1
Choose R5 = 1KV
This will result to R6 = 1.65KV
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage set point can be
more accurate by using precision resistor.
CIN =
IIN 3 Dt
DV
---(3)
Where:
CIN is the input capacitance (mF)
IIN is the input current (A)
Dt is the turn on time of the high-side switch (ms)
DV is the allowable peak to peak voltage ripple (V)
5/18
APU3037 / APU3037A
Assuming the following:
DV = 1%(V IN), Efficiency(h) = 90%
1
fS
VO 3 IO
IIN = h 3 VIN
Dt = D 3
Dt = 3.3ms
IIN = 2.93A
By using equation (3), CIN = 193.3mF
For higher efficiency, low ESR capacitor is recommended.
Choose two 100mF capacitors.
The Sanyo TPB series PosCap capacitor 100mF, 10V
with 55mV ESR is a good choice.
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is
calculated by the following relationship:
ESR [
DVO
DIO
---(4)
Where:
DVO = Output Voltage Ripple
DIO = Output Current
DVO=100mV and DIO=4A
Results to ESR=25mV
The Sanyo TPC series, PosCap capacitor is a good
choice. The 6TPC150M 150mF, 6.3V has an ESR 40mV.
Selecting two of these capacitors in parallel, results to
an ESR of ≅ 20mV which achieves our low ESR goal.
The capacitor value must be high enough to absorb the
inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage.
Inductor Selection
The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor
value causes large ripple current, resulting in the smaller
size, but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to
desired maximum ripple current in the inductor (∆i). The
optimum point is usually found between 20% and 50%
ripple of the output current.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the following relation:
Di
1
VOUT
; Dt = D3
;D=
Dt
fS
VIN
VOUT
L = (V IN - VOUT)3
---(5)
VIN3Di3fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
VIN - VOUT = L3
If Di = 20%(IO), then the output inductor will be:
L = 7mH
The Toko D124C series provides a range of inductors in
different values, low profile suitable for large currents,
10mH, 4.2A is a good choice for this application. This
will result to a ripple approximately 14% of output current.
Power MOSFET Selection
The APU3037 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is
based on maximum drain-source voltage (V DSS), gatesource drive voltage (V GS), maximum output current, Onresistance RDS(ON) and thermal management.
The MOSFET must have a maximum operating voltage
(V DSS) exceeding the maximum input voltage (V IN).
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET,
which results a shoot-through current.
The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter
the average inductor current is equal to the DC load current. The conduction loss is defined as:
2
PCOND (Upper Switch) = ILOAD 3 RDS(ON) 3 D 3 q
2
PCOND (Lower Switch) = ILOAD 3 RDS(ON) 3 (1 - D) 3 q
q = RDS(ON) Temperature Dependency
The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
6/18
APU3037 / APU3037A
For this design, AP60T03GH is a good choice. The
device provides low on-resistance in a TO-252
package.
These values are taken under a certain condition test.
For more detail please refer to the AP60T03GH data sheet.
By using equation (6), we can calculate the switching
losses.
The AP60T03GH has the following data:
PSW = 0.127W
VDSS = 30V
ID = 4.5A
RDS(ON) = 0.012V
The total conduction losses will be:
PCON(TOTAL)=P CON(Upper Switch)+PCON(Lower Switch)
2
PCON(TOTAL) = ILOAD 3 RDS(ON) 3 q
q = 1.5 according to the AP60T03GH data sheet for
1508C junction temperature
PCON(TOTAL) = 0.288W
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. With a
linear approximation, the total switching loss can be expressed as:
VDS(OFF)
tr + tf 3 ILOAD
PSW =
3
---(6)
2
T
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
Feedback Compensation
The APU3037 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 458).
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 1808 (see Figure 5). The Resonant frequency of the LC filter expressed as follows:
FLC =
1
2p3
---(7)
LO3CO
Figure 5 shows gain and phase of the LC filter. Since we
already have 1808 phase shift just from the output filter,
the system risks being unstable.
Gain
Phase
08
0dB
-40dB/decade
The switching time waveform is shown in figure 4.
VDS
90%
FLC Frequency
-1808
FLC
Frequency
Figure 5 - Gain and phase of LC filter.
10%
VGS
td(ON)
The APU3037’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
tr
td(OFF)
tf
Figure 4 - Switching time waveforms.
From AP60T03GH data sheet we obtain:
tr = 57.5ns
tf = 6.4ns
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback
the transconductance properties of the E/A become evident and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 6.
7/18
APU3037 / APU3037A
Note that this method requires that the output capacitor
should have enough ESR to satisfy stability requirements.
In general the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
The ESR zero of the output capacitor expressed as follows:
1
FESR =
---(8)
2p 3 ESR 3 Co
For:
VIN = 5V
VOSC = 1.25V
Fo = 30KHz
FESR = 26.52KHz
FLC = 2.9KHz
R5 = 1K
R6 = 1.65K
gm = 600mmho
VOUT
R6
Fb
E/A
R5
Comp
Ve
C9
VREF
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance
R4
This results to R4=104.4KV. Choose R4=105KV
Gain(dB)
H(s) dB
To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
FZ ≅ 75%FLC
FZ
Frequency
Figure 6 - Compensation network without local
feedback and its asymptotic gain plot.
The transfer function (Ve / VOUT) is given by:
(
H(s) = gm 3
R5
R6 + R5
) 3 1 +sCsR C
4
9
---(9)
9
FZ ≅ 0.75 3
1
2p
LO 3 CO
---(13)
For:
Lo = 10mH
Co = 300mF
FZ = 2.17KHz
R4 = 86.6KV
Using equations (11) and (13) to calculate C9, we get:
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
R5
|H(s)| = gm3
3 R4
---(10)
R63R5
FZ =
1
2p3R43C9
---(11)
The gain is determined by the voltage divider and E/A's
transconductance gain.
First select the desired zero-crossover frequency (Fo):
Fo > FESR and FO [ (1/5 ~ 1/10)3 fS
Use the following equation to calculate R4:
R4 =
1
VOSC Fo3FESR
R5 + R6
3
3
3 gm
VIN
FLC2
R5
C9 = 698pF
Choose C9 = 680pF
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to supress the switching noise. The additional pole
is given by:
1
FP =
C9 3 CPOLE
2p 3 R4 3
C9 + CPOLE
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
CPOLE =
---(12)
1
1
p3R43fS C9
fS
for FP <<
2
≅
1
p3R43fS
8/18
APU3037 / APU3037A
For a general solution for unconditionally stability for any
type of output capacitors, in a wide range of ESR values
we should implement local feedback with a compensation network. The typically used compensation network
for voltage-mode controller is shown in Figure 7.
VOUT
ZIN
R7
Zf
E/A
R5
Comp
Ve
VREF
Gain(dB)
1
2p3R83C10
1
(
)
C123C11
2p3R73
C12+C11
≅
1
2p3R73C12
1
2p3R73C11
1
1
FZ2 = 2p3C103(R6 + R8) ≅
2p3C103R6
Cross Over Frequency:
VIN
1
FO = R73C103
3
VOSC
2p3Lo3Co
---(15)
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
Figure 7 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
1 - gmZf
Ve
=
VOUT 1 + gmZIN
gmZIN >>1
and
---(14)
By replacing ZIN and Zf according to Figure 7, the transformer function can be expressed as:
1
3
sR6(C12+C11)
(1+sR7C11)3[1+sC10(R6+R8)]
C123C11
1+sR7
3(1+sR8C10)
C12+C11
[
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (14) regarding transconductance error amplifier.
1) Select the crossover frequency:
Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS
The error amplifier gain is independent of the transconductance under the following condition:
H(s)=
FP3 =
FZ1 =
C11
R6
Fb
gmZf >> 1
FP2 =
C12
C10
R8
FP1 = 0
(
)]
2) Select R7, so that R7 >>
3) Place first zero before LC’s resonant frequency pole.
FZ1 ≅ 75% FLC
1
C11 =
2p 3 FZ1 3 R7
4) Place third pole at the half of the switching frequency.
FP3 =
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the
necessary range.
2
gm
C12 =
fS
2
1
2p 3 R7 3 FP3
C12 > 50pF
If not, change R7 selection.
5) Place R7 in (15) and calculate C10:
The compensation network has three poles and two zeros and they are expressed as follows:
C10 [
2p 3 Lo 3 Fo 3 Co
VOSC
3
R7
VIN
9/18
APU3037 / APU3037A
6) Place second pole at the ESR zero.
FP2 = FESR
1
R8 =
2p 3 C10 3 FP2
Check if R8 >
1
gm
If R8 is too small, increase R7 and start from step 2.
7) Place second zero around the resonant frequency.
FZ2 = FLC
1
R6 =
- R8
2p 3 C10 3 FZ2
8) Use equation (1) to calculate R5.
R5 =
VREF
3 R6
VOUT - VREF
These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for
overall stability.
Start to place the power components, make all the connection in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
Figure 8 shows a suggested layout for the critical components, based on the schematic on page 14.
PGnd
PGnd
C1
C2A, B
L1
Vin
Vout
8
IC Quiescent Power Dissipation
Power dissipation for IC controller is a function of applied voltage, gate driver loads and switching frequency.
The IC's maximum power dissipation occurs when the
IC operating with single 12V supply voltage (Vcc=12V
and Vc≅24V) at 400KHz switching frequency and maximum gate loads.
7
6
5
L2
Q1
1
D D D C
3 2 1 5
2
3
5
4
C4 6
U1
3
APU3037
PGnd
Figures 9 and 10 show voltage vs. current, when the
gate drivers loaded with 470pF, 1150pF and 1540pF capacitors. The IC's power dissipation results to an excessive temperature rise. This should be considered when
using APU3037A for such application.
C7A, B
PGnd
R4 C9 7
2 C3
C8 8
R5
1 R6
4
Single Point
Analog Gnd
Connect to
Power Ground plane
Analog Gnd
Analog Gnd
Figure 8 - Suggested layout.
(Topside shown only)
Layout Consideration
The layout is very important when designing high frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
10/18
APU3037 / APU3037A
TYPICAL PERFORMANCE CHARACTERISTICS
APU3037A
Vcc vs. Icc
TA = 258C
Icc (mA)
@470PF, 1150PF and 1540PF Gate Load
14
12
10
8
6
4
2
0
CLOAD =1540pF
CLOAD =1150pF
CLOAD =470pF
0
2
4
6
8
10
12
14
Vcc (V)
Figure 9 - Vcc vs. Icc
APU3037A
Vc vs. Ic
TA = 258C
@470PF, 1150PF and 1540PF Gate Load
30
Ic (ma)
25
CLOAD =1540pF
20
CLOAD =1150pF
15
10
CLOAD =470pF
5
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
Vc (V)
Figure 10 - Vc vs. Ic
11/18
APU3037 / APU3037A
TYPICAL PERFORMANCE CHARACTERISTICS
APU3037
Output Voltage
APU3037
Output Frequency
1.3
240
230
1.28
Max
220
Max
210
Volts
Kilo Hertz
1.26
200
1.24
190
Min
Min
180
1.22
170
1.2
160
0°C
Output Voltage
+50°C
+100°C
Spec Max.
+150°C
-40°C
Spec Min.
0°C
+50°C
Oscillation Frequency
Figure 11 - Output Voltage
+100°C
Spec Max.
+150°C
Spec Min.
Figure 12 - Output Frequency
APU3037
Maximum Duty Cycle
92.0%
90.0%
88.0%
Percent Duty Cycle
-40°C
86.0%
84.0%
82.0%
80.0%
-40°C
-25°C
0°C
+25°C
+50°C
+75°C
+100°C +125°C
+150°C
Max Duty Cycle
Figure 13 - Maximum Duty Cycle
12/18
APU3037 / APU3037A
TYPICAL PERFORMANCE CHARACTERISTICS
APU3037A
Output Voltage
APU3037A
Output Frequency
820
460
Max
440
Max
810
420
800
Kilo Hertz
milli Volts
400
790
380
360
Min
Min
780
340
770
320
760
300
-40°C
-25°C
0°C
+25°C
Output Voltage
+50°C
+75°C
Spec Max.
+100°C
+150°C
-40°C
Spec Min.
-25°C
0°C
+25°C
Oscillation Frequency
+50°C
+75°C
Spec Max.
+100°C
+150°C
Spec Min.
Figure 14 - Output Voltage
Figure 15 - Output Frequency
APU3037 / APU3037A
Transconductance ( GM )
APU3037 / APU3037A
Rise Time / Fall Time
CL = 1500pF
1000
50
900
45
800
40
700
35
nano Seconds
micro Mho's
600
500
400
30
25
20
300
15
200
10
100
5
0
0
-40°C
-25°C
0°C
+25°C
Positive load GM
+50°C
+75°C
Negative load GM
Figure 16 - Transconductance
+100°C
-40°C
-25°C
0°C
+25°C
Rise Time
+50°C
+75°C
+100°C
Fall time
Figure 17 - Rise Time and Fall Time
13/18
APU3037 / APU3037A
TYPICAL APPLICATION
Single Supply 5V Input
5V
D1
1N4148
D3
1N4148
1uH
D2
1N4148
C3
0.1uF
C4
1uF
Vcc
L1
C2
2x 10TPB100ML,
100uF, 55mV
C5
0.1uF
Vc
Q1
AP60T03GH
HDrv
U1
APU3037
SS/SD
C8
0.1uF
C1
47uF
Tantalum
1N4148
L2
744311470 4.7uH
Q2
AP60T03GH
LDrv
3.3V
@ 4A
C7
2x 6TPC150M,
150uF, 40mV
R6
Comp
C9
680pF
Fb
1.65K, 1%
Gnd
R4
105K
R5
1K, 1%
Figure 18 - Typical application of APU3037 in an on-board DC-DC converter
using a single 5V supply.
14/18
APU3037 / APU3037A
TYPICAL APPLICATION
Dual Supply, 5V Bus and 12V Bias Input
5V
L1
12V
1uH
C4
0.1uF
C2
10TPB100M, 100uF,
55m V, 1.5A rms
C1
1uF
C1
47uF
1.8V/1A
APU1206-18
Q1
AP60T03GH
HDrv
C7
0.1uF
C8
2200pF
C3
47uF
Vc
Vcc
SS/SD U1
APU3037
1N4148
Q2
AP60T03GH
LDrv
2.5V/2A
L2
3.5uH @ 2.5A
C6
6TPB150M, 150uF, 55m V
R1
Comp
Fb
1K, 1%
R3
1K
1%
Gnd
R2
14K
L2
C6
3.5uH @ 2.5A
6TPB150M, 150uF, 55m V (Qty 2)
5.7uH @ 2.5A
6TPB150M, 150uF, 55m V (Qty 1)
C9
10TPB100M, 100uF,
55m V, 1.5A rms
C10
0.1uF
C11
1uF
Vc
Vcc
Q3
AP60T03GH
HDrv
U2
APU3037
SS/SD
C13
0.1uF
1N4148
Q4
AP60T03GH
LDrv
R5
14K
3.4uH @ 2A
C12
6TPB150M, 150uF, 55m V
R4
Comp
C14
2200pF
3.3V/1.8A
L3
Fb
1.65K, 1%
Gnd
R6
1K, 1%
Figure 19 - Typical application of APU3037 or APU3037A in an on-board DC-DC converter providing the Core,
GTL+, and Clock supplies for the Pentium II microprocessor.
15/18
APU3037 / APU3037A
TYPICAL APPLICATION
1.8V to 7.5V / 0.5A Boost Converter
L1
1uH
Vpwr (1.5V Min)
C1
2x 68uF
Vc/Vcc
C5
1uF
D1
1N5817
C9
2x 47uF
R1
20K
Q3
AP60T03GH
Q2
2N2222
R2
10K
Q1
2N2222
VO U T
(7.5V / 0.5A)
C10
100pF
C4
0.01uF
C5
0.1uF
R4
25K
SS/SD Comp Vc
HDrv
U1
APU3037
R3
20K
Fb
Vcc LDrv Gnd
C8
1uF
Gnd
R5
R6
1K, 1%
5K, 1%
Figure 20 - Typical application of APU3037 as a boost converter.
16/18
APU3037 / APU3037A
DEMO-BOARD APPLICATION
5V or 12V to 3.3V @ 10A
L1
VIN
5V or 12V
1uH
C2A
47uF
16V
D4
LL4148
C1
33uF
16V
D1
LL4148
C2B
47uF
16V
D2
Gnd
LL4148
C3
1uF
Vcc
C19
1uF
Vc
C8
1uF
Q1
AP60T03GH
HDrv
C6
0.1uF
L2
SS/SD
C5
0.1uF
U1
APU3037
1N4148
LDrv
VOUT
3.3V
@ 10A
3.2uH
Q2
AP60T03GH
C7
470pF
R4
4.7V
C9B
150uF
6.3V
C9C
150uF
6.3V
C13
1uF
Comp
Gnd
C4
2200pF
R6
Gnd
Fb
1.65K
R5
1K
R3
20K
Figure 21 - Demo-board application of APU3037.
Application Parts List
Ref Desig
Q1
Q2
U1
D1, D2, D4
L1
L2
C1
C2A, C2B
C9B, C9C
C5, C6
C3
C4
C7
C8, C13, C19
R3
R4
R5
R6
Description
MOSFET
MOSFET
Controller
Diode
Inductor
Inductor
Capacitor, Tantalum
Capacitor, Poscap
Capacitor, Poscap
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Resistor
Resistor
Resistor
Resistor
Value
Qty
Part#
30V, 12mV, 45A
1 AP60T03GH
30V, 12mV, 45A
1 AP60T03GH
Synchronous PWM 1 APU3037
Fast Switching
3 LL4148
1mH, 10A
1 7445601
3.2mH, 12A
1 7443550320
33mF, 16V
1 ECS-T1CD336R
47mF, 16V, 70mV
2 16TPB47M
150mF, 6.3V, 40mV 2 6TPC150M
0.1mF, Y5V, 25V
2 ECJ-2VF1E104Z
1mF, X7R, 25V
1 ECJ-3YB1E105K
2200pF, X7R, 50V
1 ECJ-2VB1H222K
470pF, X7R
1 ECJ-2VB2D471K
1mF, Y5V, 16V
3 ECJ-2VF1C105Z
20K, 5%
1
4.7V, 5%
1
1K, 1%
1
1.65K, 1%
1
Manuf
APEC
APEC
APEC
WE
WE
17/18
APU3037 / APU3037A
DEMO-BOARD WAVEFORMS
APU3037
V IN
VIN=5.0V, V OUT =3.3V
Efficiency (%)
100
90
V OUT
80
70
0
1
2
3
4
5
6
7
8
9
10
11
Output Current (A)
Figure 22 - Efficiency for APU3037 Evaluation Board.
Figure 23 - Start-up time @ IOUT=5A.
APU3037
Vss
APU3037
V OUT
IOUT = 5V
Figure 24 - Shutdown the output by
pulling down the soft-start.
APU3037
Figure 25 - 3.3V output voltage ripple @ IOUT=5A.
APU3037
2A
0A
Figure 26 - Transient response @ IOUT = 0 to 2A.
4A
0A
Figure 27 - Transient response @ IOUT = 0 to 4A.
18/18
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