LM611
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SNOSC08C – MAY 1998 – REVISED MARCH 2013
LM611 Operational Amplifier and Adjustable Reference
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FEATURES
1
OP AMP
2
•
•
•
•
•
•
•
•
•
•
•
Low Operating Current: 300 μA (op amp)
Wide Supply Voltage Range: 4V to 36V
Wide Common-Mode Range: V− to (V+−1.8V)
Wide Differential Input Voltage: ±36V
Available in Low Cost 8-pin DIP
Available in Plastic Package Rated for Military
Temperature Range Operation
REFERENCE
Adjustable Output Voltage: 1.2V to 6.3V
Tight Initial Tolerance Available: ±0.6%
Wide Operating Current Range: 17 μA to 20
mA
Reference Floats Above Ground
Tolerant of Load Capacitance
APPLICATIONS
•
•
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Transducer Bridge Driver
Process and Mass Flow Control Systems
Power Supply Voltage Monitor
Buffered Voltage References for A/D's
DESCRIPTION
The LM611 consists of a single-supply op-amp and a
programmable voltage reference in one space saving
8-pin package. The op-amp out-performs most singlesupply op-amps by providing higher speed and
bandwidth along with low supply current. This device
was specifically designed to lower cost and board
space requirements in transducer, test, measurement
and data acquisition systems.
Combining a stable voltage reference with a wide
output swing op-amp makes the LM611 ideal for
single supply transducers, signal conditioning and
bridge driving where large common-mode signals are
common. The voltage reference consists of a reliable
band-gap design that maintains low dynamic output
impedance (1Ω typical), excellent initial tolerance
(0.6%), and the ability to be programmed from 1.2V
to 6.3V via two external resistors. The voltage
reference is very stable even when driving large
capacitive loads, as are commonly encountered in
CMOS data acquisition systems.
As a member of TI's Super-Block family, the LM611
is a space-saving monolithic alternative to a multichip solution, offering a high level of integration
without sacrificing performance.
Connection Diagrams
Figure 1. Hermetic Dual-In-Line Package
Figure 2. Plastic Surface Mount Narrow Package
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LM611
SNOSC08C – MAY 1998 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Voltage on Any Pins Except VR (referred to V− pin)
36V (Max)
See (3)
−0.3V (Min)
Current through Any Input Pin and VR Pin
±20 mA
Differential Input Voltage
Military and Industrial
±36V
Commercial
±32V
−65°C≤TJ≤+150°C
Storage Temperature Range
Maximum Junction Temperature
150°C
Thermal Resistance, Junction-to-Ambient (4)
N Package
100°C/W
D Package
150°C/W
Soldering Information Soldering (10 seconds)
N Package
260°C
D Package
220°C
ESD Tolerance (5)
±1 kV
(1)
(2)
(3)
(4)
(5)
Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device beyond its rated operating conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
More accurately, it is excessive current flow, with resulting excess heating, that limits the voltages on all pins. When any pin is pulled a
diode drop below V−, a parasitic NPN transistor turns ON. No latch-up will occur as long as the current through that pin remains below
the Maximum Rating. Operation is undefined and unpredictable when any parasitic diode or transistor is conducting.
Junction temperature may be calculated using TJ = TA + PD θJA. The given thermal resistance is worst-case for packages in sockets in
still air. For packages soldered to copper-clad board with dissipation from one op amp or reference output transistor, nominal θJA is
90°C/W for the N package and 135°C/W for the D package.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Operating Temperature Range
−40°C≤TJ≤+85°C
LM611AI, LM611I, LM611BI
−55°C≤TJ≤+125°C
LM611AM, LM611M
0°C≤TJ≤70°C
LM611C
2
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Electrical Characteristics (1)
These specifications apply for V− = GND = 0V, V+ = 5V, VCM = VOUT = 2.5V, IR = 100 μA, FEEDBACK pin shorted to GND,
unless otherwise specified. Limits in standard typeface are for TJ = 25°C; limits in boldface type apply over the Operating
Temperature Range.
Symbol
Parameter
IS
Total Supply Current
VS
Supply Voltage Range
Conditions
Typical (2)
LM611AM
LM611AI
Limits (3)
LM611M
LM611BI
LM611I
LM611C
Limits (3)
Units
210
221
300
320
350
370
μA max
μA max
2.2
2.9
2.8
3
2.8
3
V min
V min
46
43
36
36
32
32
V max
V max
RLOAD = ∞,
4V ≤ V+ ≤ 36V (32V for LM611C)
OPERATIONAL AMPLIFIER
VOS1
VOS Over Supply
4V ≤ V+ ≤ 36V
(4V ≤ V+ ≤ 32V for LM611C)
1.5
2.0
3.5
6.0
5.0
7.0
mV max
mV max
VOS2
VOS Over VCM
VCM = 0V through VCM =
(V+ − 1.8V), V+ = 30V, V− = 0V
1.0
1.5
3.5
6.0
5.0
7.0
mV max
mV max
VOS3
ΔT
Average VOS Drift
See (3)
IB
Input Bias Current
10
11
25
30
35
40
nA max
nA max
IOS
Input Offset Current
0.2
0.3
4
5
4
5
nA max
nA max
IOS1
ΔT
Average Offset Drift
Current
RIN
Input Resistance
CIN
Input Capacitance
en
μV/°C
max
15
4
pA/°C
Differential
1800
MΩ
Common-Mode
3800
MΩ
Common-Mode
5.7
pF
Voltage Noise
f = 100 Hz,
Input Referred
74
nV/ √Hz
In
Current Noise
f = 100 Hz,
Input Referred
58
fA/√Hz
CMRR
Common-Mode
Rejection-Ratio
V+ = 30V, 0V ≤ VCM ≤ (V+ − 1.8V)
CMRR = 20 log (ΔVCM/ΔVOS)
95
90
80
75
75
70
dB min
dB min
PSRR
Power Supply
Rejection-Ratio
4V ≤ V+ ≤ 30V, VCM = V+/2,
PSRR = 20 log (ΔV+/ΔVOS)
110
100
80
75
75
70
dB min
dB min
AV
Open Loop
Voltage Gain
RL = 10 kΩ to GND, V+ = 30V,
5V ≤ VOUT ≤ 25V
500
50
100
40
94
40
V/mV
min
SR
Slew Rate
V+ = 30V (4)
0.70
0.65
0.55
0.45
0.50
0.45
V/μs
GBW
Gain Bandwidth
CL = 50 pF
0.80
0.50
MHz
VO1
Output Voltage
Swing High
RL = 10 kΩ to GND
V+ = 36V (32V for LM611C)
V+
+
− 1.4
V − 1.6
V+
+
− 1.7
V − 1.9
V+
+
− 1.8
V − 1.9
V min
V min
VO2
Output Voltage
Swing Low
RL = 10 kΩ to V+
V+ = 36V (32V for LM611C)
V− + 0.8
V− + 0.9
V− + 0.9
V− + 1.0
V− + 0.95
V− + 1.0
V max
V max
IOUT
Output Source
Current
VOUT = 2.5V, V+IN = 0V,
V−IN = −0.3V
25
15
20
13
16
13
mA min
mA min
(1)
(2)
(3)
(4)
Military RETS 611AMX electrical test specification is available on request. The LM611AMJ/883 can also be procured as a Standard
Military Drawing.
Typical values in standard typeface are for TJ = 25°C; values in boldface type apply for the full operating temperature range. These
values represent the most likely parametric norm.
All limits are specified at room temperature (standard type face) or at operating temperature extremes (bold face type).
Slew rate is measured with op amp in a voltage follower configuration. For rising slew rate, the input voltage is driven from 5V to 25V,
and the output voltage transition is sampled at 10V and 20V. For falling slew rate, the input voltage is driven from 25V to 5V, and output
voltage transition is sampled at 20V and 10V.
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Electrical Characteristics(1) (continued)
These specifications apply for V− = GND = 0V, V+ = 5V, VCM = VOUT = 2.5V, IR = 100 μA, FEEDBACK pin shorted to GND,
unless otherwise specified. Limits in standard typeface are for TJ = 25°C; limits in boldface type apply over the Operating
Temperature Range.
Symbol
Parameter
Conditions
Typical (2)
LM611AM
LM611AI
Limits (3)
LM611M
LM611BI
LM611I
LM611C
Limits (3)
Units
ISINK
Output Sink
Current
VOUT = 1.6V, V+IN = 0V,
V−IN = 0.3V
17
9
14
8
13
8
mA min
mA min
ISHORT
Short Circuit Current
VOUT = 0V, V+IN = 3V,
V−IN = 2V, Source
30
40
50
60
50
60
mA max
mA max
VOUT = 5V, V+IN = 2V,
V−IN = 3V, Sink
30
32
60
80
70
90
mA max
mA max
1.244
1.2365
1.2515
(±0.6%)
1.2191
1.2689
(±2.0%)
V min
V max
10
80
150
VOLTAGE REFERENCE
VR
Reference Voltage
See (5)
ΔVR
ΔTJ
Average Temperature
Drift
See (6)
ΔVR
ΔTJ
Hysteresis
Hyst = (Vro′ − Vro)/ΔTJ (7)
ΔVR
ΔIR
VR Change
with Current
VR(100 μA) − VR(17 μA)
0.05
0.1
1
1.1
1
1.1
mV max
mV max
VR(10 mA) − VR(100 μA) (8)
1.5
2.0
5
5.5
5
5.5
mV max
mV max
PPM/°C
max
μV/°C
3.2
R
Resistance
ΔVR(10→0.1 mA)/9.9 mA
ΔVR(100→17 μA)/83 μA
0.2
0.6
0.56
13
0.56
13
Ω max
Ω max
ΔVR
VRO
VR Change with
High VRO
VR(Vro = Vr) − VR(Vro = 6.3V)
(5.06V between Anode and
FEEDBACK)
2.5
2.8
7
10
7
10
mV max
mV max
ΔVR
ΔV+
VR Change with
V+ Change
VR(V+ = 5V) − VR(V+ = 36V)
(V+ = 32V for LM611C)
0.1
0.1
1.2
1.3
1.2
1.3
mV max
mV max
VR(V+ = 5V) − VR(V+ = 3V)
0.01
0.01
1
1.5
1
1.5
mV max
mV max
ΔVR
ΔVANODE
VR Change with
VANODE Change
V+ = V+ max, ΔVR = VR
(@ VANODE = V− = GND) − VR
(@ VANODE = V+ − 1.0V)
0.7
3.3
1.5
3.0
1.6
3.0
mV max
mV max
IFB
FEEDBACK Bias
Current
IFB; VANODE ≤ VFB ≤ 5.06V
22
29
35
40
50
55
nA max
nA max
en
VR Noise
10 Hz to 10,000 Hz, VRO = VR
30
(5)
(6)
(7)
(8)
4
μVRMS
VR is the cathode-feedback voltage, nominally 1.244V.
Average reference drift is calculated from the measurement of the reference voltage at 25°C and at the temperature extremes. The drift,
in ppm/°C, is 106•ΔVR/(VR[25°C]•ΔTJ), where ΔVR is the lowest value subtracted from the highest, VR[25°C] is the value at 25°C, and ΔTJ is
the temperature range. This parameter is ensured by design and sample testing.
Hysteresis is the change in VR caused by a change in TJ, after the reference has been “dehysterized”. To dehysterize the reference; that
is minimize the hysteresis to the typical value, its junction temperature should be cycled in the following pattern, spiraling in toward
25°C: 25°C, 85°C, −40°C, 70°C, 0°C, 25°C.
Low contact resistance is required for accurate measurement.
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Typical Performance Characteristics (Reference)
TJ = 25°C, FEEDBACK pin shorted to V− = 0V, unless otherwise noted
Reference Voltage vs Temp
on 5 Representative Units
Reference Voltage Drift
Figure 3.
Figure 4.
Accelerated Reference
Voltage Drift vs Time
Reference Voltage
vs Current and Temperature
Figure 5.
Figure 6.
Reference Voltage
vs Current and Temperature
Reference Voltage
vs Reference Current
Figure 7.
Figure 8.
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Typical Performance Characteristics (Reference) (continued)
TJ = 25°C, FEEDBACK pin shorted to V− = 0V, unless otherwise noted
6
Reference Voltage
vs Reference Current
Reference AC
Stability Range
Figure 9.
Figure 10.
Feedback Current
vs Feedback-to-Anode Voltage
Feedback Current
vs Feedback-to-Anode Voltage
Figure 11.
Figure 12.
Reference Noise Voltage
vs Frequency
Reference Small-Signal
Resistance vs Frequency
Figure 13.
Figure 14.
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Typical Performance Characteristics (Reference) (continued)
TJ = 25°C, FEEDBACK pin shorted to V− = 0V, unless otherwise noted
Reference Power-Up Time
Reference Voltage with
Feedback Voltage Step
Figure 15.
Figure 16.
Reference Voltage with
100∼
∼12 μA Current Step
Reference Step Response
for 100 μA ∼ 10 mA Current Step
Figure 17.
Figure 18.
Reference Voltage Change
with Supply Voltage Step
Figure 19.
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Typical Performance Characteristics (Op Amps)
+
−
V = 5V, V = GND = 0V, VCM = V+/2, VOUT = V+/2, TJ = 25°C, unless otherwise noted
8
Input Common-Mode Voltage Range
vsTemperature
VOS
vs Junction Temperature
Figure 20.
Figure 21.
Input Bias Current
vs Common-Mode Voltage
Reference Change
vs Common-Mode Voltage
Figure 22.
Figure 23.
Large-Signal
Step Response
Output Voltage Swing
vs Temp. and Current
Figure 24.
Figure 25.
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Typical Performance Characteristics (Op Amps) (continued)
+
−
V = 5V, V = GND = 0V, VCM = V+/2, VOUT = V+/2, TJ = 25°C, unless otherwise noted
Output Source Current
vs Output Voltage and Temp.
Output Sink Current
vs Output Voltage
Figure 26.
Figure 27.
Output Swing,
Large Signal
Output Impedance
vs Frequency and Gain
Figure 28.
Figure 29.
Small Signal Pulse Response
vs Temp.
Small-Signal Pulse Response
vs Load
Figure 30.
Figure 31.
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Typical Performance Characteristics (Op Amps) (continued)
+
−
V = 5V, V = GND = 0V, VCM = V+/2, VOUT = V+/2, TJ = 25°C, unless otherwise noted
10
Op Amp Voltage Noise
vs Frequency
Op Amp Current Noise
vs Frequency
Figure 32.
Figure 33.
Small-Signal Voltage Gain
vs Frequency and Temperature
Small-Signal Voltage Gain
vs Frequency and Load
Figure 34.
Figure 35.
Follower Small-Signal
Frequency Response
Common-Mode Input
Voltage Rejection Ratio
Figure 36.
Figure 37.
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Typical Performance Characteristics (Op Amps) (continued)
+
−
V = 5V, V = GND = 0V, VCM = V+/2, VOUT = V+/2, TJ = 25°C, unless otherwise noted
Power Supply Current
vs Power Supply Voltage
Positive Power Supply
Voltage Rejection Ratio
Figure 38.
Figure 39.
Negative Power Supply
Voltage Rejection Ratio
Slew Rate vs Temperature
Figure 40.
Figure 41.
Input Offset Current
vs Junction Temperature
Input Bias Current vs Junction Temperature
Figure 42.
Figure 43.
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Typical Performance Distributions
12
Average VOS Drift
Military Temperature Range
Average VOS Drift
Industrial Temperature Range
Figure 44.
Figure 45.
Average VOS Drift
Commercial Temperature Range
Average IOS Drift
Military Temperature Range
Figure 46.
Figure 47.
Average IOS Drift
Industrial Temperature Range
Average IOS Drift
Commercial Temperature Range
Figure 48.
Figure 49.
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Typical Performance Distributions (continued)
Voltage Reference Broad-Band
Noise Distribution
Op Amp Voltage
Noise Distribution
Figure 50.
Figure 51.
Op Amp Current
Noise Distribution
Figure 52.
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APPLICATION INFORMATION
VOLTAGE REFERENCE
Reference Biasing
The voltage reference is of a shunt regulator topology that models as a simple zener diode. With current Ir
flowing in the ‘forward' direction there is the familiar diode transfer function. Ir flowing in the reverse direction
forces the reference voltage to be developed from cathode to anode. The applied voltage to the cathode may
range from a diode drop below V− to the reference voltage or to the avalanche voltage of the parallel protection
diode, nominally 7V. A 6.3V reference with V+ = 3V is allowed.
Figure 53. Voltages Associated with Reference
(Current Source Ir is External)
The reference equivalent circuit reveals how Vr is held at the constant 1.2V by feedback, and how the
FEEDBACK pin passes little current.
To generate the required reverse current, typically a resistor is connected from a supply voltage higher than the
reference voltage. Varying that voltage, and so varying Ir, has small effect with the equivalent series resistance of
less than an ohm at the higher currents. Alternatively, an active current source, such as the LM134 series, may
generate Ir.
Figure 54. Reference Equivalent Circuit
Figure 55. 1.2V Reference
14
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Capacitors in parallel with the reference are allowed. See the Reference AC Stability Range curve for
capacitance values—from 20 μA to 3 mA any capacitor value is stable. With the reference's wide stability range
with resistive and capacitive loads, a wide range of RC filter values will perform noise filtering.
Adjustable Reference
The FEEDBACK pin allows the reference output voltage, Vro, to vary from 1.24V to 6.3V. The reference attempts
to hold Vr at 1.24V. If Vr is above 1.24V, the reference will conduct current from Cathode to Anode; FEEDBACK
current always remains low. If FEEDBACK is connected to Anode, then Vro = Vr = 1.24V. For higher voltages
FEEDBACK is held at a constant voltage above Anode—say 3.76V for Vro = 5V. Connecting a resistor across the
constant Vr generates a current I=R1/Vr flowing from Cathode into FEEDBACK node. A Thevenin equivalent
3.76V is generated from FEEDBACK to Anode with R2=3.76/I. Keep I greater than one thousand times larger
than FEEDBACK bias current for <0.1% error—I≥32 μA for the military grade over the military temperature range
(I≥5.5 μA for a 1% untrimmed error for a commercial part.)
Figure 56. Thevenin Equivalent of
Reference with 5V Output
R1 = Vr/I = 1.24/32μ = 39k
R2 = R1 {(Vro/Vr) − 1} = 39k {(5/1.24) − 1)} = 118k
Figure 57. Resistors R1 and R2 Program
Reference Output Voltage to be 5V
Understanding that Vr is fixed and that voltage sources, resistors, and capacitors may be tied to the FEEDBACK
pin, a range of Vr temperature coefficients may be synthesized.
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Figure 58. Output Voltage has Negative Temperature
Coefficient (TC) if R2 has Negative TC
Figure 59. Output Voltage has Positive TC
if R1 has Negative TC
Figure 60. Diode in Series with R1 Causes
Voltage Across R1 and R2 to be Proportional
to Absolute Temperature (PTAT)
Connecting a resistor across Cathode-to-FEEDBACK creates a 0 TC current source, but a range of TCs may be
synthesized.
16
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I = Vr/R1 = 1.24/R1
Figure 61. Current Source is Programmed by R1
Figure 62. Proportional-to-AbsoluteTemperature Current Source
Figure 63. Negative −TC Current Source
Hysteresis
The reference voltage depends, slightly, on the thermal history of the die. Competitive micro-power products
vary—always check the data sheet for any given device. Do not assume that no specification means no
hysteresis.
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OPERATIONAL AMPLIFIER
The amp or the reference may be biased in any way with no effect on the other, except when a substrate diode
conducts (see (1) under Electrical Characteristics). The amp may have inputs outside the common-mode range,
may be operated as a comparator, or have all terminals floating with no effect on the reference (tying inverting
input to output and non-inverting input to V− on unused amp is preferred). Choosing operating points that cause
oscillation, such as driving too large a capacitive load, is best avoided.
Op Amp Output Stage
The op amp, like the LM124 series, has a flexible and relatively wide-swing output stage. There are simple rules
to optimize output swing, reduce cross-over distortion, and optimize capacitive drive capability:
1. Output Swing: Unloaded, the 42 μA pull-down will bring the output within 300 mV of V− over the military
temperature range. If more than 42 μA is required, a resistor from output to V− will help. Swing across any
load may be improved slightly if the load can be tied to V+, at the cost of poorer sinking open-loop voltage
gain.
2. Cross-over Distortion: The LM611 has lower cross-over distortion (a 1 VBE deadband versus 3 VBE for the
LM124), and increased slew rate as shown in the Typical Performance Charactersitics curves. A resistor pullup or pull-down will force class-A operation with only the PNP or NPN output transistor conducting,
eliminating cross-over distortion.
3. Capacitive Drive: Limited by the output pole caused by the output resistance driving capacitive loads, a pulldown resistor conducting 1 mA or more reduces the output stage NPN re until the output resistance is that of
the current limit 25Ω. 200 pF may then be driven without oscillation.
Op Amp Input Stage
The lateral PNP input transistors, unlike those of most op amps, have BVEBO equal to the absolute maximum
supply voltage. Also, they have no diode clamps to the positive supply nor across the inputs. These features
make the inputs look like high impedances to input sources producing large differential and common-mode
voltages.
Typical Applications
*10k must be low
t.c. trim pot.
Figure 64. Ultra Low Noise 10.00V Reference.
Total Output Noise is Typically 14 μVRMS.
Adjust the 10k pot for 10.000V.
(1)
18
Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device beyond its rated operating conditions.
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Figure 65. Simple Low Quiescent Drain Voltage Regulator. Total Supply Current is approximately 320 μA
when VIN = 5V, and output has no load.
VOUT = (R1/R2 + 1) VREF.
R1, R2 should be 1% metal film.
R3 should be low t.c. trim pot.
Figure 66. Slow Rise-Time Upon Power-Up,
Adjustable Transducer Bridge Driver.
Rise-time is approximately 0.5 ms.
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Product Folder Links: LM611
19
LM611
SNOSC08C – MAY 1998 – REVISED MARCH 2013
www.ti.com
Figure 67. Low Drop-Out Voltage Regulator Circuit. Drop out voltage is typically 0.2V.
Figure 68. Nulling Bridge Detection System. Adjust sensitivity via 400 kΩ pot.
Null offset with R1, and bridge drive with the 10k pot.
20
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Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: LM611
LM611
www.ti.com
SNOSC08C – MAY 1998 – REVISED MARCH 2013
Simplified Schematic Diagrams
Figure 69. Op Amp
Figure 70. Reference
Figure 71. Bias
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Product Folder Links: LM611
21
LM611
SNOSC08C – MAY 1998 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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Product Folder Links: LM611
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM611CM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
0 to 70
LM611CM
LM611CMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
0 to 70
LM611CM
LM611IM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 85
LM611IM
LM611IMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM611IM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM611CMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM611IMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM611CMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LM611IMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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