EL5150, EL5151, EL5250, EL5251, EL5451 ® Data Sheet January 16, 2008 200MHz Amplifiers Features The EL5150, EL5151, EL5250, EL5251, and EL5451 are 200MHz bandwidth -3dB voltage mode feedback amplifiers with DC accuracy of 0.01%, 1mV offsets and 10kV/V open loop gains. These amplifiers are ideally suited for applications ranging from precision measurement instrumentation to high speed video and monitor applications. Capable of operating with as little as 1.4mA of current from a single supply ranging from 5V to 12V, dual supplies ranging from ±2.5V to ±5.0V, these amplifiers are also well suited for handheld, portable and battery-powered equipment. • 200MHz -3dB bandwidth FN7384.7 • 67V/µs slew rate • Very high open loop gains 50kV/V • Low supply current = 1.4mA • Single supplies from 5V to 12V • Dual supplies from ±2.5V to ±5V • Fast disable on the EL5150 and EL5250 • Low cost Single amplifiers are offered in SOT-23 packages and duals in a 10 Ld MSOP package for applications where board space is critical. Quad amplifiers are available in a 14 Ld SOIC package. Additionally, singles and duals are available in the industry-standard 8 Ld SOIC package. All parts operate over the industrial temperature range of -40°C to +85°C. • Pb-free available (RoHS compliant) Applications • Imaging • Instrumentation • Video • Communications devices Pinouts NC 1 IN- 2 IN+ 3 + VS- 4 8 CE OUT 1 7 VS+ VS- 2 6 OUT IN+ 3 INA+ 1 INB+ 5 OUT 1 5 CE VS- 2 4 IN- IN+ 3 5 VS+ + 4 IN- + - EL5451 (14 LD SOIC) TOP VIEW EL5251 (8 LD MSOP) TOP VIEW 10 INA- + VS- 3 CEB 4 + - 6 VS+ 5 NC EL5250 (10 LD MSOP) TOP VIEW CEA 2 EL5151 (5 LD SOT-23) TOP VIEW EL5150 (6 LD SOT-23) TOP VIEW EL5150 (8 LD SOIC) TOP VIEW OUTA 1 9 OUTA INA- 2 8 VS+ INA+ 3 7 OUTB 6 INB- VS- 4 8 VS+ + + OUTA 1 7 OUTB INA- 2 6 INB- INA+ 3 5 INB+ VS+ 4 - + + - OUTB 7 13 IND12 IND+ 11 VS- INB+ 5 INB- 6 1 14 OUTD 10 INC+ - + + - 9 INC8 OUTC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5150, EL5151, EL5250, EL5251, EL5451 Ordering Information PART MARKING PART NUMBER PACKAGE PKG. DWG. # EL5150IS 5150IS 8 Ld SOIC MDP0027 EL5150IS-T7* 5150IS 8 Ld SOIC (Tape and Reel) MDP0027 EL5150IS-T13* 5150IS 8 Ld SOIC (Tape and Reel) MDP0027 EL5150ISZ (Note) 5150ISZ 8 Ld SOIC (Pb-free) MDP0027 EL5150ISZ-T7* (Note) 5150ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 EL5150ISZ-T13* (Note) 5150ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 EL5150IW-T7* BEAA 6 Ld SOT-23 (Tape and Reel) MDP0038 EL5150IW-T7A* BEAA 6 Ld SOT-23 (Tape and Reel) MDP0038 EL5150IWZ-T7* (Note) BAAJ 6 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038 EL5150IWZ-T7A* (Note) BAAJ 6 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038 EL5151IW-T7* BFAA 5 Ld SOT-23 (Tape and Reel) MDP0038 EL5151IW-T7A* BFAA 5 Ld SOT-23 (Tape and Reel) MDP0038 EL5151IWZ-T7* (Note) BAAK 5 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038 EL5151IWZ-T7A* (Note) BAAK 5 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038 EL5250IY BAEAA 10 Ld MSOP MDP0043 EL5250IY-T7* BAEAA 10 Ld MSOP (Tape and Reel) MDP0043 EL5250IY-T13* BAEAA 10 Ld MSOP (Tape and Reel) MDP0043 EL5251IS 5251IS 8 Ld SOIC MDP0027 EL5251IS-T7* 5251IS 8 Ld SOIC (Tape and Reel) MDP0027 EL5251IS-T13* 5251IS 8 Ld SOIC (Tape and Reel) MDP0027 EL5251ISZ (Note) 5251ISZ 8 Ld SOIC (Pb-free) MDP0027 EL5251ISZ-T13* (Note) 5251ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 EL5251ISZ-T7* (Note) 5251ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 EL5251IY BAFAA 8 Ld MSOP MDP0043 EL5251IY-T7* BAFAA 8 Ld MSOP (Tape and Reel) MDP0043 EL5251IY-T13* BAFAA 8 Ld MSOP (Tape and Reel) MDP0043 EL5251IYZ (Note) BBBHA 8 Ld MSOP (Pb-free) MDP0043 EL5251IYZ-T13* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pb-free) MDP0043 EL5251IYZ-T7* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pb-free) MDP0043 EL5451IS 5451IS 14 Ld SOIC MDP0027 EL5451IS-T7* 5451IS 14 Ld SOIC (Tape and Reel) MDP0027 EL5451IS-T13* 5451IS 14 Ld SOIC (Tape and Reel) MDP0027 EL5451ISZ (Note) 5451ISZ 14 Ld SOIC (Pb-free) MDP0027 EL5451ISZ-T7* (Note) 5451ISZ 14 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 EL5451ISZ-T13* (Note) 5451ISZ 14 Ld SOIC (Tape and Reel) (Pb-free) MDP0027 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS and VS- . . . . . . . . . . . . . . . . . . . . 13.2V Slewrate of Voltage between VS and VS- . . . . . . . . . . . . . . . . 1V/µs Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VS + 0.5V Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C, unless otherwise specified. Electrical Specifications PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = +1, RL = 500Ω 200 MHz AV = +2, RL = 150Ω 40 MHz GBWP Gain Bandwidth Product AV = 500 40 MHz BW1 0.1dB Bandwidth AV = +1, RL = 500Ω 10 MHz SR Slew Rate VO = ±2.5V, AV = +2 67 V/µs VO = ±3.0V, AV = 1, RL = 500Ω 100 V/µs 80 ns 50 tS 0.1% Settling Time VOUT = -1V to +1V, AV = -2 dG Differential Gain Error (Note 1) AV = +2, RL = 150Ω 0.04 % dP Differential Phase Error (Note 1) AV = +2, RL = 150Ω 0.9 ° VN Input Referred Voltage Noise 12 nV/√Hz IN Input Referred Current Noise 1.0 pA/√Hz DC PERFORMANCE VOS Offset Voltage TCVOS Input Offset Voltage Temperature Coefficient AVOL Open Loop Gain -1 Measured from TMIN to TMAX 15 0.5 1 mV -2 µV/°C 56 kV/V INPUT CHARACTERISTICS CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio IB Guaranteed by CMRR test -3.5 +3.5 V 85 100 dB Input Bias Current -100 20 +100 nA IOS Input Offset Current -30 6 30 nA RIN Input Resistance 80 170 MΩ CIN Input Capacitance 1 pF OUTPUT CHARACTERISTICS VOUT IOUT Output Voltage Swing Low Output Current 3 RL = 150Ω to GND ±2.5 ±2.8 V RL = 500Ω to GND ±3.1 ±3.4 V RL = 10Ω to GND ±40 ±70 mA FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C, unless otherwise specified. (Continued) Electrical Specifications PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT ENABLE (SELECTED PACKAGES ONLY) tEN Enable Time EL5150 210 ns tDIS Disable Time EL5150 620 ns IIHCE CE Pin Input High Current CE = VS+ 1 5 25 µA IILCE CE Pin Input Low Current CE = VS+ - 5V -1 0 +1 µA VIHCE CE Input High Voltage for Powerdown Disable VILCE CE Input Low Voltage for Powerdown Enable ISON Supply Current - Enabled (per amplifier) No load, VIN = 0V, CE = +5V ISOFF+ VS+ - 1 V VS+ - 3 V SUPPLY 1.12 1.35 1.6 mA Supply Current - Disabled (per amplifier) -10 -1 +5 µA ISOFF- Supply Current - Disabled (per amplifier) No load, VIN = 0V -25 -14 0 µA PSRR Power Supply Rejection Ratio 80 110 DC, VS = ±3.0V to ±6.0V dB NOTE: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz, VOUT is swept from 0.8V to 3.4V, RL is DC-coupled. Typical Performance Curves 100 -45 60 45 40 90 20 0 1k 135 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 1. EL5150 FREQUENCY vs OPEN LOOP GAIN/PHASE 4 180 1G 90 PHASE (°) 0 PHASE (°) GAIN (dB) 80 180 AV = +1 RL= 500Ω RF = 0Ω 0 -90 AV = +2 RL = 150Ω RF = 400Ω -180 -270 100k 1M AV = +5 RL = 500Ω RF = 1.5kΩ 10M 100M 1G FREQUENCY (Hz) FIGURE 2. PHASE vs FREQUENCY FOR VARIOUS GAINS FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) 5 5 3 1 RL = 500Ω -1 RL = 200Ω RL = 300Ω -3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) AV = +1 CL= 5pF 3 VS = ±5V AV = +2 RF = RG = 402Ω 1 RL = 1kΩ -1 RL = 500Ω RL = 150Ω -3 RL = 100Ω -5 100k 1M 10M RL = 100Ω 100M -5 0.1 1G 1 FREQUENCY (Hz) 100 FREQUENCY (Hz) FIGURE 3. EL5150 GAIN vs FREQUENCY FOR VARIOUS RL FIGURE 4. EL5150 GAIN vs FREQUENCY FOR VARIOUS RL 4 5 AV = +5 RF = 1.5kΩ CL = 5pF 2 AV = +1 RL = 500Ω RL = 500Ω 0 RL = 400Ω -2 RL = 200Ω -4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10 CL = 15pF 3 CL = 8.2pF 1 CL = 3.9pF -1 CL = 0pF -3 RL = 100Ω -6 100k 1M 10M -5 100k 100M FREQUENCY (Hz) 100M 300M FIGURE 6. EL5150 GAIN vs FREQUENCY FOR VARIOUS CL 5 5 AV = +2 RL = 500Ω RF = RG = 400Ω CL = 68pF CL = 47pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10M FREQUENCY (Hz) FIGURE 5. EL5150 GAIN vs FREQUENCY FOR VARIOUS RL 3 1M CL = 22pF 1 -1 CL = 0pF -3 -5 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 7. EL5150 GAIN vs FREQUENCY FOR VARIOUS CL 5 AV = +5 RF = 1.5kΩ 3 RL = 500Ω CL = 82pF CL = 68pF 1 -1 CL = 47pF CL = 15pF -3 -5 100k CL = 0pF 1M 10M 30M FREQUENCY (Hz) FIGURE 8. EL5150 GAIN vs FREQUENCY FOR VARIOUS CL FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) 3 4 AV = +1 RL = 500Ω CL = 5pF CIN- = 18pF CIN- = 4.7pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 CIN- = 12pF CIN- = 8.2pF 1 CIN- = 3.3pF -1 CIN- = 0pF -3 CIN- = 1pF -5 100k 1M 100M 10M 2 AV = +2 RL = 500Ω CL = 5pF RF = RG = 400Ω 0 CIN = 8.2pF -2 CIN = 3.9pF CIN = 0pF -4 -6 100k 400M 1M FREQUENCY (Hz) 100M FIGURE 10. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN 4 4 AV = +5 RF = 1.5kΩ RL = 500Ω CL = 5pF CIN- = 100pF CIN- = 33pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10M FREQUENCY (Hz) FIGURE 9. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN- 2 CIN = 12pF CIN- = 68pF 0 CIN- = 8.2pF CIN- = 8pF -2 CIN- = 3.3pF CIN- = 0pF -4 2 AV = +5 RF = 1.5kΩ RL = 500Ω CL = 5pF 0 RL = 500Ω RL = 300Ω -2 RL = 200Ω -4 RL = 100Ω RL = 50Ω -6 100k 1M 10M -6 100k 40M 1M FREQUENCY (Hz) FIGURE 12. EL5250 GAIN vs FREQUENCY FOR VARIOUS RL 5 4 AV = +2 RL = 500Ω CL = 5pF RF = RG = 2kΩ 1 RF = RG = 1kΩ -1 RF = RG = 500Ω -3 -5 100k RL = 500Ω CL = 5pF RF = RG = 3kΩ NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 30M FREQUENCY (Hz) FIGURE 11. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN- 3 10M RF = RG = 100Ω 1M 10M 100M FREQUENCY (Hz) FIGURE 13. EL5150 GAIN vs FREQUENCY FOR VARIOUS RF/RG 6 2 AV = +1 0 AV = +2 -2 -4 -6 100k AV = +3 1M 10M 100M 300M FREQUENCY (Hz) FIGURE 14. EL5250 GAIN vs FREQUENCY FOR VARIOUS GAINS FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) 4 0 BOTH CHANNELS SHOWN AV = +1 POSITIVE SUPPLY 2 20 AV = +1 0 AV = +2 -2 PSRR (dB) NORMALIZED GAIN (dB) RL = 500Ω CL = 5pF 40 60 AV = +3 -4 80 -6 100k 1M 10M 100 1k 100M 10k FREQUENCY (Hz) 10M 100M FIGURE 16. PSRR vs FREQUENCY 0 -40 AV = +1 NEGATIVE SUPPLY -50 CROSSTALK (dB) 20 PSRR (dB) 1M FREQUENCY RESPONSE (Hz) FIGURE 15. EL5250 GAIN vs FREQUENCY FOR VARIOUS GAINS 40 60 80 AV = +2 RL = 500Ω CL = 5pF IN CHANNEL A OUT CHANNEL B -60 -70 -80 100 1k 10k 100k 1M 10M -90 100k 100M 1M FREQUENCY RESPONSE (Hz) 100M FIGURE 18. EL5250 CROSSTALK vs FREQUENCY 40 1.000k AV = +2 RL = 500Ω 50 CL = 5pF IN CHANNEL B OUT CHANNEL A AV = +2 IMPEDANCE (Ω) 100.000 60 70 80 90 100k 10M FREQUENCY (Hz) FIGURE 17. PSRR vs FREQUENCY CROSSTALK (dB) 100k 10.000 1.000 0.100 1M 10M 100M FREQUENCY (Hz) FIGURE 19. EL5250 CROSSTALK vs FREQUENCY 7 0.001 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 20. OUTPUT IMPEDANCE FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) 0 2500 NORMALIZED GROUP DELAY (500ps/DIV) AV = +2 CMRR (dB) 20 40 60 80 100 100 10k 1k 100k 10M 1M 1500 AV = +1 RL = 500Ω CL = 5pF 500 -500 -1500 -2500 1M 100M 10M FREQUENCY (Hz) FIGURE 22. GROUP DELAY 100.0 AV = +1 RL = 500Ω 2.5 C = 5pF L VOLTAGE NOISE (nV/√Hz) CURRENT NOISE (pA/√Hz) SUPPLY CURRENT (mA) 3.0 2.0 1.5 1.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10.0 1.0 0.1 100 5.0 10k 1k SUPPLY VOLTAGE (V) 100k FREQUENCY (Hz) FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. VOLTAGE + CURRENT NOISE vs FREQUENCY 105 90 80 100 70 3RD HD 60 2ND HD SLEW RATE (V/µs) DISTORTION (dBc) 600M FREQUENCY (Hz) FIGURE 21. CMRR 0 1.0 100M 50 40 30 AV = +1 RL = 500Ω 10 CL = 2.2pF FREQ = 1.9MHz 0 0 1 2 3 95 90 85 80 20 75 4 5 6 7 8 9 OUTPUT SWING (VP-P) FIGURE 25. DISTORTION vs OUTPUT AMPLITUDE 8 70 2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 SPLIT POWER SUPPLY (V) FIGURE 26. SLEW RATE vs POWER SUPPLY FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) -20 -30 -40 HARMONIC DISTORTION (dBc) AV = +5 VS = ±5V RL = 500Ω RF = 402Ω THD (dBc) THD_Fin = 2MHz -50 THD_Fin = 500kHz -60 -70 0 1 2 3 4 5 7 8 -30 2ND HD -50 3RD HD -60 -70 0.5 20%-80% CH3 RISE 1.874ns 80%-20% CH3 FALL 3.106ns 1.0 FIGURE 28. HARMONIC DISTORTION vs FREQUENCY AV = +1 RL = 500Ω CL = 2.2pF 20%-80% CH3 RISE 11.72ns TIME (40ns/DIV) AV = +2 RL =150Ω CL = 2.2pF 20%-80% CH3 RISE 4.337ns 80%-20% CH3 FALL 6.229ns TIME (40ns/DIV) FIGURE 31. SMALL SIGNAL STEP RESPONSE 9 80%-20% CH3 FALL 15.28ns TIME (40ns/DIV) FIGURE 30. LARGE SIGNAL STEP RESPONSE VOLTAGE (500mV/DIV) VOLTAGE (50mV/DIV) FIGURE 29. SMALL SIGNAL STEP RESPONSE 10.0 FUNDAMENTAL FREQUENCY (MHz) VOLTAGE (500mV/DIV) VOLTAGE (50mV/DIV) AV = +1 RL = 500Ω CL = 2.2pF THD -40 OUTPUT VOLTAGE (VP-P) FIGURE 27. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE AV = +5 VS = ±5V RL = 500Ω RF = 402Ω VOUT = 2VP-P AV = +2 RL = 150Ω CL = 2.2pF 20%-80% CH3 RISE 12.87ns 80%-20% CH3 FALL 15.67ns TIME (40ns/DIV) FIGURE 32. LARGE SIGNAL STEP RESPONSE FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves (Continued) AV = +1 RL = 500Ω RL = 500Ω SUPPLY = ±5.0V, ±2.7mA CH 1 CH 2 CH 4 210ns ENABLE 620ns DISABLE 800ns ENABLE TIME (400ns/DIV) TIME (1µs/DIV) 0.06 0.04 0.02 0 -0.02 -0.04 FIGURE 34. EL5250 ENABLE/DISABLE DIFFERENTIAL PHASE (°) DIFFERENTIAL GAIN (%) FIGURE 33. EL5150 ENABLE/DISABLE 0 1.5 1.0 0.5 0 -0.5 -1.0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 IRE IRE FIGURE 35. DIFFERENTIAL GAIN FIGURE 36. DIFFERENTIAL PHASE -50 AV = +1 RL = 500Ω CL = 5pF -70 0 ±2.0V -2 ±6.0V -4 -6 100k ISOSLATION (dB) NORMALIZED GAIN (dB) 4 2 520ns DISABLE AV = +1 RL = 500Ω CL = 2.7pF -90 -110 -130 10M 1M 100M 300M FREQUENCY (Hz) FIGURE 37. SMALL SIGNAL FREQUENCY vs SUPPLY 10 -150 100k 1M 10M 100M 300M FREQUENCY (Hz) FIGURE 38. INPUT-TO-OUTPUT ISOLATION WITH PART DISABLED FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 SO14 θJA = 88°C/W 1.0 909mW SO8 θJA = 110°C/W 0.8 870mW 0.6 435mW MSOP8/10 θJA = 115°C/W 0.4 SOT23-5/6 θJA = 230°C/W 0.2 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 833mW 1.2 1.136W POWER DISSPIATION (W) POWER DISSPIATION (W) 1.4 (Continued) 0.8 SO8 θJA = 160°C/W 0.4 MSOP8/10 θJA = 206°C/W 391mW 0.3 SOT23-5/6 θJA = 265°C/W 0.2 0.1 0 SO14 θJA = 120°C/W 0.7 625mW 0.6 486mW 0.5 0 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Product Description The EL5150, EL5151, EL5250, EL5251 and EL5451 are wide bandwidth, low power, low offset voltage feedback operational amplifiers capable of operating from a single or dual power supplies. This family of operational amplifiers are internally compensated for closed loop gain of +1 or greater. Connected in voltage follower mode, driving a 500Ω load members of this amplifier family demonstrate a -3dB bandwidth of about 200MHz. With the loading set to accommodate typical video application, 150Ω load and gain set to +2, bandwidth reduces to about 40MHz with a 67V/µs slew rate. Power down pins on the EL5151 and EL5251 reduce the already low power demands of this amplifier family to 12µA typical while the amplifier is disabled. Input, Output and Supply Voltage Range The EL5150 and family members have been designed to operate with supply voltage ranging from 5V to 12V. Supply voltages range from ±2.5V to ±5V for split supply operation. And of course split supply operation can easily be achieved using single supplies with by splitting off half of the single supply with a simple voltage divider as illustrated in the application circuit section. Input Common Mode Range These amplifiers have an input common mode voltage ranging from 3.5V above the negative supply (VS- pin) to 3.5V below the positive supply (VS+ pin). If the input signal is driven beyond this range the output signal will exhibit distortion. Maximum Output Swing & Load Resistance The outputs of the EL5150 and family members exhibit maximum output swing ranges from -4V to 4V for VS = ±5V with a load resistance of 500Ω. Naturally, as the load resistance becomes lower, the output swing lowers 11 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE accordingly; for instance, if the load resistor is 150Ω, the output swing ranges from -3.5V to 3.5V. This response is a simple application of Ohms law indicating a lower value resistance results in greater current demands of the amplifier. Additionally, the load resistance affects the frequency response of this family as well as all operational amplifiers; as clearly indicated by the Gain vs Frequency For Various RL curves clearly indicate. In the case of the frequency response reduced bandwidth with decreasing load resistance is a function of load resistance in conjunction with the output zero response of the amplifier. Choosing A Feedback Resistor A feedback resistor is required to achieve unity gain; simply short the output pin to the inverting input pin. Gains greater than +1 require a feedback and gain resistor to set the desired gain. This gets interesting because the feedback resistor forms a pole with the parasitic capacitance at the inverting input; as the feedback resistance increases the position of the pole shifts in the frequency domain, the amplifier's phase margin is reduced and the amplifier becomes less stable. Peaking in the frequency domain and ringing in the time domain are symptomatic of this shift in pole location. So we want to keep the feedback resistor as small as possible. You may want to use a large feedback resistor for some reason; in this case to compensate the shift of the pole and maintain stability a small capacitor in the few Pico farad range in parallel with the feedback resistor is recommended. For the gains greater than unity it has been determined a feedback resistance ranging from 500Ω to 750Ω provides optimal response. FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Gain Bandwidth Product The EL5150 and family members have a gain bandwidth product of 40MHz for a gain of +5. Bandwidth can be predicted by the following equation: (Gain) x (BW) = GainBandwidthProduct Video Performance For good video performance, an amplifier is required to maintain the same output impedance and same frequency response as DC levels are changed at the output; this characteristic is widely referred to as “diffgain-diffphase”. Many amplifiers have a difficult time with this especially while driving standard video loads of 150Ω, as the output current has a natural tendency to change with DC level. The dG and dP for these families is a respectable 0.04% and 0.9°, while driving 150Ω at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance as the current output demands placed on the amplifier lessen with increased load. Driving Capacitive Loads These devices can easily drive capacitive loads as demanding as 27pF in parallel with 500Ω while holding peaking to within 5dB of peaking at unity gain. Of course if less peaking is desired, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with the output to eliminate most peaking; however, there will be a small sacrifice of gain which can be recovered by simply adjusting the value of the gain resistor. Driving Cables Both ends of all cables must always be properly terminated; double termination is absolutely necessary for reflection-free performance. Additionally, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. ranging from 70mA and 95mA can be expected and naturally, if the output is shorted indefinitely the part can easily be damaged from overheating; or excessive current density may eventually compromise metal integrity. Maximum reliability is maintained if the output current is always held below ±40mA. This limit is set and limited by the design of the internal metal interconnect. Note that in transient applications, the part is extremely robust. Power Dissipation With the high output drive capability of these devices, it is possible to exceed the +125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA (EQ. 1) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: n PD MAX = V S × I SMAX + V OUTi ∑ ( VS – VOUTi ) × ---------------R Li (EQ. 2) i=1 For sinking: n PD MAX = V S × I SMAX + Disable/Power-Down ∑ ( VOUTi – VS ) × ILOADi (EQ. 3) i=1 Devices with disable can be disabled with their output placed in a high impedance state. The turn off time is about 330ns and the turn on time is about 130ns. When disabled, the amplifier's supply current is reduced to 17µA typically; essentially eliminating power consumption. The amplifier's power down is controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or the application of a signal that is less than 0.8V above VS- enables the amplifier. The amplifier is disabled when the signal at ENABLE pin is above VS+ - 1.5V. Output Drive Capability Members of the EL5150 family do not have internal short circuit protection circuitry. Typically, short circuit currents 12 Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current N = number of amplifiers (Max = 2) By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Power Supply Bypassing Printed Circuit Board Layout compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. Application Circuits Sallen Key Low Pass Filter A common and easy to implement filter taking advantage of the wide bandwidth, low offset and low power demands of the EL5150. A derivation of the transfer function is provided for convenience (see Figure 41). Sallen Key High Pass Filter Printed Circuit Board Layout Again, this useful filter benefits from the characteristics of the EL5150. The transfer function is very similar to the low pass so only the results are presented (see Figure 42). For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in K = 1+ 5V 1 V1 R2C2s + 1 Vo V1 − Vi Vo − Vi 1 + K − V1 + =0 1 R1 R2 C1s K H(s) = R1C1R2C2s 2 + ((1 − K )R1C1 + R1C2 + R21C2)s + 1 1 H( jw ) = 2 1 − w R1C1R2C2 + jw ((1 − K )R1C1 + R1C2 + R2C2) V2 Vo = K 0.1µF C1 R1 1k V1 1n R2 3 Holp = K U1A 4 + 1k 1 V+ C2 1n 2 VOUT R7 11 1k 1 wo = R1C1R2C2 V- - RB RA 1 Q= R1C1 R1C2 R2C2 (1 − K ) + + R2C2 R2C1 R1C1 1k RB RA 1k Holp = K 1 RC 1 Q= 3 −K wo = 0.1µF 5V Equations simplify if we let all components be equal R = C V3 FIGURE 41. SALLEN KEY LOW PASS FILTER 13 FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 5V V2 0.1µF R8 C7 1k C9 3 Holp = K U1A 4 1n 1 V+ 1n V1 C2 1n 2 R1C1R2C2 VOUT R7 11 1 Q= V- - 1 wo = + R1C1 R1C2 R2C2 (1 − K ) + + R2C2 R2C1 R1C1 1k 1k RB RA 1k Holp = K 4 −K 0.1µF 5V Q= V3 Equations simplify if we let all components be equal R = C 2 wo = RC 2 4 −K FIGURE 42. SALLEN KEY HIGH PASS FILTER Differential Output Instrumentation Amplifier The addition of a third amplifier to the conventional three amplifier Instrumentation Amplifier introduces the benefits of differential signal realization; specifically the advantage of using common mode rejection to remove coupled noise and ground –potential errors inherent in remote transmission. This configuration also provides enhanced bandwidth, wider output swing and faster slew rate than conventional three amplifier solutions with only the cost of an additional amplifier and few resistors. e1 A1 + - R3 R3 A3 R2 + RG R3 R3 R3 R3 A4 R2 A2 e2 + + R3 e o3 = – ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) eo3 + REF eo eo4 R3 e o4 = ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) e o = – 2 ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) 2f C1, 2 BW = -----------------A Di 14 A Di = – 2 ( 1 + 2R 2 ⁄ R G ) FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Strain Gauge The strain gauge is an ideal application to take advantage of the moderate bandwidth and high accuracy of the EL5150. The operation of the circuit is very straight-forward. As the strain variable component resistor in the balanced bridge is subjected to increasing strain, its resistance changes resulting in an imbalance in the bridge. A voltage variation from the referenced high accuracy source is generated and translated to the difference amplifier through the buffer stage. This voltage difference as a function of the strain is converted into an output voltage. 5V V2 0.1µF VARIABLE SUBJECT TO STRAIN 1k V5 0V R15 22 R15 1k 4 1k R14 22 4 R17 1k R18 3 U1A 4 + 1 V+ 2 VOUT (V1+V2+V3+V4) V- - RL 11 1k 1k 1k RF 0.1µF 5V V4 15 FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 16 FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 17 0.25 0° +3° -0° FN7384.7 January 16, 2008 EL5150, EL5151, EL5250, EL5251, EL5451 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7384.7 January 16, 2008