MC100EL13 5V ECL Dual 1:3 Fanout Buffer The MC100EL13 is a dual, fully differential 1:3 fanout buffer. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. www.onsemi.com Features • • • • • • • • • 500 ps Typical Propagation Delays 50 ps Output-Output Skews The 100 Series Contains Temperature Compensation PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or at VEE Internal Input Pulldown Resistors on All Inputs, Pullup Resistors on Inverted Inputs These Devices are Pb-Free, Halogen Free and are RoHS Compliant SOIC−20 WB DW SUFFIX CASE 751D−05 MARKING DIAGRAM* 20 100EL13 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Shipping† MC100EL13DWG SOIC−20 WB (Pb-Free) 38 Units/Tube MC100EL13DWR2G SOIC−20 WB (Pb-Free) 1000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 7 1 Publication Order Number: MC100EL13/D MC100EL13 Q1a Q1a Q2a 20 19 Q2a VCC Q2b Q2b Q1b Q1b VEE 17 16 15 14 13 12 11 18 1 2 Q0a Q0a 3 4 5 6 7 VCC CLKa CLKa CLKb CLKb 8 9 VCC Q0b Table 1. PIN DESCRIPTION PIN FUNCTION Qna, Qna ECL Differential Clock Outputs Qnb, Qnb ECL Differential Clock Outputs CLKn, CLKn ECL Differential Clock Inputs VCC Positive Supply VEE Negative Supply 10 Q0b * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: Assignment Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charge Device Model > 2 kV > 200 V > 4 kV Moisture Sensitivity (Note 1) Pb-Free Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 143 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 8 V −8 V 6 −6 V 50 100 mA ± 0.5 mA −40 to +85 °C VCC PECL Mode Power Supply VEE = 0 V VEE NECL Mode Power Supply VCC = 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−20 WB 90 60 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 30 to 35 °C/W Tsol Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC100EL13 Table 4. 100EL SERIES PECL DC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 30 38 Min 85°C Typ Max 30 38 Typ Max Unit 32 40 mA 3975 4050 4120 mV 3190 3295 3380 mV 3835 4120 mV 3525 3190 3525 mV 3.74 3.62 3.74 V IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3915 3995 4120 3975 4045 4120 VOL Output LOW Voltage (Note 2) 3170 3305 3445 3190 3295 3380 VIH Input HIGH Voltage (Single-Ended) 3835 4120 3835 4120 VIL Input LOW Voltage (Single-Ended) 3190 3525 3190 VBB Output Voltage Reference 3.62 3.74 3.62 VIHCMR Common Mode Range (Differential Configuration) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Min V 1.3 1.5 4.6 4.6 1.2 1.4 4.6 4.6 150 1.2 1.4 4.6 4.6 150 0.5 0.5 150 0.5 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 5. 100EL SERIES NECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 30 38 −1085 −1005 −880 −1830 −1695 −1555 Min 85°C Typ Max 30 38 −1025 −955 −880 −1810 −1705 −1620 Min Typ Max Unit 32 40 mA −1025 −955 −880 mV −1810 −1705 −1620 mV −1165 −880 mV −1810 −1475 mV −1.26 V IEE Power Supply Current VOH Output HIGH Voltage (Note 2) VOL Output LOW Voltage (Note 2) VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 VIHCMR Common Mode Range (Differential Configuration) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current V −3.7 −3.5 −0.4 −0.4 −3.8 −3.6 150 0.5 −0.4 −0.4 −3.8 −3.6 150 0.5 −0.4 −0.4 150 0.5 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 3 MC100EL13 Table 6. AC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max Min Typ Max Min TBD Typ Max Maximum Toggle Frequency tPLH tPHL Propagation Delay CLK→Q/Q tsk(O) Output-Output Skew Any Qa→Qa, Any Qb→Qb Any Qa→Any Qb 50 75 50 75 50 75 tsk(DC) Duty Cycle Skew |tPLH−tPHL| 50 50 50 tJITTER Cycle-to-Cycle Jitter VPP Input Swing (Note 2) 150 1000 150 1000 150 1000 mV Output Rise/Fall Times Q (20% − 80%) 230 500 230 500 230 500 ps 410 600 TBD Unit fmax tr tf TBD 85°C 430 TBD 620 450 TBD GHz 640 TBD ps ps ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. VEE can vary +0.8 V / −0.5 V. 2. VPPmin is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 4 MC100EL13 PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B S L A 18X e A1 SEATING PLANE c T MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ DIM A A1 b c D E e H h L q RECOMMENDED SOLDERING FOOTPRINT* 20X 20X 1.30 0.52 20 11 11.00 1 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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