Anpec APW7075KAC-TR Step-up converter and ldo combo Datasheet

APW7075
Step-Up Converter and LDO Combo
Features
General Description
•
Provided Dual Input Power Sources
The APW7075 is a PWM/PFM, high-efficiency and
step-up DC-DC converter with an integrated LDO input
switch for dual mode application. During battery mode
operation, the APW7075 acts as synchronous rectifier and step-up DC-DC converter with a fixed or ad-
Connect FB to OUT for 3.3V Output Voltage or
justable output voltage. When the VIN pin sense 5V
GND for 2.5V Output Voltage or an External
input voltage, the APW7075 is switched to LDO operation mode, maintaining the constant output voltage.
Built-In a 500mA LDO and Synchronous Step-Up
DC-DC Converter
•
•
•
Built-In PWM/PFM Operating Mode
Resistor Divider for Adjustable Output Voltage.
•
•
Fixed 300KHz Operating Frequency
The input voltage ranges from 0.6 V to 4.5V for stepup DC-DC converter. The start-up is guaranteed at1V
and the device is operating down to 0.6V. When the
device is at LDO operating mode, the suitable output
voltage 3.3V and loading current 500mA for maximum
power consumption are guaranteed.
High Efficiency Up to 94% at 200mA Output
Current
•
•
•
•
•
•
•
•
0.6V to 4.5V Operating Voltage
1V Start Up Input Voltage
Low Battery Voltage Detection
The APW7075 is suited for dual mode and portable
battery powered appliance with low-battery detector.
In dual-mode applications, the APW7075 draws power
from any available 5V USB connection and reverts to
battery power when the USB power is removed.
Reverse Voltage Protection
Internal Synchronous Rectifier
Automatic Detection Input Voltage
Compact SOP-8-P and TSSOP-8 Packages
Lead Free Available (RoHS Compliant)
Pin Description
Applications
TSSOP-8 Top View
•
•
•
•
•
Dual Mode Power System
USB Peripheral
Camcorders and Digital Camera
SOP-8-P Top View
VIN
1
8
OUT
FB
2
7
LX
SHDN
3
6
GND
LBI
4
5
LBO
LBI
VIN
1
8
FB
2
7
LX
SHDN
3
6
GND
4
5
LBO
OUT
Hand-held Instrument
= Thermal Pad
(connected to GND plane for better heat
dissipation)
PDAs
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
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APW7075
Ordering and Marking Information
Package Code
KA : SOP-8-P
O : TSSOP-8
Temp. Range
C : 0 to 70 °C
Handling Code
TU : Tube
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
APW7075
Lead Free Code
Handling Code
Temp. Range
Package Code
APW7075 KA :
APW7075
XXXXX
XXXXX - Date Code
APW7075 O :
APW7075
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Block Diagram
VIN
SHDN
Vref
VDD
VDD
FB
VDD
P-MOS
Current
Limit
Y
Q1
VDD
VOUT A
GND B
R1,R2 C
OUT
Vref
Q2
P-MOS
A
B
VDD
Y
PWM/
PFM
controller
C
phase
compensation
FB
GND
LX
Drive
Q3
Oscillator
N-MOS
voltage
reference
soft-start
Q4
LBI
Vref
2
LBO
N-MOS
SHDN
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APW7075
Absolute Maximum Ratings
Symbol
Value
Unit
Supply voltage(OUT to GND)
-0.3 to 6.0
V
VIO
Input / output pins
-0.3 to 6.0
V
TA
Operating Ambient Temperature Range
0 to 85
°C
TJ
Junction Temperature Range
0 to 150
°C
TSTG
Storage Temperature Range
-65 to +150
°C
300, 10 seconds
°C
Value
Unit
124
80
160
°C/W
VOUT
TS
Parameter
Soldering Temperature
Thermal Characteristics
Symbol
R θJA
Parameter
Thermal Resistance − Junction to Ambient
SOP-8
SOP-8-P
TSSOP-8
Electrical Characteristics
VBAT = 2V, FB = OUT (VOUT = 3.3V), RL = ∞, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.
Symbol
Parameter
Test Conditions
Step-up section
Minimum Operating Input
VBAT
Voltage (Note1)
Operating Voltage
APW7075
Min.
Typ.
Max.
0.6
Unit
V
0.6
4.5
V
1
V
Start-up Voltage
RL = 3KΩ
0.9
FSW
Operating Frequency
VOUT = 3.3VX96%
300
kHz
DMAX
Maximum PWM Duty Cycle
VOUT = 3.3VX96%
90
%
ILX = 100mA
0.3
0.6
Ω
ILX = 100mA
0.6
0.9
Ω
Power MOSFET
RDS(on)-N Active Switch ON Resistance
Synchronous Switch on
RDS(ON)-P
Resistance
Control
VOUT
Output Voltage
Output Voltage Range
FB = OUT, ILOAD = 0mA
3.234
3.3
3.366
V
FB = GND, ILOAD = 0mA
2.45
2.5
2.55
V
External divider
2.5
5.5
V
150
mV
VOUT(drop) VOUT Dropping Voltage (Note 2) VOUT = 3.3V, C OUT = 100µF
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
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APW7075
Electrical Characteristics (Cont.)
Unless otherwise noted these specifications apply over full temperature, 3.9V≤VIN<5.5V, C OUT≥10µF,
SHDN=VIN ,Typical values are at TA=+25°C.)
Symbol
Parameter
Test Conditions
APW7075
Min.
Unit
Typ.
Max.
30
100
ms
1.2
1.224
V
0.03
50
nA
TSS
Soft-start Time
VOUT = 3.3V
VREF
FB Input Threshold
ILOAD = 0mA
IFB
FB Input Current
VFB = 1.4V
IDD
Operating Current (Note3) VOUT = 3.3VX96%, ILOAD = 0mA
70
140
µA
Shutdown Current
VSHDN = 0
0.1
5
µA
SHDN Input Current
VSHDN = 0 or VOUT
0.07
50
nA
0.8
0.3
V
ISHDN
SHDN
1.176
Logic LOW (VIL)
Logic HIGH(VIH)
1.4
LBI Input Hysteresis
VLBI
LBI Threshold
0.588
ILBI
LBI Input Current
VLBI = 0.8V
VLBO
LBO Logic Low
VLBI = 0, ISINk = 1mA
ILBO
LBO Off Leakage Current VLBO = 5.5V, VLBI = 5.5V
0.8
V
10
mV
0.6
0.612
V
1
50
nA
0.2
0.4
V
0.07
1
µA
3.75
3.9
4.05
V
3.65
3.8
3.95
V
LDO Section (Note4)
VTH
Upper VIN Threshold
VIN increasing
Voltage
Lower VIN Threshold
VIN decreasing
Voltage
VIN Threshold Hysteresis
VOUT
Output Voltage
VIN(upper)
VIN(lower)
100
VOUT-2
VOUT
mV
VOUT+2
V
ILIM
Current Limit
VIN = 5V
1
A
ISHORT
Short Current
VOUT = 0V
110
mA
IOUT
Load Current
VDROP
Iq
Dropout Voltage
Quiescent Current
500
mA
ILOAD = 500mA
0.6
0.9
V
No load
800
1000
uA
ILOAD = 500mA
1.1
1.5
mA
REGLINE Line Regulation
4V<VIN<5.5V, ILOAD = 0mA
4
10
mV
REGLOAD Load Regulation
VIN = 5V, 0mA<ILOAD<500mA
20
30
mV
Note1: The min. operating voltage is dependent on the duty cycle.
Note2: The dropped output voltage is that the input power (VIN pin) is switched to battery power (LX pin),
when the VIN power is removed.
Note3: Device is boostrapped ( power to the IC comes from OUT). This correlates directly with the actual
battery supply.
Note4: If the LDO mode is used, the output voltage should be under 3.8V.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
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APW7075
Pin Function Description
VIN (Pin 1)
LBO (pin 5)
Input supply voltage for dual-mode application. Connect a schokkty diode (current rating >500mA) to USB
port or 5V adapter. If the LDO mode is not used, tie
the VIN pin to ground.
Open-drain low battery comparator output. Connect
as VLBI < 0.6V. Open-drain device is turned on during
shutdown.
FB (pin 2)
OUT (pin 8)
Internal 1.2V reference voltage. Connect to OUT for 3.
3V output,. Connect to GND for 2.5V output. Use a
resistor divider to set the output voltage from 2.5V to
5.5V.
Power output. OUT provides bootstrap power to the
IC.
LBO to OUT through a 100KΩ resistor. Output is low
GND (Pin 6)
SHDN (pin 3)
Ground pins of the circuitry and all ground pins must
be soldered to PCB with proper power dissipation.
Shutdown input. High = operating mode; Low = shutdown mode.
LX (pin 7)
LBI (Pin 4)
N-channel and P-channel power MOSFET drain
connection.
Low-battery comparator input. Internally set to trip at
0.6V.
Application Schematic
VBAT
L1
22UH
C1
10uF
1N5817
Adapter C3
5V 10uF
VOUT 3.3V
R6
1
8
VIN
OUT
2
7
FB
ON
3
R3
C2
100uF
6
SHDN
GND
LBI
LBO
4
OFF
C4
1uF
LX
5
R5
100kΩ
APW7075
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 1. Dual Model : 3.3V Output Voltage
Copyright  ANPEC Electronics Corp.
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APW7075
Application Schematic (Cont.)
VBAT
L1
22UH
C1
10uF
1N5817
Adapter
C3
5V 10uF
VOUT 2.5V
R6
1
8
VIN
2
ON
3
OUT
7
FB
C2
100uF
6
SHDN
GND
LBI
LBO
4
OFF
C4
1uF
LX
5
R5
R3
100kΩ
APW7075
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 2. Dual Model : 2.5V Output Voltage
VBAT
L1
22UH
C1
10uF
1N5817
2.5V ≦ VOUT ≦ 3.8V
Adapter C3
5V 10uF
R6
VOUT 3.6V
R1
300kΩ
1
2
ON
3
8
VIN
OUT
7
FB
C2
100uF
6
SHDN
GND
LBI
LBO
4
OFF
C4
1uF
LX
5
R5
100kΩ
R2
APW7075
150kΩ
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 3. Dual Model: Adjustable Output Voltage
Copyright  ANPEC Electronics Corp.
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APW7075
Application Schematic (Cont.)
0.6V ≦
VBAT ≦ 4.5V
VBAT
L1
22UH
C1
10uF
2.5V ≦
VOUT ≦ 5V
VOUT
R1
3.6V
300kΩ
1
2
ON
3
8
VIN
OUT
FB
LX
SHDN
GND
LBI
LBO
4
OFF
7
C4
1uF
C2
100uF
6
5
R3
100kΩ
R2
150kΩ
APW7075
Low Battery Output
R4
Figure 4. Single Boost Converter
Typical Characteristics
Power Up (VBATTERY=2.4V)
Power Up (VBATTERY=1.2V)
IOUT=100mA
IOUT=100mA
VBAT(1V/div)
VBAT(1V/div)
VOUT(1V/div)
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
Time(10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
Time(10ms/div)
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APW7075
Typical Characteristics (Cont.)
Power Down
Enable
IOUT=100mA
IOUT=100mA
SHDN(1V/div)
VBAT(2V/div)
VOUT(1V/div)
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
Time(5ms/div)
Time(10ms/div)
Shutdown
Heavy Load Operating Waveforms
IOUT=100mA
SHDN(1V/div)
IL(200mA/div)
IOUT=100mA, VOUT=3.3V
VBAT=2.4V, CBAT=10µF
COUT=100µF, L=22µH
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
LOUT(100mV/div)
Time(1ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
Time(1us/div)
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APW7075
Typical Characteristics (Cont.)
Output Current vs. Start-up Voltage
Light Load Operating Waveforms
1.4
Start-up Voltage(V)
1.2
IL(200mA/div)
IOUT=30mA, VOUT=3.3V
VBAT=2.4V, CBAT=10µF
COUT=100µF, L=22µH
LX(2V/div)
1
0.8
0.6
0.4
0.2
0
LOUT(100mV/div)
0.1
1
Effciency vs. Output Current
Effciency vs. Output Current
100
100
VIN=2.4V
90
80
80
70
Effciency(%)
Effciency(%)
100
Output Current(mA)
Time(5us/div)
90
10
VIN=1.2V
60
50
40
VOUT=2.5V, L=22µH
VIN=1.2V
60
50
40
30
30
20
VOUT=3.3V, L=22µH
20
10
10
0
0.01
70
0.1
1
10
100
0
0.01
1000
Rev. A.5 - Aug., 2005
1
10
100
1000
Output Current(mA)
Output Current(mA)
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0.1
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APW7075
Typical Characteristics (Cont.)
Efficiency vs. Output Current
Efficiency vs. Output Current
100
100
90
80
80
70
70
60
Efficiency(%)
Efficiency(%)
90
VIN=2.4V
VIN=1.2V
50
40
30
VOUT=3.3V, L=10µH
20
50
40
30
20
10
10
0
0.01
0.1
1
10
100
0
0.01
1000
0.1
1
10
100
1000
Output Current(mA)
Output Current(mA)
Maximum Output Current vs.Input Voltage
Operating Curretnt into OUT vs. Output Voltage
0.5
Operating Current into OUT(mA)
1000
Maximum Output Current (mA)
VOUT=2.5V, L=10µH
VIN=1.2V
60
L=22µH
VOUT=3.3V VOUT=3.6V
750
VOUT=2.5V
500
250
VOUT=5V
FB=1.4V
0.4
0.3
0.2
0.1
0
0
1
1.5
2
2.5
3
3.5
0
4
Input Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage(V)
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APW7075
Typical Characteristics (Cont.)
Transition from PFM to PWM vs. Input Voltage
The transition from PFM to PWM(mA)
The transition from PFM to PWM(mA)
Transition from PFM to PWM vs. Input Voltage
500
L=10µH
VOUT=3.3V
400
VOUT=3.6V
300
VOUT=2.5V
VOUT=5V
200
100
0
1
1.5
2
2.5
3
3.5
500
L=22µH
400
300
200
Input Voltage(V)
VOUT=5V
VOUT=2.5V
100
0
1
4
VOUT=3.6V
VOUT=3.3V
1.5
2
2.5
3
3.5
4
Input Voltage(V)
Line Transient Response
Input Battery Current vs. Input Battery Voltage
300
Input Battery Current(µA)
VBAT(2V/div)
250
IOUT= 100mA, VOUT=3.3V
VBAT=2V~3V
200
VOUT=3.3V
150
VOUT=2.4V
100
VOUT(200mV/div)
50
0
0
0.5
1
1.5
2
2.5
3
Input Battery Voltage(V)
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Rev. A.5 - Aug., 2005
Time(2ms/div)
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APW7075
Typical Characteristics (Cont.)
Load Transient Response
PWM to LDO
VIN (2V/div)
VOUT(200mV/div)
IOUT=100mA, VOUT=3.3V
CIN=10µF, VBAT=2.4V
VBAT=2.4V, VOUT=3.3V
L=22µH
VOUT(100mV/div)
IOUT=10~300mA
LX(2V/div)
Time(0.5ms/div)
Time(50us/div)
LDO to PWM
LDO Power Up
VIN (2V/div)
IOUT=100mA
IOUT=100mA, VOUT=3.3V
CIN=10µF, VBAT=2.4V
VIN (2V/div)
VOUT(100mV/div)
VOUT(2V/div)
LX(2V/div)
IIN(1A/div)
Time(0.2ms/div)
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Time(10ms/div)
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APW7075
Typical Characteristics (Cont.)
LDO Power Down
LDO Load Transient Response
IOUT=100mA
VIN(20V/div)
VOUT(50mV/div)
VIN=5V, VOUT=3.
VOUT(2V/div)
IOUT=10mA~500mA
IN(1A/div)
Time(10ms/div)
Time(5us/div)
LDO Load Transient Response
LBO Rising Delay Time
VOUT(50mV/div)
VBAT=2.4V, VOUT=3.3V
LBI(0.5V/div)
VIN=5V, VOUT=3.
IOUT=10mA~500mA
LBO(2V/div)
Time(5us/div)
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Time(5us/div)
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APW7075
Typical Characteristics (Cont.)
LBO Falling Delay Time
LBO Output Sink Current vs. LBO Low Voltage
30
VOUT=3.3V
25
LBO Sink Current(mA)
LBI(0.5V/div)
VBAT=2.4V, VOUT=3.3V
LBO(2V/div)
20
15
10
5
0
0
0.25
0.5
0.75
1
1.25
1.5
LBO Output Low Voltage(V)
Time(5us/div)
LDO Quiescent Current vs. LDO Input Voltage
LDO Current Limit vs. LDO Input Voltage
2
1.2
1.8
LDO Quiescent Current (A)
LDO Current Limit(A)
1
0.8
0.6
0.4
0.2
0
1.6
1.4
IOUT=10mA
1.2
1
0.8
0.6
IOUT=0mA
0.4
0.2
0
4
4.5
5
5.5
6
4
LDO Input Voltage(V)
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Rev. A.5 - Aug., 2005
4.5
5
5.5
6
LDO Input Voltage(V)
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APW7075
Typical Characteristics (Cont.)
Quiescent Current vs. LDO Output Current
Dropout Voltage vs. LDO Output Current
700
1.2
VOUT=4.2V
VIN =5V
Dropout Voltage (mV)
1
Quiescent Current (mA)
600
0.8
0.6
0.4
0.2
500
400
300
200
100
0
0
0
100
200
300
400
0
500
LDO Output Current(mA)
200
300
400
500
LDO Output Current(mA)
Output Voltage vs. Temperature
Output Voltage vs. LDO Input Voltage
3.3
3.303
IOUT=0mA
Iout=0mA
3.295
Output Voltage (V)
3.302
Output Voltage (V)
100
3.301
3.3
3.299
3.298
4.5
5
5.5
6
Rev. A.5 - Aug., 2005
3.28
3.275
-20
0
20
40
60
80
100
120
140
Temperature (℃)
LDO Input Voltage(V)
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3.27
-40
3.297
4
3.29
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APW7075
Function Description
dissipation on the P-channel MOSFET is lower than
discrete Schottky diode, thus the conversion efficiency
can be improved.
PFM Control Scheme
The APW7075 features the PFM control scheme to
improve the efficiency during light load. In PFM mode,
the inductor stores the energy during internal N-chan-
Shutdown
nel MOSFET turns on, and the energy is transferred
The APW7075 has an active high enable function. Force
to output capacitors and load during internal P-chan-
SHDN high (>1.4V) to enable the step-up converter,
nel MOSFET turns on. If the energy which is charged
SHDN low (<0.3V) to disable the step-up converter
to output capacitors exceeds the requirement of load,
and the device enters shutdown mode. In shutdown
the current will reverse from output capacitors to in-
mode, the converter stops switching and all internal
ductor and input capacitors. The PFM comparator com-
control circuits are turned off, but the output is still
pares the source (OUT) and drain (LX) of the internal
applied by input voltage through the body diode of P-
P-channel MOSFET. When the current that flows
channel MOSFET, it is about Vin-0.6V. Note that when
through the internal P-channel MOSFET is backward
the output is applied from the VIN (LDO mode), the
(from OUT to LX), the internal P-channel MOSFET will
shutdown function is disabled.
be turned off, and the output capacitor supplies the
load and maintains the output voltage. During PFM
Soft Start
mode, the IC switches only as need to serve the load,
The APW7075 provides the soft-start function to get
reducing the switching frequency and associated
the controlled output voltage rise. When battery volt-
losses in the internal switches and the external
age (<1.8V) is supplied to the device and exceeds the
inductor. Some jitter is normal during transition from
start-up voltage, the internal N-channel and P-channel
PFM to PWM mode; the transition of the PFM to PWM
MOSFETs start to switch and pump up the output volt-
is dependent on the inductance values, VIN, and VOUT.
age to 1.8V( if the battery voltage is over 1.8V, the
The output ripple is higher during PFM operation, a
output voltage will equal battery voltage during this
larger output capacitor can be used to minimize the
time ), which control circuitry can operate normally .
output ripple.
The soft start controls the rise of internal reference
voltage, when the internal reference voltage exceeds
Synchronous Rectification
the feedback voltage which is divided by the resistor
The APW7075 has an internal N-channel and a P-channel MOSFET, it is no need for external components,
the internal low RDS(ON) P-channel MOSFET replaces
the discrete Schottky diode, and it is reducing cost
and board space. During the cycle off time, the P-channel MOSFET turns on, and the power
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
from output voltage, the soft-start circuit will control
the output voltage until the output voltage is in
regulation. The soft-start interval is approximately
30ms.
16
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APW7075
Function Description (Cont.)
LDO


V OUT =  1 +
The output voltage has two operation modes. When
R1 
 × 1.2V
R2 
VIN exceeds 3.9V, the output will become the LDO
regulator and the step-up converter will be disabled.
Programming Low Battery Threshold Voltage
The LDO output is a P-channel low dropout regulator
The low battery threshold voltage can be programmed
with 1A current limit. When the VIN is below 3.8V, the
with a resistive divider from battery to LBI pin to ground
output will return to the step-up converter, and the LDO
(see Application Schematic). The internal reference
mode will be disabled. Note that when LDO mode is
voltage is 0.6V, and the low battery threshold voltage
used, the output voltage should be under 3.8V
must be below the battery voltage. The following equa-
Low Battery Detection
tion can be used to calculate the low battery threshold voltage:
The low battery detection is used to monitor the bat-


VBAT - TH = 1 +
tery voltage and to generate a signal. This function
includes two pins, LBI is the inverting input of the com-
R3 
 × 0.6V
R4 
parator and LBO is an open drain output (see block
Inductor Selection
diagram). When the LBI voltage drops below the
threshold voltage 0.6V, the open drain device will turn
The APW7075 works well with a 22uH inductor in most
on and LBO becomes low. The Low battery threshold
applications. The inductance values determine the in-
voltage can be programmed with a resistive divider from
ductor ripple current and affect the output current.
battery to LBI pin to ground. Since the LBO is an open
Higher inductance values reduce ripple and improve
drain output, it usually requires an external pull-up
efficiency. Lower inductance values have fast response
resistor.
but increase the ripple and reduce the efficiency. The
maximum allowed LX current is 1A (the maximun.
Application Information
output current shows in Typical Characteristics) and
so the peak inductor current cannot exceed it. The
Output Voltage Selection
following equations calculate the inductor current, and
The output voltage of APW7075 can be adjusted by an
output current.
external resistor divider, or connect FB pin to OUT for
3.3V and to ground for 2.5V (see Application
IOUT = IL x (1-D)
Schematic). The internal reference voltage is 1.2V and
∆IL = (VOUT− VIN) ×
the allowed output voltage is from 2.5V to 5.5V. The
Where:
following equation can be used to calculate the output
D=
voltage:
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
17
(1− D)
L× f
VOUT −VIN
VOUT
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APW7075
Function Description (Cont.)
Inductor Selection (Cont.)
Layout Considerations
The inductor’s DC resistance affects the efficiency;
The correct PCB layout is important for all switching
larger resistance dissipates more power, it should be
converters. If the layout is not carefully done, the regu-
as small as possible. It is important to choose the
lator could show stability problems as well as EMI
inductor’s saturation current rating greater than the
problems. Figure. 5 illustrates the layout guidelines,
peak current which the inductor will flow in the
the bold lines indicate the high current paths; these
application.
traces must be short and wide. The input capacitors,
Boost Converter Input Capacitor Selection
output capacitors, and the inductor should be as close
to the IC as possible. Use a common ground plane for
At least a 10uF input capacitor is recommended to
power ground and a different one for control ground to
stabilize the battery voltage and minimize the peak
minimize the effects of ground noise. Connect these
current ripple from the battery.
ground planes at a node close to the GND pin of IC.
LDO Input Capacitor Selection
The feedback and LBI resistor dividers should be placed
The LDO input capacitor with larger values and lower
as close to the IC as possible.
ESRs provide better PSRR and line transient response.
At least a 10uF capacitor is recommended.
USB 5V
The output capacitor is used for supplying the output
1
2
3
4
during internal N-channel MOSFET turns on time.
Larger capacitance and lower ESR reduce the output
voltage ripple. The output voltage supplies the power
C2
100uF
C4
1uF
C3
10uF
Output Capacitor Selection
VIN
FB
SHDN
LBI
OUT
LX
GND
LBO
8
7
6
VOUT
C1
10uF
22UH
VBAT
5
APW7075
to the IC and so the output voltage ripple must be as
small as possible to provide better PSRR. In general,
a 100uF to 220uF low ESR Tantalum capacitor is
Figure 5. Recommended Layout Diagram
recommended, a 1uF ceramic capacitor in parallel for
bypassing the noise is also recommended. The following equation calculates the output ripple.
Voripple= IOUT× (
VOUT − VBAT
+ ESR)
COUT×FSW × VOUT
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
18
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APW7075
Packaging Information
E1
E
0.015X45
SOP-8-P pin ( Reference JEDEC Registration MS-012)
H
D1
e1
e2
D
A1
1
L
0.004max.
Dim
A
Millimeters
Inches
Min.
Max.
Min.
Max.
A
A1
1.35
0
1.75
0.15
0.053
0
0.069
0.006
D
D1
4.80
5.00
0.189
0.197
E
E1
3.80
H
L
5.80
0.40
e1
e2
0.33
3.00REF
4.00
0.150
2.60REF
φ1
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
0.118REF
0.157
0.102REF
6.20
1.27
0.228
0.016
0.51
0.013
0.244
0.050
0.020
1.27BSC
0.50BSC
8°
8°
19
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APW7075
Packaging Information
TSSOP-8
e
8 7
2x E/2
E1
( 2)
E
GAUGE
PLANE
S
1 2
e/2
0.25
D
L
A2
A
b
Dim
A
A1
A2
b
D
e
E
E1
L
L1
R
R1
S
φ1
φ2
φ3
( 3)
A1
Millimeters
Min.
Inches
Max.
1.2
0.15
1.05
0.30
3.1
0.00
0.80
0.19
2.9
Min.
4.30
0.45
0.026 BSC
0.252 BSC
4.50
0.75
0.169
0.018
1.0 REF
0.09
0.09
0.2
0°
Max.
0.047
0.006
0.041
0.012
0.122
0.000
0.031
0.007
0.114
0.65 BSC
6.40 BSC
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
1
(L1)
0.177
0.030
0.039REF
0.004
0.004
0.008
0°
8°
12° REF
12° REF
8°
12° REF
12° REF
20
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APW7075
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (T L)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6
minutes
max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
21
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APW7075
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s
Package Thickness
Volume mm 3
Volume mm 3
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm 3
Volume mm 3
Volume mm 3
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t
E
P
Po
D
P1
Bo
F
W
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
D1
22
Ko
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APW7075
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
S O P - 8 -P
A
B
330 ± 1
F
5.5 ± 1
Application
T S S O P -8
J
T1
T2
W
P
E
62 +1.5
C
12.75+
0.15
2 ± 0.5
12.4 ± 0.2
2 ± 0.2
1 2 ± 0. 3
8 ± 0.1
1.75±0.1
D
D1
Po
P1
Ao
Bo
Ko
t
1.55 +0.1 1.55+ 0.25 4.0 ± 0.1
2.0 ± 0.1
6.4 ± 0.1
5.2 ± 0. 1
J
T1
T2
W
P
E
62 +1.5
C
12.75+
0.15
2 + 0.5
12.4 ± 0.2
2 ± 0.2
1 2 ± 0. 3
8 ± 0.1
1.75±0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
5.5 ± 0. 1
1.5 + 0.1
1.5 + 0.1
4.0 ± 0.1
2.0 ± 0.1
7.0 ± 0.1
3.6 ± 0.3
A
B
330 ± 1
2.1 ± 0.1 0.3 ±0.013
1.6 ± 0.1 0.3 ±0.013
(mm)
Cover Tape Dimensions
Application
SOP-8-P
TSSOP-8
Carrier Width
12
12
Cover Tape Width
9.3
9.3
Devices Per Reel
2500
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Aug., 2005
23
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