DS90CF363 +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link— 65 MHz General Description Features The DS90CF363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. n n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 170 Megabytes/sec bandwidth Up to 1.3 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 48-lead TSSOP package Falling edge data strobe Transmitter Compatible with TIA/EIA-644 LVDS standard ESD rating > 7 kV Operating Temperature: −40˚C to +85˚C Block Diagram DS90CF363 DS100032-1 Order Number DS90CF363MTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100032 www.national.com DS90CF363 +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link— 65 MHz January 2000 DS90CF363 Absolute Maximum Ratings (Note 1) Package Derating: DS90CF363 ESD Rating (HBM, 1.5 kΩ, 100 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 16 mW/˚C above +25˚C > 7 kV Recommended Operating Conditions Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 sec) +260˚C Maximum Package Power Dissipation Capacity @ 25˚C MTD48 (TSSOP) Package: DS90CF363 1.98 W Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 Nom 3.3 Max 3.6 Units V −40 0 +25 +85 2.4 100 ˚C V mVPP Max Units Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.1 0.3 V VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ± 5.1 ± 10 µA IOS Output Short Circuit Current VOUT = 0V −60 −120 mA 345 450 mV 35 mV 2.7 3.3 V LVDS DC SPECIFICATIONS VOD Differential Output Voltage ∆VOD Change in VOD between complimentary output states VOS Offset Voltage (Note 4) ∆VOS Change in VOS between complimentary output states RL = 100Ω 250 1.125 IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω IOZ Output TRI-STATE ® Current Power Down = 0V, VOUT = 0V or VCC VTH Differential Input High Threshold VCM = +1.2V VTL Differential Input Low Threshold IIN Input Current 1.25 1.375 V 35 mV −3.5 −5 mA ±1 ± 10 µA +100 mV −100 mV VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V ± 10 ± 10 µA µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTG ICCTZ Transmitter Supply Current Worst Case Transmitter Supply Current 16 Grayscale Transmitter Supply Current Power Down RL = 100Ω, CL = 5 pF, Worst Case Pattern (Figures 1, 3) f = 32.5 MHz 31 45 mA f = 37.5 MHz 32 50 mA f = 65 MHz 42 55 mA RL = 100Ω, CL = 5 pF, 16 Grayscale Pattern (Figures 2, 3) f = 32.5 MHz 23 35 mA f = 37.5 MHz 28 40 mA f = 65 MHz 31 45 mA 10 55 µA Power Down = Low Driver Outputs in TRI-STATE ® under Power Down Mode Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. www.national.com 2 (Continued) Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Note 4: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 3 ) Parameter Min 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 3 ) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 4 ) 5 ns TCCS TxOUT Channel-to-Channel Skew (Figure 5 ) TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12) TPPos1 250 ps −0.4 0 0.3 ps Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns TPPos2 Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns TCIP TxCLK IN Period (Figure 6) 15 T 50 ns TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 6) TSTC TxIN Setup to TxCLK IN (Figure 6) THTC f = 65 MHz f = 65 MHz 2.5 ns TxIN Hold to TxCLK IN (Figure 6) 0 ns TCCD TxCLK IN to TxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 7 ) 3 5.5 ns TPLLS Transmitter Phase Lock Loop Set (Figure 8 ) 10 ms TPDD Transmitter Power Down Delay (Figure 11) 100 ns AC Timing Diagrams DS100032-4 FIGURE 1. “Worst Case” Test Pattern 3 www.national.com DS90CF363 Electrical Characteristics DS90CF363 AC Timing Diagrams (Continued) DS100032-5 FIGURE 2. “16 Grayscale” Test Pattern (Notes 5, 6, 7, 8) Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. DS100032-6 FIGURE 3. DS90CF363 (Transmitter) LVDS Output Load and Transition Times DS100032-8 FIGURE 4. DS90CF363 (Transmitter) Input Clock Transition Time www.national.com 4 DS90CF363 AC Timing Diagrams (Continued) DS100032-9 Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low → High Edge FIGURE 5. DS90CF363 (Transmitter) Channel-to-Channel Skew DS100032-10 FIGURE 6. DS90CF363 (Transmitter) Setup/Hold and High/Low Times DS100032-12 FIGURE 7. DS90CF363 (Transmitter) Clock In to Clock Out Delay DS100032-14 FIGURE 8. DS90CF363 (Transmitter) Phase Lock Loop Set Time 5 www.national.com DS90CF363 AC Timing Diagrams (Continued) DS100032-16 FIGURE 9. Seven Bits of LVDS in One Clock Cycle DS100032-17 FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs DS100032-18 FIGURE 11. Transmitter Power Down Delay www.national.com 6 DS90CF363 AC Timing Diagrams (Continued) DS100032-20 FIGURE 12. Transmitter LVDS Output Pulse Position Measurement DS90CF363 Pin Description — FPD Link Transmitter I/O No. TxIN Pin Name I 21 Description TxOUT+ O 3 Positive LVDS differentiaI data output. TxOUT− O 3 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). V CC I 4 Power supply pins for TTL inputs. GND I 4 Ground pins for TTL inputs. PLL V CC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS V CC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. Applications Information and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90CF363 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant. The DS90CF363 and DS90CF364 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF563 and DS90CF564). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of both the transmitter 7 www.national.com DS90CF363 Pin Diagram DS90CF363 DS100032-23 Application DS100032-3 www.national.com 8 inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF363MTD NS Package Number MTD48 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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DS90CF363 +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link— 65 MHz Physical Dimensions