MC10H125 Quad MECL‐to‐TTL Translator Description The MC10H125 is a quad translator for interfacing data and control signals between the MECL section and saturated logic section of digital systems. The 10H part is a functional/pinout duplication of the standard MECL 10K™ family part, with 100% improvement in propagation delay, and no increase in power-supply current. Outputs of unused translators will go to low state when their inputs are left open. www.onsemi.com 16 20 1 1 Features PDIP−16 P SUFFIX CASE 648−08 • Propagation Delay, 2.5 ns Typical • Voltage Compensated • Improved Noise Margin 150 mV • • (Over Operating Voltage and Temperature Range) MECL 10K Compatible These Devices are Pb-Free, Halogen Free and are RoHS Compliant PLLC−20 FN SUFFIX CASE 775−02 MARKING DIAGRAMS* 1 20 16 MC10H125P AWLYYWWG 10H125G AWLYYWW 1 PDIP−16 A WL, L YY, Y WW, W G PLLC−20 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC10H125FNG PLLC−20 (Pb-Free) 46 Units / Tube MC10H125FNR2G PLLC−20 (Pb-Free) 500 Tape & Reel MC10H125PG PDIP−16 (Pb-Free) 25 Units / Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 August, 2016 − Rev. 14 1 Publication Order Number: MC10H125/D MC10H125 2 4 3 6 5 7 10 12 11 14 13 15 1 VBB* GND = Pin 16 VCC ( +5.0 Vdc) = Pin 9 VEE ( −5.2 Vdc) = Pin 8 *VBB to be used to supply bias to the MC10H125 only and bypassed (when used) with 0.01 mF to 0.1 mF capacitor to ground (0 V). VBB can source < 1.0 mA. Figure 1. Logic Diagram VBB 1 16 GND Ain 2 15 Din Ain 3 14 Din Aout 4 13 Dout Bout 5 12 Cout Bin 6 11 Cin Bin 7 10 Cin VEE 8 9 VCC VBB 1 AIN 2 AIN AOUT GND DIN DIN DOUT Exposed Pad (EP) 16 15 14 12 COUT 11 CIN 3 10 CIN 4 9 VCC MC10H125 5 6 BOUT BIN Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables. 13 7 8 BIN VEE Pin assignment for QFN16 Package. Figure 2. Pin Assignment Table 1. DIP CONVERSION TABLES 16−Pin DIL to 20−Pin PLCC 16 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 PIN PLCC 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 20−Pin DIL to 20−Pin PLCC 20 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 PIN PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 www.onsemi.com 2 MC10H125 Table 2. MAXIMUM RATINGS Symbol Rating Unit VEE Power Supply (VCC = 5.0 V) Characteristic −8.0 to 0 Vdc VCC Power Supply (VEE = −5.2 V) 0 to +7.0 Vdc VI Input Voltage (VCC = 5.0 V) 0 to VEE Vdc TA Operating Temperature Range 0 to +75 °C Tstg Storage Temperature Range − Plastic − Ceramic °C −55 to +150 −55 to +165 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. ELECTRICAL CHARACTERISTICS (VEE = −5.2 V +5%; VCC = 5.0 V + 5.0 %) (Note 2) 0° 25° 75° Min Max Min Max Min Max Unit Negative Power Supply Drain Current − 44 − 40 − 44 mA Positive Power Supply Drain Current − 63 − 63 − 63 mA − 40 − 40 − 40 mA IinH Input Current − 225 − 145 − 145 mA ICBO Input Leakage Current − 1.5 − 1.0 − 1.0 mA VOH High Output Voltage IOH = −1.0 mA 2.5 − 2.5 − 2.5 − Vdc VOL Low Output Voltage IOL = +20 mA − 0.5 − 0.5 − 0.5 Vdc VIH High Input Voltage (Note 1) −1.17 −0.84 −1.13 −0.81 −1.07 −0.735 Vdc VIL Low Input Voltage (Note 1) −1.95 −1.48 −1.95 −1.48 −1.95 −1.45 Vdc IOS Short Circuit Current 60 150 60 150 50 150 mA VBB Reference Voltage −1.38 −1.27 −1.35 −1.25 −1.31 −1.19 Vdc − − Symbol IE ICCH ICCL VCMR Characteristic Common Mode Range (Note 3) −2.85 to +0.3 V Typical VPP Input Sensitivity (Note 4) 150 mV 1. When VBB is used as the reference voltage. 2. Each MECL 10H™ series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. 3. Differential input not to exceed 1.0 Vdc. 4. 150 mVp−p differential input required to obtain full logic swing on output. www.onsemi.com 3 MC10H125 Table 4. AC CHARACTERISTICS 0° Symbol Characteristic 25° 75° Min Max Min Max Min Max Unit tpd Propagation Delay 0.8 3.3 0.85 3.35 0.9 3.4 ns tr Rise Time (Note 1) 0.3 1.2 0.3 1.2 0.3 1.2 ns tf Fall Time (Note 1) 0.3 1.2 0.3 1.2 0.3 1.2 ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Output Voltage = 1.0 V to 2.0 V. RL = 500 W to GND and CL = 25 pF to GND. Refer to Figure 1. APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL * RL AC TEST LOAD GND Figure 1. TTL Output Loading Used for Device Evaluation APPLICATION INFORMATION An advantage of this device is that MECL-level information can be received, via balanced twisted pair lines, in the TTL equipment. This isolates the MECL-logic from the noisy TTL environment. Power supply requirements are ground, +5.0 V and −5.2 V. The MC10H125 incorporates differential inputs and Schottky TTL “totem pole” outputs. Differential inputs allow for use as an inverting/non-inverting translator or as a differential line receiver. The VBB reference voltage is available on Pin 1 for use in single-ended input biasing. The outputs of the MC10H125 go to a low-logic level whenever the inputs are left floating, and a high-logic output level is achieved with a minimum input level of 150 mVp−p. www.onsemi.com 4 MC10H125 PACKAGE DIMENSIONS 20 LEAD PLLC FN SUFFIX CASE 775−02 ISSUE F B 0.007 (0.180) Y BRK −N− M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D −L− −M− Z W 20 D 1 X V S T L-M S N S VIEW D−D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z C H −T− VIEW S G1 0.010 (0.250) S T L-M SEATING PLANE F 0.007 (0.180) VIEW S S N T L-M S N S K 0.004 (0.100) J M K1 E G 0.007 (0.180) S NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). www.onsemi.com 5 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10 _ 0.310 0.330 0.040 −−− MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10 _ 7.88 8.38 1.02 −−− M T L-M S N S MC10H125 PACKAGE DIMENSIONS PDIP−16 P SUFFIX CASE 648−08 ISSUE V D A 16 9 E H E1 1 NOTE 8 b2 8 c B TOP VIEW END VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L A1 C D1 e SEATING PLANE M eB END VIEW 16X b SIDE VIEW 0.010 M C A M B M NOTE 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.735 0.775 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° STYLE 1: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. CATHODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE 15. ANODE 16. ANODE MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 18.67 19.69 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° STYLE 2: PIN 1. COMMON DRAIN 2. COMMON DRAIN 3. COMMON DRAIN 4. COMMON DRAIN 5. COMMON DRAIN 6. COMMON DRAIN 7. COMMON DRAIN 8. COMMON DRAIN 9. GATE 10. SOURCE 11. GATE 12. SOURCE 13. GATE 14. SOURCE 15. GATE 16. SOURCE MECL is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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