TI1 LM3200 Miniature, adjustable, step-down dc-dc converter Datasheet

LM3200
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SNVS319C – NOVEMBER 2004 – REVISED APRIL 2013
LM3200 Miniature, Adjustable, Step-Down DC-DC Converter with Bypass Mode for RF
Power Amplifiers
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FEATURES
DESCRIPTION
•
•
The LM3200 is a DC-DC converter optimized for
powering RF power amplifiers (PAs) from a single
Lithium-Ion cell. It steps down an input voltage of
2.7V to 5.5V to a variable output voltage of 0.8V to
3.6V. The output voltage is set using an analog input
( VCON) for optimizing efficiency of the RF PA at
various power levels.
1
2
•
•
•
•
•
•
•
•
2 MHz (typ.) PWM Switching Frequency
Operates from a Single Li-Ion Cell (2.7V to
5.5V)
Variable Output Voltage (0.8V to 3.6V)
300 mA Maximum Load Capability (PWM
Mode)
500 mA Maximum Load Capability (Bypass
Mode)
PWM, Forced and Automatic Bypass Mode
High Efficiency (96% Typ at 3.6VIN, 3.2VOUT at
120 mA) from Internal Synchronous
Rectification
10-pin DSBGA Package
Current Overload Protection
Thermal Overload Protection
The LM3200 offers superior features and
performance for mobile phones and similar RF PA
applications. Fixed-frequency PWM mode minimizes
RF interference. Bypass mode turns on an internal
bypass switch to power the PA directly from the
battery. LM3200 has both forced and automatic
bypass modes. Shutdown mode turns the device off
and reduces battery consumption to 0.1 µA (typ.).
The LM3200 is available in a 10-pin lead free DSBGA
package. A high switching frequency (2 MHz) allows
use of tiny surface-mount components. Only three
small external surface-mount components, an
inductor and two ceramic capacitors are required.
APPLICATIONS
•
•
•
•
Cellular Phones
Hand-Held Radios
RF PC Cards
Battery Powered RF Devices
TYPICAL APPLICATION
VIN
2.7V to 5.5V
VDD
CIN
PVIN
BYPOUT
EN
10 PF
BYP
VCON
VCON
L
2.2 PH
SW
LM3200
VOUT
0.8V to 3.6V
VOUT = 3 x VCON
FB
PGND
SGND
COUT
4.7 PF
0.267V to 1.20V
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM3200
SNVS319C – NOVEMBER 2004 – REVISED APRIL 2013
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CONNECTION DIAGRAMS
SGND
A2
SGND
A2
A3 BYPOUT
VDD A1
VCON B1
FB C1
BYPOUT A3
B3 PVIN
PVIN B3
C3 SW
SW C3
D3 PGND
BYP D1
A1 VDD
B1 VCON
C1 FB
D1 BYP
PGND D3
D2
EN
D2
EN
Figure 1. Top View
Figure 2. Bottom View
10–Bump Thin DSBGA Package, Large Bump
See NS Package Number YPA0010NHA
PIN DESCRIPTION
Pin #
Name
A1
VDD
Analog Supply Input. A 0.1 µF ceramic capacitor is recommended to be placed as close to this pin as
possible. (Figure 33)
Description
Voltage Control Analog input. VCON controls VOUT in PWM mode. Set: VOUT = 3 x VCON. Do not leave floating.
B1
VCON
C1
FB
D1
BYP
D2
EN
D3
PGND
C3
SW
Switching Node connection to the internal PFET switch and NFET synchronous rectifier.
Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit
specification of the LM3200.
B3
PVIN
Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 33)
A3
BYPOUT
Bypass FET Drain. Connect to the output capacitor. (Figure 33) Do not leave floating.
A2
SGND
Feedback Analog Input. Connect to the output at the output filter capacitor. (Figure 33)
Bypass. Use this digital input to command operation in Bypass mode. Set BYP low for normal operation.
Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown, set low.
Power Ground
Analog and Control Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
VDD, PVIN to SGND
−0.2V to +6.0V
PGND to SGND
−0.2V to +0.2V
EN, FB, BYP, VCON
(SGND −0.2V)
to (VDD +0.2V)
w/6.0V max
(PGND −0.2V)
to (PVIN +0.2V)
w/6.0V max
SW, BYPOUT
−0.2V to +0.2V
PVIN to VDD
Continuous Power Dissipation (4)
Internally Limited
Junction Temperature (TJ-MAX)
+150°C
Storage Temperature Range
−65°C to +150°C
Maximum Lead Temperature
(Soldering, 10 sec)
+260°C
ESD Rating
(5)
Human Body Model
2.0 kV
Machine Model
(1)
(2)
(3)
(4)
(5)
200V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pins.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 130°C (typ.).
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. TI recommends that all integrated circuits be handled with Appropriate
precautions. Failure to observe proper ESD handling techniques can result in damage.
OPERATING RATINGS (1) (2)
Input Voltage Range
2.7V to 5.5V
Recommended Load Current
PWM Mode
0 mA to 300 mA
Bypass Mode
0 mA to 500 mA
−25°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−25°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pins.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
THERMAL PROPERTIES
Junction-to-Ambient Thermal
Resistance (θJA), YPA10 Package
(1)
100°C/W
(1)
Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. A 1" x 1", 4 layer, 1.5 oz. Cu board was used for the measurements.
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ELECTRICAL CHARACTERISTICS (1) (2)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−25°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3200 with: PVIN = VDD = EN = 3.6V,
BYP = 0V.
Symbol
Parameter
VIN
Input Voltage Range
VFB,
VFB,
Conditions
(3)
Min
Max
Units
5.5
V
0.800
0.85
V
3.600
3.672
V
330
400
mV
160
250
320
mV
350
450
540
mV
PVIN = VDD = VIN
2.7
MIN
Feedback Voltage at
Minimum Setting
VCON = 0.267V, VIN = 3.6V
0.75
MAX
Feedback Voltage at
Maximum Setting
VCON = 1.20V, VIN = 4.2V
3.528
Typ
Over-Voltage Protection
Threshold
(4)
VBYPASS−
Auto Bypass Detection
Negative Threshold
(5)
VBYPASS+
Auto Bypass Detection
Positive Threshold
(5)
ISHDN
Shutdown Supply
Current (6)
EN = SW = BYPOUT = VCON = FB = 0V
0.1
3
µA
IQ_PWM
DC Bias Current into
VDD
VCON = 0.267V, FB = 2V, No-Load
720
850
µA
BYP = 3.6V, VCON = 0V, No-Load
720
850
µA
RDSON (P)
Pin-Pin Resistance for
PFET
ISW = 500mA
320
450
mΩ
RDSON (N)
Pin-Pin Resistance for
N-FET
ISW = - 200mA
310
450
mΩ
RDSON
Pin-Pin Resistance for
Bypass FET
IBYPOUT = 500mA
85
120
mΩ
(BYP)
ILIM-PFET
Switch Current Limit
(7)
700
820
940
mA
ILIM-BYP
Bypass FET Current
Limit
(8)
800
1000
1200
mA
FOSC
Internal Oscillator
Frequency
1.7
2
2.2
MHz
VIH
Logic High Input
Threshold for EN, BYP
1.20
VIL
Logic Low Input
Threshold for EN, BYP
IPIN
Pin Pull Down Current
for EN, BYP
Gain
VCON to VOUT Gain
ICON
VCON Input Leakage
Current
OVP
IQ_BYP
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
EN, BYP = 3.6V
VCON = 1.2V
V
5
0.4
V
10
µA
3
V/V
10
nA
All voltages are with respect to the potential at the GND pins.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most
likely norm.
The LM3200 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where
requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should
be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V.
Over-Voltage protection (OVP) threshold is the voltage above the nominal VOUT where the OVP comparator turns off the PFET switch
while in PWM mode.
VIN is compared to the programmed output voltage (VOUT). When VIN–VOUT falls below VBYPASS− for longer than TBYP the Bypass FET
turns on and the switching FETs turn off. This is called the Bypass mode. Bypass mode is exited when VIN–VOUT exceeds VBYPASS+ for
longer than TBYP, and PWM mode returns. The hysterisis for the bypass detection threshold VBYPASS+ – VBYPASS− will always be
positive and will be approximately 200 mV(typ.).
Shutdown current includes leakage current of PFET and Bypass FET.
Electrical Characteristics table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current
limit is activated). Refer to Typical Performance Characteristics (Open/Closed Loop Current Limit vs Temperature curve) for closed loop
data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor current measured in
the application circuit by increasing output current until output voltage drops by 10%.
Bypass FET current limit is defined as the load current at which the FB voltage is 1V lower than VIN.
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SYSTEM CHARACTERISTICS
The following spec table entries are specified by design if the component values in the typical application circuit are used.
These parameters are not specified by production testing.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRESPONSE Time for VOUT to Rise
from 0.8V to 3.4V in
PWM Mode
VIN = 4.2V, COUT = 4.7 µF,
RLOAD = 15Ω
L = 2.2 uH
CCON
VCON Input Capacitance
VCON = 1V,
Test frequency = 100 kHz
15
pF
TON_BYP
Bypass FET Turn On
Time In Bypass Mode
VIN = 3.6V, VCON = 0.267V,
COUT = 4.7 µF, RLOAD = 15Ω
BYP = Low to High
30
µs
20
µs
TBYP
(1)
Auto Bypass Detect
Delay Time
25
µs
(1)
10
15
VIN is compared to the programmed output voltage (VOUT). When VIN–VOUT falls below VBYPASS− for longer than TBYP the Bypass FET
turns on and the switching FETs turn off. This is called the Bypass mode. Bypass mode is exited when VIN–VOUT exceeds VBYPASS+ for
longer than TBYP, and PWM mode returns. The hysterisis for the bypass detection threshold VBYPASS+ – VBYPASS− will always be
positive and will be approximately 200 mV(typ.).
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TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit in Figure 33, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Quiescent Supply Current
vs
Supply Voltage
Shutdown Supply Current
vs
Temperature (EN = 0V)
1.0
VCON = 0.267V
FB = 2V
0.78
No Load
0.9
TA = 85°C
SHUTDOWN CURRENT (PA)
QUIESCENT CURRENT (mA)
0.80
0.76
TA = 25°C
0.74
0.72
0.70
TA = -25°C
0.68
0.8
EN = 0V
VCON = 0V
FB = SW = 0V
0.7
0.6
VIN = 3.6V
0.5
0.4
VIN = 4.2V
0.3
0.2
VIN = 2.7V
0.1
0.66
2.5
3.0
3.5
4.0
4.5
5.5
5.0
0.0
-40 -20
6.0
SUPPLY VOLTAGE (V)
0
20
40
60
80 100 120 140
JUNCTION TEMPERATURE (oC)
Figure 3.
Figure 4.
Switching Frequency Variation
vs
Temperature (VOUT = 1.5V, IOUT = 200 mA)
Output Voltage
vs
Supply Voltage (VOUT = 1.5V)
4.0
1.510
VCON = 0.5V
3.0
IOUT = 200 mA
OUTPUT VOLTAGE (V)
SWITCHING FREQUENCY VARIATION (%)
VIN = 5.5V
2.0
VIN = 3.6V
VIN = 4.2V
1.0
0.0
-1.0
-2.0
VIN = 2.7V
1.508
IOUT = 50 mA
1.506
1.504
IOUT = 300 mA
IOUT = 150 mA
1.502
-3.0
-4.0
-40
-20
0
20
40
60
80
1.500
2.0
100
2.5 3.0
AMBIENT TEMPERATURE ( C)
1.510
3.5
4.0 4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
o
Figure 5.
Figure 6.
Output Voltage
vs
Temperature (VOUT = 1.5V)
Output Voltage
vs
Temperature (VOUT = 3.25V)
3.264
1.508
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 3.25V
IOUT = 50 mA
1.506
1.504
IOUT = 300 mA
IOUT = 100 mA
1.502
1.500
-40
IOUT = 200 mA
IOUT = 100 mA
3.260
3.258
IOUT = 300 mA
3.256
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
3.254
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
Figure 7.
6
3.262
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 33, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Open/Closed Loop Current Limit
vs
Temperature (PWM Mode)
900
Output Voltage
vs
Output Current (BYP Mode, VIN = BYP = 3.6V)
0.0
VIN = 4.2V
CLOSED LOOP
VIN = 3.6V
850
VIN = 2.7V
825
VIN = 4.2V
800
VIN = 2.7V
VIN = 3.6V
0.2
DROPOUT VOLTAGE (V)
CURRENT LIMIT (mA)
875
TA = 85°C
0.4
TA = -25°C
0.6
TA = 25°C
0.8
775
Max Load
Capability
500 mA
OPEN LOOP
750
-40
1.0
-20
0
20
40
60
80
100
0
200
AMBIENT TEMPERATURE (oC)
4.0
ILIM-BYP
= 965 mA
400
600
800
1000
1200
OUTPUT CURRENT (mA)
Figure 9.
Figure 10.
VCON Voltage
vs
Output Voltage (IOUT = 200 mA)
Low VCON Voltage
vs
Output Voltage (RLOAD = 15Ω)
1.6
VIN = 3.6V
1.4
3.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VIN = 4.2V
3.0
VIN = 3.0V
2.5
VIN = 2.7V
2.0
Bypass Mode
1.5
1.0
1.2
VIN = 5.5V
1.0
VIN = 4.7V
0.8
0.6
0.4
VIN = 4.2V
0.5
0.2
IOUT = 200 mA
0.0
0.2
0.4
0.6
0.8
1.0
1.2
RLOAD = 15:
0.0
0.0
1.4
0.1
VCON VOLTAGE (V)
0.2
0.3
0.4
0.5
VCON VOLTAGE (V)
Figure 11.
Figure 12.
Output Voltage
vs
Input Voltage (BYP = 0V, Auto-Bypass Function)
Efficiency
vs
Output Voltage (VIN = 3.9V)
100
3.8
RLOAD = 15:
95
3.6
3.4
~VbypassPWM Mode
3.2
3
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
~Vbypass+
90
RLOAD = 10:
85
80
Bypass Mode
2.8 VOUT = 3.25V
75
RLOAD = 15:
2.6
5.5
5.0
4.5
VIN = 3.9V
4.0
3.5
3.0
2.5
INPUT VOLTAGE (V)
70
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT VOLTAGE (V)
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 33, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Efficiency
vs
Output Current (VOUT = 1.5V)
Efficiency
vs
Output Current (VOUT = 3.25V)
100
100
VIN = 2.7V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
80
VIN = 4.2V
VIN = 3.6V
70
60
50
VIN = 3.6V
VIN = 3.9V
80
VIN = 4.2V
70
60
50
40
40
0
50
100
150
200
250
300
350
0
OUTPUT CURRENT (mA)
50
100
150
200
250
300
Figure 15.
Figure 16.
Load Transient Response
(VOUT = 1.5V)
Load Transient Response
(VOUT = 3.25V)
VIN = 3.6V
VIN = 4.2V
VOUT = 1.5V
VOUT
VOUT = 3.25V
100 mV/DIV
VOUT
100 mV/DIV
AC Coupled
AC Coupled
IL
200 mA
IL
250 mA
IOUT
200 mA
300 mA
IOUT
50 mA
100 mA
20 Ps/DIV
20 Ps/DIV
Figure 17.
Figure 18.
Startup
(VIN = 3.6V, VOUT = 1.5V, 15Ω)
Shutdown Response
(VIN = 4.2V, VOUT = 3.25V, 15Ω)
VIN = 4.2V
5V/DIV
VSW
VOUT = 3.25V
VSW
VIN = 3.6V
VOUT = 1.5V
RLOAD = 15:
2V/DIV
1V/DIV
RLOAD = 15:
350
OUTPUT CURRENT (mA)
VOUT
VOUT
2V/DIV
IL
IL
200 mA/DIV
500 mA/DIV
EN
5V/DIV
EN
40 Ps/DIV
100 Ps/DIV
Figure 19.
8
5V/DIV
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 33, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Automatic Bypass Operation
(VIN = 4.2V to 3.0V)
VSW
VIN
Forced Bypass Operation
(VIN = 3.0V)
5V/DIV
VSW
1V/DIV
VOUT
2V/DIV
VIN = 4.2V
VOUT
1V/DIV
VIN = 3V
VCON = 0.5V
VIN = 3.0V
IL
IL
RLOAD = 15:
200 mA/DIV
200 mA/DIV
5V/DIV
BYP
RLOAD = 15:
VCON = 1.1V
100 Ps/DIV
100 Ps/DIV
Figure 21.
Figure 22.
Line Transient Response
(VIN = 3.0V to 3.6V)
VCON Voltage Response
(VIN = 4.2V, VCON = 0.5V/1.1V)
3.6V
VIN
3.0V
VSW
2V/DIV
VOUT = 1.5V
IOUT = 200 mA
50 mV/DIV
AC Coupled
VOUT
3.25V
VOUT
VIN = 4.2V
IL
200 mA/DIV
1.08V
0.5V
VCON
40 Ps/DIV
100 Ps/DIV
Figure 23.
Figure 24.
Timed Current Limit Response
(VIN = 3.6V)
Output Voltage Ripple
(VOUT = 1.5V)
VSW
2V/DIV
VOUT
1V/DIV
IL
1.5V
RLOAD = 15:
500 mA/DIV
VSW
2V/DIV
VOUT
10 mV/DIV
AC Coupled
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
RLOAD = 15:
VOUT = 1.5V
IOUT = 200 mA
400 ns/DIV
10 Ps/DIV
Figure 25.
Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 33, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Output Voltage Ripple
(VOUT = 3.25V)
Output Voltage Ripple in Dropout
(VIN = 3.57V, VOUT = 3.25V, ILOAD = 200 mA)
VSW
2V/DIV
VSW
2V/DIV
VOUT
10 mV/DIV
AC Coupled
VOUT
10 mV/DIV
AC Coupled
IL
200 mA/DIV
IL
200 mA/DIV
VIN = 4.2V
VOUT = 3.25V
VIN = 3.57V
IOUT = 300 mA
VOUT = 3.25V
400 ns/DIV
Figure 27.
Figure 28.
RDSON
vs
Temperature (P-ch)
RDSON
vs
Temperature (N-ch)
600
600
ISW = 500 mA
ISW = - 200 mA
VIN = 2.7V
500
RDS(ON) (m:)
RDS(ON) (m:)
500
400
300
VIN = 4.2V
200
-20
0
20
40
60
80
400
300
VIN = 4.2V
100
-40
100
AMBIENT TEMPERATURE (oC)
-20
0
20
40
60
80
Figure 29.
Figure 30.
RDSON
vs
Temperature (Bypass FET)
Dropout Voltage
vs
Output Current (Bypass Mode)
50
IBYPOUT = 500 mA
V IN = EN = BYP = 3.25V
45
140
DROPOUT VOLTAGE (mV)
VIN = 3.6V
VIN = 2.7V
100
80
60
100
AMBIENT TEMPERATURE (oC)
160
120
VIN = 3.6V
VIN = 2.7V
200
VIN = 3.6V
100
-40
RDS(ON) (m:)
IOUT = 200 mA
400 ns/DIV
40
35
30
250
20
15
10
VIN = 4.2V
5
40
-40
0
-20
0
20
40
60
80
100
o
100
200
300
400
500
IOUT (mA)
AMBIENT TEMPERATURE ( C)
Figure 31.
10
0
Figure 32.
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BLOCK DIAGRAM
PVIN
VDD
BYPOUT
CURRENT
SENSE
OSCILLATOR
ERROR
AMPLIFIER
FB
~
OVP
COMP
VCON
PWM
COMP
MOSFET
CONTROL
LOGIC
SW
VCON Low Voltage
DETECTOR
0.15V
BYP
MAIN CONTROL
EN
SHUTDOWN
CONTROL
SGND
PGND
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OPERATION DESCRIPTION
The LM3200 is a simple, step-down DC-DC converter with a bypass switch, optimized for powering RF power
amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. It is
designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single
Li-Ion battery cell. It is based on current-mode buck architecture, with synchronous rectification for high
efficiency. It is designed for a maximum load capability of 300 mA in PWM mode and 500 mA in bypass mode.
Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen.
The device has three-pin selectable operating modes required for powering RF PAs in mobile phones and other
sophisticated portable device with complex power management needs. Fixed-frequency PWM operation offers
regulated output at high efficiency while minimizing interference with sensitive IF and data acquisition circuits.
Bypass mode (Forced or Automatic) turns on an internal FET bypass switch to power the PA directly from the
battery. Shutdown mode turns the device off and reduces battery consumption to 0.1 µA (typ).
DC PWM mode output voltage precision is +/-2% for 3.6VOUT. Efficiency is typically around 96% for a 120 mA
load with 3.2V output, 3.6V input. PWM mode quiescent current is 0.7 mA typ. The output voltage is dynamically
programmable from 0.8V to 3.6V by adjusting the voltage on the control pin without the need for external
feedback resistors. This ensures longer battery life by being able to change the PA supply voltage dynamically
depending on its transmitting power.
Additional features include current overload protection, over voltage protection and thermal shutdown.
The LM3200 is constructed using a chip-scale 10-pin DSBGA package. This package offers the smallest
possible size, for space-critical applications such as cell phones, where board area is an important design
consideration. Use of a high switching frequency (2 MHz) reduces the size of external components. As shown in
Figure 33, only few external components are required for implementation. Use of a DSBGA package requires
special design considerations for implementation. (See DSBGA PACKAGE ASSEMBLY AND USE) Its fine
bump-pitch requires careful board design and precision assembly equipment. Use of this package is best suited
for opaque-case applications, where its edges are not subject to high-intensity ambient red or infrared light. Also,
the system controller should set EN low during power-up and other low supply voltage conditions. (See
Shutdown Mode)
VIN
2.7V to 5.5V
C4**
0.1 PF
C1*
10 PF
VDD
PVIN
BYPOUT
L1
2.2 PH
SYSTEM
CONTROLLER
BYP
DAC
ON/OFF
LM3200
VOUT
0.8V to 3.6V
SW
VCON
FB
EN
SGND
C2
4.7 PF
PGND
*Place C1 close to PVIN.
**Place C4 close to VDD.
Figure 33. Typical Operating System Circuit
Circuit Operation
Referring to Figure 33, the LM3200 operates as follows. During the first part of each switching cycle, the control
block in the LM3200 turns on the internal PFET (P-channel MOSFET) switch. This allows current to flow from the
input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a
slope of around (VIN-VOUT)/L, by storing energy in a magnetic field. During the second part of each cycle, the
controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel
MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage
that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the
stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope
around VOUT/L. The output filter capacitor stores charge when the inductor current is going high, and releases it
when inductor current is going low, smoothing the voltage across the load.
12
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The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
PWM Mode
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by
modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing
the signal from the PFET drain current to a slope-compensated reference current generated by the error
amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to
ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the
PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load
pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher
before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for
the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the
oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on-time of
PFET in PWM mode is 50 ns (typ).
Bypass Mode
The LM3200 contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass mode. In
Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output power.
When the part operates in the Bypass mode, the output voltage will be the input voltage less the voltage drop
across the resistance of the bypass PFET. Bypass mode is more efficient than operating in PWM mode at 100%
duty cycle because the resistance of the bypass PFET is less than the series resistance of the PWM PFET and
inductor. This translates into higher voltage available on the output in Bypass mode, for a given battery voltage.
The part can be placed in bypass mode by sending BYP pin high. This is called Forced Bypass Mode and it
remains in bypass mode until BYP pin goes low.
Alternatively the part can go into Bypass mode automatically. This is called Auto-bypass mode or Automatic
Bypass mode. The bypass switch turns on when the difference between the input voltage and programmed
output voltage is less than 250 mV (typ.) for more than the bypass delay time of 15 µs (typ.). The bypass switch
turns off when the input voltage is higher than the programmed output voltage by 450 mV (typ.) for longer than
the bypass delay time. The bypass delay time is provided to prevent false triggering into Automatic Bypass mode
by either spikes or dips in VIN. This method is very system resource friendly in that the Bypass PFET is turned on
automatically when the input voltage gets close to the output voltage, typical scenario of a discharging battery. It
is also turned off automatically when the input voltage rises, typical scenario of a charger connected. Another
scenario could be changes made to VCON voltage causing Bypass PFET to turn on and off automatically. It is
recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the FB
pin.
Operating Mode Selection Control
The BYP digital input pin is used to select between PWM/Auto-bypass and Bypass operating mode. Setting BYP
pin high (>1.2V) places the device in Forced Bypass mode. Setting BYP pin low (<0.4V) or leaving it floating
places the device in PWM/Auto-bypass mode.
Bypass and PWM operation overlap during the transition between the two modes. This transition time is
approximately 31 µs when changing from PWM to Bypass mode, and 15 µs when changing from Bypass to
PWM mode. This helps prevent under or overshoots during the transition period between PWM and Bypass
modes.
Shutdown Mode
Setting the EN digital pin low (<0.4V) places the LM3200 in a 0.1 µA (typ.) Shutdown mode. During shutdown,
the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of the LM3200
are turned off. Setting EN high (>1.2V) enables normal operation.
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EN should be set low to turn off the LM3200 during power-up and under voltage conditions when the power
supply is less than the 2.7V minimum operating voltage. The LM3200 is designed for compact portable
applications, such as mobile phones. In such applications, the system controller determines power supply
sequencing and requirements for small package size outweigh the benefit of including UVLO (Under Voltage
Lock-Out) circuitry.
Dynamically Adjustable Output Voltage
The LM3200 features dynamically adjustable output voltage to eliminate the need for external feedback resistors.
The output can be set from 0.8V to 3.6V by changing the voltage on the analog VCON pin. This feature is useful in
PA applications where peak power is needed only when the handset is far away from the base station or when
data is being transmitted. In other instances, the transmitting power can be reduced. Hence the supply voltage to
the PA can be reduced, promoting longer battery life. See Setting the Output Voltage for further details.
Over Voltage Protection
The LM3200 has an over voltage comparator that prevents the output voltage from rising too high. If the output
voltage rises to 330 mV over its target, the OVP comparator inhibits PWM operation to skip pulses until the
output voltage returns to the target. Typically the OVP comparator may be activated during VCON steps
particularly steps from a high to a low voltage. During the over voltage protection mode, both the PWM PFET
and the NFET synchronous rectifier are off. When the part comes out of the over voltage protection mode, the
NFET synchronous rectifier remains off for approximately 3.5 µs to avoid inductor current going negative.
Internal Synchronous Rectification
While in PWM mode, the LM3200 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
With medium and heavy loads, the internal NFET synchronous rectifier is turned on during the inductor current
down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. There
is no zero cross detect, which means that the NFET can conduct current in both directions and inductor current is
always continuous. The advantage of this method is that the part remains in PWM mode at light loads or no load
conditions. The NFET has a current limit. The NFET is designed to conduct through its intrinsic body diode
during transient intervals before it turns on, eliminating the need for an external diode.
Current Limiting
A current limit feature allows the LM3200 to protect itself and external components during overload conditions. In
PWM mode, a 940 mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output
voltage down to below approximately 0.375V, indicating a possible short to ground, then the device switches to a
timed current limit mode. In timed current limit mode, the internal PFET switch is turned off after the current
comparator trips, and the beginning of the next cycle is inhibited for 3.5 µs to force the instantaneous inductor
current to ramp down to a safe value. After the 3.5 µs interval, the internal PFET is turned on again. This cycle is
repeated until the load is reduced and the output voltage exceeds approximately 0.375V. Therefore, the device
may not startup if an excessive load is connected to the output when the device is enabled. The synchronous
rectifier is off in the timed current limit mode. Timed current limit prevents the loss of current control seen in
some products when the output voltage is pulled low in serious overload conditions.
A current limit is also provided for the NFET. This is approximately −500 mA. Both the NFET and the PFET are
turned off in negative current limit until the PFET is turned on again at the beginning of the next cycle. The
negative current limit inhibits buildup of excessive inductor current. In the Bypass mode, the bypass current limit
is 1000 mA(typ). The output voltage drops when the bypass current limit kicks in.
Thermal Overload Protection
The LM3200 has a thermal overload protection function that operates to protect the device from short-term
misuse and overload conditions. When the junction temperature exceeds around 150°C, the device inhibits
operation. Both the PFET and the NFET are turned off in PWM mode, and the Bypass PFET is turned off in
Bypass mode. When the temperature drops below 130°C, normal operation resumes. Prolonged operation in
thermal overload conditions may damage the device and is considered bad practice.
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Application Information
SETTING THE OUTPUT VOLTAGE
The LM3200 features a pin-controlled variable output voltage to eliminate the need for external feedback
resistors. It can be programmed for an output voltage from 0.8V to 3.6V by setting the voltage on the VCON pin,
as in the following formula:
VOUT = 3 x VCON
(1)
When VCON is between 0.267V and 1.20V, the output voltage will follow proportionally by 3 times of VCON.
If VCON is over 1.20V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope
compensation.
If VCON voltage is less than 0.267V (VOUT = 0.8V), the output voltage may not be regulated due to the required
on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a
limited VIN range is used. Refer to Typical Performance Characteristics (Low VCON Voltage vs Output Voltage
curve) for details. This curve is for a typical part and there could be part to part variation for output voltages less
than 0.8V over the limited VIN range. In addition, if VCON is less than approx. 0.15V, the LM3200 output is turned
off, but the internal bias circuits are still active.
INDUCTOR SELECTION
A 2.2 μH inductor with saturation current rating over 940 mA is recommended for almost all applications. The
inductor resistance should be less than 0.3Ω for better efficiency. Table 1 lists suggested inductors and
suppliers.
Table 1. Suggested Inductors and Suppliers
Model
Size (WxLxH) [mm]
Vendor
DO3314-222MX
3.3 x 3.3 x 1.4
Coilcraft
VLF3010AT-2R2M1R0
2.6 x 2.8 x 1.0
TDK
MIPW3226D2R2M
3.2 x 2.6 x 1.0
FDK
LPO3310-222MX
3.3 x 3.3 x 1.0
Coilcraft
If a higher value inductor is used the LM3200 may become unstable and exhibit large under or over shoot during
line, load and VCON transients. If smaller inductance value is used, slope compensation maybe insufficient
causing sub-harmonic oscillations. The device has been tested with inductor values in the range 1.55μH to 3.1μH
to account for inductor tolerances.
For low-cost applications, an unshielded bobbin inductor can be used. For noise-critical applications, an
unshielded or shielded-bobbin inductor should be used. A good practice is to layout the board with footprints
accommodating both types for design flexibility. This allows substitution of an unshielded inductor, in the event
that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from
current through the windings of the inductor exceeds what the inductor’s core material can support with a
corresponding magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter
like the LM3200.
CAPACITOR SELECTION
The LM3200 is designed to be used with ceramic capacitors. Use a 10 µF ceramic capacitor for the input and a
4.7 µF ceramic capacitor for the output. Ceramic capacitors such as X5R, X7R and B are recommended for both
filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones
and similar applications. Table 2 lists suggested capacitors and suppliers.
Table 2. Suggested Capacitors and Suppliers
Model
Vendor
LMK212BJ475MG
Taiyo-Yuden
C2012X5R1A475K
TDK
GRM188R61A475K
Murata
C3216X5R1A106K
TDK
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The DC bias characteristics of the capacitor must be considered when making the selection. If smaller case size
such as 0603 is selected, the dc bias could reduce the cap value by as much as 40%, in addition to the 20%
tolerances and 15% temperature coefficients. Request dc bias curves from manufacturer when making
selection.The device has been designed to be stable with output capacitors as low as 3 μF to account for
capacitor tolerances.This value includes dc bias reduction, manufacturing tolerences and temp coefficients.
The input filter capacitor supplies AC current drawn by the PFET switch of the LM3200 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the
AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR
(Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a major
factor in voltage ripple.
DSBGA PACKAGE ASSEMBLY AND USE
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in TI Application Note 1112 (SNVA009). Refer to the section Surface Mount Technology
(SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be
used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (nonsolder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a
lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the surface of the board
and interfering with mounting. See Application Note 1112 (SNVA009) for specific instructions how to do this. The
10-Bump package used for the LM3200 has 300 micron solder balls and requires 10.82 mil pads for mounting on
the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being
caught in deep corners. Initially, the trace to each pad should be 6-7 mil wide, for a section approximately 6 mil
long or longer, as a thermal relief. Then each trace should neck up or down to its optimal width. The important
criterion is symmetry. This ensures the solder bumps on the LM3200 re-flow evenly and that the device solders
level to the board. In particular, special attention must be paid to the pads for bumps B3, C3 and D3. Because
PGND and PVIN are typically connected to large copper planes, inadequate thermal relief can result in
inadequate re-flow of these bumps.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metalization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.
Do not use or power-up the LM3200 while subjecting it to high intensity red or infrared light; otherwise degraded,
unpredictable or erratic operation may result. Examples of light sources with high red or infrared content include
the sun and halogen lamps. Place the device in a case opaque to red or infrared light.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA
package and board pads. Poor solder joints can result in erratic or degraded performance. Good layout for the
LM3200 can by implemented by following a few simple design rules.
1. Place the LM3200 on 10.82 mil pads. As a thermal relief, connect to each pad with a 7 mil wide,
approximately 7 mil long traces, and when incrementally increase each trace to its optimal width. The
important criterion is symmetry to ensure the solder bumps on the LM3200 re-flow evenly (see DSBGA
Package Assembly and Use).
2. Place the LM3200, inductor and filter capacitors close together and make the trace short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Place the capacitors and inductor close to the LM3200. The input capacitor should
be placed right next to the device between PVIN and PGND pin.
3. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM3200 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM3200 by the inductor, to the output filter capacitor and then back through
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4.
5.
6.
7.
SNVS319C – NOVEMBER 2004 – REVISED APRIL 2013
ground, forming a second current loop. Routing these loops so the current curls in the same direction,
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
Connect the ground pins of the LM3200, and filter capacitors together using generous component side
copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several
vias. This reduces ground plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the LM3200 by giving it a low impedance ground connection.
Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
Route noise sensitive traces, such as the voltage feedback trace, away from noisy traces and components.
The voltage feedback trace must remain close to the LM3200 circuit and should be routed directly from FB
pin to VOUT at the output capacitor. A good approach is to route the feedback trace on another layer and to
have a ground plane between the top layer and the layer on which the feedback trace is routed. This reduces
EMI radiation on to the DC-DC converter’s own voltage feedback trace.
It is recommended to connect BYPOUT pin to VOUT at the output capacitor using a separate trace, instead of
connecting it directly to the FB pin for better noise immunity.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM3200TL/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YPA
10
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-25 to 85
SCUB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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8-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM3200TL/NOPB
Package Package Pins
Type Drawing
SPQ
DSBGA
250
YPA
10
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
8.4
Pack Materials-Page 1
1.96
B0
(mm)
K0
(mm)
P1
(mm)
2.31
0.76
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3200TL/NOPB
DSBGA
YPA
10
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YPA0010
0.600
±0.075
D
E
TLP10XXX (Rev D)
D: Max = 2.226 mm, Min =2.165 mm
E: Max = 1.862 mm, Min =1.801 mm
4215069/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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