TI BQ2010 Gas gauge ic Datasheet

bq2010
Gas Gauge IC
Features
General Description
➤ Conservative and repeatable
measurement of available charge
in rechargeable batteries
The bq2010 Gas Gauge IC is intended
for battery-pack or in-system installation to maintain an accurate record of
a battery's available charge. The IC
monitors a voltage drop across a
sense resistor connected in series between the negative battery terminal
and ground to determine charge and
discharge activity of the battery.
➤ Designed for battery pack integration
-
120µA typical standby current
-
Small size enables implementations in as little as 1 2
square inch of PCB
➤ Integrate within a system or as a
stand-alone device
-
Display capacity via singlewire serial communication
port or direct drive of LEDs
➤ Measurements compensated for
current and temperature
➤ Self-discharge compensation using internal temperature sensor
NiMH and NiCd battery self-discharge is estimated based on an internal timer and temperature sensor.
Compensations for battery temperature and rate of charge or discharge
are applied to the charge, discharge,
and self-discharge calculations to provide available charge information
across a wide range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the
course of a discharge cycle from full to
empty.
➤ 16-pin narrow SOIC
Nominal available charge may be
directly indicated using a five- or
six-segment LED display. These segments are used to indicate graphically the nominal available charge.
Pin Connections
Pin Names
➤ Accurate measurements across a
wide range of current (> 500:1)
LCOM
LCOM
1
16
VCC
SEG1/PROG1
2
15
REF
SEG2/PROG2
3
14
NC
SEG3/PROG3
4
13
DQ
SEG4/PROG4
5
12
EMPTY
SEG5/PROG5
6
11
SB
SEG6/PROG6
7
10
DISP
VSS
8
9
SR
16-Pin Narrow SOIC
LED common output
The bq2010 supports a simple
single-line bidirectional serial link to
an external processor (common
ground). The bq2010 outputs battery
information in response to external
commands over the serial link.
The bq2010 may operate directly
from 3 or 4 cells. With the REF output and an external transistor, a simple, inexpensive regulator can be built
to provide V CC across a greater
number of cells.
Internal registers include available
charge, temperature, capacity, battery
ID, battery status, and programming
pin settings. To support subassembly
testing, the outputs may also be controlled. The external processor may
also overwrite some of the bq2010
gas gauge data registers.
REF
Voltage reference output
NC
No connect
DQ
Serial communications
input/output
EMPTY
Empty battery indicator
output
SB
Battery sense input
DISP
Display control input
SEG5/PROG5 LED segment 5/
program 5 input
SR
Sense resistor input
VCC
3.0–6.5V
SEG6/PROG6 LED segment 6/
program 6 input
VSS
System ground
SEG1/PROG1 LED segment 1/
program 1 input
SEG2/PROG2 LED segment 2/
program 2 input
SEG3/PROG3 LED segment 3/
program 3 input
SEG4/PROG4 LED segment 4/
program 4 input
PN201001.eps
4/95 D
1
bq2010
SR
Pin Descriptions
LCOM
The voltage drop (VSR) across the sense resistor RS is monitored and integrated over
time to interpret charge and discharge activity. The SR input is tied to the high side of
the sense resistor. VSR < VSS indicates discharge, and VSR > VSS indicates charge. The
effective voltage drop, VSRO, as seen by the
bq2010 is VSR + VOS (see Table 5).
LED common output
Open-drain output switches VCC to source
current for the LEDs. The switch is off during initialization to allow reading of the soft
pull-up or pull-down program resistors.
LCOM is also high impedance when the display is off.
SEG1–
SEG6
LED display segment outputs (dual function with PROG1–PROG6)
DISP
Programmed full count selection inputs
(dual function with SEG1–SEG2)
These three-level input pins define the programmed full count (PFC) thresholds described in Table 2.
PROG3–
PROG4
SB
Gas gauge rate selection inputs (dual
function with SEG3–SEG4)
Self-discharge rate selection (dual function with SEG5)
EMPTY
Display mode selection (dual function
with SEG6)
DQ
Serial I/O pin
This is an open-drain bidirectional pin.
This three-level pin defines the display operation shown in Table 1.
NC
Battery empty output
This open-drain output becomes high-impedance
on detection of a valid end-of-discharge voltage
(VEDVF) and is low following the next application
of a valid charge.
This three-level input pin defines the
selfdischarge compensation rate shown in Table 1.
PROG6
Secondary battery input
This input monitors the single-cell voltage
potential through a high-impedance resistive divider network for end-of-discharge
voltage (EDV) thresholds, maximum charge
voltage (MCV), and battery removed.
These three-level input pins define the scale
factor described in Table 2.
PROG5
Display control input
DISP high disables the LED display. DISP
tied to VCC allows PROGX to connect directly
to VCC or VSS instead of through a pull-up or
pull-down resistor. DISP floating allows the
LED display to be active during discharge or
charge if the NAC registers update at a rate
equivalent to |VSRO| ≥ 4mV. DISP low activates the display. See Table 1.
Each output may activate an LED to sink
the current sourced from LCOM.
PROG1–
PROG2
Sense resistor input
REF
No connect
Voltage reference output for regulator
REF provides a voltage reference output for
an optional micro-regulator.
2
VCC
Supply voltage input
VSS
Ground
bq2010
Figure 1 shows a typical battery pack application of the
bq2010 using the LED display capability as a chargestate indicator. The bq2010 can be configured to display
capacity in either a relative or an absolute display mode.
The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. The absolute display mode uses the programmed
full count (PFC) as the full reference, forcing each segment of the display to represent a fixed amount of
charge. A push-button display feature is available for
momentarily enabling the LED display.
Functional Description
General Operation
The bq2010 determines battery capacity by monitoring
the amount of charge input to or removed from a rechargeable battery. The bq2010 measures discharge and
charge currents, estimates self-discharge, monitors the
battery for low-battery voltage thresholds, and compensates for temperature and charge/discharge rates. The
charge measurement derives from monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The available battery charge is determined by monitoring this voltage over
time and correcting the measurement for the environmental and operating conditions.
The bq2010 monitors the charge and discharge currents
as a voltage across a sense resistor (see RS in Figure 1).
A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the battery current is too great.
R1
bq2010
Gas Gauge IC
Q1
ZVNL110A
REF
LCOM
SEG1/PROG1
VCC
C1
0.1µF
SB
VCC
SEG2/PROG2
SEG3/PROG3
DISP
SEG4/PROG4
SR
VCC
SEG5/PROG5
SEG6/PROG6
RB1
RB2
RS
VSS
EMPTY
DQ
Charger
Indicates optional.
Directly connect to VCC across 3 or 4 cells (3 to 5.6V nominal)
with a resistor and a Zener diode to limit voltage during charge.
Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells.
The value of R1 depends on the number of cells.
Load
Programming resistors (6 max.) and ESD-protection diodes are not shown.
R-C on SR may be required, application-specific.
FG201001.eps
Figure 1. Battery Pack Application Diagram—LED Display
3
bq2010
charge display translation. The temperature range is
available over the serial port in 10°C increments as
shown below:
Voltage Thresholds
In conjunction with monitoring VSR for charge/discharge
currents, the bq2010 monitors the single-cell battery
potential through the SB pin. The single-cell voltage
potential is determined through a resistor/divider network according to the following equation:
TMPGG (hex)
Temperature Range
0x
< -30°C
1x
-30°C to -20°C
2x
-20°C to -10°C
3x
-10°C to 0°C
4x
0°C to 10°C
5x
10°C to 20°C
VEDV1 (early warning) = 1.05V
6x
20°C to 30°C
VEDVF (empty) = 0.95V
7x
30°C to 40°C
8x
40°C to 50°C
9x
50°C to 60°C
Ax
60°C to 70°C
Bx
70°C to 80°C
Cx
> 80°C
RB1
= N−1
RB2
where N is the number of cells, RB1 is connected to the
positive battery terminal, and RB2 is connected to the
negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV)
and for maximum cell voltage (MCV). EDV threshold
levels are used to determine when the battery has
reached an “empty” state, and the MCV threshold is used
for fault detection during charging.
Two EDV thresholds for the bq2010 are fixed at:
If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of V S B , until the next valid charge. EDV
monitoring may be disabled under certain conditions as
described in the next paragraph.
During discharge and charge, the bq2010 monitors VSR
for various thresholds. These thresholds are used to
compensate the charge and discharge rates. Refer to the
count compensation section for details. EDV monitoring
is disabled if VSR ≤ -250mV typical and resumes 1 2 second
after VSR > -250mV.
EMPTY Output
Layout Considerations
The EMPTY output switches to high impedance when
VSB < VEDVF and remains latched until a valid charge
occurs. The bq2010 also monitors VSB relative to VMCV,
2.25V. VSB falling from above VMCV resets the device.
The bq2010 measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:
Reset
The bq2010 recognizes a valid battery whenever VSB is
greater than 0.1V typical. VSB rising from below 0.25V
or falling from above 2.25V resets the device. Reset can
also be accomplished with a command over the serial
port as described in the Reset Register section.
n
The capacitors (SB and VCC) should be placed as
close as possible to the SB and VCC pins, respectively,
and their paths to VSS should be as short as possible.
A high-quality ceramic capacitor of 0.1µf is
recommended for VCC.
n
The sense resistor capacitor should be placed as close
as possible to the SR pin.
n
The sense resistor (RSNS) should be as close as
possible to the bq2010.
Temperature
The bq2010 internally determines the temperature in
10°C steps centered from -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate
compensations, self-discharge counting, and available
4
bq2010
1.
Gas Gauge Operation
The operational overview diagram in Figure 2 illustrates
the operation of the bq2010. The bq2010 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge currents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.
LMD is the last measured discharge capacity of the
battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register.
The LMD also serves as the 100% reference threshold used by the relative display mode.
The main counter, Nominal Available Charge (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).
2.
The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2010 adapts its capacity determination based on the
actual conditions of discharge.
Battery capacity (mAh) * sense resistor (Ω) =
PFC (mVh)
Selecting a PFC slightly less than the rated capacity for absolute mode provides capacity above the
full reference for much of the battery's life.
Charge
Current
Discharge
Current
Self-Discharge
Timer
Rate and
Temperature
Compensation
Rate and
Temperature
Compensation
Temperature
Compensation
+
Main Counters
and Capacity
Reference (LMD)
Programmed Full Count (PFC) or initial battery capacity:
The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The PFC also
provides the 100% reference for the absolute display mode. The bq2010 is configured for a given application by selecting a PFC value from Table 2.
The correct PFC may be determined by multiplying
the rated battery capacity in mAh by the sense resistor value:
The battery's initial capacity is equal to the Programmed
Full Count (PFC) shown in Table 2. Until LMD is updated,
NAC counts up to but not beyond this threshold during
subsequent charges. This approach allows the gas gauge to
be charger-independent and compatible with any type of
charge regime.
Inputs
Last Measured Discharge (LMD) or learned
battery capacity:
+
-
Nominal
Available
Charge
(NAC)
<
Last
Measured
Discharged
(LMD)
Temperature Step,
Other Data
Temperature
Translation
Outputs
Chip-Controlled
Available Charge
LED Display
+
Discharge
Count
Qualified Register
(DCR)
Transfer
Serial
Port
FG201002.eps
Figure 2. Operational Overview
5
bq2010
Example: Selecting a PFC Value
Select:
Given:
PFC = 33792 counts or 211mVh
PROG1 = float
PROG2 = float
PROG3 = float
PROG4 = low
PROG5 = float
PROG6 = float
Sense resistor = 0.1Ω
Number of cells = 6
Capacity = 2200mAh, NiCd battery
Current range = 50mA to 2A
Absolute display mode
Serial port only
Self-discharge = C 64
Voltage drop over sense resistor = 5mV to 200mV
The initial full battery capacity is 211mVh
(2110mAh) until the bq2010 “learns” a new capacity with a qualified discharge from full to EDV1.
Therefore:
2200mAh * 0.1Ω = 220mVh
Table 1. bq2010 Programming
Pin
Connection
PROG5
Self-Discharge Rate
PROG6
Display Mode
DISP
Display State
H
Disabled
Absolute
NAC = PFC on reset
LED disabled
Absolute
NAC = 0 on reset
LED-enabled on discharge or charge
when equivalent |VSRO| ≥ 4mV
Relative
NAC = 0 on reset
LED on
Z
NAC
L
NAC
Note:
64
47
PROG5 and PROG6 states are independent.
Table 2. bq2010 Programmed Full Count mVh Selections
1
2
Programmed
Full
Count
(PFC)
-
-
-
Scale =
1/80
Scale =
1/160
Scale =
1/320
Scale =
1/640
Scale =
1/1280
Scale =
1/2560
mVh/
count
H
H
49152
614
307
154
76.8
38.4
19.2
mVh
H
Z
45056
563
282
141
70.4
35.2
17.6
mVh
H
L
40960
512
256
128
64.0
32.0
16.0
mVh
Z
H
36864
461
230
115
57.6
28.8
14.4
mVh
Z
Z
33792
422
211
106
53.0
26.4
13.2
mVh
Z
L
30720
384
192
96.0
48.0
24.0
12.0
mVh
L
H
27648
346
173
86.4
43.2
21.6
10.8
mVh
L
Z
25600
320
160
80.0
40.0
20.0
10.0
mVh
L
L
22528
282
141
70.4
35.2
17.6
8.8
mVh
90
45
22.5
11.25
5.6
2.8
mV
PROGx
VSR equivalent to 2
counts/sec. (nom.)
PROG4 = L
PROG3 = H
PROG4 = Z
PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L
6
Units
bq2010
3.
4.
Nominal Available Charge (NAC):
Discharge Counting
NAC counts up during charge to a maximum
value of LMD and down during discharge and
self-discharge to 0. NAC is reset to 0 on initialization (PROG6 = Z or low) and on the first valid charge
following discharge to EDV1. NAC is set to PFC on
initialization if PROG6 = high. To prevent overstatement of charge during periods of overcharge,
NAC stops incrementing when NAC = LMD.
All discharge counts where VSRO < VSRD cause the NAC
register to decrement and the DCR to increment. Exceeding the fast discharge threshold (FDQ) if the rate is
equivalent to VSRO < -4mV activates the display, if enabled. The display becomes inactive after VSRO rises
above -4mV. V SRD is a programmable threshold as
described in the Digital Magnitude Filter section. The
default value for VSRD is -300µV.
Discharge Count Register (DCR):
Self-Discharge Estimation
The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0. Prior to NAC = 0 (empty
battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge
increments the DCR. The DCR resets to 0 when
NAC = LMD. The DCR does not roll over but stops
counting when it reaches ffffh.
The bq2010 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a
nominal 1 64 * NAC, 1 47 * NAC per day, or disabled as selected by PROG5. This is the rate for a battery whose
temperature is between 20°–30°C. The NAC register cannot be decremented below 0.
The DCR value becomes the new LMD value on the
first charge after a valid discharge to VEDV1 if:
Count Compensations
The bq2010 determines fast charge when the NAC updates at a rate of ≥ 2 counts/sec. Charge and discharge
activity is compensated for temperature and charge/discharge rate before updating the NAC and/or DCR. Selfdischarge estimation is compensated for temperature
before updating the NAC or DCR.
No valid charge initiations (charges greater than
256 NAC counts, where VSRO > VSRQ) occurred
during the period between NAC = LMD and EDV1
detected.
The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).
Charge Compensation
Two charge efficiency compensation factors are used for
trickle charge and fast charge. Fast charge is defined as
a rate of charge resulting in ≥ 2 NAC counts/sec (≥ 0.15C
to 0.32C depending on PFC selections; see Table 2). The
compensation defaults to the fast charge factor until the
actual charge rate is determined.
The temperature is ≥ 0°C when the EDV1 level is
reached during discharge.
The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.
Charge Counting
Temperature adapts the charge rate compensation factors
over three ranges between nominal, warm, and hot temperatures. The compensation factors are shown below.
Charge activity is detected based on a positive voltage on
the VSR input. If charge activity is detected, the bq2010
increments NAC at a rate proportional to VSRO and, if enabled, activates an LED display if the rate is equivalent to
VSRO > 4mV. Charge actions increment the NAC after
compensation for charge rate and temperature.
The bq2010 determines charge activity sustained at a
continuous rate equivalent to VSRO > VSRQ. A valid
charge equates to sustained charge activity greater than
256 NAC counts. Once a valid charge is detected, charge
counting continues until VSRO (VSR + VOS) falls below
VSRQ. VSRQ is a programmable threshold as described in
the Digital Magnitude Filter section. The default value
for VSRQ is 375µV.
Charge
Temperature
Trickle Charge
Compensation
Fast Charge
Compensation
<30°C
0.80
0.95
30–40°C
0.75
0.90
> 40°C
0.65
0.80
Discharge Compensation
Corrections for the rate of discharge are made by adjusting an internal discharge compensation factor. The discharge compensation factor is based on the namically
measured VSR.
7
bq2010
The compensation factors during discharge are:
Digital Magnitude Filter
Approximate
VSR Threshold
Discharge
Compensation
Factor
Efficiency
VSR > -150 mV
1.00
100%
VSR < -150 mV
1.05
95%
The bq2010 has a programmable digital filter to eliminate charge and discharge counting below a set threshold. The default setting is -0.30mV for V SRD and
+0.38mV for VSRQ. The proper digital filter setting can
be calculated using the following equation. Table 4
shows typical digital filter settings.
VSRD (mV) = -45 / DMF
VSRQ (mV) = -1.25 * VSRD
Temperature compensation during discharge also takes
place. At lower temperatures, the compensation factor increases by 0.05 for each 10°C temperature step below 10°C.
Table 4. Typical Digital Filter Settings
Comp. factor = 1.0 + (0.05 * N)
DMF
75
100
150 (default)
175
200
Where N = Number of 10°C steps below 10°C and
-150mV < V SR < 0.
For example:
T > 10°C : Nominal compensation, N = 0
DMF
Hex.
4B
64
96
AF
C8
VSRD
(mV)
-0.60
-0.45
-0.30
-0.26
-0.23
VSRQ
(mV)
0.75
0.56
0.38
0.32
0.28
0°C < T < 10°C: N = 1 (i.e., 1.0 becomes 1.05)
-10°C < T < 0°C: N = 2 (i.e., 1.0 becomes 1.10)
Error Summary
-20°C < T < -10°C: N = 3 (i.e., 1.0 becomes 1.15)
Capacity Inaccurate
-20°C < T < -30°C: N = 4 (i.e., 1.0 becomes 1.20)
The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value includes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated (see the
DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in
actual battery capacity.
Self-Discharge Compensation
The self-discharge compensation is programmed for a nominal rate of 1 64 * NAC, 1 47 * NAC per day, or disabled. This is
the rate for a battery within the 20–30°C temperature
range (TMPGG = 6x). This rate varies across 8 ranges from
<10°C to >70°C, doubling with each higher temperature
step (10°C). See Table 3.
A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been
updated following 64 valid charges.
Table 3. Self-Discharge Compensation
Typical Rate
Temperature
Range
PROG5 = Z
< 10°C
NAC
10–20°C
NAC
20–30°C
NAC
30–40°C
NAC
40–50°C
NAC
50–60°C
NAC
60–70°C
NAC
> 70°C
NAC
256
128
64
32
16
8
4
2
PROG5 = L
NAC
NAC
NAC
NAC
NAC
NAC
NAC
Current-Sensing Error
188
NAC
Table 5 illustrates the current-sensing error as a function of VSR. A digital filter eliminates charge and discharge counts to the NAC register when VSRO (VSR +
VOS) is between VSRQ and VSRD.
94
47
23.5
11.8
Communicating With the bq2010
5.88
The bq2010 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2010 registers. Battery characteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
2.94
1.47
8
bq2010
Table 5. bq2010 Current-Sensing Errors
Symbol
Parameter
Typical
Maximum
Units
± 50
± 150
µV
Notes
DISP = VCC.
VOS
Offset referred to VSR
INL
Integrated non-linearity
error
±2
±4
%
Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.
INR
Integrated nonrepeatability error
±1
±2
%
Measurement repeatability given
similar operating conditions.
the bq2010 should be pulled up by the host system or may
be left floating if the serial interface is not used.
communication. The data should be held for a period,
tDV, to allow the host or bq2010 to sample the data bit.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2010.
The command directs the bq2010 either to store the next
eight bits of data received to a register specified by the
command byte or to output the eight bits of data specified by the command byte.
The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period, tSSU, after the negative edge used to start communication. The final logic-high state should be held until a period, tSV, to allow time to ensure that the bit transmission
was stopped properly. The timings for data and break
communication are given in the serial communication timing specification and illustration sections.
The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using
either polled or interrupt processing. Data input from the
bq2010 may be sampled using the pulse-width capture
timers available on some microcontrollers.
Communication with the bq2010 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication sequence to read the bq2010 NAC register.
bq2010 Registers
The bq2010 command and status registers are listed in
Table 6 and described below.
Communication is normally initiated by the host processor
sending a BREAK command to the bq2010. A BREAK is
detected when the DQ pin is driven to a logic-low state for
a time, tB or greater. The DQ pin should then be returned
to its normal ready-high logic state for a time, tBR. The
bq2010 is now ready to receive a command from the host
processor.
Command Register (CMDR)
The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2010.
The CMDR register contains two fields:
The return-to-one data bit frame consists of three distinct
sections. The first section is used to start the transmission
by either the host or the bq2010 taking the DQ pin to a
logic-low state for a period, tSTRH,B. The next section is the
actual data transmission, where the data should be valid
by a period, tDSU, after the negative edge used to start
W/R bit
n
Command address
The W/R bit of the command register is used to select
whether the received command is for a read or a write
function.
Written by Host to bq2010
CMDR = 03h
LSB
n
Received by Host to bq2010
NAC = 65h
MSB
Break 1 1 0 0 0 0 0 0
LSB
MSB
1 0 1 0 011 0
DQ
TD201001.eps
Figure 3. Typical Communication with the bq2010
9
bq2010
Table 6. bq2010 Command and Status Registers
Control Field
Register Name
Symbol
Loc.
(hex)
Read/
Write
7(MSB)
6
5
4
3
2
1
0(LSB)
CMDR
Command register
00h
Write
W/R
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FLGS1
Primary status
flags register
01h
Read
CHGS
BRP
BRM
CI
VDQ
n/u
EDV1
EDVF
Temperature
TMPGG and gas gauge
register
02h
Read
TMP3
TMP2
TMP1
TMP0
GG3
GG2
GG1
GG0
NACH
Nominal available charge
high byte register
03h
R/W
NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
NACL
Nominal available charge
low byte register
17h
Read
NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
BATID
Battery
identification
register
04h
R/W
BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
LMD
Last measured
discharge register
05h
R/W
LMD7
LMD6
LMD5
LMD4
LMD3
LMD2
LMD1
LMD0
FLGS2
Secondary
status flags
register
06h
Read
CR
DR2
DR1
DR0
n/u
n/u
n/u
OVLD
PPD
Program pin
pull-down register
07h
Read
n/u
n/u
PPD6
PPD5
PPD4
PPD3
PPD2
PPD1
PPU
Program pin
pull-up register
08h
Read
n/u
n/u
PPU6
PPU5
PPU4
PPU3
PPU2
PPU1
CPI
Capacity
inaccurate
count register
09h
Read
CPI7
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
CPI0
DMF
Digital magnitude filter register
0ah
R/W
DMF7
DMF6
DMF5
DMF4
DMF3
DMF2
DMF1
DMF0
RST
Reset register
39h
Write
RST
0
0
0
0
0
0
0
Note:
n/u = not used
10
bq2010
tected after the EDV1 flag is asserted. BRP = 1 signifies
that the device has been reset.
The W/R values are:
CMDR Bits
The BRP values are:
7
6
5
4
3
2
1
0
W/R
-
-
-
-
-
-
-
FLGS1 Bits
Where W/R is:
0
The bq2010 outputs the requested register
contents specified by the address portion of
CMDR.
1
The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.
-
5
AD6 AD5
5
4
3
2
1
0
-
BRP
-
-
-
-
-
-
4
3
2
1
0
AD4
AD3
AD2
AD1
AD0
(LSB)
FLGS1 Bits
5
4
3
2
1
0
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
BRM
-
-
-
-
-
0
0.1V < VSB < 2.25V
1
0.1 V > VSB or VSB > 2.25V
The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2010 is reset. The flag is cleared
after an LMD update.
The CHGS values are:
-
VSB dropping from above MCV, VSB rising
from below 0.1V, or a serial port initiated
reset has occurred
Where BRM is:
The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when VSRO > VSRQ. A VSRO of less than VSRQ or
discharge activity clears CHGS.
6
1
FLGS1 Bits
The read-only FLGS1 register (address=01h) contains
the primary bq2010 flags.
7
Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted
The BRM values are:
Primary Status Flags Register (FLGS1)
CHGS
0
The battery removed flag (BRM) is asserted whenever
the potential on the SB pin (relative to VSS) rises above
MCV or falls below 0.1V. The BRM flag is asserted until
the condition causing BRM is removed.
CMDR Bits
6
6
Where BRP is:
The following eight bits should be written
to the register specified by the address portion of CMDR.
7
7
The CI values are:
FLGS1 Bits
Where CHGS is:
0
Either discharge activity detected or VSRO <
VSRQ
1
VSRO > VSRQ
7
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
Where CI is:
The battery replaced flag (BRP) is asserted whenever
the potential on the SB pin (relative to VSS), VSB, falls
from above the maximum cell voltage, MCV (2.25V), or
rises above 0.1V. The BRP flag is also set when the
bq2010 is reset (see the RST register description). BRP
is reset when either a valid charge action increments
NAC to be equal to LMD, or a valid charge action is de-
11
0
When LMD is updated with a valid full discharge
1
After the 64th valid charge action with no
LMD updates or the bq2010 is reset
bq2010
The EDVF values are:
The valid discharge flag (VDQ) is asserted when the
bq2010 is discharged from NAC=LMD. The flag remains
set until either LMD is updated or one of three actions
that can clear VDQ occurs:
n
n
n
FLGS1 Bits
The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EDVF
Where EDVF is:
A valid charge action sustained at VSRO > VSRQ for at
least 256 NAC counts.
The EDV1 flag was set at a temperature below 0°C
0
Valid charge action detected, VSB ≥ 0.95V
1
VSB < 0.95V providing that OVLD=0 (see
FLGS2 register description)
The VDQ values are:
Temperature and Gas Gauge Register
(TMPGG)
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
-
VDQ
-
-
-
The read-only TMPGG register (address=02h) contains
two data fields. The first field contains the battery temperature. The second field contains the available charge
from the battery.
Where VDQ is:
0
SDCR ≥ 4096, subsequent valid charge action detected, or EDV1 is asserted with the
temperature less than 0°C
1
On first discharge after NAC = LMD
TMPGG Temperature Bits
7
6
5
TMP3 TMP2
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG1, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has
been detected.
4
TMP1 TMP0
3
2
1
-
-
-
0
The bq2010 contains an internal temperature sensor.
The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient.
The temperature register contents may be translated as
shown below.
The EDV1 values are:
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EDV1
-
Where EDV1 is:
0
1
Valid charge action detected, VSB ≥ 1.05V
VSB < 1.05V providing that OVLD=0 (see
FLGS2 register description)
The final end-of-discharge warning flag (EDVF) is
used to warn that battery power is at a failure condition.
All segment drivers are turned off. The EDVF flag is
latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDVF. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery.
12
TMP3
TMP2
TMP1
TMP0
Temperature
0
0
0
0
T < -30°C
0
0
0
1
-30°C < T < -20°C
0
0
1
0
-20°C < T < -10°C
0
0
1
1
-10°C < T < 0°C
0
1
0
0
0°C < T < 10°C
0
1
0
1
10°C < T < 20°C
0
1
1
0
20°C < T < 30°C
0
1
1
1
30°C < T < 40°C
1
0
0
0
40°C < T < 50°C
1
0
0
1
50°C < T < 60°C
1
0
1
0
60°C < T < 70°C
1
0
1
1
70°C < T < 80°C
1
1
0
0
T > 80°C
bq2010
The bq2010 calculates the available charge as a function
of NAC, temperature, and a full reference, either LMD
or PFC. The results of the calculation are available via
the display port or the gas gauge field of the TMPGG
register. The register is used to give available capacity
in 1 16 increments from 0 to 15 16.
7
-
6
-
TMPGG Gas Gauge Bits
5
4
3
2
GG3 GG2
1
GG1
of the battery from full to empty. In this way the
bq2010 updates the capacity of the battery. LMD is set
to PFC during a bq2010 reset.
Secondary Status Flags Register (FLGS2)
The read-only FLGS2 register (address=06h) contains
the secondary bq2010 flags.
0
GG0
The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.
The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature dependencies. A piece-wise correction is performed as follows:
Temperature
> 0°C
-20°C < T < 0°C
< -20°C
The CR values are:
7
CR
Available Capacity Calculation
NAC / “Full Reference”
0.75 * NAC / “Full Reference”
0.5 * NAC / “Full Reference”
6
-
5
-
FLGS2 Bits
4
3
-
2
-
1
-
0
-
Where CR is:
The adjustment between > 0°C and -20°C < T < 0°C has
a 10°C hysteresis.
0
When charge rate falls below 2 counts/sec
1
When charge rate is above 2 counts/sec
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency factors are used. The time to change CR varies due to the
user-selectable count rates.
Nominal Available Charge Registers
(NACH/NACL)
The discharge rate flags, DR2–0, are bits 6–4.
The read/write NACH high-byte register (address=03h)
and the read-only NACL low-byte register (address=17h)
are the main gas gauging register for the bq2010. The
NAC registers are incremented during charge actions
and decremented during discharge and self-discharge
actions. The correction factors for charge/discharge efficiency are applied automatically to NAC.
7
-
FLGS2 Bits
5
4
3
DR1
DR0
-
6
DR2
2
-
1
-
0
They are used to determine the current discharge regime as follows:
On reset, if PROG6 = Z or low, NACH and NACL are
cleared to 0; if PROG6 = high, NACH = PFC and NACL
= 0. When the bq2010 detects a valid charge, NACL resets
to 0. Writing to the NAC registers affects the available
charge counts and, therefore, affects the bq2010 gas gauge
operation. Do not write the NAC registers to a value greater
than LMD.
DR2
0
0
DR1
0
0
DR0
0
1
VSR (V)
VSR > -150mV
VSR < -150mV
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSR < -250mV. OVLD remains asserted as long as the condition persists and is cleared
0.5 seconds after VSR > -250mV. The overload condition
is used to stop sampling of the battery terminal characteristics for end-of-discharge determination. Sampling is reenabled 0.5 secs after the overload condition is removed.
Battery Identification Register (BATID)
The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as
VCC is greater than 2V. The contents of BATID have no
effect on the operation of the bq2010. There is no default setting for this register.
7
-
Last Measured Discharge Register (LMD)
LMD is a read/write register (address=05h) that the
bq2010 uses as a measured full reference. The bq2010
adjusts LMD based on the measured discharge capacity
13
6
-
5
-
FLGS2 Bits
4
3
-
2
-
1
-
0
OVLD
bq2010
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which
this measurement is made varies with device activity.
Digital Magnitude Filter (DMF)
The read-write DMF register (address = 0ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different values into this register, the limits of VSRD and VSRQ can be
adjusted.
Program Pin Pull-Down Register (PPD)
The read-only PPD register (address=07h) contains
some of the programming pin information for the
bq2010. The segment drivers, SEG1–6, have a corresponding PPD register location, PPD1–6. A given location is set if a pull-down resistor has been detected on
its corresponding segment driver. For example, if SEG1
and SEG4 have pull-down resistors, the contents of
PPD are xx001001.
Note: Care should be taken when writing to this register. A VSRD and VSRQ below the specified VOS may adversely affect the accuracy of the bq2010. Refer to Table
4 for recommended settings for the DMF register.
Reset Register (RST)
The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. By
writing the RST register contents from 00h to 80h, a
bq2010 reset is performed. Setting any bit other than the
most-significant bit of the RST register is not allowed,
and results in improper operation of the bq2010.
PPD/PPU Bits
7
6
5
4
3
2
1
0
-
-
PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
-
-
PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
Resetting the bq2010 sets the following:
n
LMD = PFC
n
CPI, VDQ, NACH, and NACL = 0
n
CI and BRP = 1
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the
rest of the programming pin information for the bq2010.
The segment drivers, SEG1–6, have a corresponding PPU
register location, PPU1–6. A given location is set if a pullup resistor has been detected on its corresponding segment
driver. For example, if SEG3 and SEG6 have pull-up resistors, the contents of PPU are xx100100.
Note: NACH = PFC when PROG6 = H. Self-discharge is
disabled when PROG5 = H
Display
The bq2010 can directly display capacity information
using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a program high or program low, respectively.
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to indicate the number of times a battery has been charged without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the
bq2010 adapts to the changing capacity over time. A complete discharge from full (NAC=LMD) to empty (EDV1=1)
is required to perform an LMD update assuming there
have been no intervening valid charges, the temperature is
greater than or equal to 0°C, and the self-discharge counter is less than 4096 counts.
The bq2010 displays the battery charge state in either
absolute or relative mode. In relative mode, the battery
charge is represented as a percentage of the LMD. Each
LED segment represents 20% of the LMD. The sixth
segment, SEG6, is not used.
In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
mode, each segment represents 20% of the PFC, with
SEG6 representing “overfull” (charge above the PFC).
As the battery wears out over time, it is possible for the
LMD to be below the initial PFC. In this case, all of the
LEDs may not turn on in absolute mode, representing
the reduction in the actual battery capacity.
The CPI register is incremented every time a valid
charge is detected. When NAC > 0.94 * LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 * LMD. This prevents continuous trickle
charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
The capacity display is also adjusted for the present battery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does not
affect the NAC register. The temperature adjustments are
detailed in the TMPGG register description.
When DISP is tied to VCC, the SEG1–6 outputs are inactive.
When DISP is left floating, the display becomes active
14
bq2010
SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables
the display output.
whenever the NAC registers are counting at a rate equivalent to |VSRO| ≥ 4mV. When pulled low, the segment outputs become active immediately. A capacitor tied to DISP
allows the display to remain active for a short period of
time after activation by a push-button switch.
Microregulator
The segment outputs are modulated as two banks of
three, with segments 1, 3, and 5 alternating with segments 2, 4, and 6. The segment outputs are modulated
at approximately 100Hz with each segment bank active
for 30% of the period.
The bq2010 can operate directly from 3 or 4 cells. To facilitate the power supply requirements of the bq2010, an
REF output is provided to regulate an external lowthreshold n-FET. A micropower source for the bq2010
can be inexpensively built using the FET and an external resistor; see Figure 1.
Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
Notes
VCC
Relative to VSS
-0.3
+7.0
V
All other pins
Relative to VSS
-0.3
+7.0
V
REF
Relative to VSS
-0.3
+8.5
V
Current limited by R1 (see Figure 1)
VSR
Relative to VSS
-0.3
+7.0
V
Minimum 100Ω series resistor should
be used to protect SR in case of a
shorted battery (see the bq2010 application note for details).
TOPR
Operating temperature
0
+70
°C
Commercial
-40
+85
°C
Industrial
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V)
Minimum
Typical
Maximum
Unit
VEDVF
Symbol
Final empty warning
0.93
0.95
0.97
V
SB
VEDV1
First empty warning
1.03
1.05
1.07
V
SB
VSR1
Discharge compensation threshold
-120
-150
-180
mV
SR, VSR + VOS
VSRO
SR sense range
-300
-
+2000
mV
SR, VSR + VOS
VSRQ
Valid charge
375
-
-
µV
VSR + VOS (see note)
VSRD
Valid discharge
-
-
-300
µV
VSR + VOS (see note)
VMCV
Maximum single-cell voltage
2.20
2.25
2.30
V
SB
VBR
-
0.1
0.25
V
SB pulled low
Battery removed/replaced
2.20
2.25
2.30
V
SB pulled high
Note:
Parameter
Notes
Default value; value set in DMF register. VOS is affected by PC board layout. Proper layout guidelines
should be followed for optimal performance. See “LayoutConsiderations.”
15
bq2010
DC Electrical Characteristics (TA = TOPR)
Symbol
VCC
VREF
Parameter
Minimum
Typical
Maximum
Unit
Notes
Supply voltage
3.0
4.25
6.5
V
VCC excursion from < 2.0V to ≥
3.0V initializes the unit.
Reference at 25°C
5.7
6.0
6.3
V
IREF = 5µA
Reference at -40°C to +85°C
4.5
-
7.5
V
IREF = 5µA
RREF
Reference input impedance
2.0
5.0
-
MΩ
VREF = 3V
-
90
135
µA
VCC = 3.0V, DQ = 0
ICC
Normal operation
-
120
180
µA
VCC = 4.25V, DQ = 0
-
170
250
µA
VCC = 6.5V, DQ = 0
VSB
Battery input
0
-
VCC
V
RSBmax
SB input impedance
10
-
-
MΩ
IDISP
DISP input leakage
-
-
5
µA
VDISP = VSS
ILCOM
LCOM input leakage
-0.2
-
0.2
µA
DISP = VCC
RDQ
Internal pulldown
500
-
-
KΩ
VSR
Sense resistor input
-0.3
-
2.0
V
RSR
SR input impedance
VIH
Logic input high
VIL
Logic input low
VIZ
Logic input Z
VOLSL
10
-
-
MΩ
VCC - 0.2
-
-
V
0 < VSB < VCC
VSR < VSS = discharge;
VSR > VSS = charge
-200mV < VSR < VCC
PROG1–PROG6
-
-
VSS + 0.2
V
PROG1–PROG6
float
-
float
V
PROG1–PROG6
SEGX output low, low VCC
-
0.1
-
V
VCC = 3V, IOLS ≤ 1.75mA
SEG1–SEG6
VOLSH
SEGX output low, high VCC
-
0.4
-
V
VCC = 6.5V, IOLS ≤ 11.0mA
SEG1–SEG6
VOHLCL
LCOM output high, low VCC
VCC - 0.3
-
-
V
VCC = 3V, IOHLCOM = -5.25mA
VOHLCH
LCOM output high, high VCC
VCC - 0.6
-
-
V
VCC = 6.5V, IOHLCOM = -33.0mA
IIH
PROG1-6 input high current
-
1.2
-
µA
VPROG = VCC/2
IIL
PROG1-6 input low current
-
1.2
-
µA
VPROG = VCC/2
-33
-
-
mA
At VOHLCH = VCC - 0.6V
-
-
11.0
mA
At VOLSH = 0.4V
At VOL = VSS + 0.3V
DQ, EMPTY
IOHLCOM LCOM source current
IOLS
SEGX sink current
IOL
Open-drain sink current
-
-
5.0
mA
VOL
Open-drain output low
-
-
0.5
V
IOL ≤ 5mA, DQ, EMPTY
VIHDQ
DQ input high
2.5
-
-
V
DQ
VILDQ
DQ input low
-
-
0.8
V
DQ
RPROG
Soft pull-up or pull-down resistor value (for programming)
-
-
200
KΩ
PROG1–PROG6
RFLOAT
Float state external impedance
-
5
-
MΩ
PROG1–PROG6
16
bq2010
Serial Communication Timing Specification (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYCH
Cycle time, host to bq2010
3
-
-
ms
tCYCB
Cycle time, bq2010 to host
3
-
6
ms
tSTRH
Start hold, host to bq2010
5
-
-
ns
tSTRB
Start hold, bq2010 to host
500
-
-
µs
tDSU
Data setup
-
-
750
µs
tDH
Data hold
750
-
-
µs
tDV
Data valid
1.50
-
-
ms
tSSU
Stop setup
-
-
2.25
ms
tSH
Stop hold
700
-
-
µs
tSV
Stop valid
2.95
-
-
ms
tB
Break
3
-
-
ms
tBR
Break recovery
1
-
-
ms
Note:
Notes
See note
The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation. DQ
may be left floating if the serial interface is not used.
Serial Communication Timing Illustration
DQ
(R/W 1 )
V
V
DQ
(R/W 0 )
V
V
tSTRH
tSTRB
tDH
tDSU
tDV
DQ
(BREAK)
tSSU
tSV
tCYCH, tCYCB, tB
tSH
tBR
TD201002.eps
17
bq2010
16-Pin SOIC Narrow (SN)
16-Pin SN (SOIC Narrow)
D
e
Dimension
Minimum
A
0.060
A1
0.004
B
0.013
C
0.007
D
0.385
E
0.150
e
0.045
H
0.225
L
0.015
All dimensions are in inches.
B
E
H
A
C
A1
.004
L
18
Maximum
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
bq2010
Data Sheet Revision History
Change No.
Page No.
Description
3
4
EDV monitoring
3
6
Table 1, PROG5
3
7,8
Self-discharge
3
11
Capacity inaccurate
Nature of Change
Was:
EDV monitoring is disabled if VSR ≤ -150mV;
Is:
EDV monitoring is disabled if VSR ≤ -250mV
Was:
PROG5 = H = Reserved;
Is:
PROG5 = H = Disable self-discharge
Add:
or disabled as selected by PROG5
Correction: CI is asserted on the 64th charge after the
last LMD update or when the bq2010 is reset
3
13
Nominal available charge
register
NACL stops counting when NACH reaches zero
Was:
Is:
Notes:
Changes 1 and 2; please refer to the 1995 Data Book.
Change 3 = Apr. 1995 D changes from Mar. 1994 C.
3
13
Overload flag
VSR < -150mV
VSR < -250mV
Ordering Information
bq2010
Temperature Range:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2010 Gas Gauge IC
* Contact factory for availability.
19
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