AD AD8120ACPZ-R7 Triple skew-compensating video delay line with analog and digital control Datasheet

Triple Skew-Compensating Video Delay
Line with Analog and Digital Control
AD8120
FEATURES
GENERAL DESCRIPTION
Corrects for unshielded twisted pair (UTP) cable skew
Delay of up to 50 ns per channel
High speed
200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay
150 MHz BW @ VOUT = 1.4 V p-p and 50 ns delay
Excellent channel-to-channel matching
30 mV offset matching RTI
0.8% gain matching
Low output offset
±30 mV RTI
No external circuitry required to correct for offsets
Independent red, green, and blue delay controls
Drives 4 double-terminated video loads
Digital and analog delay control
6-bit SPI bus
I2C bus
Analog voltage control
Fixed gain of 2
Low noise
High differential input impedance: 500 kΩ
32-lead, 5 mm × 5 mm LFCSP
The AD8120 is a triple broadband skew-compensating delay line
that corrects for time mismatch between video signals incurred
by transmission in unshielded twisted pairs of Category 5 and
Category 6 type cables. Skew between the individual pairs exists
in most types of multipair UTP cables due to the different twist
rates that are used for each pair to minimize crosstalk between
pairs. For this reason, some pairs are longer than others, and in
long cables, the difference in propagation time between two pairs
can be well into the tens of nanoseconds.
The AD8120 contains three delay paths that provide broadband
delays up to 50 ns, in 0.8 ns increments, using 64 digital control
steps or analog control adjustment. The delay technique used in
the AD8120 minimizes noise and offset at the outputs.
The bandwidth of the AD8120 ranges from 150 MHz to 200 MHz,
depending on the delay setting. This wide bandwidth makes the
AD8120 ideal for use in applications that receive high resolution
video over UTP cables.
The logic circuitry of the AD8120 provides individual delay controls for each channel. The delay times are set independently
using a standard 4-wire SPI bus or a standard I2C bus, or by
applying analog control voltages to the VCR, VCG, and VCB pins.
Analog control offers a simple solution for systems that do not
have digital control available.
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cable
Professional video projection and distribution
HD video
Security video
General broadband delay lines
The AD8120 is designed to be used with the AD8123 triple
UTP equalizer in video over UTP applications, but it can
also be used in other applications where similar controllable
broadband delays are required.
The AD8120 is available in a 5 mm × 5 mm, 32-lead LFCSP
and is rated to operate over the industrial temperature range
of −40°C to +85°C.
R
d
G
d
B
d
07839-001
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD8120
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation .........................................................................9
General Description ......................................................................... 1
Controlling the Delay ...................................................................9
Functional Block Diagram .............................................................. 1
Setting the Delay............................................................................9
Revision History ............................................................................... 2
Analog Control ........................................................................... 10
Specifications..................................................................................... 3
Digital Control ............................................................................ 10
Absolute Maximum Ratings............................................................ 5
Applications Information .............................................................. 14
Thermal Resistance ...................................................................... 5
Typical Application Circuit for the AD8123 and AD8120 ... 14
Maximum Power Dissipation ..................................................... 5
Outline Dimensions ....................................................................... 16
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 16
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
7/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8120
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, 10% to 90% input rise/fall time (tR/tF) = 4 ns, unless otherwise noted.
Table 1.
Parameter
DELAY CHARACTERISTICS
Total Adjustable Delay Range
Delay Resolution
Propagation Delay
Channel-to-Channel Delay Error
DYNAMIC PERFORMANCE
−3 dB Video Signal Bandwidth
−3 dB Small-Signal Bandwidth
0.1 dB Video Signal Flatness
10% to 90% Rise/Fall Time
Settling Time to 1%
Slew Rate
Overshoot
Gain
Channel-to-Channel Gain Matching
Hostile Crosstalk
VIDEO INPUT CHARACTERISTICS
Input Bias Current
Input Capacitance
Input Resistance
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Integrated Output Noise
Output Offset Voltage (RTI)
Channel-to-Channel Output Offset Voltage
Matching (RTI)
Output Impedance
ANALOG CONTROL INPUT CHARACTERISTICS
Input Bias Current
Operating Range
Delay Voltage Step Size in Linear Range
Test Conditions/Comments
Min
Typ
Max
Unit
Delay Code 63 to Delay Code 0
Monotonic, 1 LSB
Delay = 0 ns
All channels at maximum delay
50
0.8
4.9
0.4
ns
ns
ns
ns
VOUT = 1.4 V p-p, delay = 0 ns
VOUT = 1.4 V p-p, delay = 50 ns
VOUT = 0.2 V p-p, delay = 0 ns
VOUT = 0.2 V p-p, delay = 50 ns
VOUT = 1.4 V p-p, delay = 0 ns
VOUT = 1.4 V p-p, delay = 50 ns
VOUT = 1.4 V step, delay = 0 ns
VOUT = 1.4 V step, delay = 50 ns
VOUT = 1.4 V step, delay = 0 ns
VOUT = 1.4 V step, delay = 50 ns
VOUT = 1.4 V step, delay = 0 ns, rising edge
VOUT = 1.4 V step, delay = 0 ns, falling edge
VOUT = 1.4 V step, delay = 50 ns, rising edge
VOUT = 1.4 V step, delay = 50 ns, falling edge
VOUT = 1.4 V step, delay = 0 ns
VOUT = 1.4 V step, delay = 50 ns
0 ns to 50 ns delay
Over all codes, among all channels
Measured on G with R and B driven at 1 MHz,
VOUT = 1.4 V p-p, delay = 0 ns
RIN, GIN, BIN
200
150
165
140
27
35
2.5/3
3/4.2
8
18
550
540
510
360
1
20
2.01
0.8
−80
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
V/μs
V/μs
V/μs
V/μs
%
%
V/V
%
dB
1.95
0.8
1
500
2.06
3
1.5
μA
pF
kΩ
ROUT, GOUT, BOUT
100 kHz to 160 MHz
Delay = 0 ns
Delay = 50 ns
Over all codes
Over all codes, among all channels
−30
Rev. 0 | Page 3 of 16
V
mA
1
4
0
30
mV rms
mV rms
mV
mV
+30
1.5
PD high, at 20 MHz
VCR, VCG, VCB
VCR, VCG, VCB
ΔVCR, ΔVCG, ΔVCB to move one delay LSB
±3.25
50
Ω
1
0
2
28
μA
V
mV
AD8120
Parameter
DIGITAL CONTROL INPUT CHARACTERISTICS
Input Bias Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SPI TIMING CHARACTERISTICS
Clock Frequency
CS Setup Time, t1
Clock Pulse High, t2
Clock Pulse Low, t3
Data Setup Time, t4
Data Hold Time, t5
CS Hold Time, t6
I2C TIMING CHARACTERISTICS
Clock Frequency
Start Setup Time, t1
Clock Pulse High, t2
Clock Pulse Low, t3
Data Setup Time, t4
Data Hold Time, t5
Hold Time, t6
POWER SUPPLY
Positive Supply Range
Negative Supply Range
Positive Quiescent Current
Negative Quiescent Current
Quiescent Current Drift
+PSRR
−PSRR
Test Conditions/Comments
SDO/SDA, SCK/SCL, SDI/A1, CS/A0, SER_SEL,
MODE
Min
Typ
Max
2
2.6
0.6
4.5
0.6
SCK
CS to SCK
SCK
SCK
SDI to SCK
SDI to SCK
SCK to CS
5
50
50
5
5
5
SCL
SDA to SCL
SCL
SCL
SDA (input) to SCL
SDA (input) to SCL
SCL to SDA
10
5
5
100
100
10
4.5
−5.5
Delay = 0 ns
Delay = 50 ns
Powered down, PD low
Delay = 0 ns
Delay = 50 ns
Powered down, PD low
TMIN to TMAX, delay = 0 ns
TMIN to TMAX, delay = 50 ns
RL = 150 Ω, delay = 50 ns
RL = 150 Ω, delay = 50 ns
Rev. 0 | Page 4 of 16
44
114
4
37
108
0.5
0.13
0.36
56
44
Unit
μA
V
V
V
V
10
MHz
ns
ns
ns
ns
ns
ns
100
kHz
ns
μs
μs
ns
ns
ns
5.5
−4.5
V
V
mA
mA
mA
mA
mA
mA
mA/°C
mA/°C
dB
dB
AD8120
ABSOLUTE MAXIMUM RATINGS
Rating
±6 V
3.5 W
VS− − 0.3 V to VS+ + 0.3 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation by reducing θJA.
To ensure optimal thermal performance, the exposed paddle
must be in an optimized thermal connection with an external
plane layer.
6
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
5 mm × 5 mm, 32-Lead LFCSP
θJA
36
θJC
2
Unit
°C/W
5
4
3
2
1
0
–40
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
07839-002
Parameter
Supply Voltage
Internal Power Dissipation
32-Lead LFCSP at TA = 25°C
Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (VS+
and VS−) times the quiescent current (IS). Power dissipated due
to load drive depends upon the particular application. It is calculated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
MAXIMUM POWER DISSIPATION (W)
Table 2.
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
on a JEDEC Standard 4-Layer Board
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8120 package is
limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by
the glass transition temperature of the plastic, is approximately
150°C. Temporarily exceeding this limit may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
ESD CAUTION
Rev. 0 | Page 5 of 16
AD8120
GND
25 VS+
26 RIN
27 GIN
28 BIN
29 SDI/A1
30 SCK/SCL
31 CS/A0
32 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DNC
3
DNC
4
PD
5
AD8120
B
SER_SEL 6
ANALOG
CONTROL
24 GND
DIGITAL
CONTROL
1
SDO/SDA 2
G
d
22 VCG
21 VCB
20 VREF
R
d
23 VCR
19 DNC
d
TOP VIEW
(Not to Scale)
NOTES
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD ON UNDERSIDE OF DEVICE
MUST BE CONNECTED TO PCB PLANE.
07839-003
VS+ 16
GND 14
VS–
ROUT 15
17 VS+
GOUT 13
8
GND 12
GND
BOUT 11
18 GND
9
7
GND 10
MODE
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 8, 10, 12, 14,
18, 24, 32
2
3, 4, 19
5
6
7
9
11
13
15
16, 17, 25
20
21
22
23
26
27
28
29
30
31
Exposed Pad
Mnemonic
GND
Description
Ground.
SDO/SDA
DNC
PD
SER_SEL
MODE
VS−
BOUT
GOUT
ROUT
VS+
VREF
VCB
VCG
VCR
RIN
GIN
BIN
SDI/A1
SCK/SCL
CS/A0
EP
Serial Data Output for SPI Bus/Bidirectional Serial Data Line for I2C Bus.
Do Not Connect.
Power-Down.
Selection of SPI Serial Bus or I2C Serial Bus (I2C = 0, SPI = 1).
Selection of Analog Control Mode or Digital Control Mode (Digital = 0, Analog = 1).
Negative Power Supply. Connect to −5 V.
Blue Channel Video Output.
Green Channel Video Output.
Red Channel Video Output.
Positive Power Supply. Connect to +5 V.
Internal Reference Bypass. Connect a 0.01 μF capacitor between this pin and GND.
Analog Delay Control Voltage, Blue Channel.
Analog Delay Control Voltage, Green Channel.
Analog Delay Control Voltage, Red Channel.
Red Channel Video Input.
Green Channel Video Input.
Blue Channel Video Input.
Serial Data Input for SPI Bus/I2C Address Bit 1.
Serial Clock for SPI Bus/Serial Clock for I2C Bus.
Chip Select for SPI Bus/I2C Address Bit 0.
Thermal Plane Connection. Connect the exposed pad on the underside of the AD8120 to any PCB
plane with voltage between VS+ and VS−.
Rev. 0 | Page 6 of 16
AD8120
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, 10% to 90% input rise/fall time (tR/tF) = 4 ns, unless otherwise noted.
6
4
DELAY CODE = 33
4
DELAY CODE = 33
2
0
–2
NORMALIZED GAIN (dB)
DELAY CODE = 1
DELAY CODE = 2
–4
–6
–8
0
–2
DELAY CODE = 1
–4
DELAY CODE = 2
–6
–8
–10
1
10
FREQUENCY (MHz)
100
1k
–12
0.3
07839-010
–12
0.3
Figure 4. Small-Signal Frequency Response for Various Delay Settings,
VOUT = 0.2 V p-p
0.25
DELAY CODE = 0
10
FREQUENCY (MHz)
100
1k
Figure 7. Video Signal Frequency Response for Various Delay Settings,
VOUT = 1.4 V p-p
1.8
DELAY CODE = 33
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 0
1.6
0.20
DELAY CODE = 63
1.4
1.2
0.15
AMPLITUDE (V)
INPUT
0.10
0.05
1.0
INPUT
0.8
0.6
0.4
0.2
0
VS = ±5V
LOAD = 150Ω
0
0
20
40
60
TIME (ns)
80
100
120
–0.2
–20
07839-012
–0.05
–20
Figure 5. Small-Signal Pulse Response for Various Delay Settings
1
50
1
07839-011
–10
12
22
DELAY CODE
33
44
VS = ±5V, LOAD = 150Ω
0
20
40
60
TIME (ns)
80
100
120
07839-013
NORMALIZED GAIN (dB)
2
AMPLITUDE (V)
DELAY CODE = 63
DELAY CODE = 63
Figure 8. Large-Signal Pulse Response for Various Delay Settings
120
55
62
110
QUIESCENT CURRENT (mA)
45
35
30
25
20
15
100
THREE CHANNELS
90
80
TWO CHANNELS
70
60
50
5
40
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ANALOG CONTROL VOLTAGE (V)
1.8
2.0
Figure 6. Relative Delay vs. Delay Code and Analog Control Voltage
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
DELAY CODE
Figure 9. Quiescent Current vs. Delay Code
Rev. 0 | Page 7 of 16
07839-018
ONE CHANNEL
10
07839-021
RELATIVE DELAY (ns)
40
AD8120
20
–20
OUTPUT LEVEL (dB)
–30
–40
DELAY CODE = 63
–50
–60
–70
–80
DELAY CODE = 0
–90
1
10
FREQUENCY (MHz)
100
1k
0
–10
–20
–30
VS+ PSRR AT DELAY CODE 0
VS+ PSRR AT DELAY CODE 63
VS– PSRR AT DELAY CODE 0
VS– PSRR AT DELAY CODE 63
–40
–50
0.3
07839-014
–100
0.3
10
1
Figure 10. Crosstalk on Green Channel vs. Frequency,
VOUT = 1.4 V p-p
INTEGRATED OUTPUT VOLTAGE NOISE (mV rms)
DELAY CODE = 63
DELAY CODE = 0
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
07839-016
OUTPUT VOLTAGE NOISE DENSITY (nV/ Hz)
1k
10
10
100
1k
Figure 13. PSRR vs. Frequency
10k
100
10
FREQUENCY (MHz)
Figure 11. Output Voltage Noise Density vs. Frequency
5
4
3
2
1
0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
DELAY CODE
07839-017
–10
POWER SUPPLY REJECTION RATIO (dB)
DRIVING R AND B SIMULTANEOUSLY
MEASURING G
07839-015
0
Figure 14. Integrated Output Voltage Noise vs. Delay Code,
100 kHz to 160 MHz
5
160
VS+, RGB DELAY CODE 63
140
QUIESCENT CURRENT (mA)
3
TYPICAL RISE TIME
2
1
120
100
80
60
40
20
0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
DELAY CODE
VS+, DISABLED
0
–40 –30 –20 –10
07839-019
RISE/FALL TIME (ns)
4
VS+, RG DELAY CODE 63, B DELAY CODE 0
VS+, R DELAY CODE 63, GB DELAY CODE 0
Figure 12. 10% to 90% Rise/Fall Time vs. Delay Code,
VOUT = 1.4 V p-p, VIN Rise/Fall = 2 ns
0
VS+, RGB DELAY CODE 0
10 20 30 40 50
TEMPERATURE (°C)
60
70
Figure 15. Quiescent Current vs. Temperature
Rev. 0 | Page 8 of 16
80
90
07839-020
TYPICAL FALL TIME
AD8120
THEORY OF OPERATION
The AD8120 is a triple, digitally controlled analog delay line,
optimized for correcting delay skew between individual channels
in common wired communication media such as unshielded
twisted pair (UTP), shielded twisted pair (STP), and coaxial
cables. In these applications, the AD8120 is used to time-align
three video signals, usually RGB or YPbPr, that arrive at a
receiver at different times due to variations in total delay per
channel. Although its primary application is analog video, the
AD8120 can be applied in other systems that require variable
analog delays up to 50 ns with 0.8 ns resolution.
The three channels consist of cascaded delay sections that are
switched in such a way as to provide a total of 50 ns total delay
difference between channels with 0.8 ns resolution. A fixed
propagation delay is common to all channels, where the associated
delay is set to 0. Therefore, the delay setting for a given channel is
a measure of the relative delay among the channels, rather than
an absolute delay.
There are three options for controlling the delay: serial peripheral interface (SPI) serial bus, I2C serial bus, and analog control
voltage. Two pins select the type of control: the MODE pin selects
analog or digital control, and the SER_SEL pin selects the SPI or
I2C serial bus (see Table 5).
Table 5. Modes of Control
0
1
1
1
MODE (Pin 7)
X
0
0
1
SER_SEL (Pin 6)
X
0
1
X
Control Type
Power-down
I2C control
SPI control
Analog control
In analog control mode, three control voltages, VCR, VCG, and
VCB, control the delay of each channel. These voltages are
converted internally to digital codes with 0.8 ns steps.
It is important to note that in skew correction applications, the
metric is the relative delay between channels, not the absolute
delay. Each channel of the AD8120 exhibits a constant delay at
its zero delay setting, referred to as its propagation delay. This
propagation delay is well matched between the channels and is
subtracted out when performing skew correction. The delay
codes, therefore, ignore the constant propagation delay and
refer only to adjustable delay beyond the propagation delay.
Delay can be calculated by multiplying the delay code by 0.8 ns.
For example, setting the red delay to 8 ns (delay code = 10), the
green delay to 16 ns (delay code = 20), and the blue delay to 28 ns
(delay code = 35) produces the following relative delays: green
delayed by 8 ns relative to red, blue delayed by 20 ns relative to
red, and blue delayed by 12 ns relative to green. If an application
requires control of absolute delay, the propagation delay must be
added to the delay corresponding to the associated delay code.
SETTING THE DELAY
In most video skew compensation applications, it is best to set
the delay of the path with the longest delay to 0, and then to add
delay to the other paths to match the longest delay. In this way,
the bandwidth of each path is maximized, and the noise of each
path is minimized. Figure 16 illustrates a case where a test step
is applied simultaneously to each cable input, and the green
cable delay is the longest.
RED CABLE OUTPUT
Each AD8120 channel has a fixed overall gain of 2 and can
drive up to four double-terminated 75 Ω cables or PCB traces.
A power-down feature can shut down the AD8120 for power
saving when not in use.
GREEN CABLE OUTPUT
28ns
BLUE CABLE OUTPUT
40ns
CONTROLLING THE DELAY
The delay time of each of the three channels is controlled in one
of three ways. One control option is the application of analog
control voltages to the VCR, VCG, and VCB inputs. The other two
control options are via the SPI or I2C serial digital bus. The delay
is set in discrete amounts with a nominal resolution of 0.8 ns per
quantization level (or LSB), even in the analog control mode.
07839-022
PD (Pin 5)
A delay code is assigned to each quantization level, ranging from
0 to 63 in decimal format. The means of control (analog, SPI, or
I2C) is selected by applying the appropriate logic levels to the
MODE and SER_SEL inputs (see Table 5). All three channels
must use the same delay control option in a given application.
Figure 16. Cable Delay Example
In the example in Figure 16, the AD8120 green delay should be
set to 0. The AD8120 red delay is then set to the delay difference
between the green and red outputs, or 40 ns. Finally, the AD8120
blue delay is set to the delay difference between the green and blue
outputs, or 28 ns. Using the digital delay codes, green delay = 0,
red delay = 50, and blue delay = 35.
Rev. 0 | Page 9 of 16
AD8120
ANALOG CONTROL
SPI Control
A number of video transmission systems do not have a microcontroller embedded or otherwise available to provide digital control.
These systems require analog control. Potentiometer control is
one of the most common ways to implement analog control (see
Figure 25). To select analog control, set the MODE pin high.
The SPI bus operates in full-duplex mode and consists of four
digital lines: SDI, SDO, SCK, and CS.
Table 7. AD8120 SPI Pin Descriptions
Pin No.
29
2
30
31
The AD8120 has one analog control input for each channel: VCR,
VCG, and VCB. The maximum recommended control voltage range
on these inputs is 0 V to 2.0 V, although the actual control range
where delay changes take effect is smaller and lies within this larger
range. An internal ADC converts the analog control voltages
into binary delay codes; therefore, the analog control is discrete
with nominally 0.8 ns resolution. Figure 6 illustrates the typical
transfer characteristic between control voltage and delay code.
Set the MODE pin low to select digital control (SPI or I2C). Set
the SER_SEL pin high to select SPI mode, or set the SER_SEL
pin low to select I2C mode. Table 6 provides the bit values for
reading and writing the red, green, and blue registers.
Figure 17 shows how to write Delay Code 42 to the green
register. Figure 18 shows how to read Delay Code 21 from
the blue register.
Table 6. Read/Write Instruction and Color Registers
R/W Bit
C1 Bit
0
0
0
0
1
1
0
1
0
1
0
1
Description
Serial data input, master out slave in (MOSI)
Serial data output, master in slave out (MISO)
Serial clock from master
Chip select; active low
The AD8120 is programmed in SPI mode using a 2-byte sequence
(see Table 8). Data is clocked into the SDI pin or clocked out of
the SDO pin on the rising edge of the clock, MSB first. The first
byte contains the read/write (R/W) instruction and the color register address (see Table 6). The second byte contains the delay
code to write to the part (R/W = 0) or the stored delay code to
read from the part (R/W = 1).
DIGITAL CONTROL
Operation
Write Red
Read Red
Write Green
Read Green
Write Blue
Read Blue
Pin
Name
SDI
SDO
SCK
CS
C0 Bit
0
0
1
1
0
0
Table 8. SPI 2-Byte Sequence
Byte 1 (R/W Bit and Color Register)
Byte 2 (Data)
SDI
Bit 7
R/W
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
C1
Bit 0
C0
Bit 7
X
Bit 6
X
Bit 5
D5
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
SDO
X
X
X
X
X
X
X
X
X
X
D5
D4
D3
D2
D1
D0
Rev. 0 | Page 10 of 16
AD8120
CS
SDI
0
0
0
0
0
0
0
1
X
X
1
0
1
0
1
0
SDO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
START
BYTE 1
R/W BIT AND COLOR REGISTER
STOP
BYTE 2
DATA
07839-025
SCK
Figure 17. Setting the Green Register to Delay Code 42 Using SPI
CS
SDI
1
0
0
0
0
0
1
0
X
X
X
X
X
X
X
X
SDO
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
START
BYTE 1
R/W BIT AND COLOR REGISTER
BYTE 2
DATA
Figure 18. Reading Delay Code 21 from the Blue Register Using SPI
Rev. 0 | Page 11 of 16
STOP
07839-026
SCK
AD8120
I2C Control
Table 10. I2C Addresses
A1 Pin
0
0
1
1
2
The I C interface of the AD8120 is a 2-wire interface consisting
of a clock input and a bidirectional data line. The AD8120
drives the SDA line either to acknowledge the master (ACK) or
to send data during a read operation. The SDA pin for the I2C
port is open drain and requires a 10 kΩ pull-up resistor.
In I2C mode, the AD8120 is programmed with a 3-byte sequence
for a write operation (see Figure 19) and a 4-byte sequence for a
read operation (see Figure 20). The first byte contains the 7-bit
device address and the R/W instruction bit. The second byte contains the color register.
Table 9. AD8120 I2C Pin Descriptions
Pin No.
2
30
29
31
Pin Name
SDA
SCL
A1
A0
I2C Address
0x38
0x39
0x3A
0x3B
A0 Pin
0
1
0
1
Description
Serial data input/output
Serial clock input
I2C Address Bit A1
I2C Address Bit A0
In write mode, the third byte contains the delay code. In read
mode, the third byte contains the device address, and the fourth
byte contains the stored delay code.
The AD8120 address consists of a built-in address of 0x38 and the
two address pins, A0 and A1. The two address pins enable up to
four AD8120 devices to be used in a system (see Table 10). Both
address pins must be terminated (high or low) for the AD8120
I2C interface to operate properly.
R/W
1
9
1
9
SCL
0
SDA
1
1
1
0
A1
A0
0
0
0
0
0
0
0
C1
C0
ACK BY
AD8120
START BY
MASTER
ACK BY
AD8120
BYTE 1
I2C ADDRESS
BYTE 2
COLOR REGISTER
1
9
SCL (CONTINUED)
X
D5
D4
D2
D3
D1
D0
ACK BY
AD8120
BYTE 3
DELAY DATA CODE
STOP BY
MASTER
07839-023
X
SDA (CONTINUED)
Figure 19. I2C Write Sequence
R/W
1
9
1
9
SCL
SDA
0
1
1
1
0
A1
A0
0
0
0
0
0
0
0
C1
C0
ACK BY
AD8120
START BY
MASTER
ACK BY
AD8120
BYTE 1
I2C ADDRESS
BYTE 2
COLOR REGISTER
R/W
1
9
1
9
SCL
0
1
1
1
0
A1
A0
1
X
X
D5
D4
D3
D2
D1
ACK BY
AD8120
START BY
MASTER
BYTE 3
I2C ADDRESS
NO ACK BY
AD8120
BYTE 4
DATA BYTE FROM AD8120
Figure 20. I2C Read Sequence
Rev. 0 | Page 12 of 16
D0
STOP BY
MASTER
07839-024
SDA
AD8120
SPI Timing
I2C Timing
Figure 21 shows the SPI 2-byte timing sequence. Table 11 lists
the timing parameters for SPI.
Figure 23 shows the I2C 3-byte timing sequence. Table 12 lists
the timing parameters for I2C.
0
0
0
C1 C0
X
X
D5 D4 D3 D2 D1 D0
Figure 23. I2C 3-Byte Timing Sequence
t6
t4
CS
SDI
t2
R/W
t3
t4 t5
SDA
D1
D0
07839-006
SCK
D5
D4
D3
D2
D1
D0
ACK
SCL
Figure 21. SPI 2-Byte Timing Sequence
t1
X X
07839-007
0
0 0 0 0 0 0
SCL
Figure 22. SPI Timing Diagram
t1
t2 t
3
t5
Figure 24. I2C Timing Diagram
Table 11. SPI Timing Parameters
Table 12. I2C Timing Parameters
Parameter
t1
t2
t3
t4
t5
t6
Parameter
t1
t2
t3
t4
t5
t6
Description
Setup time, CS to SCK
Clock pulse high, SCK
Clock pulse low, SCK
Setup time, SDI to SCK
Hold time, SDI to SCK
Hold time, SCK to CS
t6
Rev. 0 | Page 13 of 16
Description
Setup time, SDA to SCL
Clock pulse high, SCL
Clock pulse low, SCL
Setup time, SDA (input) to SCL
Hold time, SDA (input) to SCL
Hold time, SCL to SDA
07839-008
0
07839-005
R/W
SDI/SDO
0 1 1 1 0
C1
C0
ACK
SDA
SCK
A1
A0
R/W
ACK
CS
AD8120
APPLICATIONS INFORMATION
Most twisted pair (TP) cables used for video transmission are
designed for data communication and typically contain four
individual TP channels. Minimization of crosstalk between pairs
is of paramount importance in data communication applications.
This is accomplished by varying the twist rates (twists per unit
length) of each pair. For a given cable length, signals traveling
on pairs with relatively high twist rates have longer distances to
traverse than signals traveling on pairs with relatively low twist
rates. The longer relative distances translate into longer relative
delays and, similarly, the shorter relative distances translate into
shorter relative delays.
The delay of any TP channel is not flat over frequency, and
an equalizer is generally used at the receiver to produce an
approximately flat delay vs. frequency characteristic as well as
an approximately flat frequency response magnitude over the
bandwidth of interest. The term “group delay” is often used in
the delay vs. frequency context. When the group delay and the
magnitude response have been corrected to the best possible
degree at the receiver, the remaining signals are close approximations to those sent at the transmit end of the cable, but with
different delays with respect to the signals sent at the transmit
end. The signals, therefore, manifest different delays relative to
each other.
The relative delay difference between any two equalized signals
at the receiver is defined as delay skew, or simply skew, and is
measured in units of time. Some bundled coaxial cables also
exhibit delay skew between channels; these skew levels are
typically much smaller than those encountered among similar
length TP channels.
The AD8120 can be used with RGB and YPbPr, as well as other
video formats. Typically, three video component signals are transmitted over the TP cables, with each component carried on a pair.
For example, with RGB video signals, the red, green, and blue
signals are each transmitted over one pair. If these signals are
carried over a cable with skew larger than a quarter of a pixel
time and are displayed on a video monitor, the three colors will
not be properly aligned and the skew will be visible at the vertical
edges of objects displayed on the monitor. For fractional pixel
time skew levels, a rainbow-like effect appears at the vertical
edges of the objects; for skew levels longer than a pixel time,
vertical lines are visible on the vertical edges of objects. The
vertical lines are due to one color arriving earlier or later than
the others. The best way to observe skew is to view an object
against a black background.
The AD8120 is a triple adjustable delay line, and its primary
application is to realign the received, equalized video components. The pixel time of UXGA video with a refresh rate of
60 Hz is approximately 6.2 ns. In this case, the 0.8 ns delay
resolution of the AD8120 represents approximately 13% of
a pixel time.
TYPICAL APPLICATION CIRCUIT FOR THE AD8123
AND AD8120
Figure 25 illustrates a complete receiver application circuit using
sync-on common mode; this circuit comprises the AD8123
triple equalizer and the AD8120. The circuit receives balanced
RGB video signals over TP cable, performs cable equalization
and skew correction, and directly drives 75 Ω coaxial cable. The
6 dB voltage gain in the AD8120 compensates for the 6 dB double
termination loss incurred driving the coaxial cable. The low-pass
filter is optimized for short distances. Refer to the AD8123 data
sheet for details regarding the sync encoding and decoding.
The filter between the AD8123 and the AD8120 is a three-pole
low-pass filter (LPF) with a cutoff frequency of approximately
148 MHz; the LPF is included to provide high frequency noise
reduction. The filter shown in the application circuit performs
well for short to medium length cables. Note that the 1 pF capacitance of each AD8120 input is added to each filter capacitor that
is connected to each AD8120 input. Thus, for the filter shown,
the actual filter capacitance at each AD8120 input is 16 pF.
For longer cables, where much greater high frequency gain is
required from the AD8123, it may be desirable to scale the LPF
bandwidth back to provide greater noise reduction. This can be
done by simply scaling the inductor and capacitor values by the
ratio of the existing cutoff frequency of 140 MHz to the desired
new cutoff frequency. For example, if a new cutoff frequency of
100 MHz is desired, the inductor and capacitor values are scaled
by a factor of (140 MHz/100 MHz) = 1.4. This is summarized in
Table 13.
Table 13. Low-Pass Filter Component Selection
for 100 MHz Cutoff
Original Value
5.6 pF
150 nH
15 pF + 1 pF1 = 16 pF
1
Scale
Factor
1.4
1.4
1.4
Input capacitance of the AD8120.
Rev. 0 | Page 14 of 16
New Value
Ideal
7.8 pF
210 nH
22.4 pF − 1 pF1 = 21.4 pF
Standard
7.5 pF
220 nH
22 pF
Figure 25. Typical Application Circuit
–5V
4700pF
GREEN
CMV
1kΩ
1kΩ
RECEIVED
BLUE VIDEO
RECEIVED
GREEN VIDEO
RECEIVED
RED VIDEO
38
37
35
34
32
31
28
4700pF
FAIR-RITE
2743021447
47pF
47pF
0.1µF
7
8
3
475Ω
RED CMV
PD
11
0.1µF
VS–
2
1
VS+
26
VPEAK
27
VPOLE
25
VGAIN
23
VOFFSET
BLUE CMV 2
49.9Ω
49.9Ω
49.9Ω
49.9Ω
49.9Ω
49.9Ω
POWER-DOWN
CONTROL
ANALOG
CONTROL
INPUTS
13
14
0.1µF
VS–
VS+
16
0.1µF
17
0.1µF
VS–
BLUE
GREEN
RED
0.1µF
VS+
29
22
0.1µF
VS–
AD8123
VS+
19
0.1µF
33
0.1µF
VS–
VS+
36
0.1µF
9
VS–_CMP
OUTCMP2
OUTCMP1
GND
6 49.9Ω
5.6pF
100Ω
5.6pF
100Ω
CONTROL
INPUTS
15pF
150nH
15pF
150nH
15pF
5.6pF
4 49.9Ω
24, 39
OUTB 12
OUTG 15
OUTR 18
VS+_CMP
5
150nH
100Ω
31
GND
MODE
SER_SEL
PD
DNC
DNC
SDO/SDA
GND
0.1µF
–5V
8
7
6
5
4
3
2
1
32
9
10
30
29
28
AD8120
27
26
EXPOSED PADDLE
CONNECTED TO GND
SCK/SCL
11
BOUT
0.1µF
SDI/A1
12
GND
0.1µF
SERIAL BUS
FOR DIGITAL CONTROL
BIN
13
GOUT
14
15
25
16
+5V
17
18
19
20
21
22
23
75Ω
75Ω
75Ω
0.1µF
VS+
GND
DNC
VREF
VCB
VCG
VCR
+5V
24
0.1µF
GND
VS+
4700pF
GIN
GND
GND
VS–
RIN
ROUT
4700pF
CS/A0
GND
Rev. 0 | Page 15 of 16
VS+
+5V
0.1µF
+5V
0.1µF
5kΩ
7.5kΩ
5kΩ
BLUE
VSYNC OUT
HSYNC OUT
BLUE OUT
GREEN OUT
RED OUT
5kΩ
GREEN
RED
+5V
7.5kΩ
+5V
7.5kΩ
+5V
POTENTIOMETERS
FOR ANALOG CONTROL
07839-004
FAIR-RITE
2743021447
AD8120
AD8120
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
17
16
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
EXPOSED
PAD
(BOTTOM VIEW)
3.65
3.50 SQ
3.35
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
32
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
100608-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8120ACPZ-R2 1
AD8120ACPZ-R71
AD8120ACPZ-RL1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07839-0-7/09(0)
Rev. 0 | Page 16 of 16
Package Option
CP-32-4
CP-32-4
CP-32-4