ee Fr ad HS t e L Ro plian m Co CCHD-950 Model 9X14 mm SMD, 3.3V, CMOS Frequency Range: Frequency Stability: Temperature Range: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Logic: 50MHz to 125MHz ±20ppm, ±25ppm, ±50ppm 0°C to 70°C (±20ppm, ±25ppm, ±50ppm) -20°C to 70°C (±25ppm, ±50ppm) -40°C to 85°C (±25ppm, ±50ppm) -55°C to 120°C 3.3V ±0.3V 15mA Typ, 25mA Max CMOS 45/55% Max @ 50% Vdd 3ns Max @ 20% to 80% Vdd "0" = 10% Vdd Max "1" = 90% Vdd Min 15pF ±24mA Max 0.5psec Typ., 1psec RMS Max -160dBc Typ., -155dBc Max Guaranteed None <3ppm 1st/yr, <1ppm every year thereafter Load: Output current: Jitter: 12KHz to 80MHz Phase Noise Floor: Sub-Harmonics: Aging: Ultra-Low Phase Noise Clock Oscillator The CCHD-950 was designed specifically for applications requiring Ultra-Low Phase Noise. Also available in VCXO version. Available on tape and reel in quantities of 100, 250 and 500pcs. Part Number Example: CCHD-950-20-100.000 = 3.3V, 45/55, ±20ppm, 0/70°C, 100.000 MHz CCHD-950M-25-100.000 = 3.3V, 45/55, ±25ppm, -20/70°C, 100.000 MHz CCHD-950X-50-100.000 = 3.3V, 45/55, ±50ppm, -40/85°C, 100.000 MHz SUGGESTED PAD LAYOUT 0.040 (1.01) 0.560 (14.2) 0.360 (9.14) 0.560 (14.2) CRYSTEK P/N Frequency Date Code 0.210 (5.3) 1 0.050 (1.27) 2 3 4 0.070 (1.77) 0.090 (2.28) 0.200 (5.08) 0.280 (7.11) 0.200 (5.08) TEMPERATURE RECOMMENDED REFLOW SOLDERING PROFILE 260°C Ramp-Up 3°C/Sec Max. Critical Temperature Zone 80MHz Phase Noise Plot Ramp-Down 6°C/Sec. 217°C 200°C 150°C Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. 260°C for 10 Secs. Max. NOTE: Reflow Profile with 240°C peak also acceptable. Pad 1 2 3 4 Connection N/C GND OUT Vdd Specifications subject to change without notice. TD-030603 Rev. C