Data Sheet 26182.128D 6818 DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER 40 41 42 43 1 44 2 3 4 5 6 A6818xEP 29 28 30 17 27 31 16 26 32 15 25 33 14 24 34 13 23 35 12 22 36 11 21 37 10 20 38 9 19 39 8 18 7 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD .................. 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘K–’) ................ -40°C to +125°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6818– devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and 40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6818– features an increased data input rate (compared with the older UCN/UCQ5818–F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6810– (10 bits) and A6812– (20 bits). The A6818– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (E-), and extended industrial (K-) applications. The package style provided is the minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. The lead (Pb) free versions have 100% matte tin leadframe plating. FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818– Always order by complete part number: Part Number Pb-free Packing A6818EEP A6818EEP-T A6818EEPTR A6818EEPTR-T A6818KEP A6818KEP-T A6818KEPTR A6818KEPTR-T A6818SEP A6818SEP-T A6818SEPTR A6818SEPTR-T – Yes – Yes – Yes – Yes – Yes – Yes 27 pieces/tube Ambient Temperature, TA (°C) –40 to 85 450 pieces/13-in. reel 27 pieces/tube –40 to 125 450 pieces/13-in. reel 27 pieces/tube –20 to 85 450 pieces/13-in. reel 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER LOAD SUPPLY LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT3 1 V DD 44 43 42 41 40 VBB OUT32 OUT31 SERIAL DATA OUT OUT30 5 4 2 NC 6 VDD 3 A6818xEP TYPICAL INPUT CIRCUIT 7 OUT29 39 2 OUT 4 IN 9 37 10 36 REGISTER LATCHES 11 12 LATCHES 38 REGISTER 8 35 34 Dwg. EP-010-5 OUT 8 13 27 28 OUT14 NC OUT15 26 ST 24 GROUND 22 20 BLANKING 21 19 OUT18 OUT17 18 NC ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS Dwg. EP-021-19 Dwg. PP-059-2 3.0 TYPICAL OUTPUT DRIVER OUTN 25 NC OUT16 OUT13 29 STROBE 30 17 CLK 16 23 31 CLOCK 15 BLNK 32 OUT19 V BB 33 19 14 2.5 2.0 1.5 SUFFIX 'EP', RθJA = 54°C/W 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-025B 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2003 Allegro MicroSystems, Inc. 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM LOGIC SUPPLY V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE LATCHES SERIAL DATA OUT BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 Output Contents IN Blanklng I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H L X X ... P1 P2 P3 ... L = Low Logic Level X PN-1 PN H = High Logic Level www.allegromicro.com X = Irrelevant X P = Present State X ... X R = Previous State L L ... L L 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Symbol ICEX Test Conditions VOUT = 0 V Limits @ VDD = 5 V Mln. Typ. Max. Min. Typ. Max. Units — <-0.1 -15 — <-0.1 -15 µA 57.5 58.3 — 57.5 58.3 — V VOUT(1) IOUT = -25 mA VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage VIN(1) 2.2 — — 3.3 — — V VIN(0) — — 1.1 — — 1.7 V Output Voltage Input Current Input Clamp Voltage Serial Data Output Voltage Maximum Clock Frequency Logic Supply Current IIN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 µA IIN(0) VIN = 0.8 V — <-0.01 -1.0 — <-0.01 -1.0 µA IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V VOUT(1) IOUT = -200 µA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 µA — 0.15 0.3 — 0.15 0.3 V 10 33 — 10 33 — MHz VIK fc IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA IBB(1) All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 µA tdis(BQ) CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs ten(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs tp(STH-QL) RL = 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 µs tp(STH-QH) RL = 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 µs Output Fall Time tf RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Rise Time tr RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/µs IOUT = ±200 µA — 50 — — 50 — ns Load Supply Current Blanking-to-Output Delay Strobe-to-Output Delay Clock-to-Serial Data Out Delay tp(CH-SQX) Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% t p(CH-SQX) SERIAL DATA OUT DATA 50% D 50% STROBE BLANKING E LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL) 90% DATA OUT N 10% Dwg. WP-029 HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING 50% t dis(BQ) tr t en(BQ) OUT N A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ............................................... 25 ns C. Clock Pulse Width, tw(CH) ............................................... 50 ns tf 90% 10% DATA 50% Dwg. WP-030A NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............................................. 50 ns www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818EEP & A6818SEP Dimensions in Inches (controlling dimensions) 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 0.656 0.650 INDEX AREA 0.319 0.291 0.050 BSC 39 7 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in Dimensions in Millimeters (for reference only) 18 28 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 16.662 16.510 INDEX AREA 8.10 7.39 1.27 BSC 7 39 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000