AD ADV7175KS Integrated digital ccir-601 ycrcb to pal/ntsc video encoder Datasheet

a
Integrated Digital CCIR-601
YCrCb to PAL/NTSC Video Encoder
ADV7175/ADV7176
Close Captioning Support
Teletext Support (Passthrough Mode)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
+5 V CMOS Monolithic Construction
44-Pin PQFP Thermally Enhanced Package
FEATURES
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Single 27 MHz Clock Required (32 Oversampling)
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC Compatible Composite Video Output
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV
Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video
Source
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*
APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia
GENERAL DESCRIPTION
The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to output S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.
(Continued on page 6)
FUNCTIONAL BLOCK DIAGRAM
M
U 10
L
T
I
P 10
L
E
X 10
E
R
8
VAA
YUV TO
RBG
MATRIX
RESET
8
8
8
8
COLOR
DATA
P7–P0
P15–P8
4:2:2 TO
4:4:4
INTERPOLATOR
8
YCrCb
TO
YUV
MATRIX
8
8
8
ADD
SYNC
ADD
BURST
ADD
BURST
8
8
8
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
8
Y
LOW-PASS
FILTER
10
8
U
LOW-PASS
FILTER
10
8
10
V
LOW-PASS
FILTER
10
10
HSYNC
FIELD/VSYNC
VIDEO TIMING
GENERATOR
REAL-TIME
CONTROL
CIRCUIT
I2C MPU PORT
BLANK
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
10-BIT
DAC
10-BIT
DAC
GREEN/
LUMA/
Y
RED/
CHROMA/
V
10-BIT
DAC
BLUE/
COMPOSITE/
U
10-BIT
DAC
COMPOSITE
ADV7175/ADV7176
10
VOLTAGE
REFERENCE
CIRCUIT
SIN/COS
DDS BLOCK
VREF
RSET
COMP
GND
*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADV7175/ADV7176–SPECIFICATIONS
Model
Parameter
(VAA = +5 V1, VREF = 1.235 V RSET = 150 V. All specifications
TMIN to TMAX2 unless otherwise noted)
ADV7175/ADV7176
Min
Typ
Max
Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
10
Bits
±1
±1
LSB
LSB
0.8
±1
V
V
µA
pF
0.4
10
V
V
µA
pF
2
VIN = 0.4 V or 2.4 V
10
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
10
ANALOG OUTPUTS
Output Current3
Output Current4
Full-Scale DAC Output
LSB Size
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
IOUT = 0 mA
VOLTAGE REFERENCE
Voltage Reference Range, VREF
IVREFOUT = 20 µA
33
34.7
8
182.5
33.9
2
30
mA
mA
IRE
µA
%
V
kΩ
pF
1.235
1.359
V
5
140
110
0.02
155
150
0.5
V
mA
mA
%/%
7.5
2.3
MHz
MHz
3.6
1.0
MHz
MHz
8.0
3.4
MHz
MHz
4.0
1.3
MHz
MHz
%
Degree
%
Degree
dB rms
dB p-p
Degree
%
0
37
5
+1.4
15
1.112
Units
5
POWER REQUIREMENTS
VAA
IDAC6
ICCT7
Power Supply Rejection Ratio
COMP = 0.1 µF
8
DYNAMIC PERFORMANCE
Luma Bandwidth9 (Low-Pass Filter)
Stopband Cutoff
Pass Band Cutoff
Chroma Bandwidth
Stopband Cutoff
Pass Band Cutoff
Luma Bandwidth9 (Low-Pass Filter)
Stopband Cutoff
Pass Band Cutoff
Chroma Bandwidth
Stopband Cutoff
Pass Band Cutoff
Differential Gain
Differential Phase
Differential Gain
Differential Phase
SNR
SNR
Hue Accuracy
Color Saturation Accuracy
NTSC Mode
>50 dB Attenuation
<0.06 dB Attenuation
NTSC Mode
<40 dB Attenuation
>0.1 dB Attenuation
PAL MODE
>50 dB Attenuation
<0.06 dB Attenuation
PAL MODE
<40 dB Attenuation
>0.1 dB Attenuation
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
0.8
0.8
7
2
60
56
1.0
1.0
NOTES
1
± 5% for all versions.
2
Temperature range TMIN to TMAX: 0°C to 70°C.
3
Full drive into 37.5 Ω load.
4
Minimum drive with buffered/scaled output load.
5
Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 100°C.
6
IDAC is the total current to drive all four DACs. Turning off one DAC reduces IDAC correspondingly.
7
ICCT (Circuit Currrent) is the continuous currrent required to drive the device.
8
Guaranteed by characterization.
9
These specifications are for the low-pass filter only. For the other internal filters please see Figure 3.
Specifications subject to change without notice.
–2–
REV. A
ADV7175/ADV7176
AC CHARACTERISTICS1
Parameter
Min
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma Nonlinear Phase
Chroma/Luma Intermod
Chroma/Luma Intermod
Chroma/Luma Gain Ineq
Chroma/Luma Delay Ineq
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
TIMING–SPECIFICATIONS2
Parameter
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS1, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL
AND PIXEL PORT6
FCLOCK
Clock High Time t9
Clock Low Time t10
Data Setup Time t11
Data Hold Time t12
Control Setup Time t11
Control Hold Time t12
Digital Output Access Time t13
Digital Output Hold Time t14
Pipeline Delay t15
Typ
Max
0.6
1
1.7
0.2
0.4
0.6
1
0.8
60
59
Units
Condition
±%
±°
±°
±%
±%
±%
ns
±%
dB
dB
Referenced to 40 IRE
NTSC
PAL
Referenced to 714 mV (NTSC)
Referenced to 700 mV (PAL)
(VAA = +5 V3, VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX4 unless otherwise noted)
Min
Typ
0
4.0
4.7
4.0
4.7
250
Max
Units
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
1
300
4.7
5
0
24.52 27
8
8
3.5
1
4
2
Condition
After this period the first clock pulse is generated
Relevant for repeated start condition.
ns
ns
29.5
24
6
37
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
NOTES
1
Guaranteed by characterization.
2
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog Output Load ≤ 3 pF.
3
± 5% for all versions.
4
Temperature range (T MIN to TMAX); 0°C to +70°C.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following inputs:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
Specifications subject to change without notice.
REV. A
–3–
ADV7175/ADV7176
t5
t3
t3
SDATA
t6
t2
SCLOCK
t1
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
CONTROL
I/PS
t 12
t 10
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
t 11
CONTROL
O/PS
Cb
Y
t 13
HSYNC,
FIELD/VSYNC,
BLANK
t 14
Figure 2. Pixel and Control Data Timing Diagram
ABSOLUTE MAXIMUM RATINGS 1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND –0.5 to VAA
ORDERING GUIDE
Model
Temperature
Range
Package
Option
ADV7175KS
ADV7176KS
0°C to +70°C
0°C to +70°C
S-44
S-44
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
ADV7175/ADV7176
PIN DESCRIPTION
Mnemonic
Input/Output
Function
P15-P0
I
CLOCK
I
HSYNC
I/O
FIELD/VSYNC
I/O
BLANK
I/O
SCRESET/RTC
I
VREF
RSET
I/O
I
COMP
COMPOSITE
O
O
RED/CHROMA/V
GREEN/LUMA/Y
BLUE/COMPOSITE/U
SCLOCK
SDATA
ALSB
RESET
O
O
O
I
I/O
I
I
VAA
GND
P
G
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for proper operation.
Alternatively a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.
HSYNC (Modes 1 & 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may
be configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is logic level
“0.” This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high to low
transition on this pin will reset the subcarrier to field 0. Alternatively it may be configured as a Real Time Control (RTC) input.
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA.
PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for
NTSC and 1300 mV for PAL.
RED/S-VHS C/V Analog Output.
GREEN/S-VHS Y/Y Analog Output.
BLUE/Composite/U Analog Output.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal set up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7175/ADV7176 into
default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 ×
composite & S VHS out.
+5 V Supply.
Ground Pin.
RSET
GND
SCRESET /
RTC
P0
VAA
P2
P1
P3
P4
CLOCK
GND
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
VAA 1
P5 2
33 VREF
PIN 1
IDENTIFIER
32 COMPOSITE
P6 3
31 BLUE/COMPOSITE/U
P7 4
30 VAA
P8 5
P9 6
ADV7175/ADV7176
PQFP
P10 7
TOP VIEW
(Not to Scale)
29 GND
28 VAA
27 GREEN/LUMA/Y
P11 8
26 RED/CHROMA/V
P12 9
25 COMP
GND 10
24 SDATA
VAA 11
23 SCLOCK
–5–
RESET
VAA
GND
GND
ALSB
BLANK
P15
HSYNC
FIELD/
VSYNC
P13
REV. A
P14
12 13 14 15 16 17 18 19 20 21 22
ADV7175/ADV7176
(Continued from page 1)
The ADV7175/ADV7176 is protected by U.S. Patent Numbers
5,343,196 and 5,442,355 and other intellectual property rights.
The ADV7175/ADV7176 also supports both a PAL and NTSC
square pixel mode in slave mode.
DATA PATH DESCRIPTION
The video encoder accepts an 8-bit parallel pixel data stream in
CCIR-656 format or a 16-bit parallel data stream. This 4:2:2
data stream is interpolated into 4:4:4 component video (YUV).
The YUV video is interpolated to two times the pixel rate. The
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip synthesizer
(also running at two times the pixel rate). The two times pixel
rate sampling allows more accurate generation of the subcarrier
because frequency and phase errors are reduced by the higher
sampling rate. The ADV7175/ADV7176 also offers the option to
output the YUV information directly.
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
13.5 MHz data rate. The pixel data is de-multiplexed to form
three data paths. Y has a range of 16 to 235, Cr and Cb have a
range of 128 ± 112. The ADV7175/ADV7176 supports PAL
(B, D, G, H, I, N, M) and NTSC (with and without Pedestal)
standards. The appropriate SYNC, BLANK and burst levels are
added to the YCrCb data. Macrovision antitaping (ADV7175
only) and close-captioning levels are also added to Y and the
resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR filters.
The luminance and chrominance components are digitally combined and the resulting composite signal is output via a 10-bit
DAC. Three additional 10-/8-bit DACs are provided to output
S-VHS Y/C Video (10 bits), YUV or RGB Video (8 bits).
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1-3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts (and
can generate) HSYNC, VSYNC & FIELD timing signals. These
timing signals can be adjusted to change pulse width and position while the part is in the master mode. The encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively the encoder requires 24.54 MHz clock for NTSC
or 29.5 MHz clock for PAL square pixel mode operation. All internal clocks are generated on-chip. The ADV7175/ADV7176
modes are set up over a two wire serial bidirectional port (I2C
Compatible) with two slave addresses.
The YCrCb data is also used to generate RGB data with appropriate SYNC and BLANK levels. The RGB data is in sychronization with the composite video output. Alternatively analog
YUV data can be generated instead of RGB.
The four 10-bit DACs can be used to output:
1. 10-bit composite video + 8-bit RGB video.
2. 10-bit composite video + 8-bit YUV video.
3. Two 10-bit composite video signals
+ 10-bit LUMA & CHROMA (Y/C) signals.
Additionally, the ADV7175/ADV7176 allows a subcarrier phase
lock with an external video source and has a color bar generator
on-board.
Alternatively, each DAC can be individually powered off if not
required.
Functionally the ADV7175 and ADV7176 are the same with
the exception that the ADV7175 can output the Macrovision
(Revision 6.1/7.x) anticopy algorithm.
All possible video outputs are illustrated in Appendix 3, 4 and 5.
The ADV7175/ADV7176 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation.
The Y filter supports several different frequency responses including two 4.5/5.0 MHz low-pass and PAL/NTSC subcarrier
notch responses. The U and V filters have a 0.6/1 0.3 MHz
low-pass response.
INTERNAL FILTER RESPONSE
The ADV7175/ADV7176 is packaged in a 44-pin thermally enhanced PQFP package (patent pending).
FILTER SELECTION
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
MR04
0
0
0
0
1
1
1
MR03
0
0
1
1
0
1
1
These filter characteristics are illustrated in Figures 3 to 11.
PASSBAND
CUT OFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUT OFF (MHz)
STOPBAND
ATTENUATION (dB)
F3dB
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
7.5
8.0
3.57
4.43
8.0
7.5
8.0
>50
>51.3
>27.6
>29.3
>40
>54
>50.3
4.2
5.0
2.1
2.7
5.65
4.2
5.0
Figure 3. Y Filter Specifications
FILTER SELECTION
NTSC
PAL
PASSBAND
CUT OFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUT OFF (MHz)
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
F3dB
1.0
1.3
0.085
0.04
3.6
4.0
>40
>40
0.3
0.02
2.05
2.45
Figure 4. UV Filter Specifications
–6–
REV. A
ADV7175/ADV7176
0
0
TYPE A
TYPE A
–20
–40
AMPLITUDE – dB
AMPLITUDE – dB
–20
TYPE B
–60
–80
–100
TYPE B
–40
–60
–80
–100
–120
–120
0
2
4
6
8
FREQUENCY – MHz
10
12
0
0
0
–20
–20
–40
–40
–60
–80
6
8
FREQUENCY – MHz
10
12
–60
–80
–100
–100
–120
–120
0
2
4
6
8
FREQUENCY – MHz
10
0
12
Figure 6. NTSC Notch Filter
2
AMPLITUDE – dB
–20
–40
–60
–80
–100
–120
0
4
6
8
FREQUENCY – MHz
10
Figure 8. PAL Notch Filter
0
2
4
6
8
FREQUENCY – MHz
10
12
Figure 9. NTSC/PAL Extended Mode Filter
REV. A
4
Figure 7. PAL Low-Pass Filter
AMPLITUDE – dB
AMPLITUDE – dB
Figure 5. NTSC Low-Pass Filter
2
–7–
12
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE – dB
AMPLITUDE – dB
ADV7175/ADV7176
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
2
4
6
8
FREQUENCY – MHz
10
0
12
2
4
6
8
FREQUENCY – MHz
10
12
Figure 11. PAL UV Filter
Figure 10. NTSC UV Filter
COLOR BAR GENERATION
The ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
CLOCK
COMPOSITE
VIDEO
e.g. VCR
OR CABLE
SCRESET/RTC
VIDEO
DECODER
(e.g.SAA7110)
GREEN/LUMA/Y
M
U
X
MPEG
DECODER
SQUARE PIXEL MODE
The ADV7175/ADV7176 can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.54 MHz
is required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal filters scale accordingly for
square pixel mode operation.
RED/CHROMA/V
P7–P0
BLUE/COMPOSITE/U
COMPOSITE
HSYNC
FIELD/VSYNC
ADV7175/ADV7176
Figure 12. RTC Connections
COLOR SIGNAL CONTROL
PIXEL TIMING DESCRIPTION
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
The ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.
BURST SIGNAL CONTROL
8-Bit YCrCb Mode
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on
a rising clock edge.
NTSC PEDESTAL CONTROL
The pedestal information on both odd and even fields can be
controlled on a line by line basis using the NTSC Pedestal
Control Registers. This allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. The
data is loaded on every second rising clock edge of CLOCK.
The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
SUBCARRIER RESET
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. The subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.
VIDEO TIMING DESCRIPTION
The ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing generator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
REAL TIME CONTROL
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. The real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digital datastream in the RTC format (such as a Phillips SAA7110
video decoder), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This
digital datastream is 67 bits wide and the subcarrier is contained in bits 0 to 21. Each bit is 2 clock cycles long.
The ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
(Continued on page 15)
–8–
REV. A
ADV7175/ADV7176
Mode 0 (CCIR-656): Slave Option.
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high in this mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
8 1 8 1 F 0 0 X C Y C C Y C C Y C
r b
r
r b
0 0 0 0 F 0 0 Y b
0 F F A A A
0 F F B B B
F 0 0 X 8 1 8 1
C C
Y
F 0 0 Y 0 0 0 0
r b
INPUT PIXELS
ANCILLARY DATA
(HANC)
4 PIXELS
4 PIXELS
268 PIXELS
NTSC SYSTEM
1440 PIXELS
4 PIXELS
4 PIXELS
PAL SYSTEM
280 PIXELS
1440 PIXELS
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 13. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option.
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 16.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
H
V
F
ODD FIELD
EVEN FIELD
Figure 14. Timing Mode 0 (NTSC Master Mode)
REV. A
–9–
274
283
284
285
ADV7175/ADV7176
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
H
V
F
ODD FIELD
EVEN FIELD
Figure 15. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 16. Timing Mode 0 Data Transitions (Master Mode)
–10–
REV. A
ADV7175/ADV7176
Mode 1: Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC)
and Figure 18 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 17. Timing Mode 1 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 18. Timing Mode 1 (PAL)
REV. A
–11–
319
320
334
335
336
ADV7175/ADV7176
Mode 1: Master Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). Figure 19 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2
Figure 19. Timing Mode 1 Odd/Even Field Transitions
Mode 2: Slave Option. HSYNC, VSYNC, BLANK.
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL).
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
11
20
21
22
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
261
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 20. Timing Mode 2 (NTSC)
–12–
REV. A
ADV7175/ADV7176
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
EVEN FIELD
VSYNC
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 2 (PAL)
Mode 2: Master Option. HSYNC, VSYNC, BLANK.
(Timing Register 0 TR0 = X X X X X 1 0 1 )
In this mode the ADV7175/ADV7176 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). Figure 22 illustrates the
HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 23 illustrates the HSYNC,
BLANK and VSYNC for an odd to even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PAL = 12* CLOCK/2
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
PAL = 132* CLOCK/2
NTSC = 118 * CLOCK/2
LINE 3
LINE 4
Figure 22. Timing Mode 2 Even-to-Odd Field Transition
REV. A
–13–
Y
Cr
Y
ADV7175/ADV7176
HSYNC
VSYNC
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2
LINE 266
LINE 265
Figure 23. Timing Mode 2 Odd-to-Even Field Transition
Mode 3: Master/Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 24. Timing Mode 3 (NTSC)
–14–
REV. A
ADV7175/ADV7176
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 25. Timing Mode 3 (PAL)
(Continued from page 8)
In addition the ADV7175/ADV7176 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input pixel clock of 24.54 MHz for NTSC and an input pixel
clock of 29.5 MHz for PAL. The internal horizontal line
counters place the various video waveform sections in the correct location for the new clock frequencies.
The ADV7175/ADV7176 has 8 distinct master or slave timing
configurations. These are divided into 4 timing modes which
operate at one discrete clock frequency (27 MHz). Timing control is established with the bidirectional SYNC, BLANK and
FIELD/VSYNC pins. Timing Mode Register 1 can also be
used to vary the timing pulse widths and the where they occur in
relation to each other.
OUTPUT VIDEO TIMING
The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes the following sequences are synchronized with the input
timing control signals. In master modes the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
NTSC–Interlaced: Scan lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for close captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
PAL–Interlaced: Scan lines 1–6, 311–318 and 624–625 are always blanked and vertical sync pulses are included in Fields 1,
2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always
blanked and vertical sync pulses are included in Fields 3, 4, 7
and 8. The remaining scan lines in the vertical interval are also
blanked and can be used for close captioning data. Burst is disabled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and
6. Burst is disabled on lines 1–5, 311–319 and 623–625 in
Fields 3, 4, 7 and 8.
PAL–Noninterlaced: Scan lines 1–6 and 311–312 are always
blanked and vertical sync pulses are included. The remaining
scan lines in the vertical interval are also blanked and can be
used for close captioning data. Burst is disabled on lines 1–5,
310–312.
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high to low transition on the
RESET pin. This initializes the pixel port such that the pixel
inputs P7–P0 are selected. After reset, the ADV7175/ADV7176
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16 HEX is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. All bits in Mode Register 0
are set to Logic Level “0” except Bit MR02. Bit MR02 of
Mode Register 0 is set to Logic “1.” This enables the 7.5 IRE
pedestal.
NTSC–Noninterlaced: Scan lines 1–9 are always blanked
and vertical sync pulses are included. Scan lines 10–21 are also
blanked and can be used for close captioning data. Burst is disabled on lines 1–6, 261–262.
REV. A
–15–
ADV7175/ADV7176
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read information from the peripheral.
MPU PORT DESCRIPTION
The ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175 and ADV7176 each have four possible slave addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
1
1
0
1
0
1
A1
The ADV7175/ADV7176 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long supporting the
7-bit addresses plus the R/W bit. The ADV7175 has 33 subaddresses and the ADV7176 has 19 subaddresses to enable access to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. There is one exception. The
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. The auto increment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. The subcarrier frequency registers should not be accessed independently.
X
ADDRESS
CONTROL
SET UP BY
ALSB
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start condition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the following action will be taken:
READ/WRITE
CONTROL
0
1
WRITE
READ
Fig 26. ADV7175 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.
WRITE
READ
Fig 27. ADV7176 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high to low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
WRITE
SEQUENCE
S
A(S)
SLAVE ADDR
SUB ADDR
A(S)
S
SLAVE ADDR
S = START BIT
P = STOP BIT
A(S)
Figure 28 illustrates an example of data transfer for a read sequence and the start and stop conditions.
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
START ADDR R/W ACK SUBADDRESS ACK
DATA
8
9
P
ACK
STOP
Figure 28. Bus Data Transfer
Figure 29 shows bus write and read sequences.
DATA
A(S)
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will return to the idle condition.
SUB ADDR
A(S) S
SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 29. Write and Read Sequences
–16–
REV. A
ADV7175/ADV7176
SR7
SR6
SR5
SR4
SR3
SR1
SR2
SR0
SUBADDRESS REGISTER
SR7–SR5
(000)
SR4 SR3 SR2 SR1 SR0
ZERO SHOULD
BE WRITTEN TO
THESE BITS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
1
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING MODE REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING MODE REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTERS (ADV7175 ONLY)
"
"
"
"
"
"
MACROVISION REGISTERS (ADV7175 ONLY)
Figure 30. Subaddress Register
REGISTER ACCESSES
Subaddress Register (SR7–SR0)
The MPU can write to or read from all of the registers of the
ADV7175/ADV7176 except the subaddress register which is a
write only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to the
subaddress register. Then a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.
The communications register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress set up. The subaddress
register determines to/from which register the operation takes
place.
REGISTER PROGRAMMING
Register Select (SR4–SR0):
Figure 30 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–
SR5.
The following section describes each register, including
subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers and
NTSC pedestal control registers in terms of its configuration.
These bits are setup to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Mode Register 0 is a 8-bit wide register.
Figure 31 shows the various operations under the control of
Mode Register 0. This register can be read from as well written to.
MR07
MR06
MR05
MR04
OUTPUT SELECT
MR07
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR02
YC OUTPUT
RGB/YUV OUTPUT
0
0
1
1
0
1
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
RGB SYNC
0
1
MR01 MR00
0
0
1
1
PEDESTAL CONTROL
MR02
MR05
0
1
DISABLE
ENABLE
–17–
MR00
OUTPUT VIDEO
STANDARD SELECTION
MR04 MR03
Figure 31. Mode Register 0
REV. A
MR01
FILTER SELECT
MR06
0
1
MR03
PEDESTAL OFF
PEDESTAL ON
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
ADV7175/ADV7176
MODE REGISTER 0 (MR07–MR00) BIT DESCRIPTION
Encode Mode Control (MR01–MR00):
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
These bits are used to set up the encode mode. The ADV7175/
ADV7176 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL (M) and PAL (N) standard video.
Mode Register 1 is a 8-bit wide register.
Figure 32 shows the various operations under the control of Mode
Register 1. This register can be read from as well written to.
Pedestal Control (MR02)
MODE REGISTER 1 (MR17–MR10) BIT DESCRIPTION
Interlaced Mode Control (MR10):
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7175/ADV7176 is configured in PAL mode.
This bit is used to setup the output to interlaced or non-interlaced mode. This mode is only relevant when the part is in
composite video mode.
Luminance Filter Control (MR04–MR03)
These bits are used for selecting between a filter for the luminance signal. These filters automatically are set to the cutoff frequency for the low-pass filters and the subcarrier frequency for
the notch filter. The extended mode filter is a 5.5 MHz low-pass
filter. The filters are illustrated in Figures 3 to 11.
Closed Captioning Field Control (MR12–MR11)
These bits control the field that close captioning data is displayed
on close captioning information can be displayed on an odd field,
even field or both fields.
DAC Control (MR16–MR13)
RGB Sync (MR05)
These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7175/ADV7176
if any of the DACs are not required in the application.
This bit is used to set up the RGB outputs with the sync information encoded.
Output Control (MR06)
Color Bar Control (MR17)
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that in RGB/YUV mode the main composite
signal is still available.
MR17
MR16
MR15
MR14
COMPOSITE DAC
CONTROL
MR16
0
1
COLOR BAR
CONTROL
0
1
DISABLE
ENABLE
MR13
0
1
MR10
MR12 MR11
NORMAL
POWER DOWN
BLUE/COMPOSITE
DAC CONTROL
0
1
MR11
CLOSED CAPTIONING
FIELD SELECTION
MR14
NORMAL
POWER DOWN
MR12
GREEN/LUMA
DAC CONTROL
MR15
MR17
This bit can be used to generate and output an internal color
bar. The color bar configuration is 75/75/75/7.5 for NTSC and
100/0/75/0 for PAL.
0
0
1
1
0
1
0
1
RED/CHROMA
DAC CONTROL
0
1
INTERLACE
CONTROL
MR10
MR13
NORMAL
POWER DOWN
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
NORMAL
POWER DOWN
0
1
INTERLACED
NON-INTERLACED
Figure 32. Mode Register 1
–18–
REV. A
ADV7175/ADV7176
SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0)
(Address (SR4–SR0) = 05H–02H)
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4-SR0) = 07H)
These 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers are calculated by using the
following equation:
Timing Register 0 is a 8-bit wide register.
Subcarrier Frequency Register =
Figure 34 shows the various operations under the control of
Timing Register 0. This register can be read from as well
written to.
232 –1
* F SCF
FCLK
TIMING REGISTER 0 (TR07–TR00)
BIT DESCRIPTION
Master/Slave Control (TR00)
i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5796 MHz
Subcarrier Frequency Register =
This bit controls whether the ADV7175/ADV7176 is in master
or slave mode.
232 – 1
* 3.579545 × 10 6
27 × 10 6
Subcarrier Frequency Register = 21F07C16 HEX
Figure 33 shows how the frequency is set up by the 4 registers.
SUBCARRIER
FREQUENCY
REG 0
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 3
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7175/ADV7176
These modes are described in the Timing and Control section
of the data sheet.
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
BLANK Control (TR03)
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC9
FSC1
This bit controls whether the BLANK input is used when the
part is in slave mode.
FSC8
Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
FSC0
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.
Figure 33. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7–FP0):
(Address (SR4–SR0) = 06H)
Timing Register Reset (TR07)
This 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
TR06
TR07
TR05
Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after setting up a
new timing mode.
TR04
TR03
TR02
MASTER/SLAVE
CONTROL
TR03
TR07
0
1
PIXEL PORT
CONTROL
TR06
0
1
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
8-BIT
16-BIT
TR00
ENABLE
DISABLE
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
0
0
1
1
0
1
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
0
1
TR02 TR01
0
0
1
1
0
1
0
1
Figure 34. Timing Register 0
REV. A
TR01
–19–
MODE 0
MODE 1
MODE 2
MODE 3
SLAVE TIMING
MASTER TIMING
ADV7175/ADV7176
CLOSED CAPTIONING EXTENDED DATA REGISTERS
1–0 (CED15–CED00)
(Address (SR4–SR0) = 09–08H)
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
These 8-bit wide registers are used to set up the closed
captioning extended data bytes. Figure 35 shows how the high
and low bytes are set up in the registers.
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7175/ADV7176 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
CED15 CED14 CED13 CED12 CED11 CED10
VSYNC Width (TR15–TR14)
When the ADV7175/ADV7176 is in Timing Mode 2, these bits
adjust the VSYNC pulse width.
BYTE 1
CED7
BYTE 0
CED6
CED5
CED4
CED3
CED2
CED9
CED1
CED8
CED0
CLOSED CAPTIONING DATA REGISTERS 1–0
(CCD15–CCD00)
(Subaddress (SR4–SR0) = 0B–0AH)
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
These 8-bit wide registers are used to set up the closed
captioning data bytes. Figure 36 shows how the high and low
bytes are set up in the registers.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address (SR4-SR0) = 0DH)
Figure 35. Closed Captioning Extended Data Register
Mode Register 2 is an 8-bit wide register.
BYTE 1
BYTE 0
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
Figure 38 shows the various operations under the control of
Mode Register 2. This register can be read from as well written to.
CCD8
CCD0
MODE REGISTER 2 (MR27–MR20) BIT DESCRIPTION
Square Pixel Mode Control (MR20)
Figure 36. Closed Captioning Data Register
TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0CH)
This bit is used to setup square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Timing Register 1 is an 8-bit wide register.
Genlock Control (MR22–MR21)
Figure 37 shows the various operations under the control of
Timing Register 1. This register can be read from as well
written to. This register can be used to adjust the width and
position of the master mode timing signals.
These bits control the genlock feature of the ADV7175/
ADV7176 Setting MR21 to a Logic “1” configures the
SCRESET/RTC pin as an input. Setting MR22 to logic level
“0” configures the SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0 following a
low to high transition on the SCRESET/RTC pin. Setting
MR22 to Logic Level “1” configures the SCRESET/RTC pin as
a real time control input.
TIMING REGISTER 1 (TR17–TR10) BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulse width.
TR17
TR16
TR15
HSYNC TO PIXEL
DATA ADJUSTMENT
0
1
0
1
TR13
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
0
0
1
1
TR14
TR11
TR12
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
TR15 TR14
0 x TPCLK
1 x TPCLK
2 x TPCLK
3 x TPCLK
x
x
0
1
Tc
0
0
1
1
Tb
Tb + 32µs
0
1
0
1
1 x TPCLK
3 x TPCLK
16 x TPCLK
64 x TPCLK
TR10
HSYNC WIDTH
Ta
TR11 TR10
0
0
1
1
0
1
0
1
1 x TPCLK
4 x TPCLK
16 x TPCLK
128 x TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x TPCLK
4 x TPCLK
16 x TPCLK
64 x TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
LINE 313
LINE 314
Ta
Tc
Tb
FIELD/VSYNC
Figure 37. Timing Register 1
–20–
REV. A
ADV7175/ADV7176
MR27
MR26
MR25
0
1
RGB OUTPUT
YUV OUTPUT
LOWER POWER
MODE
BURST
CONTROL
DISABLE
ENABLE
0
1
MR21
MR20
GENLOCK SELECTION
ENABLE COLOR
DISABLE COLOR
x
0
0
1
1
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
CCIR624/CCIR601
CONTROL
MR25
0
1
MR22
MR22 MR21
MR24
MR26
MR27
MR23
CHROMINANCE
CONTROL
RGB/YUV
CONTROL
0
1
MR24
SQUARE PIXEL
CONTROL
MR23
ENABLE BURST
DISABLE BURST
0
1
MR20
0
1
CCIR624 OUTPUT
CCIR601 OUTPUT
DISABLE
ENABLE
Figure 38. Mode Register 2
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
CCIR624/CCIR601 Control (MR23)
This bit switches the video output between CCIR624 and
CCIR601 video standard.
FIELD 1/3
PCO7
Chrominance Control (MR24)
FIELD 1/3
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
This bit enables the color information to be switched on and off
the video output.
PCO9
PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7
FIELD 2/4
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Figure 39. Pedestal Control Registers
Lower Power Control (MR27)
MODE REGISTER 3 MR3 (MR37–30)
(Address (SR4–SR0) = 12H)
This bit enables the lower power mode of the ADV7175/
ADV7176.
Mode Register 3 is an 8-bit wide register.
Figure 34 shows the various operations under the control of
Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”
should be written to them.
NTSC PEDESTAL CONTROL REGISTERS 3–0
(PCE15–0, PCO15–0)
(Subaddress (SR4–SR0) = 11-0EH)
MODE REGISTER 3 (MR37–MR30) DESCRIPTION
DAC Switching Control (MR37)
These 8-bit wide registers are used to set up the NTSC pedestal
on a line by line basis in the vertical blanking interval for both
odd and even fields. Figure 39 shows the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal off on the equivalent line.
MR37
MR36
MR35
This bit is used to switch the luminance signal onto the composite DAC. Figure 40 illustrates the DAC outputs and how they
switch when MR 37 is set to Logic “1”.
MR34
MR33
MR32
MR36-MR30
(RESERVED)
ZERO SHOULD BE
WRITTEN TO THESE BITS
DAC OUTPUT
SWITCHING
MR37
0
1
DAC A
DAC B
DAC C
DAC D
COMPOSITE
BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y
GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure 40. Mode Register 3
REV. A
–21–
MR31
MR30
ADV7175/ADV7176
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7175/ADV7176 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate
performance is achieved. The “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
The layout should be optimized for lowest noise on the
ADV7175/ADV7176 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should by minimized so
as to minimize inductive ringing.
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7175/ADV7176 must have at least one
0.1 µF decoupling capacitor to GND. These capacitors should
be placed as close as possible to the device.
It is important to note that while the ADV7175/ADV7176
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7175/ADV7176 should be isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
Ground Planes
The ground plane should encompass all ADV7175/ADV7176
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175/ADV7176, the analog output traces,
and all the digital signal traces leading up to the ADV7175/
ADV7176. The ground plane is the board’s common ground
plane.
Due to the high clock rates involved, long clock lines to the
ADV7175/ADV7176 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC), and not the
analog power plane.
Power Planes
Analog Signal Interconnect
The ADV7175/ADV7176 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7175/ADV7176.
The ADV7175/ADV7176 should be located as close as possible
to the output connectors to minimize noise pickup and reflections due to impedance mismatch.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175/ADV7176 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
Digital inputs, especially pixel data inputs and clocking signals
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω
load resistor connected to GND. These resistors should be
placed as close as possible to the ADV7175/ADV7176 so as to
minimize reflections.
The ADV7175/ADV7176 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
–22–
REV. A
ADV7175/ADV7176
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1µF
0.01µF
L1
(FERRITE BEAD)
+5V (VAA)
+5V (VAA)
+5V (VCC)
+5V (VAA)
1, 11, 20, 28, 30, 37
0.1µF
0.1µF
GND
VAA
25 COMP
33 VREF
GREEN/
LUMA/ 27
Y
75Ω
RED/
CHROMA/ 26
V
75Ω
BLUE/
COMPOSITE/ 31
U
75Ω
ADV7175
ADV7176
38–42,
2–9, 12–14
P15–P0
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
33µF
10µF
35 SCRESET/RTC
S VIDEO
15 HSYNC
16 FIELD/VSYNC
COMPOSITE 32
+5V (VCC)
5kΩ
5kΩ
SCLOCK 23
22 RESET
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
+5V (VCC)
75Ω
17 BLANK
MPU BUS
SDATA 24
44 CLOCK
+5V (VAA)
ALSB
RSET 34
GND
150Ω
18
10kΩ
10, 19, 21
29, 36, 43
Figure 41. Recommended Analog Circuit Layout
The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if
13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7175/ADV7176 in the correct sequence.
D
CLOCK
Q
D
CK
CK
HSYNC
Figure 42. Circuit to Generate 13.5 MHz
REV. A
–23–
Q
13.5MHz
ADV7175/ADV7176
APPENDIX 2
CLOSED CAPTIONING
The ADV7175/ADV7176 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of line 21 of the odd fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. Sixteen bits of data follow the start
bit. These consist of two 8-bit bytes. The data for these bytes is stored in closed captioning data registers 0 and 1.
The ADV7175/ADV7176 also supports the extended closed captioning operation which is active during even fields and is encoded
on scan line 284. The data for this operation is stored in closed captioning extended data registers 0 and 1.
All clock run-in signals and timing to support closed captioning on lines 21 and 282 are generated automatically by the ADV7175/
ADV7176. All pixels inputs are ignored during lines 21 and 282.
FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA208 describe the closed captioning information for lines
21 and 284.
13.407µs
S
T
A
R
T
50 IRE
D6–D0
P
A
R
I
T
Y
D6–D0
P
A
R
I
T
Y
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003µs
17.379µs
33.764µs
Figure 43. Closed Captioning Waveform (NTSC)
–24–
REV. A
ADV7175/ADV7176
APPENDIX 3
NTSC WAVEFORMS (With Pedestal)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
Figure 44. NTSC Composite Video Levels
100 IRE
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
Figure 45. NTSC Luma Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
232.2mV
0mV
Figure 46. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
Figure 47. NTSC RGB Video Levels
REV. A
–25–
387.5mV
331.4mV
45.9mV
ADV7175/ADV7176
NTSC WAVEFORMS (Without Pedestal)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV
BLANK/BLACK LEVEL
0 IRE
–40 IRE
338mV
SYNC LEVEL
52.1mV
REF WHITE
1052.2mV
Figure 48. NTSC Composite Video Levels
100 IRE
714.2mV
BLANK /BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
338mV
52.1mV
Figure 49. NTSC Luma Video Levels
PEAK CHROMA
1101.6mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
198.4mV
0mV
Figure 50. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
BLANK/BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
336.5mV
51mV
Figure 51. NTSC RGB Video Levels
–26–
REV. A
ADV7175/ADV7176
PAL WAVEFORMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
Figure 52. PAL Composite Video Levels
1047mV
REF WHITE
696.4mV
350.7mV
BLANK/BLACK LEVEL
SYNC LEVEL
50.8mV
Figure 53. PAL Luma Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 54. PAL Chroma Video Levels
1050.2mV
REF WHITE
698.4mV
351.8mV
BLANK /BLACK LEVEL
SYNC LEVEL
51mV
Figure 55. PAL RGB Video Levels
REV. A
–27–
ADV7175/ADV7176
APPENDIX 4
REGISTER VALUES
The ADV7175/ADV7176 registers can be set depending on the
user standard required.
PAL (M)
The following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the timing register 0 control the timing
modes. For a detailed explanation of each bit in the command
registers, please turn to the register programming section of the
data sheet. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples
this register is programmed in default mode.
NTSC
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
04 Hex
00 Hex
16 Hex
7C Hex
F0 Hex
21 Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
PAL (B, D, G, H, I)
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
01 Hex
00 Hex
CB Hex
8A Hex
09 Hex
2A Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
06 Hex
00 Hex
A3 Hex
EF Hex
E6 Hex
21 Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
PAL (N)
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
–28–
05 Hex
00 Hex
CB Hex
8A Hex
09 Hex
2A Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
REV. A
ADV7175/ADV7176
APPENDIX 5
OUTPUT FILTER
If an output filter is required for the composite output of the ADV7175/ADV7176. The following filter can be used.
Plots of the filter characteristics can be produced on request.
L
1µH
L
2.7µH
L
0.7µH
IN
OUT
C
470pF
C
330pF
Figure 56. Output Filter
REV. A
–29–
C
56pF
ADV7175/ADV7176
APPENDIX 6
OUTPUT WAVEFORMS
Figure 57. 100/75% Color Bars NTSC
Figure 58. 100/75% Color Bars NTSC (Chrominance Only)
–30–
REV. A
ADV7175/ADV7176
Figure 59. 100/75% Color Bars NTSC (Luminance Only)
Figure 60. 100/75% Color Bars PAL
REV. A
–31–
ADV7175/ADV7176
Figure 61. Differential Phase and Gain Measurements (PAL)
Figure 62. Vectorscope Measurements (PAL)
–32–
REV. A
ADV7175/ADV7176
Figure 63. Modulated Ramp Measurements (PAL)
REV. A
–33–
ADV7175/ADV7176
INDEX
Contents
Page No.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
ADV7175/ADV7176 SPECIFICATIONS . . . . . . . . . . . . . . 2
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 4
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PIN DESCRIPTION/PIN CONFIGURATION . . . . . . . . . 5
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 6
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 6
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 8
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 8
COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8
BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 8
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8
Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 15
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 16
Contents
Page No.
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 17
Subaddress Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . 19
Subcarrier Phase Register . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Closed Captioning Extended Data Registers 1-0 . . . . . . 20
Closed Captioning Data Registers 1-0 . . . . . . . . . . . . . . 20
Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
NTSC Pedestal Control Registers 3-0 . . . . . . . . . . . . . . 21
APPENDIX 1. BOARD DESIGN AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 22
APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 24
APPENDIX 3. VIDEO WAVEFORMS . . . . . . . . . . . . . . 25
APPENDIX 4. REGISTER VALUES . . . . . . . . . . . . . . . 28
APPENDIX 5. OUTPUT FILTER . . . . . . . . . . . . . . . . . 29
APPENDIX 6. OUTPUT WAVEFORMS . . . . . . . . . . . . 30
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 35
–34–
REV. A
ADV7175/ADV7176
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
MAX
0.398 (10.11)
0.390 (9.91)
0.037 (0.94)
8°
0.8°
0.025 (0.64)
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
4
4
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
11
0.032 (0.81)
0.083 (2.11)
0.077 (1.96)
REV. A
12
1
–35–
0.033 (0.84)
0.016 (0.41)
0.029 (0.74)
0.012 (0.30)
–36–
PRINTED IN U.S.A.
C213a–4– /96