High Precision, Wideband RMS-to-DC Converter AD637 FEATURES FUNCTIONAL BLOCK DIAGRAM BUFF IN BUFF OUT 25kΩ VIN DEN INPUT ABSOLUTE VALUE SQUARER/ DIVIDER RMS OUT CAV 25kΩ dB OUTPUT OUTPUT OFFSET BIAS COMMON AD637 CS 00788-001 High accuracy 0.02% maximum nonlinearity, 0 V to 2 V rms input 0.10% additional error to crest factor of 3 Wide bandwidth 8 MHz at 2 V rms input 600 kHz at 100 mV rms Computes True rms Square Mean square Absolute value dB output (60 dB range) Chip select/power-down feature allows Analog three-state operation Quiescent current reduction from 2.2 mA to 350 μA 14-lead SBDIP, 14-lead low cost CERDIP, and 16-lead SOIC_W Figure 1. GENERAL DESCRIPTION The AD637 is a complete, high accuracy, monolithic rms-to-dc converter that computes the true rms value of any complex waveform. It offers performance that is unprecedented in integrated circuit rms-to-dc converters and comparable to discrete and modular techniques in accuracy, bandwidth, and dynamic range. A crest factor compensation scheme in the AD637 permits measurements of signals with crest factors of up to 10 with less than 1% additional error. The wide bandwidth of the AD637 permits the measurement of signals up to 600 kHz with inputs of 200 mV rms and up to 8 MHz when the input levels are above 1 V rms. As with previous monolithic rms converters from Analog Devices, Inc., the AD637 has an auxiliary dB output available to users. The logarithm of the rms output signal is brought out to a separate pin, allowing direct dB measurement with a useful range of 60 dB. An externally programmed reference current allows the user to select the 0 dB reference voltage to correspond to any level between 0.1 V and 2.0 V rms. A chip select connection on the AD637 permits the user to decrease the supply current from 2.2 mA to 350 μA during periods when the rms function is not in use. This feature facilitates the addition of precision rms measurement to remote or handheld applications where minimum power consumption is critical. In addition, when the AD637 is powered down, the output goes to a high impedance state. This allows several AD637s to be tied together to form a wideband true rms multiplexer. The input circuitry of the AD637 is protected from overload voltages in excess of the supply levels. The inputs are not damaged by input signals if the supply voltages are lost. The AD637 is available in accuracy Grade J and Grade K for commercial temperature range (0°C to 70°C) applications, accuracy Grade A and Grade B for industrial range (−40°C to +85°C) applications, and accuracy Grade S rated over the −55°C to +125°C temperature range. All versions are available in hermetically sealed, 14-lead SBDIP, 14-lead CERDIP, and 16-lead SOIC_W packages. The AD637 computes the true root mean square, mean square, or absolute value of any complex ac (or ac plus dc) input waveform and gives an equivalent dc output voltage. The true rms value of a waveform is more useful than an average rectified signal because it relates directly to the power of the signal. The rms value of a statistical signal is also related to the standard deviation of the signal. The AD637 is laser wafer trimmed to achieve rated performance without external trimming. The only external component required is a capacitor that sets the averaging time period. The value of this capacitor also determines low frequency accuracy, ripple level, and settling time. The on-chip buffer amplifier can be used either as an input buffer or in an active filter configuration. The filter can be used to reduce the amount of ac ripple, thereby increasing accuracy. Rev. K Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD637 TABLE OF CONTENTS Features .............................................................................................. 1 Choosing the Averaging Time Constant....................................9 Functional Block Diagram .............................................................. 1 Frequency Response .................................................................. 11 General Description ......................................................................... 1 AC Measurement Accuracy and Crest Factor ........................ 12 Revision History ............................................................................... 2 Connection for dB Output........................................................ 12 Specifications..................................................................................... 3 dB Calibration............................................................................. 13 Absolute Maximum Ratings............................................................ 5 Low Frequency Measurements................................................. 14 ESD Caution.................................................................................. 5 Vector Summation ..................................................................... 14 Pin Configurations and Function Descriptions ........................... 6 Evaluation Board ............................................................................ 16 Functional Description .................................................................... 7 Outline Dimensions ....................................................................... 19 Standard Connection ................................................................... 8 Ordering Guide .......................................................................... 20 Chip Select..................................................................................... 8 Optional Trims for High Accuracy ............................................ 8 REVISION HISTORY 2/11—Rev. J to Rev. K Changes to Figure 15...................................................................... 11 Changes to Figure 16...................................................................... 12 Changes to Evaluation Board Section and Figure 23................. 16 Added Figure 24; Renumbered Sequentially .............................. 17 Changes to Figure 25 Through Figure 29.................................... 17 Changes to Figure 30...................................................................... 18 Added Figure 31.............................................................................. 18 Deleted Table 6; Renumbered Sequentially ................................ 18 Changes to Ordering Guide .......................................................... 20 4/07—Rev. I to Rev. J Added Evaluation Board Section ................................................. 16 Updated Outline Dimensions ....................................................... 20 10/06—Rev. H to Rev. I Changes to Table 1............................................................................ 3 Changes to Figure 4.......................................................................... 7 Changes to Figure 7.......................................................................... 9 Changes to Figure 16, Figure 18, and Figure 19 ......................... 12 Changes to Figure 20...................................................................... 13 4/05—Rev. F to Rev. G Updated Format..................................................................Universal Changes to Figure 1...........................................................................1 Changes to General Description .....................................................1 Deleted Product Highlights .............................................................1 Moved Figure 4 to Page ....................................................................8 Changes to Figure 5...........................................................................9 Changes to Figure 8........................................................................ 10 Changes to Figure 11, Figure 12, Figure 13, and Figure 14....... 11 Changes to Figure 19...................................................................... 14 Changes to Figure 20...................................................................... 14 Changes to Figure 21...................................................................... 16 Updated Outline Dimensions....................................................... 17 Changes to Ordering Guide .......................................................... 18 3/02—Rev. E to Rev. F Edits to Ordering Guide ...................................................................3 12/05—Rev. G to Rev. H Updated Format..................................................................Universal Changes to Figure 1.......................................................................... 1 Changes to Figure 11...................................................................... 10 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 Rev. K | Page 2 of 20 AD637 SPECIFICATIONS At 25°C and ±15 V dc, unless otherwise noted. 1 Table 1. Parameter TRANSFER FUNCTION Min AD637J/AD637A Typ Max VOUT = avg × (VIN )2 CONVERSION ACCURACY Total Error, Internal Trim 2 (Figure 5) TMIN to TMAX vs. Supply +VIN = 300 mV vs. Supply −VIN = −300 mV DC Reversal Error at 2 V Nonlinearity 2 V Full Scale 3 Nonlinearity 7 V Full Scale Total Error, External Trim ERROR VS. CREST FACTOR 4 Crest Factor 1 to 2 Crest Factor = 3 Crest Factor = 10 AVERAGING TIME CONSTANT INPUT CHARACTERISTICS Signal Range, ±15 V Supply Continuous RMS Level Peak Transient Input Signal Range, ±5 V Supply Continuous RMS Level Peak Transient Input Maximum Continuous Nondestructive Input Level (All Supply Voltages) Input Resistance Input Offset Voltage FREQUENCY RESPONSE 5 Bandwidth for 1% Additional Error (0.09 dB) VIN = 20 mV VIN = 200 mV VIN = 2 V ±3 dB Bandwidth VIN = 20 mV VIN = 200 mV VIN = 2 V Min AD637K/AD637B Typ Max VOUT = avg × (VIN )2 Max Unit avg × (VIN )2 VOUT = ±1 ± 0.5 ±0.5 ± 0.2 ±1 ± 0.5 mV ±% of reading ±3.0 ± 0.6 ±2.0 ± 0.3 ±6 ± 0.7 30 150 30 150 30 150 mV ± % of reading μV/V 100 300 100 300 100 300 μV/V % of reading % of FSR % of FSR mV ± % of reading 0.25 0.1 0.25 0.04 0.05 0.02 0.05 0.04 0.05 ±0.5 ± 0.1 ±0.25 ± 0.05 ±0.5 ± 0.1 Specified accuracy ±0.1 Specified accuracy ±0.1 Specified accuracy ±0.1 ±1.0 ±1.0 ±1.0 25 25 25 0 to 7 0 to 7 ±15 0 to 4 ±6 ±15 8 0 to 7 ±15 0 to 4 6.4 AD637S Typ Min 9.6 ±0.5 6.4 8 ±15 V rms V p-p ±6 ±15 V rms V p-p V p-p 9.6 ±0.5 kΩ mV 0 to 4 ±6 ±15 9.6 ±0.2 6.4 8 % of reading % of reading ms/μF CAV 11 66 200 11 66 200 11 66 200 kHz kHz kHz 150 1 8 150 1 8 150 1 8 kHz MHz MHz Rev. K | Page 3 of 20 AD637 Parameter OUTPUT CHARACTERISTICS Offset Voltage vs. Temperature Voltage Swing, ±15 V Supply, 2 kΩ Load Voltage Swing, ±3 V Supply, 2 kΩ Load Output Current Short-Circuit Current Resistance Chip Select High Resistance Chip Select Low dB OUTPUT Error, VIN 7 mV to 7 V rms, 0 dB = 1 V rms Scale Factor Scale Factor Temperature Coefficient Min IREF for 0 dB = 1 V rms IREF Range BUFFER AMPLIFIER Input Output Voltage Range Input Offset Voltage Input Current Input Resistance Output Current Short-Circuit Current Small Signal Bandwidth Slew Rate 6 DENOMINATOR INPUT Input Range Input Resistance Offset Voltage CHIP SELECT (CS) RMS On Level RMS Off Level IOUT of Chip Select CS Low CS High On Time Constant Off Time Constant POWER SUPPLY Operating Voltage Range Quiescent Current Standby Current 5 1 AD637J/AD637A Typ Max 0 to 12.0 ±0.05 13.5 0 to 2 2.2 ±1 ±0.089 0 to 12.0 ±0.04 13.5 0 to 2 2.2 Min AD637S Typ 0 to 12.0 ±0.04 13.5 0 to 2 2.2 V ±0.5 ±0.056 Max Unit ±1 ±0.07 mV mV/°C V 20 0.5 20 0.5 20 0.5 mA mA Ω 100 100 100 kΩ ±0.5 ±0.3 ±0.5 dB −3 +0.33 −3 +0.33 −3 +0.33 mV/dB % of reading/°C dB/°C μA μA 6 6 −0.033 20 80 100 −VS to (+VS − 2.5 V) ±0.8 ±2 108 −0.13 5 1 −0.033 20 ±0.5 ±2 108 ±2 ±10 +5 0 to 10 25 ±0.2 6 80 100 −VS to (+VS − 2.5 V) −0.13 20 1 5 20 AD637K/AD637B Typ Max Min −0.033 20 5 1 −VS to (+VS − 2.5 V) ±0.8 ±2 108 ±1 ±5 +5 −0.13 20 1 5 30 ±0.5 20 0 to 10 25 ±0.2 80 100 V ±2 ±10 +5 20 1 5 30 ±0.5 0 to 10 25 ±0.2 20 30 ±0.5 Open or 2.4 V < VC < +VS VC < 0.2 V VC < 0.2 V Open or 2.4 V < VC < +VS VC < 0.2 V Open or 2.4 V < VC < +VS 10 0 10 + ((25 kΩ) × CAV) 10 + ((25 kΩ) × CAV) 10 0 10 + ((25 kΩ) × CAV) 10 + ((25 kΩ) × CAV) 10 0 10 + ((25 kΩ) × CAV) 10 + ((25 kΩ) × CAV) ±3.0 2.2 350 ±18 3 450 ±3.0 2.2 350 1 ±18 3 450 ±3.0 2.2 350 ±18 3 450 mV nA Ω mA mA MHz V/μs V kΩ mV μA μA μs μs V mA μA Specifications shown in bold are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units. 2 Accuracy specified 0 V rms to 7 V rms dc with AD637 connected, as shown in Figure 5. 3 Nonlinearity is defined as the maximum deviation from the straight line connecting the readings at 10 mV and 2 V. 4 Error vs. crest factor is specified as additional error for 1 V rms. 5 Input voltages are expressed in volts rms. Percent is in % of reading. 6 With external 2 kΩ pull-down resistor tied to −VS. Rev. K | Page 4 of 20 AD637 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter ESD Rating Supply Voltage Internal Quiescent Power Dissipation Output Short-Circuit Duration Storage Temperature Range Lead Temperature (Soldering 10 sec) Rated Operating Temperature Range AD637J, AD637K AD637A, AD637B AD637S, 5962-8963701CA Rating 500 V ±18 V dc 108 mW Indefinite −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 0°C to 70°C −40°C to +85°C −55°C to +125°C Rev. K | Page 5 of 20 AD637 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 14 BUFF OUT NC 2 13 VIN 12 NC COMMON 3 AD637 BUFF IN 1 COMMON 3 TOP VIEW 11 +VS (Not to Scale) 10 –VS CS 5 OUTPUT OFFSET 4 OUTPUT OFFSET 4 CS 5 9 RMS OUT dB OUTPUT 7 8 CAV DEN INPUT 6 dB OUTPUT 7 00788-002 DEN INPUT 6 NC = NO CONNECT 16 BUFF OUT NC 2 NC 8 15 VIN AD637 14 NC 13 +VS TOP VIEW (Not to Scale) 12 –VS 11 RMS OUT 10 CAV 9 NC NC = NO CONNECT Figure 2. 14-Lead SBDIP/CERDIP Pin Configuration 00788-003 BUFF IN 1 Figure 3. 16-Lead SOIC_W Pin Configuration Table 3. 14-Lead SBDIP/CERDIP Pin Function Descriptions Table 4. 16-Lead SOIC_W Pin Function Descriptions Pin No. 1 2, 12 3 4 5 6 7 8 9 10 11 13 14 Pin No. 1 2, 8, 9, 14 3 4 5 6 7 10 11 12 13 15 16 Mnemonic BUFF IN NC COMMON OUTPUT OFFSET CS DEN INPUT dB OUTPUT CAV RMS OUT −VS +VS VIN BUFF OUT Description Buffer Input No Connection Analog Common Output Offset Chip Select Denominator Input dB Output Averaging Capacitor Connection RMS Output Negative Supply Rail Positive Supply Rail Signal Input Buffer Output Rev. K | Page 6 of 20 Mnemonic BUFF IN NC COMMON OUTPUT OFFSET CS DEN INPUT dB OUTPUT CAV RMS OUT −VS +VS VIN BUFF OUT Description Buffer Input No Connection Analog Common Output Offset Chip Select Denominator Input dB Output Averaging Capacitor Connection RMS Output Negative Supply Rail Positive Supply Rail Signal Input Buffer Output AD637 FUNCTIONAL DESCRIPTION FILTER/AMPLIFIER BUFF OUT 14 1 BUFFER AMPLIFIER A5 24kΩ A4 I4 I1 24kΩ Q4 Q1 ABSOLUTE VALUE VOLTAGE TO CURRENT CONVERTER 6kΩ Q2 6kΩ Q5 Q3 BIAS I3 A3 12kΩ 125Ω CAV 11 +VS 9 RMS OUT 7 dB OUTPUT 3 COMMON 5 CS 6 DEN INPUT 4 OUTPUT OFFSET 10 –VS 24kΩ A2 VIN 13 8 AD637 A1 00788-004 BUFF IN ONE QUADRANT SQUARER/DIVIDER Figure 4. Simplified Schematic The AD637 embodies an implicit solution of the rms equation that overcomes the inherent limitations of straightforward rms computation. The actual computation performed by the AD637 follows the equation ⎡ V 2 ⎤ V rms = Avg ⎢ IN ⎥ ⎣⎢ V rms ⎦⎥ Figure 4 is a simplified schematic of the AD637, subdivided into four major sections: absolute value circuit (active rectifier), squarer/divider, filter circuit, and buffer amplifier. The input voltage (VIN), which can be ac or dc, is converted to a unipolar current I1 by the active rectifiers A1 and A2. I1 drives one input of the squarer/divider, which has the transfer function 2 I4 = I1 I3 To compute the absolute value of the input signal, the averaging capacitor is omitted. However, a small capacitance value at the averaging capacitor pin is recommended to maintain stability; 5 pF is sufficient for this purpose. The circuit operates identically to that of the rms configuration, except that I3 is now equal to I4, giving I4 = I 12 I4 I4 = |I1| The denominator current can also be supplied externally by providing a reference voltage (VREF) to Pin 6. The circuit operates identically to the rms case, except that I3 is now proportional to VREF. Therefore, I 4 = Avg The output current of the squarer/divider I4 drives A4, forming a low-pass filter with the external averaging capacitor. If the RC time constant of the filter is much greater than the longest period of the input signal, then the A4 output is proportional to the average of I4. The output of this filter amplifier is used by A3 to provide the denominator current I3, which equals Avg I4 and is returned to the squarer/divider to complete the implicit rms computation I 12 I3 and VOUT = VIN 2 VDEN This is the mean square of the input signal. ⎡I 2 ⎤ I 4 = Avg ⎢ 1 ⎥ = I 1 rms ⎣ I4 ⎦ and VOUT = VIN rms Rev. K | Page 7 of 20 AD637 20 AD637 1 BUFF IN 2 NC +VS 4.7kΩ (OPTIONAL) SQUARER/ DIVIDER +VS 5 CS 25kΩ –VS DEN 6 INPUT 25kΩ 11 10 9 +VS –VS VOUT = VIN2 + CAV CAV 8 00788-005 7 dB OUTPUT 5 0 ±3 ±5 ±10 ±15 SUPPLY VOLTAGE – DUAL SUPPLY (V) ±18 CHIP SELECT VIN NC 12 BIAS 10 Figure 6. Maximum VOUT vs. Supply Voltage VIN 13 3 COMMON 15 0 BUFF OUT 14 NC ABSOLUTE VALUE OUTPUT 4 OFFSET MAX VOUT (Volts 2kΩ Load) The AD637 is simple to connect for a majority of rms measurements. In the standard rms connection shown in Figure 5, only a single external capacitor is required to set the averaging time constant. In this configuration, the AD637 computes the true rms of any input signal. An averaging error, the magnitude of which is dependent on the value of the averaging capacitor, is present at low frequencies. For example, if the filter capacitor, CAV, is 4 μF, the error is 0.1% at 10 Hz and increases to 1% at 3 Hz. To measure ac signals, the AD637 can be ac-coupled by adding a nonpolar capacitor in series with the input, as shown in Figure 5. 00788-006 STANDARD CONNECTION The AD637 includes a chip select feature that allows the user to decrease the quiescent current of the device from 2.2 mA to 350 μA. This is done by driving CS, Pin 5, to below 0.2 V dc. Under these conditions, the output goes into a high impedance state. In addition to reducing the power consumption, the outputs of multiple devices can be connected in parallel to form a wide bandwidth rms multiplexer. Tie Pin 5 high to disable the chip select. OPTIONAL TRIMS FOR HIGH ACCURACY Figure 5. Standard RMS Connection The performance of the AD637 is tolerant of minor variations in the power supply voltages; however, if the supplies used exhibit a considerable amount of high frequency ripple, it is advisable to bypass both supplies to ground through a 0.1 μF ceramic disc capacitor placed as close to the device as possible. The output signal range of the AD637 is a function of the supply voltages, as shown in Figure 6. The output signal can be used buffered or nonbuffered, depending on the characteristics of the load. If no buffer is needed, tie the buffer input (Pin 1) to common. The output of the AD637 is capable of driving 5 mA into a 2 kΩ load without degrading the accuracy of the device. The AD637 includes provisions for trimming out output offset and scale factor errors resulting in significant reduction in the maximum total error, as shown in Figure 7. The residual error is due to a nontrimmable input offset in the absolute value circuit and the irreducible nonlinearity of the device. Referring to Figure 8, the trimming process is as follows: • Offset trim: Ground the input signal (VIN) and adjust R1 to give 0 V output from Pin 9. Alternatively, R1 can be adjusted to give the correct output with the lowest expected value of VIN. • Scale factor trim: Resistor R4 is inserted in series with the input to lower the range of the scale factor. Connect the desired full-scale input to VIN, using either a dc or a calibrated ac signal, and trim Resistor R3 to give the correct output at Pin 9 (that is, 1 V dc at the input results in a dc output voltage of l.000 V dc). A 2 V p-p sine wave input yields 0.707 V dc at the output. Remaining errors are due to the nonlinearity. Rev. K | Page 8 of 20 AD637 5.0 EO IDEAL EO AD637K MAX DC ERROR = AVERAGE OF OUTPUT – IDEAL 2.5 INTERNAL TRIM 0 DOUBLE-FREQUENCY RIPPLE 00788-009 ERROR (mV) AVERAGE ERROR AD637K EXTERNAL TRIM TIME Figure 9. Typical Output Waveform for a Sinusoidal Input –2.5 AD637K: 0.5mV ± 0.2% 0.25mV ± 0.05% EXTERNAL 0 0.5 1.0 INPUT LEVEL (V) 1.5 2.0 00788-007 –5.0 This ripple can add a significant amount of uncertainty to the accuracy of the measurement being made. The uncertainty can be significantly reduced through the use of a postfiltering network or by increasing the value of the averaging capacitor. Figure 7. Maximum Total Error vs. Input Level AD637K Internal and External Trims AD637 1 BUFF IN 2 NC OUTPUT OFFSET TRIM +VS R1 50kΩ –VS BUFF OUT ABSOLUTE VALUE 3 COMMON R2 1MΩ +VS OUTPUT 4 OFFSET 4.7kΩ SQUARER/ DIVIDER 5 CS R4 13 147Ω VIN NC 12 –VS 25kΩ DEN 6 INPUT 25kΩ 1 in % of reading 0.16 + 6.4 τ2 f 2 14 NC VIN +VS BIAS The dc error appears as a frequency dependent offset at the output of the AD637 and follows the relationship 11 10 9 Because the averaging time constant, set by CAV, directly sets the time that the rms converter holds the input signal during computation, the magnitude of the dc error is determined only by CAV and is not affected by postfiltering. +VS –VS VOUT = VIN2 100 SCALE FACTOR TRIM R3 1kΩ Figure 8. Optional External Gain and Offset Trims CHOOSING THE AVERAGING TIME CONSTANT The AD637 computes the true rms value of both dc and ac input signals. At dc, the output tracks the absolute value of the input exactly; with ac signals, the AD637 output approaches the true rms value of the input. The deviation from the ideal rms value is due to an averaging error. The averaging error comprises an ac component and a dc component. Both components are functions of input signal frequency f and the averaging time constant τ (τ: 25 ms/μF of averaging capacitance). Figure 9 shows that the averaging error is defined as the peak value of the ac component (ripple) and the value of the dc error. The peak value of the ac ripple component of the averaging error is defined approximately by the relationship 50 in % of reading where (τ > 1 f ) 6.3 τf 10 PEAK RIPPLE 1.0 DC ERROR 0.1 10 100 1k SINE WAVE INPUT FREQUENCY (Hz) 10k 00788-010 8 00788-008 CAV 7 dB OUTPUT DC ERROR OR RIPPLE (% of Reading) + CAV Figure 10. Comparison of Percent DC Error to the Percent Peak Ripple over Frequency Using the AD637 in the Standard RMS Connection with a 1 × μF CAV The ac ripple component of averaging error is greatly reduced by increasing the value of the averaging capacitor. There are two major disadvantages to this: the value of the averaging capacitor becomes extremely large and the settling time of the AD637 increases in direct proportion to the value of the averaging capacitor (TS = 115 ms/μF of averaging capacitance). A preferable method of reducing the ripple is by using the postfilter network, as shown in Figure 11. This network can be used in either a 1pole or 2-pole configuration. For most applications, the 1-pole filter gives the best overall compromise between ripple and settling time. Rev. K | Page 9 of 20 AD637 REQUIRED CAV (µF) + CAV 1 FOR A SINGLE-POLE FILTER SHORT RX AND REMOVE C3 00788-011 C2 24kΩ 100 1k INPUT FREQUENCY (Hz) 100 *%dc ERROR + %RIPPLE (PEAK) ACCURACY ±20% DUE TO COMPONENT TOLERANCE REQUIRED CAV (AND C2) C2 = 3.3 × CAV 1 1 0.1 0.01 1 10 100 1k INPUT FREQUENCY (Hz) 0.1 10k 0.01 100k 100 100 10 10 R RO R ER O % R 01 ER OR 0. R R ER RO ER 1 1 1% 0. 5% REQUIRED CAV (AND C2 + C3) C2 = C3 = 2.2 × CAV Figure 13. Values of CAV, C2, and 1% Settling Time for Stated % of Reading Averaging Error* for 1-Pole Post Filter (see * in Figure) 1% Figure 14 can be used to determine the required value of CAV, C2, and C3 for the desired level of ripple and settling time. R O R R ER O R % 01 R ER 0. O R 1% R 0. ER RO ER For applications that are extremely sensitive to ripple, the 2-pole configuration is suggested. This configuration minimizes capacitor values and the settling time while maximizing performance. 10 5% The symmetry of the input signal also has an effect on the magnitude of the averaging error. Table 5 gives the practical component values for various types of 60 Hz input signals. These capacitor values can be directly scaled for frequencies other than 60 Hz—that is, for 30 Hz, these values are doubled, and for 120 Hz they are halved. 10 100 1% Figure 13 shows the relationship between the averaging error, signal frequency settling time, and averaging capacitor value. Figure 13 is drawn for filter capacitor values of 3.3× the averaging capacitor value. This ratio sets the magnitude of the ac and dc errors equal at 50 Hz. As an example, by using a 1 μF averaging capacitor and a 3.3 μF filter capacitor, the ripple for a 60 Hz input signal is reduced from 5.3% of the reading using the averaging capacitor alone to 0.15% using the 1-pole filter. This gives a factor of 30 reduction in ripple, and yet the settling time only increases by a factor of 3. The values of filter Capacitor CAV and Filter Capacitor C2 can be calculated for the desired value of averaging error and settling time by using Figure 13. 0.01 100k Figure 12. Values for CAV and 1% Settling Time for Stated % of Reading Averaging Error* Accuracy Includes ±2% Component Tolerance (see * in Figure) Figure 11. 2-Pole Sallen-Key Filter Figure 12 shows values of CAV and the corresponding averaging error as a function of sine wave frequency for the standard rms connection. The 1% settling time is shown on the right side of Figure 12. 10k FOR 1% SETTLING TIME IN SECONDS MULTIPLY READING BY 0.400 RX 24kΩ 10 00788-012 *%dc ERROR + %RIPPLE (PEAK) 0.01 + FOR 1% SETTLING TIME IN SECONDS MULTIPLY READING BY 0.115 0.1 00788-013 CAV 8 0.1 0.1 0.01 0.1 *%dc ERROR + %RIPPLE (PEAK) ACCURACY ±20% DUE TO COMPONENT TOLERANCE 1 10 100 1k INPUT FREQUENCY (Hz) 10k FOR 1% SETTLING TIME IN SECONDS MULTIPLY READING BY 0.365 7 dB OUTPUT 1.0 0.01 100k Figure 14. Values of CAV, C2, and C3 and 1% Settling Time for Stated % of Reading Averaging Error* for 2-Pole Sallen-Key Filter (see * in Figure) Rev. K | Page 10 of 20 00788-014 9 –VS R DEN 6 INPUT 25kΩ R 10 1.0 R –VS 25kΩ +VS R +VS 4.7kΩ 5 CS 11 RO ER +VS O R ER BIAS C3 10 RO ER NC 12 SQUARER/ DIVIDER 10 + % 10 OUTPUT 4 OFFSET VIN 1% 3 COMMON RO ER VIN 13 ABSOLUTE VALUE RMS OUT % 01 0. BUFF OUT 14 1% 0. 2 NC 100 100 AD637 1 BUFF IN AD637 Table 5. Practical Values of CAV and C2 for Various Input Waveforms Input Waveform and Period Absolute Value Circuit Waveform and Period 1/2T T A Minimum R × CAV Time Constant 1/2T Recommended Standard Values for CAV and C2 for 1% Averaging Error @ 60 Hz with T = 16.6 ms C2 (μF) CAV (μF) 0.47 1.5 1% Settling Time 181 ms T 0.82 2.7 325 ms 10 (T − T2) 6.8 22 2.67 sec 10 (T − 2T2) 5.6 18 2.17 sec 0V Symmetrical Sine Wave T T B 0V Sine Wave with dc Offset T C T T2 T2 0V Pulse Train Waveform T T D T2 0V T2 FREQUENCY RESPONSE 10 7V RMS INPUT 2V RMS INPUT To take full advantage of the wide bandwidth of the AD637, care must be taken in the selection of the input buffer amplifier. To ensure that the input signal is accurately presented to the converter, the input buffer must have a −3 dB bandwidth that is wider than that of the AD637. Note the importance of slew rate in this application. For example, the minimum slew rate required for a 1 V rms, 5 MHz, sine wave input signal is 44 V/μs. The user is cautioned that this is the minimum rising or falling slew rate and that care must be exercised in the selection of the buffer amplifier, because some amplifiers exhibit a two-to-one difference between rising and falling slew rates. The AD845 is recommended as a precision input buffer. Rev. K | Page 11 of 20 1V RMS INPUT 1 1% 0.1 0.01 10% ±3dB 100mV RMS INPUT 10mV RMS INPUT 1k 10k 100k INPUT FREQUENCY (Hz) 1M Figure 15. Frequency Response 10M 00788-015 VOUT (V) The frequency response of the AD637 at various signal levels is shown in Figure 15. The dashed lines show the upper frequency limits for 1%, 10%, and ±3 dB of additional error. For example, note that for 1% additional error with a 2 V rms input, the highest frequency allowable is 200 kHz. A 200 mV signal can be measured with 1% error at signal frequencies up to 100 kHz. AD637 1.5 AC MEASUREMENT ACCURACY AND CREST FACTOR INCREASE IN ERROR (%) 1.0 Crest factor is often overlooked in determining the accuracy of an ac measurement. Crest factor is defined as the ratio of the peak signal amplitude to the rms value of the signal (CF = VP/V rms). Most common waveforms, such as sine and triangle waves, have relatively low crest factors (≤2). Waveforms that resemble low duty cycle pulse trains, such as those occurring in switching power supplies and SCR circuits, have high crest factors. For example, a rectangular pulse train with a 1% duty cycle has 0.5 0 –0.5 POSITIVE INPUT PULSE CAV = 22µF –1.0 –1.5 Vp 100µs e0 eIN(RMS) = 1 V RMS 1 MAGNITUDE OF ERROR (% of RMS Level) INCREASE IN ERROR (%) CAV = 22µF 1 CF = 10 0.1 5 6 7 CREST FACTOR 8 9 10 11 1.8 1.6 1.4 1.2 1000 00788-017 CF = 3 Figure 17. AD637 Error vs. Pulse Width Rectangular Pulse Figure 18 is a curve of additional reading error for the AD637 for a 1 V rms input signal with crest factors from 1 to 11. A rectangular pulse train (pulse width 100 μs) is used for this test because it is the worst-case waveform for rms measurement (all the energy is contained in the peaks). The duty cycle and peak amplitude were varied to produce crest factors from l to 10 while maintaining a constant 1 V rms input amplitude. CF = 10 1.0 0.8 CF = 7 0.6 0.4 0.2 0 10 100 PULSE WIDTH (µs) 4 2.0 10 1 3 Figure 18. Additional Error vs. Crest Factor Figure 16. Duty Cycle Timing 0.01 2 CF = 3 0 0.5 1.0 VIN (V RMS) 1.5 2.0 00788-019 0 100µs η = DUTY CYCLE = T CF = 1/ η 00788-016 T 00788-018 a crest factor of 10 (CF = 1 η ). Figure 19. Error vs. RMS Input Level for Three Common Crest Factors CONNECTION FOR dB OUTPUT Another feature of the AD637 is the logarithmic, or decibel, output. The internal circuit that computes dB works well over a 60 dB range. Figure 20 shows the dB measurement connection. The user selects the 0 dB level by setting R1 for the proper 0 dB reference current, which is set to cancel the log output current from the squarer/divider circuit at the desired 0 dB point. The external op amp is used to provide a more convenient scale and to allow compensation of the +0.33%/°C temperature drift of the dB circuit. The temperature resistor R3, as shown in Figure 20, is available from Precision Resistor Co., Inc., in Largo, Fla. (Model PT146). Consult its website for additional information. Rev. K | Page 12 of 20 AD637 dB CALIBRATION Refer to Figure 20: • Set VIN = 1.00 V dc or 1.00 V rms • Adjust R1 for 0 dB out = 0.00 V • Set VIN = 0.1 V dc or 0.10 V rms • Adjust R2 for dB out = −2.00 V Any other dB reference can be used by setting VIN and R1 accordingly. R2 33.2kΩ SIGNAL INPUT dB SCALE FACTOR ADJUST 5kΩ +VS BUFFER AD637 1 BUFF IN R3 1kΩ* BUFF OUT 14 60.4Ω 2 NC ABSOLUTE VALUE 3 COMMON OUTPUT 4 OFFSET +VS 4.7kΩ BIAS SECTION 3 +VS 25kΩ 5 CS –VS +VS 10 9 7 dB OUTPUT 8 –VS VOUT + FILTER 4 6 COMPENSATED dB OUTPUT + 100mV/dB –VS 11 DEN 6 INPUT 25kΩ 7 AD707JN VIN 13 NC 12 SQUARER/DIVIDER 2 1µF CAV 10kΩ NC = NO CONNECT +VS R1 500kΩ +2.5 V AD508J 00788-020 0dB ADJUST *1kΩ + 3500ppm SEE TEXT Figure 20. dB Connection Rev. K | Page 13 of 20 AD637 V+ 1µF 3.3MΩ BUFFER 2 NC 3 COMMON +VS OUTPUT OFFSET 50kΩ ADJUST VIN 13 AD548JN 2 4 6 FILTERED V RMS OUTPUT V– SIGNAL INPUT 6.8MΩ NC 12 BIAS SECTION OUTPUT 4 OFFSET 1MΩ +VS –VS ABSOLUTE VALUE 7 3 1µF BUFF OUT 14 AD637 1 BUFF IN 3.3MΩ SQUARER/DIVIDER 25kΩ 5 CS 4.7kΩ +VS –VS 25kΩ 11 10 + FILTER CAV 8 –VS VOUT 9 6 DEN INPUT 7 dB OUTPUT 1000pF +VS 100µF VIN2 V RMS 499kΩ 1% R CAV1 3.3µF 00788-021 NOTES 1. VALUES CHOSEN TO GIVE 0.1% AVERAGING ERROR @ 1Hz. 2. NC = NO CONNECT. Figure 21. AD637 as a Low Frequency RMS Converter LOW FREQUENCY MEASUREMENTS VECTOR SUMMATION If the frequencies of the signals to be measured are below 10 Hz, the value of the averaging capacitor required to deliver even 1% averaging error in the standard rms connection becomes extremely large. Figure 21 shows an alternative method of obtaining low frequency rms measurements. The averaging time constant is determined by the product of R and CAV1, in this circuit, 0.5 sec/μF of CAV. This circuit permits a 20:1 reduction in the value of the averaging capacitor, permitting the use of high quality tantalum capacitors. It is suggested that the 2-pole, Sallen-Key filter shown in Figure 21 be used to obtain a low ripple level and minimize the value of the averaging capacitor. Vector summation can be accomplished through the use of two AD637s, as shown in Figure 22. Here, the averaging capacitors are omitted (nominal 100 pF capacitors are used to ensure stability of the filter amplifier), and the outputs are summed as shown. The output of the circuit is If the frequency of interest is below 1 Hz, or if the value of the averaging capacitor is still too large, the 20:1 ratio can be increased. This is accomplished by increasing the value of R. If this is done, it is suggested that a low input current, low offset voltage amplifier, such as the AD548, be used instead of the internal buffer amplifier. This is necessary to minimize the offset error introduced by the combination of amplifier input currents and the larger resistance. VOUT = VX 2 + VY 2 This concept can be expanded to include additional terms by feeding the signal from Pin 9 of each additional AD637 through a 10 kΩ resistor to the summing junction of the AD711 and tying all of the denominator inputs (Pin 6) together. If CAV is added to IC1 in this configuration, then the output is VX 2 + VY 2 If the averaging capacitor is included on both IC1 and IC2, the output is V X 2 + VY 2 This circuit has a dynamic range of 10 V to 10 mV and is limited only by the 0.5 mV offset voltage of the AD637. The useful bandwidth is 100 kHz. Rev. K | Page 14 of 20 AD637 EXPANDABLE BUFFER 1 BUFF IN IC1 AD637 ABSOLUTE VALUE 2 NC 3 COMMON 14 VXIN 13 NC 12 BIAS SECTION OUTPUT 4 OFFSET SQUARER/DIVIDER 25kΩ 5 CS +VS –VS 11 10 4.7kΩ VOUT 25kΩ 6 DEN INPUT 7 +VS –VS 9 100pF FILTER dB OUTPUT BUFFER 1 BUFF IN 2 NC IC2 AD637 ABSOLUTE VALUE 3 COMMON +VS BIAS SECTION DEN 6 INPUT BUFF OUT 14 VYIN AD711K 13 10kΩ NC 12 SQUARER/DIVIDER 25kΩ 5 CS 4.7kΩ CAV 10kΩ 10kΩ OUTPUT 4 OFFSET 5pF 8 +VS –VS 25kΩ 11 +VS 10 9 20kΩ –VS VOUT 100pF 7 dB OUTPUT FILTER 8 VOUT = Figure 22. Vector Sum Configuration Rev. K | Page 15 of 20 VX2 + VY2 00788-022 +VS BUFF OUT AD637 EVALUATION BOARD amp, and is configured on the AD637-EVALZ as a low-pass Sallen-Key filter whose fC < 0.5 Hz. Users can connect to the buffer by moving the FILTER switch to the on position. DC_OUT is still the output of the AD637, and the test loop, BUF_OUT, is the output of the buffer. The R2 trimmer adjusts the output offset voltage. Referring to the schematic in Figure 30, the input connector RMS_IN is capacitively coupled to Pin 15 (VIN of SOIC package) of the AD637. The DC_OUT connector is connected to Pin 11, RMS OUT, with provisions for connections to the output buffer between Pin 1 and Pin 16. The buffer is an uncommitted op The LPF frequency is changed by changing the component values of CF1, CF2, R4, and R5. See Figure 24 and Figure 30 to locate these components. Note that a wide range of capacitor and resistor values can be used with the AD637 buffer amplifier. 00788-123 Figure 23 shows a digital image of the AD637-EVALZ, an evaluation board specially designed for the AD637. It is available at www.analog.com and is fully tested and ready for bench testing after connecting power and signal I/O. The circuit is configured for dual power supplies, and standard BNC connectors serve as the signal input and output ports. Figure 23. AD637-EVALZ Rev. K | Page 16 of 20 00788-124 00788-127 AD637 Figure 27. Evaluation Board—Secondary Side Copper 00788-125 00788-128 Figure 24. AD637-EVALZ Assembly Figure 25. Component Side Silkscreen 00788-129 00788-126 Figure 28. Evaluation Board—Internal Power Plane Figure 29. Evaluation Board—Internal Ground Plane Figure 26. Evaluation Board—Component Side Copper Rev. K | Page 17 of 20 AD637 –VS GND1 GND2 GND3 GND4 C1 10µF 25V +VS + C2 10µF 25V + –VS +VS FILTER BUF_IN 4 1 2 OUT 5 3 6 1 IN BUFF OUT BUFF IN 16 2 3 +VS R1 1MΩ R2 50kΩ +VS 4 R3 4.7kΩ 5 –VS 6 7 NC Z1 AD637 COMMON NC OUTPUT OFFSET +VS CS –VS DEN INPUT dB OUTPUT DB_OUT 8 VIN RMS OUT CAV NC NC R4 24.3kΩ 15 + RMS_IN 14 CIN 22µF 16V RMS_IN 13 12 11 BUF_OUT C3 0.1µF C4 0.1µF +VS –VS DC_OUT DC_OUT + CAV 10 22µF 16V 9 + CF1 R5 24.3kΩ 47µF 25V 00788-130 + CF2 47µF 25V Figure 30. Evaluation Board Schematic AC OR DC INPUT SIGNAL SOURCE FROM PRECISION CALIBRATOR OR FUNCTION GENERATOR PRECISION DMM TO MONITOR VOUT Figure 31. AD637-EVALZ Typical Bench Configuration Rev. K | Page 18 of 20 00788-131 POWER SUPPLY AD637 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.080 (2.03) MAX 8 14 1 PIN 1 0.310 (7.87) 0.220 (5.59) 7 0.100 (2.54) BSC 0.765 (19.43) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN SEATING PLANE 0.070 (1.78) 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 32. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-14) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 14 1 PIN 1 0.098 (2.49) MAX 8 0.310 (7.87) 0.220 (5.59) 7 0.100 (2.54) BSC 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 14-Lead Ceramic Dual In-Line Package [CERDIP] (Q-14) Dimensions shown in inches and (millimeters) Rev. K | Page 19 of 20 AD637 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 10.00 (0.3937) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 5962-8963701CA AD637AQ AD637AR AD637ARZ AD637BQ AD637BR AD637BRZ AD637JD AD637JDZ AD637JQ AD637JR AD637JR-REEL AD637JR-REEL7 AD637JRZ AD637JRZ-RL AD637JRZ-R7 AD637KD AD637KDZ AD637KQ AD637KRZ AD637SD AD637SD/883B AD637SQ/883B AD637-EVALZ 1 2 Notes 2 Temperature Range −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 14-Lead CERDIP 14-Lead CERDIP 16-Lead SOIC_W 16-Lead SOIC_W 14-Lead CERDIP 16-Lead SOIC_W 16-Lead SOIC_W 14-Lead SBDIP 14-Lead SBDIP 14-Lead CERDIP 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 14-Lead SBDIP 14-Lead SBDIP 14-Lead CERDIP 16-Lead SOIC_W 14-Lead SBDIP 14-Lead SBDIP 14-Lead CERDIP Evaluation Board Z = RoHS Compliant Part. A standard microcircuit drawing is available. ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00788-0-2/11(K) Rev. K | Page 20 of 20 Package Option Q-14 Q-14 RW-16 RW-16 Q-14 RW-16 RW-16 D-14 D-14 Q-14 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 D-14 D-14 Q-14 RW-16 D-14 D-14 Q-14