MCP6L71/1R/2/4 2 MHz, 150 µA Op Amps Features Description • • • • • • The Microchip Technology Inc. MCP6L71/1R/2/4 family of operational amplifiers (op amps) supports general purpose applications. The combination of rail-to-rail input and output, low quiescent current and bandwidth fit into many applicaitons. Gain Bandwidth Product: 2 MHz (typical) Supply Current: IQ = 150 µA (typical) Supply Voltage: 2.0V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: –40°C to +125°C Available in Single, Dual and Quad Packages Typical Applications • • • • • Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery Powered Systems This family has a 2 MHz Gain Bandwidth Product (GBWP) and a low 150 µA per amplifier quiescent current. These op amps operate on supply voltages between 2.0V and 6.0V, with rail-to-rail input and output swing. They are available in the extended temperature range. Package Types MCP6L71 SOT-23-5 Design Aids • • • • FilterLab® Software MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes R2 VOUT VIN R3 VREF VOUT 1 5 VDD VOUT 1 VSS 2 VDD 2 VIN+ 3 4 VIN– VIN+ 3 MCP6L71 SOIC, MSOP Typical Application R1 MCP6L71R SOT-23-5 MCP6L71 Inverting Amplifier 4 VIN– MCP6L72 SOIC, MSOP NC 1 8 NC VOUTA 1 8 VDD VIN– 2 7 VDD VINA– 2 7 VOUTB VIN+ 3 6 VOUT VINA+ 3 6 VINB– 5 NC 5 VINB+ VSS 4 VSS 4 MCP6L74 SOIC, TSSOP VOUTA 1 14 VOUTD VINA– 2 13 VIND– VINA+ 3 12 VIND+ VDD 4 VINB+ 5 © 2009 Microchip Technology Inc. 5 VSS 11 VSS 10 VINC+ VINB– 6 9 VINC– VOUTB 7 8 VOUTC DS22145A-page 1 MCP6L71/1R/2/4 NOTES: DS22145A-page 2 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Difference Input Voltage ...................................... |VDD – VSS| †† See Section 4.1.2 “Input Voltage and Current Limits”. VDD – VSS ........................................................................7.0V Current at Input Pins ....................................................±2 mA Analog Inputs (VIN+ and VIN–) †† .. VSS – 1.0V to VDD + 1.0V Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ................................... –65°C to +150°C Junction Temperature (TJ) .........................................+150°C ESD Protection On All Pins (HBM/MM) ................ ≥ 4 kV/400V 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1). Parameters Sym Min (Note 1) Typ Max (Note 1) Units Conditions Input Offset VOS –4 ±1 +4 Input Offset Temperature Drift Input Offset Voltage ΔVOS/ΔTA — ±1.3 — Power Supply Rejection Ratio PSRR — 89 — dB IB — 1 — pA IB — 50 — pA TA= +85°C IB — 2000 — pA TA= +125°C IOS — ±1 — pA mV µV/°C TA = –40°C to +125°C, Input Bias Current and Impedance Input Bias Current Input Offset Current Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Common Mode Input Voltage Range VCMR -0.3 — +5.3 V Common Mode Rejection Ratio CMRR — 91 — dB VCM = –0.3V to 5.3V AOL — 105 — dB VOUT = 0.2V to 4.8V, VCM = VSS VOL — — 0.020 V G = +2 V/V, 0.5V input overdrive VOH 4.980 — — V G = +2 V/V, 0.5V input overdrive ISC — ±25 — mA Common Mode Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short Circuit Current Note 1: For design guidance only; not tested. © 2009 Microchip Technology Inc. DS22145A-page 3 MCP6L71/1R/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1). Parameters Sym Min (Note 1) Max (Note 1) VDD 2.0 — 6.0 V IQ 50 150 240 µA Typ Units Conditions Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: IO = 0 For design guidance only; not tested. TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. (Refer to Figure 1-1). Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 2.0 — MHz Phase Margin PM — 65 — ° Slew Rate SR — 0.9 — V/µs G = +1 V/V Noise Input Noise Voltage Eni — 4.6 — µVP-P Input Noise Voltage Density eni — 19 — nV/√Hz f = 10 kHz Input Noise Current Density ini — 3 — fA/√Hz f = 1 kHz TABLE 1-3: f = 0.1 Hz to 10 Hz TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA –40 — +125 °C Operating Temperature Range TA –40 — +125 °C Storage Temperature Range TA –65 — +150 °C Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. DS22145A-page 4 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 1.3 Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. CF 6.8 pF RG 100 kΩ VP G DM = R F ⁄ R G CB1 100 nF MCP6L7X V CM = ( V P + V DD ⁄ 2 ) ⁄ 2 VDD/2 CB2 1 µF VIN– V OST = V IN– – V IN+ V OUT = ( V DD ⁄ 2 ) + ( V P – V M ) + V OST ( 1 + G DM ) Where: GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode Input Voltage (V) © 2009 Microchip Technology Inc. VDD VIN+ EQUATION 1-1: VOST = Op Amp’s Total Input Offset Voltage RF 100 kΩ (mV) VM RG 100 kΩ RL 10 kΩ RF 100 kΩ CF 6.8 pF VOUT CL 60 pF VL FIGURE 1-1: AC and DC Test Circuit for Most Specifications. DS22145A-page 5 MCP6L71/1R/2/4 NOTES: DS22145A-page 6 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. 250 VDD = 2.0V Representitive Part Common Mode Range (V) Input Offset Voltage (µV) 300 200 150 100 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 50 0 -50 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -100 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 VCMRH – VDD One Wafer Lot VCMRL – VSS -50 -25 Common Mode Input Voltage (V) FIGURE 2-1: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.0V. PSRR, CMRR (dB) Input Offset Voltage (µV) 150 TA = +125°C 100 50 TA = +85°C TA = +25°C TA = -40°C 0 -50 110 100 CMRR (V CM = -0.3V to +5.3V) 90 PSRR (V CM = VSS) 80 70 60 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -100 -50 -25 FIGURE 2-2: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-5: Temperature. 300 200 150 100 50 VDD = 2.0V VDD = 5.5V -50 25 50 75 100 125 CMRR, PSRR vs. 110 100 CMRR, PSRR (dB) VCM = VSS Representative Part 250 0 Ambient Temperature (°C) Common Mode Input Voltage (V) Input Offset Voltage (µV) 125 120 VDD = 5.5V Representitive Part 200 0 100 FIGURE 2-4: Input Common Mode Range Voltage vs. Ambient Temperature. 300 250 0 25 50 75 Ambient Temperature (°C) CMRR 90 80 70 60 50 PSRR– PSRR+ 40 30 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-3: Output Voltage. Input Offset Voltage vs. © 2009 Microchip Technology Inc. 20 1 10 1.E+02 100 1.E+03 1k 10k 1.E+05 100k 1.E+06 1M 1.E+00 1.E+01 1.E+04 Frequency (Hz) FIGURE 2-6: Frequency. CMRR, PSRR vs. DS22145A-page 7 MCP6L71/1R/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 Input, Output Voltage (V) Input Current Magnitude (A) 6 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VDD = 5.0V G = +2 V/V 5 4 3 2 VIN 1 VOUT 0 -1 Input Voltage (V) Input Current vs. Input 0 100 -30 80 -60 Phase 60 40 -90 -120 Gain 20 -150 0 -180 FIGURE 2-8: Frequency. Frequency (Hz) Open-Loop Gain, Phase vs. 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-11: Supply Voltage. 10 0.1 1 10 100 1k 10k 100k 1M 1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 01 0 1 Frequency 2 3(Hz) 4 5 6 Input Noise Voltage Density Ouptut Short-Circuit Current (mA) Input Noise Voltage Density (nV/√Hz) TA = +125°C TA = +85°C TA = +25°C TA = -40°C 100 Quiescent Current vs. 35 100 DS22145A-page 8 150 1k 10k 100k 1M 10M 1,000 FIGURE 2-9: vs. Frequency. 200 0 1.E+07 1.E+06 1.E+05 1.E+04 100 1.E+03 10 1.E+02 1 1.E+01 0.1 1.E+00 -210 1.E-01 -20 250 Quiescent Current (µA/amplifier) 120 FIGURE 2-10: The MCP6L71/1R/2/4 Show No Phase Reversal. Open-Loop Phase (°) Open-Loop Gain (dB) FIGURE 2-7: Voltage. Time (1 ms/div) 30 25 20 15 10 5 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-12: Output Short Circuit Current vs. Supply Voltage. © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 50 45 40 35 30 25 20 15 10 5 0 1.8 1.6 VOL – VSS -IOUT Slew Rate (V/µs) VDD – VOH IOUT Falling Edge 1.2 1.0 0.8 V DD = 2.0V 0.6 Rising Edge 0.4 0.2 0.0 1 Output Current Magnitude (mA) 10 FIGURE 2-13: Ratio of Output Voltage Headroom vs. Output Current Magnitude. -50 0 25 50 75 Ambient Temperature (°C) FIGURE 2-16: Temperature. 100 125 Slew Rate vs. Ambient 10 G = +1 V/V VDD = 5.0V 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Maximum Output Voltage Swing (V P-P) 5.0 VDD = 5.5V VDD = 2.0V 1 Time (5 µs/div) Large Signal Non-inverting 10k 100k Frequency (Hz) 1M 1.E+07 1.E+03 1k 0.0 1.E+06 0.1 0.5 FIGURE 2-14: Pulse Response. -25 1.E+05 0.1 Output Voltage (V) V DD = 5.5V 1.4 1.E+04 Ratio of Output Headroom to Output Current (mV/mA) Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. 10M FIGURE 2-17: Maximum Output Voltage Swing vs. Frequency. Output Voltage (10 mV/div) G = +1 V/V Time (2 µs/div) FIGURE 2-15: Pulse Response. Small Signal Non-inverting © 2009 Microchip Technology Inc. DS22145A-page 9 MCP6L71/1R/2/4 NOTES: DS22145A-page 10 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6L71 MCP6L71R Symbol Description MSOP, SOIC SOT-23-5 SOT-23-5 2 4 4 VIN– Inverting Input 3 3 3 VIN+ Non-inverting Input 4 2 5 VSS Negative Power Supply 6 1 1 VOUT Analog Output 7 5 2 VDD Positive Power Supply 1,5,8 — — NC No Internal Connection TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6L72 MCP6L74 MSOP, SOIC SOIC, TSSOP Symbol 3.1 Description 1 1 VOUTA Analog Output (op amp A) 2 2 VINA– Inverting Input (op amp A) 3 3 VINA+ Non-inverting Input (op amp A) 8 4 VDD 5 5 VINB+ Non-inverting Input (op amp B) 6 6 VINB– Inverting Input (op amp B) 7 7 VOUTB Analog Output (op amp B) — 8 VOUTC Analog Output (op amp C) Positive Power Supply — 9 VINC– Inverting Input (op amp C) — 10 VINC+ Non-inverting Input (op amp C) Negative Power Supply 4 11 VSS — 12 VIND+ Non-inverting Input (op amp D) — 13 VIND– Inverting Input (op amp D) — 14 VOUTD Analog Output (op amp D) Analog Outputs The output pins are low impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high impedance CMOS inputs with low bias currents. © 2009 Microchip Technology Inc. 3.3 Power Supply Pins The positive power supply (VDD) is 2.0V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS22145A-page 11 MCP6L71/1R/2/4 NOTES: DS22145A-page 12 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 4.0 APPLICATION INFORMATION 4.1.3 NORMAL OPERATIONS The MCP6L71/1R/2/4 family of op amps is manufactured using Microchip’s state of the art CMOS process, specifically designed for low cost, low power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth make the MCP6L71/1R/2/4 ideal for battery powered applications. The input stage of the MCP6L71/1R/2/4 op amps uses two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other at high VCM. With this topology, and at room temperature, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS (typically at +25°C). 4.1 The transition between the two input stage occurs when VCM = VDD – 1.1V. For the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. 4.1.1 Rail-to-Rail Inputs PHASE REVERSAL The MCP6L71/1R/2/4 op amps are designed to prevent phase inversion when the input pins exceed the supply voltages. Figure 2-10 shows an input voltage exceeding both supplies without any phase reversal. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit they are in must limit the currents (and voltages) at the input pins (see Section 1.1 “Absolute Maximum Ratings †”). Figure 4-1 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and dump any currents onto VDD. VDD D1 V1 R1 D2 MCP6L7X VOUT V2 4.2 Rail-to-Rail Output The output voltage range of the MCP6L71/1R/2/4 op amps is VDD – 20 mV (minimum) and VSS + 20 mV (maximum) when RL = 10 kΩ is connected to VDD/2 and VDD = 5.0V. Refer to Figure 2-13 for more information. 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-2) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG RF RISO VOUT R2 CL RN MCP6L7X R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-1: Inputs. Protecting the Analog FIGURE 4-2: Output Resistor, RISO Stabilizes Large Capacitive Loads. Bench measurements are helpful in choosing RISO. Adjust RISO so that a small signal step response (see Figure 2-15) has reasonable overshoot (e.g., 4%). A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-7. Applications that are high impedance may need to limit the usable voltage range. © 2009 Microchip Technology Inc. DS22145A-page 13 MCP6L71/1R/2/4 4.4 Supply Bypass Guard Ring With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.5 Unused Amplifiers An unused op amp in a quad package (MCP6L74) should be configured as shown in Figure 4-3. These circuits prevent the output from toggling and causing crosstalk. In Circuit A, R1 and R2 produce a voltage within its output voltage range (VOH, VOL). The op amp buffers this voltage, which can be used elsewhere in the circuit. Circuit B uses the minimum number of components and operates as a comparator. ¼ MCP6L74 (A) 1. ¼ MCP6L74 (B) VDD VDD R1 FIGURE 4-4: Layout. 2. VDD VREF R2 V REF FIGURE 4-3: 4.6 Unused Op Amps. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP6L71/1R/2/4 family’s bias current at +25°C (1 pA, typical). VIN+ Example Guard Ring For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity Gain Buffer: a) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. b) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. 4.7 R2 = V DD ⋅ -----------------R1 + R2 VIN– Application Circuits 4.7.1 INVERTING INTEGRATOR An inverting integrator is shown in Figure 4-5. The circuit provides an output voltage that is proportional to the negative time-integral of the input. The additional resistor R2 limits DC gain and controls output clipping. To minimize the integrator’s error for slow signals, the value of R2 should be much larger than the value of R1. + VOUT MCP6L71 _ C1 VIN R1 The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. Figure 4-4 shows an example of this type of layout. R2 1 V OUT = – ------------R1 C1 ∫ 0VIN dt t R2 » R1 FIGURE 4-5: DS22145A-page 14 Inverting Integrator. © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6L71/1R/2/4 family of op amps. 5.1 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.2 MAPS (Microchip Advanced Part Selector) 5.4 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884: “Driving Capacitive Loads With Op Amps”, DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. 5.3 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Some boards that are especially useful are: • • • • • • • MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV © 2009 Microchip Technology Inc. DS22145A-page 15 MCP6L71/1R/2/4 NOTES: DS22145A-page 16 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP6L71, MCP6L71R) Device XXNN Code MCP6L71 WGNN MCP6L71R WFNN WG25 Note: Applies to 5-Lead SOT-23 8-Lead MSOP (MCP6L71, MCP6L72) Example: XXXXXX 6L72E YWWNNN 911256 8-Lead SOIC (150 mil) (MCP6L71, MCP6L72) XXXXXXXX XXXXYYWW NNN MCP6L72E e3 SN^^0911 256 Legend: XX...X Y YY WW NNN e3 * Note: Example: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22145A-page 17 MCP6L71/1R/2/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6L74) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6L74) XXXXXXXX YYWW NNN DS22145A-page 18 MCP6L74 e3 E/SL^^ 0911256 Example: 6L74EST 0911 256 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 3# 4# 5$8 %1 4 44"" 5 5 7 ( !1# 6$# ! 4 56 ()* !1# 6, 9 # ! !1 / / # !%% 6, <!# ! !1 / 6, 4 # <!# )* : ; : ( : ( " : " : ; : .#4 # 4 : = .# # 4 ( : ; .# > : > 4 ; : = !/ 4 !<!# 8 : ( !"!#$! !% #$ !% #$ # & ! !# "'( )*+ ) # & #, $ --#$## ! - * ) © 2009 Microchip Technology Inc. DS22145A-page 19 MCP6L71/1R/2/4 !" .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 3# 4# 5$8 %1 44"" 5 5 =()* 6, 9 # / # !%% 6, <!# ! !1 / 6, 4 # 7 ; 1# ! !1 / 56 : : ( ;( ( : ( " <!# )* " )* )* .#4 # 4 .# # 4 .# > : ;> 4 ; : !/ = ; (". 4 !<!# 8 : 1, $ ! &% #$ , 08$#$ #8 # !-## # ! !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * ) DS22145A-page 20 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 #$%&'()*+, .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 3# 4# 5$8 %1 44"" 5 5 7 )* 6, 9 # / # !%%? 6, <!# ! !1 / 56 ; 1# ! !1 / β : : ( : : : ( " <!# 6, 4 # ( =)* " )* )* * % @ # A ( : ( .#4 # 4 : .# # 4 .# > : ;> 4 !/ : ( 4 !<!# ". 8 : ( ! %# (> : (> ! %# )## (> : (> 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * () © 2009 Microchip Technology Inc. DS22145A-page 21 MCP6L71/1R/2/4 #$%&'()*+, .# #$ # / ## +22--- 2 DS22145A-page 22 ! - / 0 # 1 / % # # ! # © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 -. #$%&'()*+, .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 3 e h b A2 A c φ L A1 β L1 3# 4# 5$8 %1 44"" 5 5 7 )* 6, 9 # / # !%%? 6, <!# ! !1 / 56 1# ! !1 / α h : : ( : : : ( " <!# 6, 4 # ( =)* " )* ;=()* * % @ # A ( : ( .#4 # 4 : .# # 4 .# > : ;> 4 !/ : ( 4 !<!# ". 8 : ( ! %# (> : (> ! %# )## (> : (> 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * =() © 2009 Microchip Technology Inc. DS22145A-page 23 MCP6L71/1R/2/4 .# #$ # / ## +22--- 2 DS22145A-page 24 ! - / 0 # 1 / % # # ! # © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 -. / / ! #.&.)* .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 e b A2 A c A1 φ L L1 3# 4# 5$8 %1 44"" 5 5 7 1# =()* 6, 9 # ! !1 / 56 / # !%% 6, <!# : : ; ( ( : ( " =)* ! !1 / <!# " ! !1 / 4 # ( ( .#4 # 4 ( = ( .# # 4 .# I > : ;> 4 : !/ ( ". 4 !<!# 8 : 1, $ ! &% #$ , 08$#$ #8 # !-## # ! !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * ;) © 2009 Microchip Technology Inc. DS22145A-page 25 MCP6L71/1R/2/4 NOTES: DS22145A-page 26 © 2009 Microchip Technology Inc. MCP6L71/1R/2/4 APPENDIX A: REVISION HISTORY Revision A (March 2009) • Original data sheet release. © 2008 Microchip Technology Inc. DS22145A-page 27 MCP6L71/1R/2/4 NOTES: DS22145A-page 28 © 2008 Microchip Technology Inc. MCP6L71/1R/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX Temperature Range Package Examples: a) Device b) c) Device: MCP6L71T: MCP6L71RT: MCP6L72T: MCP6L74T: Single Op Amp (Tape and Reel) (MSOP, SOIC, SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) Dual Op Amp (Tape and Reel) (MSOP, SOIC) Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Temperature Range: E = -40°C to +125°C Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6L71, MCP6L71R) MS = Plastic MSOP, 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mm Body), 14-lead © 2009 Microchip Technology Inc. MCP6L71T-E/OT: Tape and Reel, 5LD SOT-23 package. MCP6L71T-E/MS: Tape and Reel, 8LD MSOP package. MCP6L71T-E/SN: Tape and Reel, 8LD SOIC package. a) MCP6L71RT-E/OT: Tape and Reel, 5LD SOT-23 package. a) MCP6L72T-E/MS: Tape and Reel, 8LD MSOP package. MCP6L72T-E/SN: Tape and Reel, 8LD SOIC package. b) a) MCP6L74T-E/SL: b) MCP6L74-E/ST: Tape and Reel, 14LD SOIC package. Tape and Reel, 14LD TSSOP package. DS22145A-page 29 MCP6L71/1R/2/4 NOTES: DS22145A-page 30 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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