Intersil ISL65426 6a dual synchronous buck regulator with integrated mosfet Datasheet

ISL65426
®
Data Sheet
February 21, 2007
FN6340.2
6A Dual Synchronous Buck Regulator
with Integrated MOSFETs
Features
The ISL65426 is a high efficiency dual output monolithic
synchronous buck converter operating over an input
voltage range of 2.375V to 5.5V. This single chip power
solution provides two output voltages which are selectable
or externally adjustable from 1V to 80% of the supply
voltage while delivering up to 6A of total output current. The
two PWMs are synchronized 180° out of phase reducing
the RMS input current and ripple voltage.
• Fixed Frequency: 1MHz
The ISL65426 switches at a fixed frequency of 1MHz and
utilizes current-mode control with integrated compensation
to minimize the size and number of external components
and provide excellent transient response. The internal
synchronous power switches are optimized for good
thermal performance, high efficiency, and eliminate the
need for an external Schottky diode.
• Ultra-Compact DC/DC Converter Design
A unique power block architecture allows partitioning of six
1A capable blocks to support one of four configuration
options. One master power block is associated with each
synchronous converter channel. Four floating slave power
blocks allow the user to assign them to either channel.
Proper external configuration of the power blocks is verified
internally prior to soft-start initialization.
Independent enable inputs allow for synchronization or
sequencing soft-start intervals of the two converter
channels. A third enable input allows additional sequencing
for multi-input bias supply designs. Individual power good
indicators (PG1, PG2) signal when output voltage is within
regulation window.
The ISL65426 integrates protection for both synchronous
buck regulator channels. The fault conditions include
overcurrent, undervoltage, and IC thermal monitor.
High integration contained in a thin Quad Flat No-lead
(QFN) package makes the ISL65426 an ideal choice to
power many of today’s small form factor applications. A
single chip solution for large scale digital ICs, like field
programmable gate arrays (FPGA), requiring separate core
and I/O voltages.
• High Efficiency: Up to 95%
• Operates From 2.375V to 5.5V Supply
• ±1% Reference
• Flexible Output Voltage Options
- Programmable 2-Bit VID Input
- Adjustable Output From 0.6V to 4.0V
• User-Partitioned Power Blocks
• PWMs Synchronized 180° Out of Phase
• Independent Enable Inputs and System Enable
• Stable All Ceramic Solutions
• Excellent Dynamic Response
• Independent Output Digital Soft-Start
• Power Good Output Voltage Monitor
• Short-Circuit and Thermal-Overload Protection
• Overcurrent and Undervoltage Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• FPGA, CPLD, DSP, and CPU Core and I/O Voltages
- Xilinx Spartan IIITM, Virtex IITM, Virtex II ProTM,
Virtex 4TM
- Altera StratixTM, Stratix IITM, CycloneTM, Cyclone IITM
- Actel FusionTM, LatticeSCTM, LatticeECTM
• Low-Voltage, High-Density Distributed Power Systems
• Point-of-Load Regulation
• Distributed Power Systems
• Set-Top Boxes
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10
QFN
L50.5x10
ISL65426IRZA* ISL65426 IRZ -40 to +85 50 Ld 5x10
QFN
L50.5x10
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2006-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL65426
Pinout
PG2
FB2
PG1
EN
ISET2
EN2
EN1
FB1
ISL65426
(50 LD QFN)
TOP VIEW
50 49 48 47 46 45 44 43
PGND 1
42 PGND
PGND 2
41 PGND
PGND 3
40 PGND
PGND 4
39 PGND
LX1 5
38 LX6
LX1 6
37 LX6
PVIN1 7
36 PVIN6
PGND
PVIN2 8
35 PVIN5
LX2 9
34 LX5
PGND 10
33 PGND
PGND 11
32 PGND
LX3 12
31 LX4
PVIN3 13
30 PVIN4
VCC 14
29 PGND
VCC 15
28 PGND
VCC 16
27 GND
PGND 17
26 GND
2
PGND
PGND
V2SET2
V2SET1
ISET1
V1SET2
PGND
V1SET1
18 19 20 21 22 23 24 25
FN6340.2
February 21, 2007
ISL65426
Typical Application Schematics
SINGLE INPUT SUPPLY
EN
EN2
EN1
3.3V
PG2
PG1
3.3V
PVIN1
PVIN6
PVIN2
PVIN5
3.3V
3.3V
C1
22μF
C4
PVIN4
PVIN3
LX1
LX6
LX2
LX5
L2
L1
1μH
C2
200μF
LX4
FB1
FB2
2.5V
3A
1μH
C3
200μF
ISL65426
LX3
VCC
3.3V
C5
0.1μF
GND
V2SET1
V1SET2
V2SET2
ISET2
V1SET1
PGND
ISET1
1.2V
3A
22μF
3.3V
FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION
3
FN6340.2
February 21, 2007
ISL65426
Typical Application Schematics (Continued)
DUAL INPUT SUPPLY
PG2
EN
EN1
5.0V
EN2
PG1
3.3V
PVIN1
PVIN6
PVIN2
5.0V
3.3V
PVIN3
C1
22μF
PVIN5
C4
22μF
PVIN4
LX6
L2
LX5
1.0μH
ISL65426
C3
100μF
LX1
LX2
L1
FB2
LX3
0.6μH
C2
200μF
VCC
LX4
5.0V
C5
0.1μF
FB1
GND
V2SET2
V1SET1
ISET2
V2SET1
V1SET2
PGND
ISET1
1.5V
4A
1.8V
2A
3.3V
FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION
4
FN6340.2
February 21, 2007
ISL65426
Typical Application Schematics (Continued)
EN
EN2
EN1
5.0V
PG2
PG1
5.0V
PVIN1
PVIN5
PVIN2
5.0V
C2
22μF
PVIN3
C1
22μF
C4
5.0V
22μF
PVIN4
PVIN6
LX5
L2
2.2μH
ISL65426
LX1
C3
100μF
3.3V
1A
LX2
LX3
L1
FB2
LX4
1.0μH
C2
330μF
VCC
LX6
2.5V
5A
5.0V
C5
0.1μF
FB1
31.6kΩ
GND
10kΩ
V1SET2
V1SET1
ISET1
V2SET2
V2SET1
ISET2
PGND
5.0V
FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION
5
FN6340.2
February 21, 2007
ISL65426
Functional Block Diagram
EN2
EN
VCC GND
POWER-ON
RESET (POR)
EN1
PVINx
PVINx
CURRENT
SENSE
SLOPE
COMPENSATION
SOFT
START
EA
FB1
V1SET1
V1SET2
OUTPUT
VOLTAGE
CONFIG
GM
PWM
CONTROL
LOGIC
GATE
DRIVE
LXx
COMPENSATION
EPAD GND
UV
POWER GOOD
PGOOD1
THERMAL
MONITOR
PWM
REFERENCE
0.60V
SOFT
START
POWER
DEVICE
CONFIG
ISET1
ISET2
PVINx
POR
SLOPE
COMPENSATION
SOFT
START
EA
FB2
V2SET1
V2SET2
OUTPUT
VOLTAGE
CONFIG
CURRENT
SENSE
GM
PWM
CONTROL
LOGIC
GATE
DRIVE
LXx
COMPENSATION
EPAD GND
OV UV
POWER GOOD
PGOOD2
6
FN6340.2
February 21, 2007
ISL65426
Absolute Maximum Ratings
Thermal Information
VCC, PVINx, LXx . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +6V
FBx, ENx, VxSETx, ISETx, PGOODx . . . . . . . . -0.3V to VCC+0.3V
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Resistance
Recommended Operating Input Range
VCC, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.375V to +5.5V
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
23
2.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +260°C
Ambient Temperature Range (ISL65426HRZ). . . . .-10°C to +100°C
Ambient Temperature Range (ISL65426IRZA) . . . . .-40°C to +85°C
Operating Junction Temperature Range . . . . . . . . .-10°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150°C junction may trigger the shutdown of
the device even before 150°C, since this number is specified as typical.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
Recommended operating conditions unless otherwise noted. VCC = PVIN = 5.0V,
TA = -10°C to +100°C for ISL65426HRZ and TA = -40°C to +85°C for ISL65426IRZA. (Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Quiescent Supply Current
EN1 = EN2 = EN = VCC = 5V, IOUT1 = IOUT2 = 0mA
30
Shutdown Supply Current
EN1 = EN2 = EN = GND, VCC = PVIN = 5.5V
5.4
7
mA
EN1 = EN2 = EN = GND, VCC = PVIN = 3.3V
2.8
3.2
mA
EN1 = EN2 = EN = GND, VCC = PVIN = 2.375V
1.7
mA
1
mA
mA
PHASE CONFIGURATION
LX Pull Down
LX1,LX3, LX4, LX5, LX6 Only - Configuration Only
LX Output Leakage
Low Level, Single LX output
-5
5
μA
High Level, Single LX output
-5
5
μA
Minimum Controllable ON time
(Note 3)
125
ns
OUTPUT VOLTAGE TOLERANCE
Reference Voltage Tolerance
Programmed Output Voltage Tolerance
TJ = -40°C to +100°C
0.594
0.6
0.606
V
TJ = 100°C to +125°C
0.591
0.6
0.609
V
TJ = -40°C to +125°C
2
2
%
1.15
MHz
OSCILLATOR
Accuracy
0.85
1
Maximum LX Pulse Width
950
ns
Minimum LX Pulse Width
50
ns
OUTPUT VOLTAGE SELECTION
VxSETx Input High Threshold
VxSETx Pull Down
0.4
1.2
1.5
V
7
10
15
μA
0.4
1.2
1.5
V
7
10
15
μA
POWER BLOCKS
ISETx Input High Threshold
ISETx Pull Up
7
FN6340.2
February 21, 2007
ISL65426
Electrical Specifications
Recommended operating conditions unless otherwise noted. VCC = PVIN = 5.0V,
TA = -10°C to +100°C for ISL65426HRZ and TA = -40°C to +85°C for ISL65426IRZA. (Note 2) (Continued)
PARAMETER
TEST CONDITIONS
Maximum Output Current
MIN
TYP
MAX
UNITS
Per Block; VCC = PVIN = 5.0V; VOUT = 1.8V (Note 3)
1.0
A
Per Block; VCC = PVIN = 2.375V; VOUT = 1.2V
(Note 3)
1.0
A
Peak Output Current Limit
Per Block
2.0
A
Upper Device rDS(ON)
0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V
60
Lower Device rDS(ON)
0.4A Per Block, VCC = PVIN = 3.3V, VOUT = 1.8V
30
Efficiency
0.5A Per Block, VCC = PVIN = 3.3V, VOUT = 1.1V
90
%
0.5A Per Block, VCC = PVIN = 5V, VOUT = 2.5V
95
%
100
140
mΩ
55
85
mΩ
POWER-ON RESET AND ENABLE PINS
VCC POR Threshold
PVIN POR Threshold
PVIN Bias Output Voltage Enable Threshold
EN1/EN2 Threshold
VCC Rising
2.15
2.25
2.35
V
VCC Falling
2.05
2.15
2.25
V
PVIN Rising; Configuration 5:1
1.9
2.05
2.15
V
PVIN Falling; Configuration 5:1
1.75
1.90
2.00
V
VOUT2 = 3.3V; VCC = PVIN
4.1
4.3
4.5
V
VOUT2 = 2.5V; VCC = PVIN
2.8
2.9
3.0
V
Rising Threshold; VCC = 5V
1.0
1.2
1.45
V
Hysteresis
Rising Threshold; VCC = 3.3V
280
0.75
Hysteresis
Rising Threshold; VCC = 2.375V
EN1/EN2 Pull Up
EN Sink Current
EN = GND
1.20
200
0.55
Hysteresis
EN Threshold
0.98
mV
0.82
V
mV
1.05
185
V
mV
7
10
15
μA
0.57
0.6
0.63
V
7
11
15
μA
Soft-Start Time
4
ms
POWER GOOD SIGNAL
Rising Threshold
As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V
110
115
120
%
Rising Hysteresis
As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V
5
7
9
%
Falling Threshold
As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V
80
85
90
%
Falling Hysteresis
As % of VREF; VOUT1 = 1.8V; VOUT2 = 3.3V
4
7
9
%
Power Good Drive
VCC = 5V; PG1 = PG2 = 0.4V
1
mA
Power Good Leakage
1
μA
PROTECTION FEATURES
Undervoltage Monitor
Undervoltage Trip Threshold
As % of VREF
70
75
80
%
Undervoltage Recovery Threshold
As % of VREF
82
89
95
%
THERMAL MONITOR
Thermal Shutdown Temperature (Note 3)
150
°C
NOTE:
3. Not production tested.
8
FN6340.2
February 21, 2007
ISL65426
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C.
100
100
90
90
80
80
70
2.5VIN
3.3VIN
60
70
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
5.5VIN
50
40
30
30
10
10
1.0
2.0
3.0
2.5VIN
40
20
0.1
0
0.1
4.0
1.0
OUTPUT LOAD (A)
3.0
4.0
FIGURE 5. VOUT1 = 1.5V EFFICIENCY vs LOAD
100
100
90
90
80
80
3.3VIN
70
5.5VIN
60
2.5VIN
50
40
30
70
EFFICIENCY (%)
EFFICIENCY (%)
2.0
OUTPUT LOAD (A)
FIGURE 4. VOUT1 = 1.2V EFFICIENCY vs LOAD
50
20
10
2.0
3.0
5.5VIN
30
10
1.0
3.3VIN
40
20
0.1
2.5VIN
60
0
0
0.1
4.0
0.5
OUTPUT LOAD (A)
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 6. VOUT1 = 1.8V EFFICIENCY vs LOAD
FIGURE 7. VOUT2 = 1.8V EFFICIENCY vs LOAD
100
100
90
90
80
80
4VIN
70
EFFICIENCY (%)
EFFICIENCY (%)
5.5VIN
50
20
0
3.3VIN
60
60
50
5.5VIN
3VIN
40
30
4.5VIN
70
60
5.5VIN
50
5VIN
40
30
20
20
10
10
0
0
0.1
0.5
1.0
1.5
OUTPUT LOAD (A)
FIGURE 8. VOUT2 = 2.5V EFFICIENCY VS LOAD
9
2.0
0.1
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 9. VOUT2 = 3.3V EFFICIENCY vs LOAD
FN6340.2
February 21, 2007
ISL65426
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C. (Continued)
1.235
1.235
1.225
1.225
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Typical Performance Curves
1.215
5.5VIN
1.205
1.195
1.185
3.3VIN
2.5VIN
1.175
1.165
0.1
1.0
NO LOAD
1.205
1.195
1.185
4A LOAD
1.175
2.0
OUTPUT LOAD (A)
3.0
1.165
2.0
4.0
1.545
1.535
1.535
OUTPUT VOLTAGE (V)
1.525
5.5VIN
1.505
1.495
1.485
2.5VIN
1.475
1.465
1.0
2.0
3.0
4.0
4.5
5.0
5.5
2A LOAD
1.525
1.515
NO LOAD
1.505
1.495
1.485
1.475
1.455
2.0
4.0
4A LOAD
2.5
3.0
OUTPUT LOAD (A)
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 12. VOUT1 = 1.5V REGULATION vs LOAD
FIGURE 13. VOUT1 = 1.5V REGULATION vs VIN
1.845
1.845
1.825
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.5
1.465
3.3VIN
1.455
0.1
3.0
FIGURE 11. VOUT1 = 1.2V REGULATION vs VIN
1.545
1.515
2.5
INPUT VOLTAGE (V)
FIGURE 10. VOUT1 = 1.2V REGULATION vs LOAD
OUTPUT VOLTAGE (V)
2A LOAD
1.215
5.5VIN
1.805
1.785
2.5VIN
1.765
1.745
0.1
1.0
2.0
OUTPUT LOAD (A)
3.3VIN
3.0
FIGURE 14. VOUT1 = 1.8V REGULATION vs LOAD
10
4.0
1.825
2A LOAD
NO LOAD
1.805
1.785
1.765
1.745
2.0
4A LOAD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 15. VOUT1 = 1.8V REGULATION vs VIN
FN6340.2
February 21, 2007
ISL65426
Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C. (Continued)
1.845
OUTPUT VOLTAGE (V)
1.845
1.825
OUTPUT VOLTAGE (V)
3.3VIN
2.5VIN
1.805
1.785
5.5VIN
1.765
1.825
NO LOAD
1.805
1.785
1.765
1A LOAD
2A LOAD
1.745
0.1
1.745
0.5
1.0
OUTPUT LOAD (A)
1.5
2.0
2.0
2.565
2.565
2.545
2.545
3.3VIN
2.525
4VIN
2.505
2.485
2.465
5.5VIN
2.445
2.425
0.1
1.0
OUTPUT LOAD (A)
2A LOAD
2.0
2.5
3.0
3.5
4.0
4.5
1A LOAD
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 19. VOUT2 = 2.5V REGULATION vs VIN
3.400
3.380
3.380
3.360
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.465
3.400
5.5VIN
4.5VIN
3.320
3.300
3.280
3.260
3.240
3.220
3.200
0.1
5.5
2.485
2.0
1.5
5.0
2.505
2.445
FIGURE 18. VOUT2 = 2.5V REGULATION vs LOAD
3.340
3.5
4.0
4.5
INPUT VOLTAGE (V)
NO LOAD
2.525
2.425
0.5
3.0
FIGURE 17. VOUT2 = 1.8V REGULATION vs VIN
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 16. VOUT2 = 1.8V REGULATION vs LOAD
2.5
3.360
NO LOAD
3.340
3.320
3.300
3.280
3.260
3.240
3.220
5VIN
2A LOAD
1A LOAD
3.200
0.5
1.0
1.5
OUTPUT LOAD (A)
FIGURE 20. VOUT2 = 3.3V REGULATION vs LOAD
11
2.0
4.0
4.25
4.5
4.75
5.0
5.25
5.5
INPUT VOLTAGE (V)
FIGURE 21. VOUT2 = 3.3V REGULATION vs VIN
FN6340.2
February 21, 2007
ISL65426
Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C. (Continued)
EN1 5V/DIV
EN1 5V/DIV
VOUT1 500mV/DIV
VOUT1 500mV/DIV
IL1 1A/DIV
IL1 1A/DIV
PG1 5V/DIV
PG1 5V/DIV
FIGURE 22. START-UP VOUT1 = 1.2V (NO LOAD)
FIGURE 23. START-UP VOUT1 = 1.2V (UNDER PRE-BIASED)
EN1 5V/DIV
EN1 5V/DIV
VOUT1 500mV/DIV
VOUT1 500mV/DIV
IL1 2A/DIV
IL1 1A/DIV
PG1 5V/DIV
POK1 5V/DIV
FIGURE 24. START-UP VOUT1 = 1.2V (FULL LOAD)
FIGURE 25. SHUTDOWN VOUT1 = 1.2V
EN2 5V/DIV
EN2 5V/DIV
VOUT2 1V/DIV
VOUT2 1V/DIV
IL2 1A/DIV
IL2 1A/DIV
PG2 5V/DIV
FIGURE 26. START-UP VOUT2 = 3.3V (NO LOAD)
12
PG2 5V/DIV
FIGURE 27. START-UP VOUT2 = 3.3V (UNDER PRE-BIASED)
FN6340.2
February 21, 2007
ISL65426
Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C. (Continued)
EN2 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 1V/DIV
IOUT1 1A/DIV
IL2 1A/DIV
VOUT2 RIPPLE 20mV/DIV
PG2 5V/DIV
FIGURE 28. START-UP VOUT2 = 3.3V (FULL-LOAD)
FIGURE 29. VOUT1 = 1.2V LOAD TRANSIENT
VOUT1 RIPPLE 20mV/DIV
LX1 5V/DIV
IOUT1 500mA/DIV
VOUT1 500mV/DIV
VOUT2 RIPPLE 50mV/DIV
IL1 5A/DIV
PG1 5V/DIV
FIGURE 30. VOUT1 = 1.2V LOAD TRANSIENT
FIGURE 31. VOUT1 = 1.2V OUTPUT SHORT CIRCUIT
LX1 5V/DIV
LX2 5V/DIV
VOUT1 500mV/DIV
VOUT2 1V/DIV
IL2 5A/DIV
IL1 5A/DIV
PG1 5V/DIV
FIGURE 32. VOUT1 = 1.2V OUTPUT SHORT CIRCUIT
RECOVERY
13
PG2 5V/DIV
FIGURE 33. VOUT2 = 3.3V OUTPUT SHORT CIRCUIT
FN6340.2
February 21, 2007
ISL65426
Typical Performance Curves
Circuit of Figure 2. VIN = 5V, IOUT1 = 4A, IOUT2 = 2A, TA = -10°C to +100°C unless otherwise
noted. Typical values are at TA = +25°C. (Continued)
LX2 5V/DIV
VOUT2 1V/DIV
IL2 5A/DIV
PG2 5V/DIV
Pin Descriptions
FB2
PG2
ISET2
PG1
EN
EN2
EN1
FB1
FIGURE 34. VOUT2 = 3.3V OUTPUT SHORT CIRCUIT RECOVERY
VCC
50 49 48 47 46 45 44 43
PGND 1
42 PGND
PGND 2
41 PGND
PGND 3
40 PGND
PGND 4
39 PGND
LX1 5
38 LX6
LX1 6
37 LX6
PVIN1 7
36 PVIN6
PGND
PVIN2 8
35 PVIN5
LX2 9
34 LX5
PGND 10
33 PGND
PGND 11
32 PGND
LX3 12
The bias supply input for the small signal circuitry. Connect
this pin to the highest supply voltage available if two or more
options are available. Locally filter this pin using a quality
0.1μF ceramic capacitor and 5Ω resistor (optional).
PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6
These pins are the power supply pins for the corresponding
PWM power blocks. Associated power blocks must all tie to
the same power supply. The power supply must fall in the
range of 2.375V to 5.5V.
GND
Signal ground. All small signal components connect to this
ground, which in turn connects to PGND at one point.
31 LX4
PVIN3 13
30 PVIN4
VCC 14
29 PGND
VCC 15
28 PGND
VCC 16
27 GND
PGND 17
PGND
Power ground for the PWM power blocks and thermal relief
for the package. The exposed pad must be connected to
PGND and soldered to the PCB. Connect these pins closely
to the negative terminal of input and output capacitors.
26 GND
PGND
PGND
V2SET2
V2SET1
ISET1
V1SET2
V1SET1
PGND
18 19 20 21 22 23 24 25
FB1, FB2
Voltage feedback input. Depending on voltage selection pin
settings, connect an optional resistor divider between VOUT
and GND for selection of a variable output voltage.
LX1, LX2, LX3, LX4, LX5, LX6
Switch node connection to inductor. This pin connects to the
internal synchronous power MOSFET switches. The
average voltage of this node is equal to the regulator output
voltage.
14
FN6340.2
February 21, 2007
ISL65426
EN
System enable for voltage monitoring with programmable
hysteresis. This pin has a POR rising threshold of 0.6V. This
enable is intended for applications where two or more input
power supplies are used and bias rise time is an issue.
The remaining four floating power blocks can be partitioned
in one of four valid states outlined in Table 1. The controller
detects the programmed configuration based on the state of
logic signals at pins ISET1 and ISET2. The controller checks
the power block configuration versus the programmed
configuration before the either converter can soft-start.
EN1, EN2
These pins are threshold-sensitive enable inputs for the
individual PWM converters. These pins have low current
(10μA) internal pull-ups to VCC. This pin disables the
respective converter until pulled above a 1V rising threshold.
ISET1, ISET2
Each power block has a separate power supply connection
pin, PVINx, and common channels must join these inputs to
one input power supply. Common synchronous power switch
connection points for each channel must be tied together
and to an external inductor. See the “Typical Application
Schematics” for pin connection guidance.
Power block configuration inputs. Select the proper state for
each pin according to Table 1.
TABLE 1. POWER BLOCK CONFIGURATION
I1SET I2SET IOUT1
V1SET1, V1SET2, V2SET1, V2SET2
CHANNEL 1
CONNECTIONS
IOUT2
CHANNEL 2
CONNECTIONS
Output voltage configuration inputs. Select the proper state
of each pin per the electrical specification table.
1
1
3A
LX1,LX2,LX3
3A
LX4,LX5,LX6
1
0
4A
LX1,LX2,LX3,LX4
2A
LX5,LX6
PG1, PG2
0
1
5A
1A
LX5
Power good output. Open drain logic output that is pulled to
ground when the output voltage is outside regulation limits.
LX1,LX2,LX3,LX4
,LX6
0
0
2A
LX1,LX2
4A
LX3,LX4,LX5,LX6
Invalid LX Configurations: SS Prevented
Functional Description
The ISL65426 is a monolithic, constant frequency, currentmode dual output buck converter controller with user
configurable power blocks. Designed to provide a total
DC/DC solution for FPGAs, CPLDs, core processors, and
ASICs.
PVIN1
PVIN6
POWER BLOCK 1
POWER BLOCK 6
LX1
LX6
PVIN2
PVIN5
POWER BLOCK 2
LX2
POWER BLOCK 5
LX5
PVIN3
PVIN4
POWER BLOCK 3
POWER BLOCK 4
LX3
LX4
MASTER POWER BLOCK
FLOATING POWER BLOCK
FIGURE 35. POWER BLOCK DIAGRAM
Power Blocks
A unique power block architecture allows partitioning of six
1A capable modules to support one of four power block
configuration options. The block diagram in Figure 3
provides a top level view of the power block layout. One
master power block is assigned to each converter output
channel. Power Block 2 is allotted to converter Channel 1
and Power Block 5 to Channel 2. The master power blocks
must not be tied together or the controller will not soft-start.
15
X
X
1A
LX2
5A
LX1,LX3,LX4,
LX5,LX6
Each power block has a scaled pilot device providing current
feedback. The configuration pin settling determines how the
controller handles separation and summing of the individual
current feedback signals.
Main Control Loop
The ISL65426 is a monolithic, constant frequency, currentmode step-down DC/DC converter. During normal operation,
the internal top power switch is turned on at the beginning of
each clock cycle. Current in the output inductor ramps up
until the current comparator trips and turns off the top power
MOSFET. The bottom power MOSFET turns on and the
inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier
monitors VOUT and compares it with the internal voltage
reference. The error amplifier’s output voltage drives a
proportional current to the pilot. If VOUT is low the pilot’s
current level is increased and the trip off current level of the
output is increased. The increased current works to raise the
VOUT level into agreement with the voltage reference.
Output Voltage Programming
The feedback voltage applied to the inverting input of the
error amplifier is scaled internally relative to the 0.6V internal
reference voltage based on the state of logic signals at pins
V1SET1, V1SET2, V2SET1 and V2SET2. The output
voltage configuration logic decodes the 2-bit voltage
identification codes into one of the discrete voltages shown
FN6340.2
February 21, 2007
ISL65426
in Table 2. When Each pin is pulled to GND by an internal
10μA pull down, this default condition programs the output
voltage to the lowest level. The pull down prevents situations
where a pin could be left floating for example (cold solder
joint) from causing the output voltage to rise above the
programmed level and damage a sensitive load device.
TABLE 2. OUTPUT VOLTAGE PROGRAMMING
VOUT1
V1SET1
V1SET2
VOUT2
V2SET1
V2SET2
1.8V
1
1
3.3V
1
1
1.5V
0
1
2.5V
0
1
1.2V
1
0
1.8V
1
0
0.6V
0
0
0.6V
0
0
ISL65426
commanded output voltage is within the proper window of
operation, the power good signal corresponding to the active
channel changes state from low to high indicating proper
operation initialization.
Power-On Reset
The POR circuitry prevents the controller from attempting to
soft-start before sufficient bias is present at vital power
supply input pins. These include the VCC and PVINx pins.
The VCC pins have a variable POR threshold based on the
output voltage configuration pin configuration of VOUT2. If
the configuration pins are set for 2.5V, the VCC POR rising
threshold is typically 2.9V. The 3.3V configuration increases
the VCC POR level to 4.3V. This variable rising threshold
guarantees that the controller can properly switch the
internal power blocks at the assigned output voltage levels.
EXTERNAL CONDITIONS
LOUT
LX
The PVINx pins have a set POR rising threshold for all
output voltage configurations. While the voltage on these
pins are below this threshold, as defined in the “Electrical
Specifications” table on page 7, the controller inhibits
switching of the internal power MOSFETs.
VOUT
1.4V
COUT
R1
13.3kΩ
FB
R2
10kΩ
FIGURE 36. EXTERNAL OUTPUT VOLTAGE SELECTION
For designers requiring an output voltage level outside those
shown Table 2, the ISL65426 allows user programming with
an external resistor divider (see Figure 4). First, both
channel selection pins associated with that output channel
must tied to GND to set the internal reference to 0.6V. Next,
the output voltage is set by an external resistive divider
according to Equation 1. R2 is selected arbitrarily, but 5kΩ or
10kΩ is usually a good starting point. The designer can
configure the output voltage from 1V to 4V from a 5V power
supply. Lower input supply voltages reduce the maximum
programmable output voltage to 80% of the input voltage
level.
V OUT – 0.6V
R1 = R2 ⋅ ---------------------------------0.6V
(EQ. 1)
Switching Frequency
The controller features an internal oscillator running at a
fixed frequency of 1MHz. The oscillator tolerance is +10%
over input bias and load range.
Operation Initialization
The ISL65426 initializes based on the state of three enable
inputs (EN, EN1, EN2) and power-on reset (POR) monitors
on VCC and PVINx inputs. Successful initialization of the
controller prompts a one time power block configuration
check. Verification of proper phase connections lead to a
soft-start interval. The controller begins slowly ramping the
output voltages based on the enable input states. Once the
16
Built-in hysteresis between the rising and falling thresholds
insures that once enabled, the controller will not
inadvertently toggle turn off unless the bias voltage drops
substantially. While these pins are below the POR rising
threshold, the synchronous power switch LX pins are held in
a high-impedance state.
If additional POR control is required, a system enable input
can be used to govern initialization as described in the next
section.
Enable and Disable
If the POR input requirements are met, the ISL65426
remains in shutdown until the voltage at the enable inputs
rise above their enable thresholds. Independent enable
inputs, EN1 and EN2, allow initialization of either buck
converter channel separately, sequenced, or simultaneously.
Both pins feature a 10mA pull-up which will initialize both
sides once the voltage at their respective pins exceeds the
rising enable threshold, as defined in the “Electrical
Specifications” table on page 7.
Both converters are governed by the presence of a system
enable, EN (See Figure 5). When two separate input
supplies are used for each channel of power blocks or an
external signal needs to govern the power-up sequence, the
system enable provides a startup sequencing mechanism.
The system enable features an internal 10mA pull-down
which is only active when the voltage on the EN pin is below
the enable threshold. The current sink pulls the EN pin low.
As VCC2 rises the enable level is not set exclusively by the
resistor divider from VCC2. With the current sink active, the
enable level is defined in Equation 2. R1 is the resistor EN to
VCC2 and R2 is the resistor from EN to GND.
FN6340.2
February 21, 2007
ISL65426
0.6V
V ENABLE = R1 ⋅ ------------ + 10μA + 0.6V
R2
(EQ. 2)
Once the voltage at the EN pin reaches the enable
threshold, the 10μA current sink turns off.
With the part enabled and the current sink off, the disable
level is set by the resistor divider. The disable level is
defined in Equation 3.
R1 + R2
V DISABLE = 0.6V ⋅ ---------------------R2
(EQ. 3)
The difference between the enable and disable levels
provides the user with configurable hysteresis to prevent
nuisance tripping.
To enable the controller, the system enable must be high,
and one or both of the channel enables must be high. The
POR circuitry must be satisfied for both VCC and PVINx
inputs. Once these conditions are met, the controller
immediately initiates a power block configuration check.
ISL65426
EXTERNAL CONDITIONS
common LX connections are checked versus the decoded
valid configuration. Each floating power block has a pulldown active only during the configuration check to remove
noise related false positive detections.
A successful configuration check initiates a soft-start interval
100μs after completion. Failing the configuration check, the
controller will attempt a configuration check again 100μs
after completing the first check cycle. The controller repeats
the configuration check cycle every 100μs until a valid
configuration is detected or the controller is powered down.
Once successful, the configuration check is not implemented
again until VCC falls below the POR falling threshold.
Re-enabling the controller after a successful configuration
check will immediately initiate a soft-start interval.
Soft-start Interval
Once the controller is enabled and power block configuration
is successful, the digital soft-start function clamps the error
amplifier reference. The digital soft-start circuitry ramps the
output voltage by stepping the reference up gradually over a
fixed interval of 4ms. The controlled ramp of the output
voltage reduces the in-rush current during startup.
Power Good Signal
+VCC1
VCC
+VCC2
SYSTEM ENABLE
COMPARATOR
R1
EN
POR
LOGIC
+
R2
-
10μA
0.6V
FIGURE 37. SYSTEM ENABLE INPUT
Power Block Configuration Check
After VCC exceeds its POR rising threshold, the controller
decodes ISET1 and ISET2 states into one of four valid
power block configurations, see Table 1.These pins are not
checked again unless VCC falls below the POR falling
threshold. The valid configuration is saved for comparison
with the LX slave connectivity result determined during the
configuration check.
Once the POR and enable circuitry is satisfied, the controller
initiates a configuration check. The master power block of
output Channel 1 (Power Block 2) pulses high for 100ns.
The configuration check circuitry detects which power blocks
share a common LX connection and compare this to the
decoded valid configuration. The master power block of
output Channel 2 (Power Block 5) pulses and again the LX
pins of the other non-master blocks are monitored. The
17
Each power good pin (PG1, PG2) is an open-drain logic
output which indicates when the converter output voltage is
within regulation limits. The power good pins pull low during
shutdown and remain low when the controller is enabled.
After a successful converter channel soft-start, the power
good pin signal associated with that channel releases and
the power good pin voltage rises with an external pull-up
resistor. The power good signal transitions low immediately
upon the removal of individual channel or system enable.
The power good circuitry monitors both output voltage FB
pins and compares them to the rising and falling limits shown
in the “Electrical Specifications” table on page 7. If either
channel’s feedback voltage exceeds the typical rising limit of
115% of the reference voltage, the power good pin pulls low.
The power good pin continues to pull low until the feedback
voltage recovers down by a typical of 110% of the reference
voltage. If either channel’s feedback voltage drops below a
typical of 85% of the reference voltage, the power good pin
related to the offending channel(s) pulls low. The power
good pin continues to pull low until the feedback voltage
rises to within 90% of the reference voltage. The power good
pin then releases and signals the return of the output voltage
within the power good window.
Fault Monitoring and Protection
The ISL65426 actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the controller and external
load device. Individual power good indicators provide
options for linking to external system monitors.
FN6340.2
February 21, 2007
ISL65426
Undervoltage Protection
Separate hysteretic comparators monitor the feedback pin
(FB) of each converter channel. The feedback voltage is
compared to a set undervoltage (UV) threshold based on the
output voltage selected. Once one of the comparators trip,
indicating a valid UV condition, a 4-bit UV counter
increments. If both channel comparators detect an UV
condition during the same switching cycle, the 4-bit counter
increments twice. Once the 4-bit counter overflows, the UV
protection logic shuts down both regulators.
The comparator is reset if the feedback voltage rises back
up above the UV threshold plus a specified amount of
hysteresis outlined in the Electrical Specification Table. If
both converter channels experience an UV condition and
one rises back within regulation, then the counter continues
to progress toward overflow.
interval, the OC counter must overflow before the controller
shutdowns both outputs again. This hiccup mode continues
indefinitely until both outputs soft-start successfully.
Note: It is recommended to add a small Schottky diode, part
number MBR0520, from LX1 to PGND and from LX5 to
PGND to avoid server negative ringing that can disturb the
OC counter.
Thermal Monitor
Thermal-overload protection limits total power dissipation in
the ISL65426. An internal thermal sensor monitors die
temperature continuously. If controller junction temperature
exceeds +150°C, the thermal monitor commands the POR
circuitry to shutdown both channels and latch-off. The POR
latch is reset by cycling VCC to the controller.
Overvoltage Response
Component Selection Guide
If the output voltage exceeds the overvoltage (OV) level for
the power good signal, the controller will fight this condition
by actively trying to regulate the output voltage back down to
the reference level. This method of fighting the rise in output
voltage is limited by the reverse current capability of the total
number of power blocks associated with the output. The
approximate reverse current capability of each power block
is 0.5A. The power good signal will drop indicating the output
voltage is out of specification. This signal will not transition
high again until the output voltage has dropped below the
falling PGOOD OV threshold.
This design guide is intended to provide a high-level
explanation of the steps necessary to create a power
converter. It is assumed the reader is familiar with many of
the basic skills and techniques referenced below. In addition
to this guide, Intersil provides a complete reference design
that includes schematic, bill of material, and example board
layout.
Overcurrent Protection
A pilot device is integrated into the upper device structure of
each master power block. The pilot device samples current
through the master power block upper device each cycle. This
Channel current feedback is scaled based on the state of the
ISET1 and ISET2 pins. The Channel current information is
compared to an overcurrent (OC) limit based on the power
block configuration. Each 1A power block tied to the master
power block increases the OC limit by 2A. For example, if
both masters have two slaves associated with each of them
then the OC limit for each output is 6A for a 3A configuration.
If the sampled current exceeds the OC threshold, a 4-bit OC
up/down counter increments by one LSB. If the sampled
current falls below the OC threshold before the counter
overflows, the counter is reset. If both regulators experience
an OC event during the same cycle, the counter increments
twice. Once the OC counter reaches 1111, both channels are
shutdown. If both channels fall below the over-current limit
during the same cycle, the OC counter is reset.
Once in shutdown, the controller enters a delay interval,
equivalent to the SS interval, allowing the die to cool. The
OC counter is reset entering the delay interval. The
protection logic initiates a normal SS internal once the delay
interval ends. If the outputs both successfully soft-start, the
power good signal goes high and normal operation
continues. If OC conditions continue to exist during the SS
18
Output Filter Design
The output inductor and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase node. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter limits the system transient
response. The output capacitors must supply or sink load
current while the current in the output inductors increases or
decreases to meet the demand. The output filter is usually
the most costly part of the circuit. Output filter design begins
with minimizing the cost of these components.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output capacitors
are the maximum size of the load step (ΔI), the load-current
slew rate (di/dt), and the maximum allowable output voltage
deviation under transient loading (ΔVMAX). Capacitors are
characterized according to their capacitance, ESR (Equivalent
Series Resistance), and ESL (Equivalent Series Inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount shown in Equation 4.
FN6340.2
February 21, 2007
ISL65426
di
ΔV ≈ ESL × ----- + [ ESR × ΔI ]
dt
(EQ. 4)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current, a voltage develops
across the bulk capacitor VPPMAX. See Equation 5.
V PP
MAX
( V IN – V OUT )V OUT
= ESR × ----------------------------------------------------L × f s × V IN
(EQ. 5)
The recommended load capacitance recommended is based
on Equation 6.
C OUT = 0.5 × I OUT
MAX
× 100μF
(EQ. 6)
( 1.25 ) ⋅ C
L ≤ ------------------------- ΔV MAX – ( ΔI ⋅ ESR ) ⎛ V IN – V O⎞
⎝
⎠
( ΔI ) 2
(EQ. 9)
The other concern when selecting an output inductor is the
internally set current mode slope compensation. Designs
should not allow inductor ripple currents below 0.125 times
the maximum output current to prevent regulation issues. A
good rule of thumb for selection of the output inductance
value is 1/3 of the maximum load current for inductor ripple.
(V – V
)×V
IN
OUT
OUT
L ≅ --------------------------------------------------------------I
OUT
MAX
V × f × ----------------------------IN s
3
(EQ. 10)
The rule of thumb value, see Equation 10, with fall between
the minimum inductance value calculated in Equation 7 and
the maximum values determined from Equations 8 and 9.
Input Capacitor Selection
Input capacitors are responsible for sourcing the AC
component of the input current flowing into the switching
power devices. Their RMS current capacity must be
sufficient to handle the AC component of the current drawn
by the switching power devices which is related to duty
cycle. The maximum RMS current required by the regulator
is closely approximated by Equation 11.
I RMS
=
MAX
2
V OUT ⎛
2 1 ⎛ V IN – V OUT V OUT⎞ ⎞
----------------- × ⎜ I
+ ------ × ⎜ ---------------------------------- × -----------------⎟ ⎟
OUT
V IN
12 ⎝
L × fs
V IN ⎠ ⎠
⎝
MAX
(EQ. 11)
OUTPUT INDUCTOR SELECTION
Once the output capacitors are selected, the maximum
allowable ripple voltage, VPPMAX, determines the lower limit
on the inductance. See Equation 7.
( V IN – V OUT )V OUT
L ≥ ESR × ----------------------------------------------------f s × V IN × V PP
(EQ. 7)
MAX
Since the output capacitors are supplying a decreasing
portion of the load current while the regulator recovers from
the transient, the capacitor voltage becomes slightly
depleted. The output inductors must be capable of assuming
the entire load current before the output voltage decreases
more than ΔVMAX. This places an upper limit on inductance.
Equation 8 gives the upper limit on output inductance for the
cases when the trailing edge of the current transient causes
the greater output voltage deviation than the leading edge.
Equation 9 addresses the leading edge. Normally, the
trailing edge dictates the inductance selection because duty
cycles are usually less than 50%. Nevertheless, both
inequalities should be evaluated, and inductance should be
governed based on the lower of the two results. In each
equation, L is the output inductance and C is the total output
capacitance.
2 ⋅ C ⋅ VO
L ≤ ------------------------- ΔV MAX – ( ΔI ⋅ ESR )
( ΔI ) 2
19
(EQ. 8)
The important parameters to consider when selecting an
input capacitor are the voltage rating and the RMS current
rating. For reliable operation, select capacitors with voltage
ratings above the maximum input voltage. Their voltage
rating should be at least 1.25 times greater than the
maximum input voltage, while a voltage rating of 1.5 times is
a conservative guideline. The capacitor RMS current rating
should be higher than the largest RMS current required by
the circuit.
Layout Considerations
Careful printed circuit board (PCB) layout is critical in highfrequency switching converter design. Current transitions
from one device to another at this frequency induce voltage
spikes across the interconnecting impedances and parasitic
elements. These spikes degrade efficiency, lead to device
overvoltage stress, radiate noise into sensitive nodes, and
increase thermal stress on critical components. Careful
component placement and PCB layout minimizes the
voltage spikes in the converter.
The following multi-layer printed circuitry board layout
strategies minimize the impact of board parasitics on
converter performance and optimize the heat-dissipating
capabilities of the printed circuit board. This section
highlights some important practices which should not be
overlooked during the layout process. Figure 6 provides a
top level view of the critical components, layer utilization,
and signal routing for reference.
FN6340.2
February 21, 2007
ISL65426
Component Placement
Determine the total implementation area and orient the
critical switching components first. These include the
controller, input and output capacitors, and the output
inductors. Symmetry is very important in determining how
available space is filled and depends on the power block
configuration selected. The controller must be placed
equidistant from each output stage with the LX, or phase,
connection distance minimized.
An output stage consists of the area reserved for the output
inductor, and input capacitors, and output capacitors for a
single channel. Place the inductor such that one pad is a
minimal distance from the associated phase connection.
Orient the inductor such that the load device is a short
distance from the other pad. Placement of the input
capacitors a minimal distance from the PVIN pins prevents
long distances from adding too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductor and the load device, while
keeping them in close proximity. Care should be taken not to
add inductance through long trace lengths that could cancel
the usefulness of the low inductance components. Keeping
the components in tight proximity will help reduce parasitic
impedances once the components are routed together.
Bypass capacitors, CBP, supply critical filtering and must be
placed close to their respective pins. Stray trace parasitics
will reduce their effectiveness, so keep the distance between
the VCC bias supply pad and capacitor pad to a minimum.
Plane Allocation
usually an internal layer underneath the component side of
the board, for a ground plane and make all critical
component ground connections with vias to this layer.
One additional solid layer is dedicated as a power plane and
broken into smaller islands of common voltage. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit board layers for small signal wiring and additional
power or ground islands as required.
Signal Routing
If the output stage component placement guidelines are
followed, stray inductance in the switch current path is
minimized along with good routing techniques. Great
attention should be paid to routing the PHASE plane since
high current pulses are driven through them. Stray
inductance in this high-current path induce large noise
voltages that couple into sensitive circuitry. By keeping the
PHASE plane small, the magnitude of the potential spikes is
minimized. It is important to size traces from the LX pins to
the PHASE plane as large and short as possible to reduce
their overall impedance and inductance.
Sensitive signals should be routed on different layers or
some distance away from the PHASE plane on the same
layer. Crosstalk due to switching noise is reduced into these
lines by isolating the routing path away from the PHASE
plane. Layout the PHASE planes on one layer, usually the
top or bottom layer, and route the voltage feedback traces on
another layer remaining.
PCB designers typically have a set number of planes
available for a converter design. Dedicate one solid layer,
KEY
VIN
VIN
THICK TRACE ON CIRCUIT PLANE LAYER
PVIN
VCC
ISLAND ON CIRCUIT PLANE LAYER
CIN
CBP
ISLAND ON POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
ISL65426
PHASE
LOUT
VOUT
LX
COUT
CHFOUT
LOAD
GND
FB
PGND
FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
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ISL65426
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
PGND pad of the ISL65426 to the ground plane with multiple
vias is recommended. This heat spreading allows the IC to
achieve its full thermal potential. If possible, place the
controller in a direct path of any available airflow to improve
thermal performance.
21
FN6340.2
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ISL65426
L50.5x10
50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 7/06
5.00
0.10 M C A B
0.05 M C
A
B
4
0.25
0.50
43
A
PIN 1 INDEX AREA
(C 0.40)
50
42
1
26
17
9.20
0.50x16=8.00 REF
0.50
8.10
10.00
PIN 1
INDEX AREA
0.15 (4X)
A
25
18
VIEW "A-A"
0.40±0.10
3.30
0.50x7=3.50 REF
0.40±0.10
TOP VIEW
4.20
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
SEATING PLANE
0.08 C
SIDE VIEW
MAX. 1.00
9.80
C
8.10
0.2 REF
5
0.00 MIN.
0.05 MAX.
(46 x 0.50)
DETAIL "X"
(50 x 0.25)
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MM.
(50 x 0.60)
2. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL ±0.05
ANGULAR ±2×
3. DIMENSIONING AND TOLERANCE PER ASME Y 14.5M-1994.
4. DIMENSION LEAD WIDTH APPLIES TO THE PLATED TERMINAL
AND IS MEASURED BETWEEN 0.23MM AND 0.28MM FROM
THE TERMINAL TIP.
3.30
4.80
RECOMMENDED LAND PATTERN
5. TIEBAR SHOWN (if present) IS A NON-FUNCTIONAL FEATURE
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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