AD AD823AARZ-R7 Wide supply dual, 17 mhz, rail-to-rail Datasheet

Single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 3 V to 36 V
High load drive
Capacitive load drive of 470 pF (G = +1, 25% overshoot)
Linear output current of 40 mA, 0.5 V from supplies
Excellent ac performance on 2.6 mA/amplifier
−3 dB bandwidth of 17 MHz, G = +1
325 ns settling time to 0.01% (2 V step)
Slew rate of 30 V/μs
Low distortion: −108 dBc at 20 kHz (G = −1, RL = 2 kΩ)
Good dc performance
700 μV maximum input offset voltage
1 μV/°C offset voltage drift
25 pA maximum input bias current
Low noise: 14 nV/√Hz at 10 kHz
No phase inversion with inputs to the supply rails
CONNECTION DIAGRAM
OUT1 1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
AD823A
09439-001
FEATURES
Figure 1. 8-Lead SOIC
AD823A
OUT1 1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
–VS
5
+IN2
4
TOP VIEW
(Not to Scale)
09439-102
Data Sheet
Wide Supply Dual, 17 MHz, Rail-to-Rail
FET Input Amplifier
AD823A
Figure 2. 8-Lead MSOP
VS = 3V
CL = 50pF
G = +1
3.0V
APPLICATIONS
Photodiode preamps
Active filters
12-bit to 16-bit data acquisition systems
Medical instrumentation
Precision instrumentation
1.5V
The AD823A is a dual precision, 17 MHz, JFET input op amp
manufactured in the extra fast complementary bipolar (XFCB)
process. The AD823A can operate from a single supply of 3 V
to 36 V or from dual supplies of ±1.5 V to ±18 V. It has true
single-supply capability with an input voltage range extending
below ground in single-supply mode. Output voltage swing extends
to within 20 mV of each rail for IOUT ≤ 100 μA, providing
outstanding output dynamic range. It also has a linear output
current of 40 mA, 0.5 V from the supply rails.
An offset voltage of 700 μV maximum, an offset voltage drift of
1 μV/°C, and typical input bias currents of 0.3 pA provide dc
precision with source impedances up to 1 GΩ. The AD823A
provides 17 MHz, −3 dB bandwidth, and a 30 V/μs slew rate with
a low supply current of only 2.6 mA per amplifier. It also provides
low input voltage noise of 14 nV/√Hz and −108 dB SFDR at
20 kHz. The AD823A has low input capacitances (0.6 pF differential and 1.3 pF common mode) and drives more than 500 pF
of direct capacitive load as a follower. This lets the amplifier
handle a wide range of load conditions.
500mV/DIV
200µs/DIV
09439-049
0V
GENERAL DESCRIPTION
Figure 3. Output Swing, +VS = +3 V, G = +1
This combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile amplifier for applications such as ADC drivers, high speed active filters,
and other low voltage, high dynamic range systems.
The AD823A is available over the industrial temperature range
of −40°C to +85°C and is offered in an 8-lead SOIC package and
an 8-lead MSOP package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD823A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................7
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Theory of Operation ...................................................................... 14
Connection Diagram ....................................................................... 1
Output Impedance ..................................................................... 14
Revision History ............................................................................... 2
Applications Information .............................................................. 15
Specifications..................................................................................... 3
Input Characteristics .................................................................. 15
5 V Operation ............................................................................... 3
Output Characteristics............................................................... 15
3.3 V Operation ............................................................................ 4
Wideband Photodiode Preamp ................................................ 16
±15 V Operation ........................................................................... 5
Active Filter ................................................................................. 18
Absolute Maximum Ratings............................................................ 6
Maximizing Performance Through Proper Layout ............... 19
Thermal Resistance ...................................................................... 6
Outline Dimensions ....................................................................... 20
ESD Caution .................................................................................. 6
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/12—Rev. A to Rev. B
Added Text to Absolute Maximum Ratings Section .................... 6
Changes to Equation 8 ................................................................... 18
5/12—Revision A: Initial Version
Rev. B | Page 2 of 20
Data Sheet
AD823A
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Full Power Response
Slew Rate
Settling Time
To 0.1%
To 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion (SFDR)
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1, VOUT ≤ 0.2 V p-p
VOUT = 2 V p-p
G = −1, VOUT = 4 V step
14.1
17
4.8
30
MHz
MHz
V/µs
G = −1, VOUT = 2 V step
G = −1, VOUT = 2 V step
240
325
ns
ns
f = 10 kHz
f = 1 kHz
VOUT = 2 V p-p, f = 20 kHz, G = −1, RF = RG = 4 kΩ
VOUT = 2 V p-p, f = 20 kHz, G = +1, RL = 1 kΩ
14
1
−108
−99
nV/√Hz
fA/√Hz
dBc
dBc
RL = 5 kΩ
RL = 5 kΩ
−123
−77
dB
dB
VCM = 0 V to 4 V
VCM = 0 V to 4 V
0.12
0.2
1
0.3
10
0.3
3.5
175
VOUT = 0.2 V to 4 V, RL = 2 kΩ
25
40
25
−0.2 to +3
Differential Mode
Common Mode
VCM = 0 V to 3 V
60
VOUT = 0.5 V to 4.5 V
Sourcing to 2.5 V
Sinking to 2.5 V
G = +1
Rev. B | Page 3 of 20
70
0.7
1.3
25
25
20
Unit
mV
mV
µV/°C
pA
pA
pA
pA
V/mV
V/mV
−0.2 to +3.8
1013
0.6
1.3
73
V
Ω
pF
pF
dB
0.009 to 4.98
0.026 to 4.96
0.097 to 4.88
40
50
101
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
Max
5.1
94
36
5.7
V
mA
dB
AD823A
Data Sheet
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, RL = 2 kΩ to 1.65 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Full Power Response
Slew Rate
Settling Time
To 0.1%
To 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion (SFDR)
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1, VOUT ≤ 0.2 V p-p, VCM = 0.65 V
VOUT = 2 V p-p
G = −1, VOUT = 2 V step, VCM = 0.65 V
13.8
17.3
3.7
23
MHz
MHz
V/µs
G = −1, VOUT = 2 V step
G = −1, VOUT = 2 V step
350
460
ns
ns
f = 10 kHz
f = 1 kHz
VOUT = 2 V p-p, f = 20 kHz, G = −1, RF = RG = 4 kΩ
VOUT = 2 V p-p, f = 20 kHz, G = +1, RL = 100 Ω
14
1
−108
−70
nV/√Hz
fA/√Hz
dBc
dBc
RL = 5 kΩ
RL = 5 kΩ
−123
−77
dB
dB
VCM = 0 V to 2 V
VCM = 0 V to 2 V
0.14
0.3
1
0.3
10
0.3
3.5
63
VOUT = 0.2 V to 2 V, RL = 2 kΩ
18
16
14
−0.2 to
+1
Differential Mode
Common Mode
VCM = 0 V to 1 V
54
VOUT = 0.5 V to 2.5 V
Sourcing to 1.5 V
Sinking to 1.5 V
G = +1
Rev. B | Page 4 of 20
70
1
1.8
25
25
20
Unit
mV
mV
µV/°C
pA
pA
pA
pA
V/mV
V/mV
−0.2 to +1.8
V
1013
0.6
1.3
71
Ω
pF
pF
dB
0.006 to 3.28
0.04 to 3.26
0.093 to 3.18
40
44
86
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 3.3 V to 15 V, TMIN to TMAX
Max
5.0
80
36
5.7
V
mA
dB
Data Sheet
AD823A
±15 V OPERATION
TA = 25°C, VS = ±15 V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Full Power Response
Slew Rate
Settling Time
To 0.1%
To 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion (SFDR)
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1, VOUT ≤ 0.2 V p-p
VOUT = 2 V p-p
G = −1, VOUT = 10 V step
16.5
19
5.6
35
MHz
MHz
V/µs
G = −1, VOUT = 10 V step
G = −1, VOUT = 10 V step
380
510
ns
ns
f = 10 kHz
f = 1 kHz
VOUT = 10 V p-p, f = 20 kHz, G = −1, RF = RG =
4 kΩ
VOUT = 10 V p-p, f = 20 kHz, G = +1, RL = 600 Ω
13
1
−101
nV/√Hz
fA/√Hz
dBc
−89
dBc
RL = 5 kΩ
RL = 5 kΩ
−123
−77
dB
dB
VCM = 0 V
VCM = −10 V
VCM = 0 V
0.8
1.0
1
1.3
3.5
55
1.3
9.5
450
VOUT = +10 V to −10 V, RL = 2 kΩ
31
100
80
−15.2 to +13
Differential Mode
Common Mode
VCM = −15 V to +13 V
70
VOUT = −14.5 V to +14.5 V
Sourcing to 0 V
Sinking to 0 V
G = +1
Rev. B | Page 5 of 20
70
3.5
5
25
95
20
Unit
mV
mV
µV/°C
pA
pA
pA
pA
pA
V/mV
V/mV
−15.2 to +13.8
1013
V
Ω
0.6
1.3
90
pF
pF
dB
−14.9 to +14.96
−14.97 to +14.96
−14.91 to +14.89
44
78
124
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
Max
6.3
94
36
8.4
V
mA
dB
AD823A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
36 V
See Figure 4
±VS ± 0.7 V
±VS
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
4500 V
1250 V
The specification is for the device in free air.
Table 5. Thermal Resistance
Package Type
8-Lead SOIC_N
8-Lead MSOP
θJA
120
133
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Use the part with caution at the 30 V supply as excessive output
current may overheat and damage the part.
Unit
°C/W
°C/W
TJ = 150°C
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
0
–45 –35 –25 –15 –5
5 15 25 35 45 55
AMBIENT TEMPERATURE (°C)
65
75
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
Rev. B | Page 6 of 20
85
09439-004
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
ESD Ratings (Human Body Model)
ESD Ratings (Charged Device Model)
Data Sheet
AD823A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN1 2
7 OUT2
+IN1 3
6 –IN2
5 +IN2
–VS 4
AD823A
09439-001
8 +VS
OUT1 1
Figure 5. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT1
−IN1
+IN1
−VS
+IN2
−IN2
OUT2
+VS
Description
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
OUT1 1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
5
+IN2
–VS
4
TOP VIEW
(Not to Scale)
09439-105
AD823A
Figure 6. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT1
−IN1
+IN1
−VS
+IN2
−IN2
OUT2
+VS
Description
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
Rev. B | Page 7 of 20
AD823A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1
14
VS = ±2.5V
47 AMPLIFIERS
σ = 110fA
x = 270fA
12
0
10
UNITS
GAIN (dB)
–1
–2
8
6
–3
4
–4
1k
10k
100k
1M
0
09439-005
10M
FREQUENCY (Hz)
0
100
3
INPUT BIAS CURRENT (pA)
600
700
800
VS = +5V
40
30
20
10
1
0
–1
–2
–3
–4
–300
–200
–100
0
100
200
300
400
INPUT OFFSET VOLTAGE (µV)
–5
–5
09439-059
0
–400
–1
0
1
2
3
4
5
125
1000
VS = +5V
VCM = 0V
INPUT BIAS CURRENT (pA)
80
–2
Figure 11. Input Bias Current vs. Common-Mode Voltage
VS = +5V
–55°C TO +125°C
240 AMPLIFIERS
x = 991nV/°C
σ = 1.04µV/°C
90
–3
COMMON-MODE VOLTAGE (V)
Figure 8. Typical Distribution of Input Offset Voltage
100
–4
09439-008
UNITS
500
2
50
70
60
50
40
30
100
10
1
20
10
0
–4
0.1
–2
0
2
4
6
8
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
10
09439-007
UNITS
400
Figure 10. Typical Distribution of Input Bias Current
VS = +5V
350 UNITS
σ = 113µV
x = 10µV
60
300
INPUT BIAS CURRENT (fA)
Figure 7. Small Signal Bandwidth, G = +1
70
200
09439-010
–5
09439-009
2
VS = +5V
VOUT = 0.2V p-p
G = +1
0
25
50
75
100
TEMPERATURE (°C)
Figure 12. Input Bias Current vs. Temperature
Figure 9. Typical Distribution of Input Offset Voltage Drift
Rev. B | Page 8 of 20
Data Sheet
AD823A
100
–40
VS = ±15V
G = –1
RF = RG = 4kΩ
INPUT BIAS CURRENT (pA)
–50
VS = 3V
VOUT = 2V p-p
RL = 100Ω
–60
10
VS = 5V
VOUT = 2V p-p
RL = 1kΩ
THD (dB)
–70
–80
VS = 3V
VOUT = 2V p-p
RL = 5kΩ
VS = 30V
VOUT = 10V p-p
RL = 600Ω
–90
1
–100
–12
–8
–4
0
4
8
12
16
COMMON-MODE VOLTAGE (V)
–120
100
09439-069
1k
10k
100k
Figure 13. Input Bias Current vs. Common-Mode Voltage
Figure16. Total Harmonic Distortion vs. Frequency
103
120
RL = 2kΩ
VS = ±2.5V
110
OPEN-LOOP GAIN (dB)
100
102
101
1
10
99
–55
09439-011
80
0.1
100
LOAD RESISTANCE (kΩ)
OPEN-LOOP GAIN (dB)
10
1
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (V)
09439-065
OPEN-LOOP GAIN (kV/V)
RL = 100Ω
–1.5
95
125
120
VS = +5V
RL = 2kΩ
CL = 20pF 100
PHASE
RL = 1kΩ
–2.0
65
120
100
0.1
–2.5
35
Figure 17. Open-Loop Gain vs. Temperature
VS = ±2.5 V
RL = 10kΩ
5
TEMPERATURE (°C)
Figure 14. Open-Loop Gain vs. Load Resistance
1000
–25
09439-014
100
90
Figure 15. Open-Loop Gain vs. Output Voltage, VS = ±2.5 V
80
80
60
60
GAIN
40
40
20
20
0
0
–20
100
1k
10k
100k
1M
10M
–20
100M
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase Margin vs. Frequency
Rev. B | Page 9 of 20
PHASE MARGIN (Degrees)
OPEN-LOOP GAIN (dB)
VS = ±2.5V
100
1M
FREQUENCY (Hz)
09439-060
0.1
–16
09439-516
VS = 5V
VOUT = 2V p-p
RL = 5kΩ
–110
AD823A
Data Sheet
10
OUTPUT STEP SIZE FROM 0V TO VSHOWN (V)
+VS = +5V
30
20
10
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
8
0.1%
0.01%
4
2
0
–2
0.1%
–4
1%
0.01%
–6
–8
VS = ±15V
CL = 20pF
200
300
400
500
600
700
SETTLING TIME (ns)
Figure 19. Input Voltage Noise vs. Frequency
Figure 22. Output Step Size vs. Settling Time (Inverter)
100
1
VS = ±2.5V
CL = 20pF
RL = 2kΩ
G = +1
0
–1
+125°C
–55°C
+VS = +5V
70
CMRR (dB)
–2
+25°C
VS = ±15V
90
80
CLOSED-LOOP GAIN (dB)
1%
6
–10
100
09439-016
INPUT VOLTAGE NOISE (nV/√Hz)
40
09439-020
50
60
50
–3
40
–4
6.24
9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00
FREQUENCY (MHz)
20
10
10
OUTPUT SATURATION VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
10
1
0.1
10k
100k
1M
10M
FREQUENCY (Hz)
09439-053
0.01
1k
10k
100k
1M
10M
Figure 23. Common-Mode Rejection Ratio vs. Frequency
+VS = +5V
VS = +5V
G = +1
0.001
100
1k
FREQUENCY (Hz)
Figure 20. Closed-Loop Bandwidth vs. Temperature
100
100
Figure 21. Output Resistance vs. Frequency, +VS = +5 V, G = +1
1
0.1
VS TO VOH
25°C
0.01
VOL
25°C
0.001
0.1
1
10
LOAD CURRENT (mA)
Figure 24. Output Saturation Voltage vs. Load Current
Rev. B | Page 10 of 20
100
09439-021
3.27
09439-052
–5
0.30
09439-061
30
Data Sheet
AD823A
8
16
7
14
6
12
+VS = +5V
VIN
RS
+125°C
5
+25°C
–55°C
4
3
2
1
10
8
Φm = 45°
6
4
Φm = 20°
2
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (±V)
0
09439-525
0
0
3
4
5
6
7
8
9
10
Figure 28. Series Resistance vs. Capacitive Load
–60
100
VS = +5V
GAIN = +1
–70 RL = 2kΩ
+VS = 5V
+PSRR
90
80
–PSRR
–80
CROSSTALK (dB)
70
60
50
40
30
–90
–100
–110
20
–120
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–130
1k
100k
1M
10M
FREQUENCY (Hz)
Figure 26. Power Supply Rejection Ratio vs. Frequency
30
10k
Figure 29. Crosstalk vs. Frequency
RL = 2kΩ
G = +1
VS = 3V
G = –1
VOUT = 2.9V p-p
25
3V
20
VS = ±15V,
VIN = –15.2V TO +13.8V
15
1.5V
10
0V
VS = +5V, VIN = –0.2V TO +3.8V
VS = +3V, VIN = –0.2V TO +1.5V
100k
1M
FREQUENCY (Hz)
10M
10µs/DIV
09439-125
500mV/DIV
0
10k
Figure 30. Output Swing, +VS = ±1.5 V, G = −1
Figure 27. Large Signal Frequency Response
Rev. B | Page 11 of 20
09439-025
5
09439-063
10
09439-526
POWER SUPPLY REJECTION RATIO (dB)
2
CAPACITANCE (pF × 1000)
Figure 25. Quiescent Current vs. Supply Voltage
OUTPUT VOLTAGE (V p-p)
1
09439-067
SERIES RESISTANCE (Ω)
QUIESCENT CURRENT (mA)
CL
AD823A
Data Sheet
5.0
VS = 5V
G = +2
RL = 2kΩ VOUT = 2V p-p
CL = 50pF
VS = 5V
4.5 G = –1
RF = RG = 2kΩ
4.0 RL = 300Ω
CL = 50pF
1V
AMPLITUDE (V)
3.5
3.0
2.5
0V
2.0
1.5
–1V
0.5
500mV/DIV
200µs/DIV
0
500mV/DIV
09439-048
09439-328
1.0
100ns/DIV
Figure 34. Pulse Response, +VS = ±2.5 V, G = +2
Figure 31. Output Swing, +VS = +5 V, G = −1
RL = 604Ω
VS = ±15V
G = +1
CL = 50pF
VOUT = 20V p-p
VS = 5V
G = +1
VOUT = 3V p-p
RL = 2kΩ
CL = 50pF
4V
10V
0V
2.5V
–10V
20µs/DIV
500mV/DIV
Figure 32. Output Swing, VS = ±15 V, G = +1
Figure 35. Pulse Response, +VS = ±2.5 V, G = +1
VS = 3V
G = +1
VIN = 100mV STEP
1.55V
100ns/DIV
09439-535
5V/DIV
09439-028
1V
VS = 5V
G = +1
RL = 2kΩ
CL = 470pF
3V
1.5V
2.5V
2V
50ns/DIV
500mV/DIV
Figure 33. Pulse Response, +VS = ±3 V, G = +1
200ns/DIV
Figure 36. Pulse Response, +VS = +5 V, G = +1, CL = 470 pF
Rev. B | Page 12 of 20
09439-034
25mV/DIV
09439-533
1.45V
Data Sheet
AD823A
VS = ±15V
G = +1
RL = 100kΩ
CL = 50pF
10V
0V
5V/DIV
500ns/DIV
09439-035
–10V
Figure 37. Pulse Response, VS = ±15 V, G = +1
Rev. B | Page 13 of 20
AD823A
Data Sheet
THEORY OF OPERATION
With 105 dB of open-loop gain, the output impedance is reduced
to <0.01 Ω. At higher frequencies, the output impedance rises as
the open-loop gain of the op amp drops; however, the output also
becomes capacitive due to the integrator capacitor. This
prevents the output impedance from ever becoming excessively
high (see Figure 21), which can cause stability problems when
driving capacitive loads. In fact, the AD823A has excellent
capacitive load drive capability for a high frequency op amp.
The AD823A is a dual voltage feedback amplifier with an
N-channel JFET input stage and a rail-to-rail bipolar output
stage. It is fabricated on the Analog Devices, Inc. XFCB process,
a dielectrically isolated complementary bipolar process featuring
high speed 36 V bipolar devices along with JFETs and thin film
resistors. The N-channel input stage handles signals up to 200 mV
below the negative supply while maintaining picoamp level
input currents. The rail-to-rail output maximizes the amplifier’s
output range and can provide up to 40 mA linear drive current
with output voltages within .5 V of either power rail. Lasertrimmed thin film resistors are used to optimize offset voltage
(3.5 mV max over the entire supply range) and offset voltage
drift (typical 1 uV/°C).
Figure 36 shows the results of the AD823A connected as a
follower while driving a 470 pF direct capacitive load. Under
these conditions, the phase margin is approximately 35°. For a
greater phase margin, use a low value resistor in series with the
output to decouple the effect of the load capacitance from the
op amp (see Figure 28). In addition, running the part at higher
gains also improves the capacitive load drive capability of the
op amp.
Figure 38 shows the architecture of an amplifier. Two stages are
used, with the first stage folded cascode input driving the
differential input of the second stage output. The voltage swing
at nodes S1p and S1n are kept small to minimize the generation
of nonlinear currents due to junction capacitances. This improves
distortion performance. Inputs and outputs of the amplifier are
fully protected with dedicated ESD diodes.
OUTPUT IMPEDANCE
The low frequency open-loop output impedance of the commonemitter output stage used in this design is approximately 50 kΩ.
Although this is significantly higher than a typical emitter follower
output stage, when it is connected with feedback, the open-loop
gain of the op amp reduces the output impedance.
+VS
VBIAS
–IN
OUTPUT
DRIVE
+IN
OUT
S1N
09439-138
S1P
–VS
Figure 38. Simplified Schematic
Rev. B | Page 14 of 20
Data Sheet
AD823A
APPLICATIONS INFORMATION
INPUT CHARACTERISTICS
In the AD823A, N-channel JFETs provide a low offset, low noise,
high impedance input stage. Minimum input common-mode
voltage extends from 0.2 V below −VS to 1.2 V < +VS. Driving
the input voltage closer to the positive rail causes a loss of
amplifier bandwidth and increased common-mode voltage error.
The AD823A does not exhibit phase reversal for input voltages
up to and including +VS. Figure 39 shows the response of an
AD823A voltage follower to a 0 V to 5 V (+VS) square wave
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +VS, with no phase
reversal. The reduced bandwidth above a 4 V input causes the
rounding of the output waveform. For input voltages greater
than +VS, a resistor (RP) in series with the AD823A noninverting
input prevents phase reversal, at the expense of greater input
voltage noise. The value of RP ranges from 1 kΩ to 10 kΩ. This
is illustrated in Figure 40.
5.0V
Because the input stage uses N-channel JFETs, input current
during normal operation is negative; the current flows out from the
input terminals. If the input voltage is driven more positive than
+VS − 0.7 V, the input current reverses direction as internal device
junctions become forward biased. This is illustrated in Figure 11.
A current limiting resistor should be used in series with the input
of the AD823A if the input voltage can be driven over 300 mV
more positive than +Vs or 300 mV more negative than –Vs. The
amplifier will be damaged if either condition persists for more than
10 seconds. A 1 kΩ resistor in series with the AD823A input allows
the amplifier to withstand up to 10 V of continuous overvoltage
and increases input voltage noise by a negligible amount.
The AD823A is designed for 14 nV/√Hz wideband input voltage
noise (see Figure 19). This noise performance, along with the
AD823A low input current and current noise, means that the
AD823A contributes negligible noise for applications with high
source resistances. Figure 41 shows that the source resistance
contributes to negligible noise for source impedances lower
than 10 kΩ. The low input capacitance of 0.6 pF also means that
one can use a source impedance up to 13 kΩ without cutting
into the G = +1 small signal bandwidth region.
100
TOTAL AMPLIFIER NOISE
INPUT
OUTPUT
1V
09439-064
0V
2µs
NOISE (nV/ Hz)
2.5V
10
AMPLIFIER VOLTAGE AND
CURRENT NOISE
Figure 39. Input and Output Response: RP = 0 kΩ, VIN = 0 V to +VS
OUTPUT
1
10
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
09439-338
INPUT
6V
SOURCE RESISTANCE
NOISE
Figure 41. RTI Noise vs. Source Resistance
OUTPUT CHARACTERISTICS
3V
The unique bipolar rail-to-rail output stage of the amplifier swings
within 20 mV of the supplies with no external resistive load.
The approximate output saturation resistance of the AD823A
is 33 Ω sourcing and sinking. This can be used to estimate the
output saturation voltage when driving heavier current loads.
For instance, when driving 5 mA, the saturation voltage to the
rails is approximately 165 mV.
0V
1V
10µs
5V
RP
AD823A
VOUT
09439-039
VIN
Figure 40. Input and Output Response: VIN = 0 V to +VS + 1 V,
VOUT = 0 V to +VS + 400 mV, RP = 4.99 kΩ
Rev. B | Page 15 of 20
AD823A
Data Sheet
WIDEBAND PHOTODIODE PREAMP
including CS and the amplifier input capacitance CD and CM. RF
and the total capacitance produce a pole with loop frequency (fp).
CF
RF
fp =
–
CM
CS
+
VB
VOUT
CD
RSH = 1011Ω
CM
AD823A
09439-055
IPHOTO
Figure 42. Wideband Photodiode Preamp
The AD823A is an excellent choice for photodiode preamp
application. Its low input bias current minimizes the DC error
at the preamp output. In addition, its high gain bandwidth
product and low input capacitance maximizes the signal
bandwidth of the photodiode preamp. Figure 42 shows the
AD823A as a current-to-voltage (I/V) converter with an
electrical model of a photodiode.
The transimpedance gain of the photodiode preamp can be
described by the basic transfer function:
VOUT =
I PHOTO × R F
1 + sC F R F
(1)
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth (see
the I to V gain curve in Figure 43). Note that one should set RF
such that the maximum attainable output voltage corresponds
to the maximum diode current IPHOTO. This allows one to utilize
the full output swing.
The signal bandwidth that is attainable with this preamp is a
function of RF, the gain bandwidth product (fu) of the amplifier,
and the total capacitance at the amplifier summing junction,
1
2πR F C S
(2)
With the additional pole from the amplifier’s open loop
response, the two-pole system results in peaking and instability
due to an insufficient phase margin (Figure 43(A), Without
Compensation).
Adding CF creates a zero in the loop transmission that compensates
for the effect of the input pole. This stabilizes the photodiode
preamp design because of the increased phase margin. It also sets
the signal bandwidth (Figure 43(B), With Compensation). The
signal bandwidth and the zero frequency are determined by
fz =
1
2 π RF C F
(3)
Setting the zero at the frequency fx maximizes the signal
bandwidth with a 45° phase margin. Since fx is the geometric
mean of fp and fu, it can be calculated by
fx =
f p × fu
(4)
Combining Equation 2, Equation 3 and Equation 4, the value of
CF that produces fx is defined by
CF =
CS
2π × RF × f u
The frequency response in this case shows about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half results in a flat frequency response with
about 5% transient overshoot.
Rev. B | Page 16 of 20
(5)
Data Sheet
AD823A
OPEN-LOOP GAIN
|A (s)|
|A| (dB)
OPEN-LOOP GAIN
fx
fx
I TO V GAIN
fz
G = R2C1s
fn
G = 1 + CS/CF
G=1
PHASE (°)
f
fu
fp
fu
fp
0°
90°
–45°
45°
–90°
G = RFCS(s)
G=1
log f
log f
f
0°
–135°
–45°
–180°
(A) WITHOUT COMPENSATION
09439-400
–90°
(B) WITH COMPENSATION
–135°
Figure 43. Gain and Phase Plot of the Transimpedance Amplifier Design
The dominant sources of output noise in the wideband
photodiode preamp design are the input voltage noise of the
amplifier, VNOISE and the resistor noise due to RF. The gray curve
in Figure 43 shows the noise gain over frequencies for the
photodiode preamp. The noise bandwidth is at the frequency fN,
and it can be calculated by
VOUT
AD823A
(6)
Figure 44 shows the AD823A configured as a transimpedance
photodiode amplifier. The amplifier is used in conjunction with
a photodiode detector with input capacitance of 5 pF. Figure 45
shows the transimpedance response of the AD823A when IPHOTO
is 1 µA p-p. The amplifier has a bandwidth of 2.2 MHz when it
is maximized for a 45° phase margin with CF = 1.2 pF. Note that
with the PCB parasitics added to CF, the peaking is only 0.5 dB
and the bandwidth is slightly reduced. Increasing CF to 2.7 pF
completely eliminates the peaking. However, it reduces the
bandwidth to 1.2 MHz.
Table 8 shows the noise sources and total output noise for the
photodiode preamp, where the preamplifier is configured to
have a 45° phase margin for maximal bandwidth and fz = fx = fn
in this case.
0.1µF
100Ω
–5V
Figure 44. Photodiode Preamplifier
95
94
93
IPHOTO = 1µA p-p
CF = 2.7pF
92
91
90
IPHOTO = 1µA p-p
CF = 1.2pF
89
88
87
86
85
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 45. Photodiode Preamplifier Frequency Response
Rev. B | Page 17 of 20
10M
09439-144
(C S + C F ) C F
0.1µF
–5V
09439-050
fu
49.9kΩ
+5V
TRANSIMPEDANCE GAIN (dB)
fN =
1.2pF
AD823A
Data Sheet
Table 8. RMS Noise Contributions of Photodiode Preamp
Contributor
RF
(μV)1
55.17
Expression
4kT  RF  f N 
VNOISE
VNOISE 
π
2
CS  CM
 C F  2C D 

CF
π
2
138.5
 fN
RSS Total
1
149.1
RMS noise with RF = 50 kΩ, CS = 5 pF, CF = 1.2 pF, CM = 1.3 pF, and CD = 0.6 pF.
ACTIVE FILTER
The AD823A is an ideal candidate for an active filter because of
its low input bias current and its low input capacitance. Low
input bias current reduces dc error in the signal path while low
input capacitance improves the accuracy of the active filter.
Figure 47 shows the two-pole Butterworth active filter’s response.
Note that it has a maximally flat pass band, a −3 dB bandwidth
of 1 MHz, and a 12 dB/octave roll-off in the stop band.
The cutoff frequency (fc) and the Q factor of the Butterworth
filter can be calculated by:
As a general rule of thumb, the bandwidth of the amplifier should
be at least 10 times bigger than the cutoff frequency of the filter
implemented. Therefore, the AD823A is capable of implementing
active filters of up to 1.7 MHz.
fc 
C1
200pF
RT
49.9Ω
R2
1.12kΩ
C2
100pF
+VS
AD823A
VOUT
–VS
Figure 46. Two-Pole Sallen-Key Active Filter
Figure 46 shows an example of a second-order Butterworth
filter, which is implemented by the Sallen-Key topology. This
structure can be duplicated to produce higher-order filters.
3
0
–3
–9
–12
–15
–18
–21
–24
–27
–30
–33
1k
10k
100k
1M
FREQUENCY (Hz)
10M
09439-147
MAGNITUDE (dB)
–6
–36
100
2 R1 R2 C1C 2
R1 R2C1C 2
R1  R2   C2
(7)
(8)
Therefore, one can easily adjust the cutoff frequency by
appropriately factoring the resistor and capacitor values. For
example, a 100 kHz filter can be implemented by increasing the
values of R1 and R2 by 10 times. Note that the Q factor remains
the same in this case.
09439-146
VIN
R1
1.12kΩ
Q
1
Figure 47. Two-Pole Butterworth Active Filter Response
Rev. B | Page 18 of 20
Data Sheet
AD823A
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
VOUT
VOUT
VIN
VIN
AD823A
AD823A
VIN
09439-152
VOUT
AD823A
Figure 48. Guard Ring Layout and Connections to
Reduce PCB Leakage Currents
V+
R1
R2
AD823A
R2
R1
VIN1
VIN2
GUARD
RING
GUARD
RING
VREF
VREF
V–
Figure 49. Top View of AD823A SOIC Layout with Guard Rings
Rev. B | Page 19 of 20
09439-153
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD823A, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around the
amplifier inputs further reduces leakage currents. Figure 48 shows
how the guard rings should be configured, and Figure 49 shows
the top view of how a surface-mount layout can be arranged. The
guard ring does not need to be a specific width, but it should form
a continuous loop around both inputs. By setting the guard ring
voltage equal to the voltage at the non-inverting input, parasitic
capacitance is minimized as well. For further reduction of leakage
currents, components can be mounted to the PCB using Teflon®
standoff insulators.
AD823A
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Models1
AD823AARZ
AD823AARZ-RL
AD823AARZ-R7
AD823AARMZ
AD823AARMZ-R7
AD823A-2AR-EBZ
AD823A-2ARM-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13” Tape and Reel
8-Lead SOIC_N, 7” Tape and Reel
8-lead MSOP
8-lead MSOP, 7” Tape and Reel
Evaluation Board for 8-Lead SOIC
Evaluation Board for 8-Lead MSOP
Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09439-0-6/12(B)
Rev. B | Page 20 of 20
Package Option
R-8
R-8
R-8
RM-8
RM-8
Branding
H34
H34