EC24C02B 2Kbit I2C SERIAL EEPROM Description Features The EC24C02B is a 2 Kbit Electrically Erasable PROM, The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.8V, with standby and active currents of only 1µA and 1 mA, respectively. The EC24C02B also has a page write capability for up to 8 bytes of data. The EC24C02B is available in the standard 8-pin PDIP, surface mount SOP, TSSOP,DFN, SOT23 package. Single supply with operation down to 1.8v Low-power CMOS technology: 1 mA active current, typical 1 µA standby current, typical(l-temp) Organized as 1 block of 256 bytes (1×256×8) 2 2-wire serial interface bus, l C compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce 400 kHz (24C02B) compatibility Self-timed write cycle (including auto-erase) Page write buffer for up to 8 bytes Hardware write-protect for entire memory Can be operated as a serial ROM Factory programming (QTP) available ESD protection>4,000V 1,000,000 erase/write cycles Data retention>200 years Pb-free finish available Pin Configuration SOP-8 TSSOP-8 Top-View Top-View Pin Name A0 - A2 SDA SCL WP GND VCC Functions Address Inputs Serial Data Serial Clock Input Write Protect Ground Power Supply PDIP-8 DFN-8L Top-View SOT23-5 Top-View E-CMOS Corp. (www.ecmos.com.tw) Page 1 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM Ordering Information EC24C XXXX XX X X R = Tape Reel T = Tube Circuit Type Device Function： 02BN=2 Kbit(256×8) C (Green Product) Package： M1 = SOP-8 E1 = TSSOP-8 P1 = PDIP-8 F6 = DFN -8 B2=SOT23-5 Marking Information Package type DFN-8 Part Number Marking EC24C02BNF6CR SOT23-5 EC24C02BNB2CR K02 24C02B LLLLL PDIP-8 SOP-8 EC24C02BNP1CR EC24C02BNM1CR TSSOP-8 EC24C02BNE1CR 24CXXB LLLLL YYWWT Marking Information LLLLL is the last five numbers of wafer lot number XX is the memory of production. LLLLL is the last five numbers of wafer lot number YYWW is Date Code. T is tracking Code ,T=X Block Diagram E-CMOS Corp. (www.ecmos.com.tw) Page 2 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM Electrical Characteristics Absolute Maximum Ratings(t) Vcc…………………………………………………………………………………………………………… .6.5V All inputs and outputs w.r.t. Vss………………………………………………………………. -0.3Vto Vcc+1.0V Storage temperature………………………………………………………………………………-50℃ to+125℃ Ambient temperature with power applied……………………………………………………….-25℃ to+75 ℃ ESD protection on all pins ……………………………………………………………………………………≥4KV NOTICE: Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC Electrical Characteristics Parameter High-Level input Voltage Low-level input Voltage Hysteresis of Schmitt Trigger inputs Symbol VIH VIL Min. 0.7x VCC --- Typ. ----- Max. -0.3xVCC Unit V V VHYS 0.05xVCC --- --- V Low-level output voltage VOL --- --- 0.4 V Input leakage Current Output Leakage Current ILI ILO ----- ----- ±1 ±1 μA μA Pin Capacitance (all inputs / outputs) CIN --- --- 10 ICC write --- 0.1 3 mA ICC read --- 0.05 1 mA --- 0.01 1 uA --- --- 5 uA Operating Current Standby Current pF COUT ICCS Conditions ----(Note) IOL=3.0mA, VCC=2.5V VIN = VCC or GND VOUT = VCC or GND VCC = 5.0V(Note) TA=25 ℃,fCLK=1MHz VCC=5.5V, SCL=400kHz ---SDA=SCL=VCC WP=GND (Industrial) SDA=SCL=VCC WP=GND (Automotive) Note：This parameter is periodically sampled and not 100% tested E-CMOS Corp. (www.ecmos.com.tw) Page 3 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM TABLE 1-2:AC Electrical Characteristics Parameter Clock Frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock(Note 2) Bus free time：Time the Bus must be free before A new transmission can Start Output fall time from VIH Minimum to VIL maximum Input filter spike Suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance Note Symbol Min. Typ. Max. Units Conditions THIGH TLOW ---600 1300 ------- 400 100 ---- kHz KHz ns ns TR --- --- 300 ns TF THD:STA THD:STA THD：DAT TSU：DAT TSU：STO TAA --600 600 0 100 600 --- --------------- 300 ----------900 ns ns ns ns ns ns ns 2.5V≦VCC≦5.5V VCC<2.5V 2.5V≦VCC≦5.5V 2.5V≦VCC≦5.5V 2.5V≦VCC≦5.5V (Note 1) (Note 1) 2.5V≦VCC≦5.5V 2.5V≦VCC≦5.5V (Note 2) 2.5V≦VCC≦5.5V 2.5V≦VCC≦5.5V 2.5V≦VCC≦5.5V TBUF 1300 --- --- ns 2.5V≦VCC≦5.5V TOF 20+0.1CB --- 250 ns 2.5V≦VCC≦5.5V TSP --- --- 50 ns (Note 1 and 3) TWC --- ---1M ----- 5 --- ms cycles --25℃(Note 4) fCLK 1: Not 100% tested. CB=total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintendcd gcncration of Start or Stop conditions. 3: The combined Tsp and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a Tl specification for standard operation. E-CMOS Corp. (www.ecmos.com.tw) Page 4 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM FIGURE 1-1:BUS TIMING DATA FIGURE 1-2:BUS TIMING START/STOP 2.0 FUNCTIONAL DESCRIPTION The EC24C02B supports a bidirectional,2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock(SCL), controls the bus access and generates the Start and stop conditions,while the EC24C02B works as slave. Both master and slave can operate as transmitter or receiver,but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: ․Data transfer may be initiated only when the bus is not busy. ․During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly,the following bus conditions have been defined(Figure 3-1). 3.1 Bus Not Busy(A) Both data and clock lines remain high. E-CMOS Corp. (www.ecmos.com.tw) Page 5 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM 3.2Start Data Transfer(B) A high-to-low transition of the SDA line while the clock( SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.3 Stop Data Transfer(C) A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 3.4 Data Valid(D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock Pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception ofeach byte.The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The EC24C02B does not generate any Acknowledge bits is if an internal programming cycle in progress. The device that acknowledges has to pull down the SDA line during the acknowledage clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (EC24C02B) will leave the data line high to enable the master to generate the Stop condition. E-CMOS Corp. (www.ecmos.com.tw) Page 6 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS 3.6 Device Addressing A control byte is the first byte received following the Start condition from the master device. The control byte consists of a four-bit control code. For the EC24C02B, this is set as ‘1010’ binary for read and write operations. The next three bites of the control byte are “don’t cares” for the EC24C02B. The last bit of the control byte defines the operation to be performed. When set to’1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the start condition, the EC24C02B monitors the SDA bus, checking the device type identifier being transmitted and ,upon a ‘1010’ code,the slave device outputs an Acknowledge signal on the SDAline. Depending on the state of the bit,the EC24C02B will select a read or write operation. Operation Control Code Block Select Read 1010 Block address 1 Write 1010 Block address 0 FIGURE 3-2：CONTROL BYTE ALLOCATION E-CMOS Corp. (www.ecmos.com.tw) Page 7 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM 4.0 WRITE OPERATION 4.1 Byte Write Following the Start condition from the master , the device code (4 bits), the block address (3 bits, “don’t cares”) and the R/W bit which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore,the will next byte transmitted by the master is the word address and be written into the address Pointer of the EC24C02B.After receiving another Acknowledge signal from the EC24C02B,the master device will transmit the data word to be written into the addressed memory location.The EC24C02B acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the EC24C02B will not generate Acknowledge Signals (Figure 41). 4.2 Page Write The write-control byte, word address and the first data byte are transmitted to the EC24C02B in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 8 data bytes to the EC24C02B,whichare temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a Stop condition.Upon receipt of each word,the four lowerorder Address Pointer bits are internally incremented by ‘1’. The higher-order 7 bits of the word address remain constant. If the master should transmit more than 8 words prior to generating the Stop condition,the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-2). Note: Page write operations are limited to writing bytes within a single physical page regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size -1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. E-CMOS Corp. (www.ecmos.com.tw) Page 8 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM FIGURE 4-1: BYTE WRITE FIGURE 4-2 PAGE WRITE 5.0 ACKNOWLEDGE PCLLING Since the device will not acknowledge during a write cycle ,this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput).Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W=0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for a flow diagram of this operation. 6.0 WRITEPROTECTION The WP pin allows the user to write-protect the entire array (00-FF) when the pin is tied to Vcc. If tied to Vss, the write protection is disabled. E-CMOS Corp. (www.ecmos.com.tw) Page 9 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM FIGURE 5-1: ACKNOWLEDGE POLLING FLOW 7.0 READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations; current address read, random read and sequential read. 7.1Current Address Read The EC24C02B contains an address counter that maintains the address of the last word accessed.Internally incremented by ‘1’. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n+ 1, Upon receipt of the slave address with R/W bit set to ‘1’, the EC24C02B issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the EC24C02B discontinues transmission (Figure 7-1). 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the EC24C02B as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX02 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the EC24C02B will discontinue transmission (figure 7-2). E-CMOS Corp. (www.ecmos.com.tw) Page 10 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM 7.3 Sequential Read Sequential reads are initiated in the same way as a random read, except that once the EC24C02B transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the EC24C02B to transmit the next sequentially-addressed 8-bit word (Figure 7-3). To provide sequential reads, the EC24C02B contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise Protection The EC24C02B employs a Vcc threshold detector circuit which disables the internal erase/write logic if the Vcc is below 1.5V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. FIGURE 7-1: CURRENT ADDRESS READ FIGURE 7-2 RANDOM READ FIGURE 7-3:SEQUENTIAL READ E-CMOS Corp. (www.ecmos.com.tw) Page 11 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 8-1. TABLE 8-1: PIN FUNCTION TABLE Name A0 A1 A2 GND SDA SCL WP Vcc PDIP 1 2 3 4 5 6 7 8 SOP 1 2 3 4 5 6 7 8 TSSOP Description 1 Not Connected 2 Not Connected 3 Not Connected 4 Ground 5 Serial Address/Data I/O 6 Serial Clock 7 Write-Protect Input 8 +1.8V to 5.5V Power Supply 8.1Serial Address/Data Input/Output(SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to Vcc ( typical 10 KΩ for 100KHz, 2KΩ for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low, Changes during SCL high are reserved for indicating Start and Stop conditions. 8.2 Serial Clock (SCL) The SCL input is used to synchronize the data transfer to and from the device. 8.3 Write-Protect(WP) The WP pin must be connected to either Vss or Vcc. If tied to GND, normal memory operation is enabled (read/write the entire memory 00-FF). If tied to Vcc, write operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the EC24C02B as a serial ROM when WP is enabled (tied to Vcc). 8.4 A0,A1,A2 These A0,A1 and A2 pins are not used by the EC24C02B. They may be left floating or tied to either GND or Vcc. E-CMOS Corp. (www.ecmos.com.tw) Page 12 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM OUTLINE DRAWING PDIP-8L Units Dimension Limits N P A A2 A1 E E1 D L C B1 B eB a ß MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent:MS-001 Drawing No.C04-018 E-CMOS Corp. (www.ecmos.com.tw) Page 13 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM OUTLINE DRAWING SOP-8L Units Dimension Limits n p A A2 A1 E E1 D h L Ø c B a ß MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MIN 1.35 1.32 0.10 5.79 3.71 4.80 0.25 0.48 0 0.20 0.33 0 0 MILLIMETERS NOM 8 1.27 1.55 1.42 0.18 6.02 3.91 4.90 0.38 0.62 4 0.23 0.42 12 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010”(0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 E-CMOS Corp. (www.ecmos.com.tw) Page 14 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM OUTLINE DRAWING TSSOP-8L Units Dimension Limi ts n p A A2 A1 E E1 D L Ø c B a ß MIN INCHES NOM MAX MIN 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 0.85 0.05 6.25 4.30 2.90 0.50 0 0.09 0.19 0 0 MILLIMETERS* NOM 8 0.65 0.90 0.10 6.38 4.40 3.00 0.60 4 0.15 0.25 5 5 MAX 1.10 0.95 0.15 6.50 4.50 3.10 0.70 8 0.20 0.30 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005”(0.127mm) per side. JEDEC Equivalent:MO-153 Drawing No. C04-086 E-CMOS Corp. (www.ecmos.com.tw) Page 15 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM OUTLINE DRAWING DFN-8L E-CMOS Corp. (www.ecmos.com.tw) Page 16 of 17 5F12N-Rev. F002 EC24C02B 2Kbit I2C SERIAL EEPROM OUTLINE DRAWING SOT23-5L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 A3 b b1 c c1 D E E1 e L θ E-CMOS Corp. (www.ecmos.com.tw) MIN 1.05 0 1.00 0.55 0.30 0.33 0.10 0.14 2.72 2.60 1.40 MAX 1.30 0.10 1.20 0.75 0.50 0.38 0.21 0.16 3.12 3.00 1.80 0.95 BSC 0.30 0° 0.60 8° Page 17 of 17 5F12N-Rev. F002