CPC5620/CPC5621 LITELINK® III Phone Line Interface IC (DAA) INTEGRATED CIRCUITS DIVISION Features Description • Superior voice solution with low noise, excellent part-to-part gain accuracy • 3 kVrms line isolation • Transmit power of up to +10 dBm into 600 • Data access arrangement (DAA) solution for modems at speeds up to V.92 • 3.3 or 5 V power supply operation • Caller ID signal reception function • Easy interface with modem ICs and voice CODECs • Worldwide dial-up telephone network compatibility • CPC5620 and CPC5621 can be used in circuits that comply with the requirements of TIA/EIA/IS-968 (FCC part 68), UL1950, UL60950, EN/IEC 60950-1 Supplementary Isolation compliant, EN55022B, CISPR22B, EN55024, and TBR-21 • Line-side circuit powered from telephone line • Compared to other silicon DAA solutions, LITELINK: - Uses fewer passive components - Takes up less printed-circuit board space - Uses less telephone line power - Offers simplified operation - Is a single-IC solution LITELINK III is a single-package silicon phone line interface (PLI) DAA used in voice and data communication applications to make connections between low-voltage equipment and high-voltage telephone networks. LITELINK provides a high-voltage isolation barrier, AC and DC phone line terminations, switch hook, 2-wire to 4-wire hybrid, ring detection, and on-hook signal detection. LITELINK can be used in both differential and single-ended signal applications. LITELINK uses on-chip optical components and a few inexpensive external components to form a complete voice or high-speed data phone line interface. LITELINK eliminates the need for large isolation transformers or capacitors used in other interface configurations. It includes the required high-voltage isolation barrier in a surface-mount SOIC package. The CPC5620 (half-wave ringing detect) and CPC5621 (full-wave ringing detect) build upon IXYS Integrated Circuits Division’s LITELINK product line, with improved insertion loss control, improved noise performance, and lower minimum current draw from the phone line. The new mode pin enables worldwide implementation. Applications • • • • • • • Computer telephony and gateways, such as VoIP PBXs Satellite and cable set-top boxes V.92 (and other standard) modems Fax machines Voicemail systems Embedded modems for POS terminals, automated banking, remote metering, vending machines, security, and surveillance Ordering Information Part Number Description CPC5620A CPC5620ATR CPC5621A CPC5621ATR 32-pin SOIC, half-wave ring detect, 50/Tube 32-pin SOIC, half-wave ring detect, 1000/Reel 32-pin SOIC, full-wave ring detect, 50/Tube 32-pin SOIC, full-wave ring detect, 1000/Reel CPC5620/CPC5621 Block Diagram TIP+ Isolation Barrier Transmit Isolation Amplifier Tx+ Tx- Transmit Diff. Amplifier Transconductance Stage 2-4 Wire Hybrid AC/DC Termination Hookswitch VI Slope Control AC Impedance Control Current Limit Control MODE OH 3kVrms CID Isolation e3 Rx- Receive Diff. Amplifier CID/ RING MUX Snoop Amplifier DS-CPC5620/CPC5621-R05 RING- Vref Gain Trim Receive Isolation Amplifier Rx+ Pb Vref Gain Trim RING www.ixysic.com CSNOOP RSNOOP CSNOOP RSNOOP 1 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 1 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 5 2 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Resistive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 9 3 Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 On-hook Operation: OH=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Ringing Signal Reception via the Snoop Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Polarity Reversal Detection with CPC5621 in On-hook State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 On-hook Caller ID Signal Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Off-Hook Operation: OH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Start-up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Setting a Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Mode Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 11 11 12 12 12 13 13 13 13 13 13 14 4 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Manufacturing Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 1. Electrical Specifications 1.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit VDD -0.3 6 V Logic Inputs -0.3 VDD + 0.3 V Continuous Tip to Ring Current (RZDC = 5.2) - 150 mA Total Package Power Dissipation - 1 W Isolation Voltage - 3000 Vrms Operating temperature -40 +85 °C Storage temperature -40 +125 °C R05 Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. www.ixysic.com 3 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 1.2 Performance Parameter Minimum Typical Maximum Unit Conditions DC Characteristics Operating Voltage VDD 3.0 - 5.50 V Low-voltage side Operating Current IDD - 9 13 mA Low-voltage side Operating Voltage VDDL 2.8 - 3.2 V Operating Current IDDL - 7 8 mA Line side, drawn from tip and ring while off-hook On-hook Characteristics Metallic DC Resistance 10 - - M Tip to ring, 100 VDC applied Longitudinal DC Resistance 10 - - 150 VDC applied from tip and ring to Earth ground 15 Hz ring signal applied tip to ring -3 dB corner frequency @ 166 Hz, in IXYS Integrated Circuits Division application circuit 120 Vrms 60 Hz common-mode signal across tip and ring Line side, derived from tip and ring Ringing Signal Detect Level 5 - - M Vrms Ringing Signal Detect Level 28 - - Vrms Snoop Circuit Frequency Response 166 - >4000 Hz Snoop Circuit CMRR 1 Ringer Equivalence 60 40 0.1B - - dB REN dB 40 - 600 26 - dB dB Tip to ring, using resistive termination application circuit Per FCC part 68 Into 600 at 1800 Hz 30 - 4000 Hz - 36 - dB -0.4 0 0.4 dB Average In-band Noise Harmonic Distortion - -126 -80 - Transmit Level - - 2.2 dBm/Hz dB VP-P -3 dB corner frequency 30 Hz Into 600 at 1800 Hz, with C18 in the resistive termination application circuit 30 Hz to 4 kHz, for resistive termination application circuit with MODE de-asserted and for reactive termination application circuit with MODE asserted. 4 kHz flat bandwidth 60 90 2.2 0.5 120 VP-P 3000 2000 - - Vrms Longitudinal Balance 1 Off-Hook Characteristics AC Impedance Longitudinal Balance Return Loss Transmit and Receive Characteristics Frequency Response Transhybrid Loss Transmit and Receive Insertion Loss Receive Level RX+/RX- Output Drive Current TX+/TX- Input Impedance Isolation Characteristics Isolation Voltage Surge Rise Time MODE, OH, and CID Control Logic Inputs Input Low Voltage mA k V/S 68 Hz ring signal applied tip to ring Per FCC part 68 -3 dBm, 600 Hz, 2nd harmonic Single-tone sine wave. Or 0 dBm into 600 Single-tone sine wave. Or 0 dBm into 600 Sink and source Line side to low-voltage side, one minute duration No damage via tip and ring - - 0.8 VIL 2.0 - - VIH High Level Input Current - - -120 A VIN VDD Low Level Input Current RING Output Logic Levels Output High Voltage - - -120 A VIN = GND VDD -0.4 - - V IOUT = -400 A - - 0.4 V IOUT = 1 mA Input High Voltage Output Low Voltage Specifications subject to change without notice. All performance characteristics based on the use of IXYS Integrated Circuits Division application circuits. Functional operation of the device at conditions beyond those specified here is not implied. All specifications at 25°C and VDD = 5V unless otherwise noted. 1) This parameter is layout and component tolerance dependent. 4 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 1.3 Pin Description Pin Name 1 2 VDD TXSM 3 TX- 4 TX+ 5 TX 6 MODE 7 8 9 GND OH RING 10 CID 11 RX- 12 RX+ 13 14 15 16 SNP+ SNPRXF RX 17 VDDL 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 R05 RXS RPB BRZDC DCS2 DCS1 NTF GAT NTS BRTXSL ZNT ZTX TXF REFL Figure 1. Pinout Function Low-voltage (CPE) side power supply Transmit summing junction Negative differential transmit signal to DAA from low-voltage side Positive differential transmit signal to DAA from low-voltage side Transmit differential amplifier output When asserted low, changes gain of TX path (-7 dB) and RX path (+7 dB) to accommodate reactive termination networks Low-voltage (CPE) side analog ground Assert logic low for off-hook operation Ringing Detect Output Assert logic low while on hook to allow CID information to be passed to the RX+ and RXoutput pins. Negative differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. Positive differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. Positive differential snoop input Negative differential snoop input Receive photodiode amplifier output Receive photodiode summing junction Power supply for line side, regulated from tip and ring. Receive isolation amp summing junction Receive LED pre-bias current set Bridge rectifier return Electronic inductor DCR/current limit DC feedback output V to I slope control Network amplifier feedback External MOSFET gate control Receive signal input Bridge rectifier return Transmit photodiode summing junction Receiver impedance set Transmit transconductance gain set Transmit photodiode amplifier output 1.25 VDC reference 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 www.ixysic.com VDD TXSM TXTX+ TX MODE GND OH RING CID RXRX+ SNP+ SNPRXF RX REFL TXF ZTX ZNT TXSL BRNTS GAT NTF DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 2. Application Circuits LITELINK can be used with telephone networks worldwide. Some public telephone networks, notably in North America and Japan require resistive line termination. Other telephone networks, as in Europe and elsewhere, require a reactive line termination. The application circuits below address both line termination models. The reactive termination application circuit (see Figure 3 on page 8) describes the TBR-21 implementation. This circuit can be adapted easily for other reactive termination needs. 2.1 Resistive Termination Application Circuit Figure 2. Resistive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1μ FB1 600 Ω 200 mA C16 10μ TXTX+ A U1 A R1 (RTX) 80.6K 1 VDD TXF ZTX 0.1μ 3 TX- C2 0.1μ 4 TX+ RING RXRX+ C14 TXSL 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 9 RING NTF C4 0.1μ 11 RX- R5 (RTXF) 60.4K R12 (RNTF) 24 DCS2 499K RPB 15 RXF RXS 19 BR- C8 (CSNP+) 4 220pF C15 0.01μ 500V R20 (RVDDL) 2 5% BR- + DB1 TIP R18 (RZTX) 3.32K C18 15p 3 R10 (RZNT) 301 BR- BR- SP1 1 RING BR- R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R7 (RSNP+2) R45 (RSNP+1) 1.8M 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of IXYS Integrated Circuits Division application note AN-146, Guidelines for Effective LITELINK Designs for more information. 6 BR- 47 5% R76 (RHTF) 200K R8 221K (RHTX) R4 (RPB) 68.1 R3 (RSNPD) 1.5M C12 (CDCS) 0.027μ Q1 CPC5602C BR- VDDL 17 C7 (CSNP-) 4 220pF R21 (RDCS1B) 6.49M R14 (RGAT) R16 (R 3 ZDC) 8.2 18 R2 (RRXF) 130K C21 100p (CGAT) 1.69M BR- 20 14 SNP- BR- R22 (RDCS1A) 6.49 M R15 (RDCS2) 22 ZDC 21 13 SNP+ C10 0.01μ 500V R13 (RNTS) 1M R75 (RNTX) 261K BR- DCS1 23 0.1μ 12 RX+ 16 RX BR- 30 ZNT 10 CID CID C9 0.1μ 31 29 5 TX OH REFL 32 2 TXSM C13 A LITELINK ³Optional for enhanced transhybrid loss. 4Use voltage ratings based on the isolation requirements of your application. www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 2.1.1 Resistive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 F, 16 V, ±10% 0.1 F, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C18 (optional) C21 R1 R2 R3 R4 R5 220 pF, ±5% 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 1 SP1 1 1 Q1 U1 4 1Use 2 0.01 F, 500 V, ±10% 0.027 F, 16 V, ±10% 10 F, 16 V, ±10% 15 pF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 k, 1/16 W, ±1% 130 k, 1/16 W, ±1% 1.5 M, 1/16 W, ±1% 68.1 , 1/16 W, ±1% 60.4 k, 1/16 W, ±1% Supplier(s) AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 M, 1/10 W, ±1% 221 k, 1/16 W, ±1% 301 , 1/16 W, ±1% 499 k, 1/16 W, ±1% Panasonic, Electro Films, FMI, Vishay, 1 M, 1/16 W, ±1% etc. 47 , 1/16 W, ±5% 1.69 M, 1/16 W, ±1% 8.2 , 1/8 W, ±1% 3.32 k 1/16 W, ±1% 2 , 1/16 W, ±5% 6.49 M, 1/16 W, ±1% 10 1/16 W, ±5%, or 220 H inductor 261 k, 1/16 W, ±1% 200 k, 1/16 W, ±1% 600 , 200 mA ferrite bead Murata BLM11A601S or similar S1ZB60 bridge rectifier Shindengen, Diodes, Inc. Bourns (TISP4350H3) or 350 V Teccor (P3100SC) CPC5602 FET IXYS Integrated Circuits Division CPC5620/CPC5621 LITELINK voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. Use components that allow enough space to account for the possibility of high-voltage arcing. R05 www.ixysic.com 7 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION Figure 3. Reactive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1μ FB1 600 Ω 200 mA C16 10μ TXTX+ A U1 A R1 (RTX) 80.6K 1 VDD TXF 3 TX- ZTX C2 0.1μ 4 TX+ ZNT 29 TXSL 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 9 RING NTF RING 10 CID CID C14 0.1μ 11 RX- C4 0.1μ 12 RX+ R5 (RTXF) 60.4K R12 (RNTF) DCS2 14 SNP- RPB 15 RXF RXS BR- R14 (RGAT) Q1 CPC5602C 47 5% TIP BR- R10 59 (RZNT1) C20 (CZNT) 0.68μ DB1 - 200K R4 (RPB) 68.1 BR- + BRR76 (RHTF) 200K R8 (RHTX) VDDL 17 C15 0.01μ 500V R20 (RVDDL) 2 5% R16 (R 3 ZDC) 8.2 18 R2 (RRXF) 130K C12 (CDCS) 0.027μ 1.69M ZDC 21 19 R21 (RDCS1B) 6.49M R15 (RDCS2) 22 BR- 20 R22 (RDCS1A) 6.49M C21 100p BR- (CGAT) 221K DCS1 23 C10 0.01μ 500V R13 (RNTS) 1M R75 (RNTX) 110K BR- 24 13 SNP+ 16 RX BR- 30 0.1μ OH C9 0.1μ 31 C13 A RX+ REFL 32 2 TXSM 5 TX RX- LITELINK R18 (RZTX) 10K BR- BR- SP1 1 RING R11 169 (RZNT2) BR- C7 (CSNP-) 4 220p R3 (RSNPD) 1.5M C8 (CSNP+) 4 220p R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R7 (RSNP+2) R45 (RSNP+1) 1.8M 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of IXYS Integrated Circuits Division application note AN-146, Guidelines for Effective LITELINK Designs for more information. 3 RZDC sets the loop-current limit, see “Setting a Current Limit” on page 13. Also see IXYS Integrated Circuits Division’s application note AN-146 for heat sinking recommendations for the CPC5602C FET. 4 Use voltage ratings based on the isolation requirements of your application. 8 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 2.1.2 Reactive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 F, 16 V, ±10% 0.1 F, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C20 C21 R1 R2 R3 R4 R5 220 pF, ±5% 2 1 1 1 1 1 1 1 1 1 0.01 F, 500 V, ±10% 0.027 F, 16 V, ±10% 10 F, 16 V, ±10% 0.68 F, 16 V, ±10% 100 pF, 16 V, 10% 80.6 k, 1/16 W, ±1% 130 k, 1/16 W, ±1% 1.5 M, 1/16 W, ±1% 68.1 , 1/16 W, ±1% 60.4 k 1/16 W, ±1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R11 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 200 k, 1/16 W, ±1% 59 , 1/16 W, ±1% 169 , 1/16 W, ±1% 221 k, 1/16 W, ±1% 1 M, 1/16 W, ±1% 47 , 1/16 W, ±5% 1.69 M, 1/16 W, ±1% 8.2 , 1/8 W, ±1% 10 k, 1/16 W, ±1% 2 , 1/16 W, ±5% 6.49 M, 1/16 W, ±1% 10 , 1/16 W, ±5%, or 220 H inductor 110 k, 1/16 W, ±1% 200 k, 1/16 W, ±1% 600 200 mA ferrite bead S1ZB60 bridge rectifier 1 SP1 350 V 1 1 Q1 U1 CPC5602 FET CPC5620/CPC5621 LITELINK 4 1Use 2 Supplier AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 M, 1/10 W, ±1% Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S or similar Shindengen, Diodes, Inc. Bourns (TISP4350H3) or Teccor (P3100SC) IXYS Integrated Circuits Division voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. Use components that allow enough space to account for the possibility of high-voltage arcing. R05 www.ixysic.com 9 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 3. Using LITELINK As a full-featured telephone line interface, LITELINK performs the following functions: • • • • • • • DC termination and V/I slope control AC impedance control 2-wire to 4-wire conversion (hybrid) Current limiting Ringing signal reception Caller ID signaling reception Switch hook Asserting OH low causes LITELINK to answer or originate a call by entering the off-hook state. In the off-hook state, loop current flows through LITELINK. LITELINK can accommodate specific application features without sacrificing basic functionality and performance. Application features include, but are not limited to: • • • • • • • • High transmit power operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (line intrusion) Battery reversal detection Line presence detection World-wide programmable operation This section of the data sheet describes LITELINK operation in standard configuration for usual operation. IXYS Integrated Circuits Division offers additional application information on-line (see Section 5 on page 14). These include information on the following topics: • • • • • • Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection EMI considerations Other specific application materials are also referenced in this section as appropriate. 3.1 Switch Hook Control (On-hook and Off-hook States) LITELINK operates in one of two conditions, on-hook and off-hook. In the on-hook condition the telephone line is available for calls. In the off-hook condition the telephone line is engaged. The OH control input is used to place LITELINK in one of these two states. 10 With OH high, LITELINK is on-hook and ready to make or receive a call. While on-hook, the CID control is used to select between passing the caller-ID tones from Tip and Ring to the RX+ and RX- outputs and the ringing detect function. Setting CID to a logic low enables the CID path while placing CID to a logic high configures the LITELINK to detect ringing. 3.2 On-hook Operation: OH=1 The LITELINK application circuit leakage current is less than 10 A with 100 V across ring and tip, equivalent to greater than 10 M on-hook resistance. 3.2.1 Ringing Signal Reception via the Snoop Circuit In the on-hook state (OH and CID not asserted), an internal multiplexer turns on the snoop circuit. This circuit monitors the telephone line for two conditions; an incoming ring signal, and caller ID data bursts. Refer to the application schematic diagram (see Figure 2. on page 6). C7 (CSNP-) and C8 (CSNP+) provide a high-voltage isolation barrier between the telephone line and SNP- and SNP+ on the LITELINK while coupling AC signals to the snoop amplifier. The snoop circuit “snoops” the telephone line continuously while drawing no current. In the LITELINK, ringing signals are compared to a threshold. The comparator output forms the RING signal output from LITELINK. This signal must be qualified by the host system as a valid ringing signal. A low level on RING indicates that the LITELINK ring signal threshold has been exceeded. For the CPC5620 (with the half-wave ring detector), the frequency of the RING output follows the frequency of the ringing signal from the central office (CO), typically 20 Hz. The RING output of the CPC5621 (with the full-wave ring detector) is twice the ringing signal frequency. Hysteresis is employed in the LITELINK ring detector circuit to provide noise immunity. The set-up of the ring detector comparator causes RING output pulses to remain low for most of the ringing signal half-cycle. The RING output returns high for the entire negative www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION half-cycle of the ringing signal for the CPC5620. For the CPC5621, the RING output returns high for a short period near the zero-crossing of the ringing signal before returning low during the positive half-cycle. For both the CPC5620 and CPC5621, the RING output remains high between ringing signal bursts. The ringing detection threshold depends on the values of R3 (RSNPD), R6 & R44 (RSNP-), R7 & R45 (RSNP+), C7 (CSNP-), and C8 (CSNP+). The value of these components shown in the application circuits are recommended for typical operation. The ringing detection threshold can be changed according to the following formula: 750mV V RINGPK = ----------------- R SNPD R SNP TOTAL 2 1 + R SNPD + -------------------------------------2 f RING C SNP Where: • RSNPD = R3 in the application circuits shown in this data sheet. • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits shown in this data sheet. • CSNP = C7 = C8 in the application circuits shown in this data sheet. • And ƒRING is the frequency of the ringing signal. IXYS Integrated Circuits Division Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the ringing detection threshold will also change the caller ID gain and the timing of the polarity reversal detection pulse, if used. 3.2.2 Polarity Reversal Detection with CPC5621 in On-hook State The full-wave ringing detector in the CPC5621 makes it possible to detect on-hook tip and ring polarity reversal using the RING output. When the polarity of tip and ring reverses, a pulse on RING indicates the event. Your system logic must be able to discriminate this single pulse of approximately 1 msec (using the recommended snoop circuit external components) from a valid ringing signal. R05 3.2.3 On-hook Caller ID Signal Reception On-hook caller ID (CID) signals are processed by LITELINK by coupling the CID data burst through the snoop circuit to the LITELINK RX outputs under control of the CID pin. In North America, CID data signals are typically sent between the first and second ringing signal. In North American applications, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: 1. 2. 3. 4. Detect the first ringing signal outputs on RING. Assert CID low. Process the CID data from the RX outputs. De-assert CID (high or floating). Note: Taking LITELINK off-hook (via the OH pin) disconnects the snoop path from both the receive outputs and the RING output, regardless of the state of the CID pin. CID gain from tip and ring to RX+ and RX- is determined by: 6R SNPD GAIN CID dB = 20 log ------------------------------------------------------------------------------------------------2 1 R SNP + R SNPD + -------------------------2TOTAL fC SNP Where: • RSNPD = R3 in the application circuits in this data sheet • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits in this data sheet • CSNP = C7 = C8 in the application circuits in this data sheet • and where ƒ is the frequency of the CID signal The recommended components in the application circuit yield a gain 0.27 dB at 2000 Hz. IXYS Integrated Circuits Division Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the CID gain will also change the ring detection threshold and the timing of the polarity reversal detection pulse, if used. www.ixysic.com 11 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION For single-ended receive applications where only one RX output is used, the snoop circuit gain can be adjusted back to 0 dB by changing the value of the snoop series resistors R6, R7, R44 and R45 from 1.8M to 715k This change results in negligible modification to the ringing detect threshold. On the equipment’s low voltage side of the barrier, the receive signal is converted by a photodiode into a photocurrent. The photocurrent, a linear representation of the receive signal, is amplified and converted to a differential voltage output on RX+ and RX-. 3.3 Off-Hook Operation: OH=0 Variations in gain are controlled to within ±0.4 dB by factory gain trim, which sets the output to unity gain. 3.3.1 Receive Signal Path To accommodate single-supply operation, LITELINK includes a small DC bias on the RX outputs of 1.0VDC. Most applications should AC couple the RX outputs as shown in Figure 4. Signals to and from the telephone network appear on the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by the LITELINK two-wire to four-wire hybrid. Next, the receive signal is converted to infrared light by the receive photodiode amplifier and receive path LED. The intensity of the light is modulated by the receive signal and coupled across the electrical isolation barrier by a reflective dome. LITELINK may be used for differential or single-ended output as shown in Figure 4. Single-ended use will produce 6 dB less signal output amplitude. Do not exceed 0 dBm into 600 (2.2 VP-P) signal input with the standard application circuit. See application note AN-157, Increased LITELINK III Transmit Power for more information. Figure 4. Differential and Single-ended Receive Path Connections to LITELINK Low-Voltage Side CODEC or Voice Circuit 0.1µF RX+ LITELINK RX+ 0.1µF RX- RX- 0.1µF RX 3.3.2 Transmit Signal Path Connect transmit signals from the low-voltage side equipment to the TX+ and TX- pins of LITELINK. Do not exceed a signal level of 0 dBm in 600 (or 2.2 VP-P). Differential transmit signals are converted to single-ended signals in LITELINK. The signal is coupled to the transmit photodiode amplifier in a similar manner to the receive path. See application note AN-157, Increased LITELINK III Transmit Power for more information. RX+ stage where the transmit signal modulates the telephone line loop current. As in the receive path, gain is set to unity at the factory, limiting insertion loss variation to ±0.4 dB. Differential and single-ended transmit signals into LITELINK should not exceed a signal level of 0 dBm referenced to 600 (or 2.2 VP-P). For output power levels above 0dBm consult the application note AN-157, Increased LITELINK III Transmit Power for more information. The output of the photodiode amplifier is coupled to a voltage-to-current converter via a transconductance 12 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION Figure 5. Differential and Single-ended Transmit Path Connections to LITELINK LITELINK Low-Voltage Side CODEC or Transmit Circuit TXA1 TXA2 0.1µf TX- 0.1µf TX+ + LITELINK Low-Voltage Side CODEC or Transmit Circuit 0.1µf TX- 0.1µf TX+ TXA1 3.4 Start-up Requirements OH must be de-asserted (set logic high) once after power-up for at least 50ms to transfer internal gain trim values within LITELINK. This would be normal operation in most applications. Failure to comply with this requirement will result in transmission gain errors and possibly distortion. 3.5 DC Characteristics The CPC5620 and CPC5621 are designed for worldwide application, including use under the requirements of TBR-21. The ZDC, DCS1, and DCS2 pins control the VI slope characteristics of LITELINK. Selecting appropriate resistor values for RZDC (R16) and RDCS (R15) in the provided application circuits assure compliance with DC requirements. + refer to the guidelines for FET thermal management provided in AN-146, Guidelines for Effective LITELINK Designs. 3.6 AC Characteristics 3.6.1 Resistive Termination Applications North American and Japanese telephone line AC termination requirements are met with a resistive 600 AC termination. Receive termination is applied to the LITELINK ZNT pin (pin 29) as a 301 resistor, RZNT (R10). 3.6.2 Reactive Termination Applications Many countries use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. 3.5.1 Setting a Current Limit Line Impedance Model LITELINK includes a telephone line current limit feature that is selectable by choosing the desired value for RZDC (R16) using the following formula: RS 1V I CL Amps = ------------- + 0.008A R ZDC RP IXYS Integrated Circuits Division recommends using 8.2 for RZDC for most applications, limiting telephone line current to 130 mA. Whether using the recommended value above or when setting RZDC higher for a lower loop current limit R05 CP Australia China TBR 21 RS RP 220 820 200 680 270 750 CP 120 nF 100 nF 150 nF Proper gain and termination impedance circuits for a complex impedance requires the use of complex network on ZNT as shown in the “Reactive Termination Application Circuit Schematic” on page 8. www.ixysic.com 13 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 3.6.3 Mode Pin Usage Assert the MODE pin low to introduce a 7 dB pad into the transmit path and add 7 dB of gain to the receive path. These changes compensate for the gain changes made to the transmit and receive paths in reactive termination implementations. Insertion loss with MODE de-asserted and the resistive termination application circuit is 0 dB. Insertion loss with the reactive termination application circuit and MODE asserted is also 0 dB. 4. Regulatory Information LITELINK III can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. LITELINK provides supplementary isolation. Metallic surge requirements are met through the inclusion of a Sidactor in the application circuit. Longitudinal surge protection is provided by LITELINK’s optical barrier technology and the use of high-voltage components in the application circuit as needed. The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using LITELINK are advised to carefully verify that their end-product design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electro-static discharges resulting from inadequate protection measures at the board or system level. 5. LITELINK Design Resources The IXYS Integrated Circuits Division web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. See the following links: LITELINK datasheets and reference designs Application note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-152 LITELINK II to LITELINK III Design Conversion Application note AN-155 Understanding LITELINK Display Feature Signal Routing and Applications 14 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 6. LITELINK Performance The following graphs show LITELINK performance using the North American application circuit shown in this data sheet. Figure 6. Receive Frequency Response at RX Figure 9. Transmit THD on Tip and Ring 0 2 0 -20 -2 -40 -4 -60 Gain -6 dBm THD+N dB -80 -8 -100 -10 -120 -12 -14 0 500 1000 1500 2000 2500 3000 3500 4000 -140 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 7. Transmit Frequency Response at TX Figure 10.Transhybrid Loss 0 2 -5 0 -10 -2 -15 -4 THL -20 dB Gain dBm -6 -25 -8 -30 -10 -35 -40 -12 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 2000 2500 3000 3500 4000 Frequency Frequency Figure 11.Return Loss Figure 8. Receive THD on RX 60 0 -20 55 -40 50 -60 THD+N dB -80 Return Loss 45 (dB) -100 40 -120 35 -140 0 500 1000 1500 2000 2500 3000 3500 4000 30 Frequency 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) R05 www.ixysic.com 15 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION Figure 12.Snoop Circuit Frequency Response 5 0 -5 Gain (dBm ) -10 -15 -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Figure 13.Snoop Circuit THD + N +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 500 1k 1.5k 2k Hz 2.5k 3k 3.5k 4k Figure 14.Snoop Circuit Common Mode Rejection +0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 500 1K 2K 4K Frequency (Hz) 16 www.ixysic.com R05 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 7. Manufacturing Information 7.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC5620A / CPC5621A MSL 3 7.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 7.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC5620A / CPC5621A 260°C for 30 seconds 7.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used Pb R05 e3 www.ixysic.com 17 CPC5620/CPC5621 INTEGRATED CIRCUITS DIVISION 7.5 Mechanical Dimensions Figure 15. CPC5620A/CPC5621A Package Dimensions 7.239 ± 0.051 (0.285 ± 0.002) 10.287 ± .254 (0.405 ± 0.010) PCB Land Pattern 0.203 (0.008) 7.493 ± 0.127 (0.295 ± 0.005) 9.30 (0.366) 1.90 (0.0748) 10.363 ± 0.127 (0.408 ± 0.005) Pin 1 0.635 ± 0.076 (0.025 ± 0.003) 0.330 ± 0.051 (0.013 ± 0.002) 0.635 x 45º 1.016 Typ. (0.025 x 45º) (0.040 Typ.) 0.635 (0.025) 0.40 (0.0157) 1.981 ± 0.051 (0.078 ± 0.002) 2.134 Max (0.084 Max) 9.525 ± 0.076 (0.375 ± 0.003) Dimensions mm (inches) MIN 0, MAX 0.102 (MIN 0, MAX 0.004) Figure 16. CPC5620ATR/CPC5621ATR Tape and Reel Dimensions 330.2 DIA. (13.00 DIA.) W=16 (0.630) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) B0=10.70 (0.421) K0=3.20 (0.126) A0=10.90 (0.429) P=12.00 (0.472) K1=2.70 (0.106) Embossed Carrier Embossment NOTES: 1. All dimensions carry tolerances of EIA Standard 481-2 2. The tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2 Dimensions mm (inches) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5620/CPC5621-R05 Copyright © 2012, IXYS Integrated Circuits Division LITELINK® is a registered trademark of IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/22/2012 18 www.ixysic.com R05