EMC EM39LV040-45RFDC 4m (512kx8) bits flash memory Datasheet

EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
General Description
The EM39LV040 is a 4M bits Flash memory organized as 512K x 8 bits. The EM39LV040
uses a single 3.0 volt-only power supply for both Read and Write functions. Featuring high
performance Flash memory technology, the EM39LV040 provides a typical Byte-Program
time of 11 µsec and a typical Sector-Erase time of 40 ms. The device uses Toggle Bit or
Data# Polling to detect the completion of the Program or Erase operation. To protect against
inadvertent write, the device has on-chip hardware and software data protection schemes.
The device offers typical 100,000 cycles endurance and a greater than 10 years data retention.
The EM39LV040 conforms to JEDEC standard pin outs for x8 memories. It is offered in
package types of 32-lead PLCC, 32-pin TSOP, and known good die (KGD). For KGD, please
contact ELAN Microelectronics or its representatives for detailed information (see Appendix at
the bottom of this specification for Ordering Information).
The EM39LV040 devices are developed for applications that require memories with
convenient and economical updating of program, data or configurations, e.g., Networking
cards, CD-RW, Scanner, Digital TV, Electronic Books, GPS, Router/Switcher, etc.
Features
Single Power Supply
Full voltage range from 2.7 to 3.6 volts
for both read and write operations
Regulated voltage range: 3.0 to 3.6 volts
for both read and write operations
End-of-Program or End-of-Erase
Detection
Data# Polling
Toggle Bit
Sector-Erase Capability
Uniform 4Kbyte sectors
CMOS I/O Compatibility
Sector-Erase Capability
Uniform 64Kbyte sectors
JEDEC Standard
Pin-out and software command sets
compatible with single-power supply
|Flash memory
Read Access Time
Access time: 45, 55, 70 and 90 ns
Power Consumption
Active current: 5 mA (Typical)
Standby current: 1 µA (Typical)
High Reliability
Endurance cycles: 100K (Typical)
Data retention: 10 years
Erase/Program Features
Sector-Erase Time: 40 ms (Typical)
Chip-Erase Time:
40 ms (Typical)
Byte-Program Time: 11µs (Typical)
Chip Rewrite Time: 6 seconds (Typical)
Package Option
32-pin PLCC
32-pin TSOP
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 1 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Functional Block Diagram
Flash
Mem ory Array
X-Decoder
Address Buffer &
Latches
Mem ory Address
CE#
OE#
Y-Decoder
I/O Buffers and Data Latches
Control Logic
W E#
DQ7-DQ0
Figure 0a: Functional Block Diagram
Pin Assignments
32-Lead PLCC
A12 A15 A16 A18 VDD WE# A17
32 31 30
29
A14
6
28
A13
A5
7
27
A8
A4
8
26
A9
25
A11
A7
5
A6
4
3
2
1
32-Lead PLCC
Top View
A3
9
A2
10
24
OE#
A1
11
23
A10
A0
12
22
DQ0
13
21
14 15 16 17 18 19 20
CE#
DQ7
DQ1DQ2 VSS DQ3DQ4DQ5DQ6
Figure 0b: PLCC Pin Assignments
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 2 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
32-Lead TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
A17
W E#
V DD
A18
A16
A15
A12
A7
A6
A5
A4
Standard TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 0c: TSOP Pin Assignments
Pin Description
Pin Name
Function
A0–A18
19 addresses
DQ7–DQ0
Data inputs/outputs
CE#
Chip enable
OE#
Output enable
WE#
Write enable
VDD
3.0 volt-only single power supply*
VSS
Device ground
*See Appendix for ordering information on speed options
and voltage supply tolerances.
Table 1: Pin Description
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 3 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Device Operation
The EM39LV040 uses Commands to initiate the memory operation functions. The
Commands are written to the device by asserting WE# Low while keeping CE# Low. The
address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data
bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the EM39LV040 is controlled by CE# and OE#. Both have to be Low
for the system to obtain data from the outputs. CE# is used for device selection. When CE#
is high, the chip is deselected and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for
further details.
Byte Program
The EM39LV040 is programmed on a byte-by-byte basis. Before programming, the sector
where the byte is located; must be erased completely. The Program operation is
accomplished in three steps:
The first step is a three-byte load sequence for Software Data Protection.
The second step is to load byte address and byte data. During the Byte Program
operation, the addresses are latched on the falling edge of either CE# or WE#, whichever
occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever
occurs first.
The third step is the internal Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro gram operation, once initiated,
will be completed within 16 µs. See Figures 2 and 3 for WE# and CE# controlled
Program operation timing diagrams respectively and Figure 12 for the corresponding
flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform additional tasks. Any command
issued during the internal Program operation is ignored.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 4 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
EM39LV040 Device Operation
Operation
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
Erase
VIL
VIH
VIL
X*
Sector or Block address, XXH for
Chip-Erase
Standby
VIH
X
X
High Z
X
Write Inhibit
X
VIL
X
High Z/DOUT
X
Write Inhibit
X
X
VIH
High Z/DOUT
X
Software Mode
VIL
VIL
VIH
See Table 3
Product
Identification
* X can be VIL or VIH, but no other value.
Table 2: EM39LV040 Device Operation
Write Command/Command Sequence
The EM39LV040 provides two software methods to detect the completion of a Program or
Erase cycle in order to optimize the system write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates the internal Program or Erase
operation. The actual completion of the write operation is asynchronous with the system;
therefore, either a Data# Polling or Toggle Bit read may be simultaneously completed with the
write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data
may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection,
when an erroneous result occurs, the software routine should include an additional two times
loop to read the accessed location. If both reads are valid, then the device has completed the
write cycle, otherwise the rejection is valid.
Chip Erase
The EM39LV040 provides Chip-Erase feature, which allows the entire memory array to be
erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte
command sequence with Chip-Erase command (10H) at address 5555H in the last byte
sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,
whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and
Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and
Figure 15 for the corresponding flowchart. Any command issued during the Chip-Erase
operation is ignored.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 5 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Sector Erase
The EM39LV040 offers Sector-Erase mode. The Sector-Erase operation allows the system
to erase the device on a sector-by-sector basis. The sector architecture is based on uniform
sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H) and Sector Address (SA) in the last
bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse,
while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal
Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be
determined by using either Data# Polling or Toggle Bit method. See Figures 7 for timing
waveforms. Any command issued during the Sector-Erase operation is ignored.
Data# Polling (DQ7)
When the EM39LV040 is in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7
will produce the true data. Note that even though DQ7 may have valid data immediately
following the completion of an internal Program operation, the remaining data outputs may still
be invalid (valid data on the entire data bus will appear in subsequent successive Read cycles
after an interval of 1 µs). During internal Erase operation, any attempt to read DQ7 will
produce a “0”. Once the internal Erase operation is completed, DQ7 will produce a “1”. The
Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-Erase or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 13 for the
corresponding flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will
produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or
Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the
next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-Erase or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 13
for the corresponding flowchart.
Data Protection
The EM39LV040 provides both hardware and software features to protect the data from
inadvertent write.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 6 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Hardware Data Protection
Noise/Glitch Protection:
VDD Power Up/Down Detection:
Write Inhibit Mode:
A WE# or CE# pulse of less than 5 ns will not initiate a
write cycle.
The Write operation is inhibited when VDD is less than
1.5V.
Forcing OE# Low, CE# High, or WE# High will inhibit the
Write operation. This prevents inadvertent write during
power-up or power-down.
Software Data Protection (SDP)
The EM39LV040 provides the JEDEC approved Software Data Protection (SDP) scheme for
Program and Erase operations. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write operations, especially during the system
power-up or power-down transition. Any Erase operation requires the inclusion of six-byte
sequence. See Table 3 below for the specific software command codes. During SDP
command sequence, invalid commands will abort the device to Read mode within TRC.
Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Addr1
Addr1
Addr1
Addr1
Data
Addr1
Data
Data
Data
Data
2
Data
Byte Program
5555H
AAH
2AAAH
55H
5555H
A0H
BA
Sector Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SAX3
30H
Chip Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Software ID
Entry4
5555H
AAH
2AAAH
55H
5555H
90H
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0000H
7FH
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0003H
7FH
Manufacture ID
5555H
AAH
2AAAH
55H
5555H
90H
0040H
1FH
2AAAH
55H
5555H
90H
0001H 29FH
2AAAH
55H
5555H
F0H
Device ID
5555H
AAH
Software ID Exit
5
XXH
F0H
Software ID Exit
5
5555H
AAH
Data
Notes:
1. Address format A18-A0 (Hex) & Address A16 can be VIL or VIH, (but no other value) for the Command sequence.
2. BA = Program byte address.
3. SAX for Sector-Erase; uses A19-A12 address lines.
4. The device does not remain in Software Product ID mode if powered down (see Figure 9 for more information).
5. Both Software ID Exit operations are equivalent.
Table 3: Software Command Sequence
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 7 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Absolute Maximum Ratings
NOTE
Applied conditions greater than these specified ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these
conditions or conditions greater than those defined in the operational sections of this
specification, are not implied. Exposure to absolute maximum stress rating condition may
affect device reliability.
Temperature Under Bias ..............................................................–55°C to 125°C
Storage Temperature ....................................................................–65°C to 150°C
D.C. Voltage on Any Pin to Ground Potential ...............................–0.5 V to VDD+0.5V
Transient Voltage (<20ns) on Any Pin to Ground Potential ...........–2.0V to VDD +2.0V
Voltage on A9 Pin to Ground Potential...........................................–0.5 V to 13.2V
Package Power Dissipation Capability (Ta=25°C).........................1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) ............240°C
Output Short Circuit Current * ........................................................50mA
* Output shorted for no more than one second.
No more than one output shorted at a time.
Operating Range
Model Name
Range
Ambient Temperature
Commercial
0°C to +70°C
VDD
Full voltage range: 2.7~3.6V
Regulated voltage range: 3.0~3.6V
AC39LV040
Industrial
–40°C to +85°C
Full voltage range: 2.7~3.6V
Regulated voltage range: 3.0~3.6V
Table 4: Operating Range
AC Conditions for Testing
Input Rise/Fall Time........................................................................5ns
Output Load....................................................................................CL=30pF for 45Rns
Output Load....................................................................................CL=100pF for 70ns/90ns
See Figures 10 and 11 for more details.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 8 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
DC CHARACTERISTICS (CMOS Compatible)
Parameter
Description
Test Conditions
Power Supply Current
IDD
Min
Max
Unit
Address Input =VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
Read
CE#=OE#=VIL, WE#=VIH, all I/Os open
20
mA
Program and Erase
CE#=WE#=VIL, OE#=VIH,
30
mA
ISB
Standby VDD Current
CE#=VIHC, VDD=VDD Max
10
µA
ILI
Input Leakage Current
VIN=GND to VDD, VDD=VDD Max
1
µA
ILO
Output Leakage Current
VOUT=GND to VDD, VDD=VDD Max
10
µA
VIL
Input Low Voltage
VDD=VDD Min
0.8
V
VIH
Input High Voltage
VDD=VDD Max
0.7 VDD
V
VIHC
Input High Voltage (CMOS)
VDD=VDD Max
VDD-0.3
V
VOL
Output Low Voltage
IOL=100µA, VDD=VDD Min
VOH
Output High Voltage
IOH=-100µA, VDD=VDD Min
0.2
VDD-0.2
V
V
Table 5: DC Characteristics (Cmos Compatible)
Recommended System Power-up Timing
Parameter
TPU-READ*
TPU-WRITE*
Description
Min
Unit
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 6: Recommended System Power-up Timing
Capacitance (Ta = 25°C, f = 1Mhz, other pins open)
Parameter
Description
CI/O*
CIN*
Test Conditons
Max
I/O Pin Capacitance
VI/O=0V
12pF
Input Capacitance
VIN=0V
6pF
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 7: Capacitance (Ta = 25°C, f = 1Mhz, Other Pins Open)
Reliability Characteristics
Symbol
Parameter
Min Specification
Unit
Test Method
NEND*
TDR*
Endurance
10,000
Cycles
JEDEC Standard A117
Data Retention
10
Years
JEDEC Standard A103
ILTH*
Latch Up
100+IDD
mA
JEDEC Standard 78
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 8: Reliability Characteristics
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 9 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
AC Characteristics
Read Cycle Timing Parameters
Symbol
45REC
Parameter
55REC
70REC
90REC
Min Max Min Max Min Max Min Max
45
55
TRC
Read Cycle Time
TCE
Chip Enable Access Time
45
55
70
90
ns
TAA
Address Access Time
45
55
70
90
ns
TOE
TCLZ*
Output Enable Access Time
30
30
35
45
ns
CE# Low to Active Output
0
0
0
0
ns
TOLZ*
TCHZ*
OE# Low to Active Output
0
0
0
0
ns
CE# High to High-Z Output
15
15
25
30
ns
TOHZ*
OE# High to High-Z Output
15
15
25
30
ns
TOH*
Output Hold from Address Change
0
0
70
0
0
90
Unit
ns
0
ns
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 9: Read Cycle Timing Parameters
Program/Erase Cycle Timing Parameter
Symbol
Parameter
Min
Max
Unit
16
µs
TBP
Byte-Program Time
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH*
WE# Pulse Width High
30
ns
TCPH*
CE# Pulse Width High
30
ns
TDS
TDH*
Data Setup Time
40
ns
Data Hold Time
0
ns
TIDA*
Software ID Access and Exit Time
150
ns
TSE
Sector Erase
60
ms
TSCE
Chip Erase
60
ms
* This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 10: Program/Erase Cycle Timing Parameter
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 10 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Timing Diagrams
Read Cycle Timing Diagram
TRC
TAA
A18~A0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCHZ
TOH
TCLZ
HIGH-Z
Data Valid
DQ7-0
Data Valid
HIGH-Z
Figure 1: Read Cycle Timing Diagram
WE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
TBP
A18~A0
5555
2AAA
5555
ADDR
TAH
WE#
TDH
TWP
TWPH
TDS
TAS
OE#
TCH
CE#
TCS
DQ7-0
AA
55
A0
SW0
SW1
SW2
DATA
Byte
(ADDR/DATA)
Figure 2: WE# Controlled Program Cycle Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 11 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
CE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
TBP
A18~A0
5555
2AAA
5555
ADDR
TAH
CE#
TDH
TCP
TCPH
TDS
TAS
OE#
TCH
WE#
TCS
DQ7-0
AA
55
A0
SW0
SW1
SW2
DATA
Byte
(ADDR/DATA)
Figure 3: CE# Controlled Program Cycle Timing Diagram
Data# Polling Timing Diagram
A18~A0
TCE
CE#
TOEH
TOES
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA#
Figure 4: Data# Polling Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 12 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Toggle Bit Timing Diagram
A18~A0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6
Two Read Cycles
With Same Outputs
Figure 5: Toggle Bit Timing Diagram
WE# Controlled Chip-Erase Timing Diagram
TSCE
Six-Byte Code For Chip-Erase
A18~A0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ7-0
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 10)
Figure 6: WE# Controlled Chip-Erase Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 13 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
WE# Controlled Sector-Erase Timing Diagram
TSE
Six-Byte Code For Block-Erase
2AAA
5555
A18~A0
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
AA
SW0
DQ7-0
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 10)
SAX=Sector Address
X can be VIL or VIH, but no other value.
Figure 7: WE# Controlled Sector-Erase Timing Diagram
Software ID Entry/Exit and Read
Software ID Entry and Read
Three-Byte Sequence For
Software ID Entry
Address A14-0
5555
2AAA
5555
0000H 0003H 0040H 0001H
CE#
OE#
T IDA
T WP
W E#
T AA
T W PH
DQ7-0
AA
SW 0
55
SW 1
90
7F
7F
1F
29h
SW 2
Figure 8: Software ID Entry and Read
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 14 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Software ID Exit and Reset
Three-Byte Sequence For
Software ID Exit and Reset
Address A14-0
DQ7-0
2AAA
5555
5555
55
AA
F0
T IDA
CE#
OE#
TW P
W E#
SW 0 T W PH SW 1
SW 2
Figure 9: Software ID Exit and Reset
AC Input/Output Testing
AC Input/Output Reference Waveforms
VIHT
Input
VIT
Reference Points
VOT
Output
VILT
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT(0.1 VDD) for a logic "0".
Measurement reference points for inputs and outpputs are VIT(0.5 VDD) and VOT(0.5 VDD). Input
rise and fall time (10% - 90% ) is <5ns
Note: VIT = Vinput Test
VOT = Voutput Test
VIHT = Vinput HIGH Test
VILT = Vinput LOW Test
Figure 10: AC Input/Output Reference Waveforms
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 15 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
An AC Test Load Example
TO TESTER
TO DUT
CL
Figure 11: An AC Test Load Example
Flow Charts
Byte-Program Algorithm
Start
Load Data: AAH
Address: 5555H
Load Data: 55H
Address: 2AAAH
Load Data: A0H
Address: 5555H
Load Byte
Address/Byte Data
W ait for end of Program
(T BP , Data# Polling bit, or
Toggle bit operation)
Program Com pleted
Figure 12: Byte-Program Algorithm Flowchart
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 16 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Wait Options
Internal Tim er
Toggle Bit
Data# Polling
Progrm /Erase
Initiated
Progrm/Erase
Initiated
Progrm /Erase
Initiated
W ait T BP , T SCE ,
T SE or T BE
Read Byte
Read DQ7
Progrm /Erase
Com pleted
Read Sam e
Byte
Is DQ7=true
data?
No
Yes
Does DQ6
m atch?
No
Progrm /Erase
Com pleted
Yes
Progrm/Erase
Com pleted
Figure 13: Wait Options Flowchart
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 17 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Software ID Commands
Software ID Entry
Comm and Sequence
Software ID Exit Comm and
Sequence
Load Data: AAH
Address: 5555H
Load Data: AAH
Address: 5555H
Load Data: F0H
Address: XXH
Load Data: 55H
Address: 2AAAH
Load Data: 55H
Address: 2AAAH
W ait T IDA
Load Data: 90H
Address: 5555H
Load Data: F0H
Address: 5555H
Return to Norm al
Operation
W ait T IDA
W ait T IDA
Read Software ID
Return to Norm al
Operation
X can be VIL or VIH, but no other value.
Figure 14: Software ID Command Flowcharts
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 18 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Erase Command Sequence
Chip-Erase
Com m and Sequence
Sector-Erase
Com mand Sequence
Load Data: AAH
Address: 5555H
Load Data: AAH
Address: 5555H
Load Data: 55H
Address: 2AAAH
Load Data: 55H
Address: 2AAAH
Load Data: 80H
Address: 5555H
Load Data: 80H
Address: 5555H
Load Data: AAH
Address: 5555H
Load Data: AAH
Address: 5555H
Load Data: 55H
Address: 2AAAH
Load Data: 55H
Address: 2AAAH
Load Data: 10H
Address: 5555H
Load Data: 30H
Address: SA X
W ait T SCE
W ait T SE
Chip Erased to FFH
Sector Erased to FFH
X can be VIL or VIH, but no other value.
Figure 15: Erase Command Sequence Flowchart
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 19 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Appendix
ORDERING INFORMATION (Standard Products)
The order number is defined by a combination of the following elements.
EM39LV040 -70 F
M
C
Description
Temperature Range (1 digit)
C
= Commercial (0°C to +70°C)
I
= Industrial (-40°C to +85°C)
Package Type (1-3 digit)
M
= TSOP (Type 1, die up, 8mm x 14mm)
L
= 32-pin PLCC
H
= Chip Form
D
= Known Good Dice (for wafer dice sell)
F
= PB (Lead) free package
Speed Option (2-3 digits)
45R = 45ns
55
= 55ns
70
= 70ns
90
= 90ns
**
= VDD = 2.7~3.6V Full voltage range
**R
= VDD = 3.0~3.6V
Regulated voltage range
Device Number/Description
EM39LV040
4 Megabit (512K x 8-Bit) Flash Memory
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 20 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
ORDERING INFORMATION (Non-Standard Products)
For Known Good Dice (KGD), please contact ELAN Microelectronics at the following contact
information or its representatives.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Science-based Industrial Park
Hsinchu, Taiwan, R.O.C. 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information Technology
Group
Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
[email protected]
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
USA
Tel: +1 408 366-8223
Fax: +1 408 366-8220
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp.
(Europe)
Elan (Shenzhen)
Microelectronics Corp., Ltd.
Elan Electronics (Shanghai)
Corporation, Ltd.
Dubendorfstrasse 4
8051 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S. Ave.
Shenzhen Hi-Tech Industrial Park
Shenzhen, Guandong, CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
23/Bldg. #115 Lane 572, Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA
Tel: +86 021 5080-3866
Fax: +86 021 5080-4600
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 21 of 21
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