fax id: 1075 CY7C1020V 32K x 16 Static RAM Features (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). • 3.3V operation (3.0V - 3.6V) • High speed — tAA = 10 ns • Low active power — 540 mW (max., 12 ns) • Very Low standby power — 330 µW (max., “L” version) • Automatic power-down when deselected • Independent Control of Upper and Lower bytes • Available in 44-pin TSOP II and 400-mil SOJ Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O 9 to I/O16. See the truth table at the back of this datasheet for a complete description of read and write modes. Functional Description The CY7C1020V is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020V is available in standard 44-pin TSOP type II and 400-mil-wide SOJ packages. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable Logic Block Diagram Pin Configuration SOJ / TSOP II Top View SENSE AMPS A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array I/O1 – I/O8 I/O9 – I/O16 COLUMN DECODER A7 A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE 1020V-1 NC A 14 A 13 A 12 A 11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A 10 A9 A8 A7 NC 1 44 2 3 4 43 42 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A3 A4 A5 A6 NC 1020V-2 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) • 7C1020V-12 7C1020V-15 7C1020V-20 10 12 15 20 130 120 110 100 L 100 90 80 70 1 1 1 1 L 0.1 0.1 0.1 0.1 Maximum CMOS Standby Current (mA) Cypress Semiconductor Corporation 7C1020V-10 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 1996 – Revised April 13, 1998 CY7C1020V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied ............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[1] .....................................–0.5V to VCC +0.5V Commercial Industrial [1] DC Input Voltage ..................................–0.5V to VCC +0.5V Ambient Temperature[2] VCC 0°C to +70°C 3.0V - 3.6V –40°C to +85°C 3.0V - 3.6V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1020V-10 7C1020V-12 Min. Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = – 4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3V VIL Input LOW Voltage[1] –0.5 IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX L Automatic CE Power-Down Current — CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 ISB1 ISB2 Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 2 2.4 2.4 0.4 L Max. Unit V 0.4 V 2.0 VCC + 0.3V V 0.8 –0.5 0.8 V –1 +1 –1 +1 µA –2 +2 –2 +2 µA 130 120 mA 100 90 mA 15 15 mA 7 7 mA 1 1 mA 100 100 µA CY7C1020V Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = – 4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current IOZ Output Leakage Current ICC VCC Operating Supply Current ISB1 ISB2 7C1020V-15 7C1020V-20 Min. Min. Max. 2.4 VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX L Automatic CE Power-Down Current — CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 Unit 0.4 V V 2.4 0.4 GND < VI < VCC GND < VI < VCC, Output Disabled Max. V 2.0 VCC + 0.3V 2.0 VCC + 0.3V –0.5 0.8 –0.5 0.8 V –1 +1 –1 +1 µA +2 –2 –2 L +2 µA 110 100 mA 80 70 mA 15 15 mA 7 7 mA 1 1 mA 100 100 µA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Notes: 3. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R 481 Ω 3.3V R 481Ω ALL INPUT PULSES 3.3V OUTPUT 3.0V 90% OUTPUT 30 pF R2 255Ω INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT R2 255Ω 5 pF INCLUDING JIG AND SCOPE (b) 167Ω GND <3ns 10% 90% 10% <3ns 1020V-3 1020V-4 1.73V 30 pF 3 CY7C1020V Switching Characteristics[4] Over the Operating Range Parameter Description 7C1020V-10 7C1020V-12 7C1020V-15 Min. Min. Min. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[5, 6] tLZCE CE LOW to Low Z 10 12 10 3 12 3 0 3 [5, 6] 15 3 ns 7 3 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 12 12 15 ns tDBE Byte enable to Data Valid 5 6 7 ns tLZBE Byte enable to Low Z tHZBE Byte disable to High Z 0 6 ns ns 0 6 5 ns 3 0 5 [6] 15 0 0 0 5 7 0 ns 0 6 ns ns 7 ns WRITE CYCLE[7] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-Up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-Up to Write End 5 6 10 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns WE HIGH to Low Z [6] tHZWE WE LOW to High Z [5, 6] tBW Byte enable to end of write tLZWE 5 7 6 8 7 9 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 4 CY7C1020V Switching Characteristics[4] Over the Operating Range (continued) 7C1020V-20 Parameter Description Min. Max. Unit 20 ns 20 ns 9 ns READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z 20 3 tLZCE CE LOW to Low Z CE HIGH to High Z[5, 6] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE Byte enable to Data Valid tLZBE Byte enable to Low Z tHZBE Byte disable to High Z ns 0 [6] tHZCE ns ns 3 ns 9 0 ns ns 20 ns 9 ns 0 ns 9 ns WRITE CYCLE[7] tWC Write Cycle Time 20 ns tSCE CE LOW to Write End 12 ns tAW Address Set-Up to Write End 12 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 12 ns tSD Data Set-Up to Write End 10 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z[6] 3 tHZWE WE LOW to High Z[5, 6] tBW Byte enable to end of write ns 9 12 ns ns Switching Waveforms Read Cycle No.1 [8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1020V-5 Notes: 8. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL 9. WE is HIGH for read cycle. 5 CY7C1020V Switching Waveforms (continued) Read Cycle No.2 (OE Controlled) [9, 10] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE V CC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IICC CC 50% 50% IISB SB 1020V-6 Write Cycle No. 1 (CE Controlled) [11, 12] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O 1020V-7 Notes: 10. Address valid prior to or coincident with CE transition LOW. 11. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 12. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 6 CY7C1020V Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O 1020V-8 Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE 7 1020V-10 CY7C1020V Truth Table CE OE H X L L L X WE BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) L I/O1 - I/O8 I/O9 - I/O16 Mode Power H L High Z Data In Write - Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 15 20 Ordering Code Package Name Package Type Operating Range CY7C1020V33-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33L-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33-10ZC Z44 44-Lead TSOP Type II Commercial Commercial CY7C1020V33L-10ZC Z44 44-Lead TSOP Type II CY7C1020V33-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33L-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33-12ZC Z44 44-Lead TSOP Type II Commercial Commercial CY7C1020V33L-12ZC Z44 44-Lead TSOP Type II CY7C1020V33-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33L-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1020V33-15ZC Z44 44-Lead TSOP Type II Commercial CY7C1020V33L-15ZC Z44 44-Lead TSOP Type II Commercial CY7C1020V33-15ZI Z44 44-Lead TSOP Type II Industrial CY7C1020V33L-20ZC Z44 44-Lead TSOP Type II Commercial Document #: 38-00543-B 8 CY7C1020V Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 44-Pin TSOP II Z44 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.