Freescale MC68HC805P18CDW Specification (general release) Datasheet

Freescale Semiconductor, Inc.
HC805P18GRS/D
REV 1.0
68HC805P18
Freescale Semiconductor, Inc...
SPECIFICATION
(General Release)
 December 7, 1995
CSIC System Design Group
Austin, Texas
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph
Title
Page
Freescale Semiconductor, Inc...
SECTION 1
INTRODUCTION
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Port A (PA0 through PA7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Port B (PB5/SDO, PB6/SDI, and PB7/SCK). . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1,
PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.8
Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.9
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.10 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
2.5
2.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
User Mode Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
User EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
SECTION 3
CENTRAL PROCESSING UNIT
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.2
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Rev. 1.0
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iii
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph
3.2.3
3.2.4
3.2.5
Title
Page
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Freescale Semiconductor, Inc...
SECTION 4
INTERRUPTS
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.3
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
SECTION 5
RESETS
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.3
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
SECTION 6
OPERATING MODES
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.5
iv
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
User Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
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MC68HC805P18
Rev. 1.0
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph
Title
Page
SECTION 7
INPUT/OUTPUT PORTS
Freescale Semiconductor, Inc...
7.1
7.2
7.3
7.4
7.5
7.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SECTION 8
EEPROM
8.1
8.2
8.3
8.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
EEPROM Programming Register (EEPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Mask Option Registers (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SECTION 9
ANALOG-TO-DIGITAL CONVERTER
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.3.1
9.3.2
9.3.3
9.4
9.5
9.6
9.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Conversion Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Multi-Channel Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
A/D Subsystem During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
A/D Subsystem Operation During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Rev. 1.0
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TABLE OF CONTENTS
Paragraph
Title
Page
Freescale Semiconductor, Inc...
SECTION 10
16-BIT TIMER
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Timer Status Register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Timer Operation During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
SECTION 11
SERIAL INPUT/OUTPUT PORT
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3.2 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.3 SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
SECTION 12
INSTRUCTION SET
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.4 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.2.8 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
vi
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MC68HC805P18
Rev. 1.0
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TABLE OF CONTENTS
Paragraph
Title
Page
12.3.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.3.4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.3.5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.4 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Freescale Semiconductor, Inc...
SECTION 13
ELECTRICAL SPECIFICATIONS
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Active Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
A/D Converter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
SECTION 14
MECHANICAL SPECIFICATIONS
14.1
14.2
14.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
28-Pin Dual In-Line Package (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
SECTION 15
ORDERING INFORMATION
15.1
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
APPENDIX A
EMULATION
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LIST OF FIGURES
Freescale Semiconductor, Inc...
Figure
Title
Page
1-1
1-2
1-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
2-1
2-2
2-3
2-4
MC68HC805P18 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
MC68HC805P18 I/O and Control Registers Memory Map . . . . . . . . . . . . . . 2-4
MC68HC805P18 I/O and Control Registers $0000–$000F . . . . . . . . . . . . . 2-5
MC68HC805P18 I/O and Control Registers $0010-$001F. . . . . . . . . . . . . . 2-6
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4-1
4-2
Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
5-1
5-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Unimplemented Vector and COP Watchdog Timer Register . . . . . . . . . . . . 5-2
6-1
6-2
Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
7-1
7-2
7-3
7-4
Port A I/O Circuitry
Port B I/O Circuitry
Port C I/O Circuitry
Port D I/O Circuitry
8-1
8-2
8-3
EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
9-1
9-2
A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
10-1
10-2
10-3
10-4
10-5
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Timer Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-4
State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Rev. 1.0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
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LIST OF FIGURES
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Figure
Title
Page
10-6
10-7
10-8
10-9
10-10
10-11
Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Output Compare Software Initialization Example . . . . . . . . . . . . . . . . . . . . 10-7
Input Compare Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
11-1
11-2
11-3
11-4
11-5
SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
13-1
13-2
13-3
SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Power-On Reset and External Reset Timing Diagram . . . . . . . . . . . . . . . . 13-8
A-1
A-2
A-3
A-4
MC68HC705P3 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
MC68HC705P6 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
MC68HC705P9 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
MC68HC805P18 Mask Option Registera . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
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LIST OF TABLES
Freescale Semiconductor, Inc...
Table
Title
Page
4-1
Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
6-1
6-2
6-3
Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
7-1
7-2
7-3
7-4
Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
8-1
8-2
Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
9-1
A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . 9-5
12-1
12-2
12-3
12-4
12-5
12-6
12-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
15-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
A-1
A-2
A-3
A-4
Elements of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
Memory Breakdown by Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
P-Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 1
INTRODUCTION
4
1.1 Introduction
Freescale Semiconductor, Inc...
3
The Motorola MC68HC805P18 microcontroller is a member of the M68HC05
microcontroller family with a 4-channel, 8-bit analog-to-digital (A/D) converter, a
16-bit timer with output compare and input capture, a serial communications port
(SIOP), a computer operating properly (COP) watchdog timer, and 21 input/output
(I/O) pins (20 bidirectional, one input-only). The memory map contains 192 bytes
of RAM, 8064 bytes of program EEPROM (for user code), 512 bytes of boot ROM,
and128 bytes of EEPROM (for data storage). This device is available in a 28-pin
dual in-line package (DIP) or a small outline (SOIC) package. A functional block
diagram of the MC68HC805P18 is shown in Figure 1-1.
1.2 Features
5
6
7
8
9
10
•
Low-cost HC05 core running at 2 MHz bus speed
•
28-pin DIP or SOIC package
•
4 MHz on-chip crystal/ceramic resonator oscillator
•
8064 bytes of user EEPROM including 48 bytes of page zero EEPROM and
16 bytes of user vectors
•
192 bytes of on-chip RAM
•
128 bytes of EEPROM
•
Low-voltage reset
•
4-channel, 8-bit A/D converter
•
SIOP serial communications port
•
COP watchdog timer with active pulldown on RESET
•
16-bit timer with output compare and input capture
•
20 bidirectional I/O lines and one input-only line
•
High current sink and source on two I/O pins (PC0 and PC1)
11
12
13
14
A
16
17
18
19
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GENERAL RELEASE SPECIFICATION
8
COP
PH2
÷2
OSC 1
OSC
OSC 2
2
÷4
ALU
RESET
68HC05 CPU
IRQ
4
PROGRAM COUNTER
COND CODE REG
1 1 1H I NZC
PD5/CKOUT
PC7/VREFH
PC6/AD0
MUX
A/ D CONVERTER
0 0 0 0 0 0 0 0 1 1 STK PNTR
PORT C
INDEX REGISTER
7
PC5/AD1
PC4/AD2
PC3/AD3
PC2
PC1
PC0
8
SRAM — 192 BYTES
USER EEPROM — 8064 BYTES
10
11
EEPROM — 128 BYTES
PA6
PA5
PORT A
DATA DIRECTION REGISTER
PA7
9
13
TCMP
ACCUMULATOR
6
12
PD7/TCAP
CPU REGISTERS
5
Freescale Semiconductor, Inc...
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
DATA DIRECTION REGISTER
3
CPU CONTROL
PA4
PA3
PA2
PA1
PA0
PB5/SDO
PB6/SDI
PB7/SCK
14
PORT B AND
SIOP
REGISTERS
AND LOGIC
VDD
VSS
Figure 1-1. Block Diagram
A
16
17
18
19
20
INTRODUCTION
1-2
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GENERAL RELEASE SPECIFICATION
1.3 Mask Options
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EEPROM mask option register (MOR) selectable options include the following. For
additional information, refer to 8.4 Mask Option Registers (MOR).
8
2
•
IRQ is edge- and level-sensitive or edge-sensitive only.
•
SIOP most significant bit (MSB) first or least significant bit (LSB) first
•
SIOP clock rate set to oscillator divided by 2, 4, 8, or 16
•
COP watchdog timer enabled or disabled
•
Stop instruction enabled or converted to halt mode
•
Option to enable clock output pin to replace PD5
•
Option to individually enable pullups/interrupts on each of the eight port A
pins
6
•
LVR reset enabled or disabled
7
3
4
5
8
NOTE
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the
following sections will refer to the nominal values. The exact values
and their tolerance or limits are specified in SECTION 13
ELECTRICAL SPECIFICATIONS.
9
10
11
12
13
14
A
16
17
18
19
20
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GENERAL RELEASE SPECIFICATION
1.4 Functional Pin Description
8
The following paragraphs describe the functionality of each pin on the
MC68HC805P18 package. Pins connected to subsystems described in other
sections provide a reference to the section instead of a detailed functional
description.The pinout is shown in Figure 1-2.
2
3
4
Freescale Semiconductor, Inc...
5
6
7
8
9
RESET
1
28
VDD
IRQ
2
27
OSC1
PA7
3
26
OSC2
PA6
4
25
PD7/TCAP
PA5
5
24
TCMP
PA4
6
23
PD5/CKOUT
PA3
7
22
PC0
PA2
8
21
PC1
PA1
9
20
PC2
PA0
10
19
PC3/AD3
SDO/PB5
11
18
PC4/AD2
SDI/PB6
12
17
PC5/AD1
SCK/PB7
13
16
PC6/AD0
VSS
14
15
PC7/VREFH
10
Figure 1-2. User Mode Pinout
11
12
1.4.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS. VDD is connected to a
regulated positive supply and VSS is connected to ground.
13
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, take special care to provide good power supply bypassing at the
MCU. Use bypass capacitors with good high-frequency characteristics, and
position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
14
A
16
17
18
19
20
INTRODUCTION
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GENERAL RELEASE SPECIFICATION
1.4.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip oscillator.
The OSC1 and OSC2 pins can accept the following:
1. A crystal as shown in Figure 1-3(a)
2. A ceramic resonator as shown in Figure 1-3(a)
8
2
3
Freescale Semiconductor, Inc...
3. An external clock signal as shown in Figure 1-3(b)
The frequency, fosc, of the oscillator or external clock source is divided by two to
produce the internal PH2 bus clock operating frequency, fop. The oscillator cannot
be turned off by software if the stop-to-halt conversion is enabled via mask option
register 1. Refer to 8.4 Mask Option Registers (MOR).
1.4.3 Crystal
4
5
6
7
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. Follow the crystal manufacturer’s recommendations, as the
crystal parameters determine the external component values required to provide
maximum stability and reliable startup. The load capacitance values used in the
oscillator circuit design should include all stray capacitances. Mount the crystal and
components as close as possible to the pins for startup stabilization and to
minimize output distortion.
Ceramic Resonator
8
9
10
11
In cost-sensitive applications, use a ceramic resonator instead of a crystal. Use
the circuit in Figure 1-3(a) for a ceramic resonator and follow the resonator
manufacturer’s recommendations, as the resonator parameters determine the
external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include
all stray capacitances. Mount the resonator and components as close as
possible to the pins for startup stabilization and to minimize output distortion.
12
13
14
A
External Clock
An external clock from another CMOS-compatible device can be connected to
the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b).
16
17
18
19
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GENERAL RELEASE SPECIFICATION
TO VDD (OR STOP)
8
MCU
TO VDD (OR STOP)
MCU
2
OSC1
3
OSC2
OSC1
OSC2
4.7 MΩ
UNCONNECTED
4
EXTERNAL CLOCK
5
Freescale Semiconductor, Inc...
37 pF
37 pF
6
7
8
9
(b)
External Clock Source
Connections
(a)
Crystal or Ceramic
Resonator Connections
Figure 1-3. Oscillator Connections
1.4.4 Reset (RESET)
10
Driving this input low will reset the MCU to a known startup state. As an output,
the RESET pin indicates that an internal MCU reset has occurred. The RESET pin
contains an internal Schmitt trigger to improve its noise immunity. Refer to
SECTION 5 RESETS.
11
12
1.4.5 Port A (PA0 through PA7)
13
These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during power-on or
reset. The pullups and interrupt options (active low) on the port A pins can be
individually programmed in the mask option register 2 (MOR2). For further
information, refer to SECTION 4 INTERRUPTS and SECTION 7 INPUT/OUTPUT
PORTS.
14
A
16
17
18
19
20
INTRODUCTION
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GENERAL RELEASE SPECIFICATION
1.4.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK)
These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software programmable and all
port B lines are configured as inputs during power-on or reset. For further
information, refer to SECTION 7 INPUT/OUTPUT PORTS and SECTION 11
SERIAL INPUT/OUTPUT PORT.
Freescale Semiconductor, Inc...
1.4.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH)
These eight I/O pins comprise port C and are shared with the A/D converter
subsystem. The state of any pin is software programmable and all port C lines are
configured as inputs during power-on or reset. Port pins PC0 and PC1 are capable
of sourcing and sinking high currents. For further information, refer to SECTION 7
INPUT/OUTPUT PORTS and SECTION 9 ANALOG-TO-DIGITAL CONVERTER.
8
2
3
4
5
6
7
1.4.8 Port D (PD5/CKOUT and PD7/TCAP)
These two I/O pins comprise port D, and one of them is shared with the 16-bit timer
subsystem. The state of PD5/CKOUT is software programmable and is configured
as an input during power-on or reset (unless clock output has been selected). PD7
is always an input; it may be read at any time, regardless of the mode of operation
the 16-bit timer may be in. For further information, refer to SECTION 7
INPUT/OUTPUT PORTS and SECTION 10 16-BIT TIMER. The PD5/CKOUT pin
can be turned into a clock output pin by programming mask option register 1. Clock
output is a buffered OSC2 signal with a CMOS output driver.
8
9
10
11
12
1.4.9 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after
reset. For further information, refer to SECTION 10 16-BIT TIMER.
1.4.10 Maskable Interrupt Request (IRQ)
This input pin drives the asynchronous interrupt function of the MCU. The MCU will
complete the current instruction being executed before it responds to the IRQ
interrupt request. When IRQ is driven low, the event is latched internally to signify
an interrupt has been requested. When the MCU completes its current instruction,
the interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit
(I bit) in the condition code register is clear, the MCU will begin the interrupt
sequence.
13
14
A
16
17
18
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GENERAL RELEASE SPECIFICATION
Depending on the programming option selected in the mask option register 1
(MOR1), the IRQ pin will trigger this interrupt on either a negative-going edge at
the IRQ pin and/or while the IRQ pin is held in the low state. In either case, the IRQ
pin must be held low for at least one tILIH time period. If the edge- and
level-sensitive edge is programmed in the MOR1,the IRQ input requires an
external resistor connected to VDD for wired-OR operation. If the IRQ pin is not
used, it must be tied to the VDD supply. The IRQ pin contains an internal Schmitt
trigger as part of its input circuitry to improve noise immunity. For further
information, refer to SECTION 4 INTERRUPTS.
8
2
3
4
5
Freescale Semiconductor, Inc...
NOTE
6
If the voltage level applied to the IRQ pin exceeds VDD, it may affect
the MCU’s mode of operation. See SECTION 6 OPERATING
MODES.
7
8
9
10
11
12
13
14
A
16
17
18
19
20
INTRODUCTION
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 2
MEMORY
4
2.1 Introduction
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3
The MC68HC805P18 utilizes 14 address lines to access an internal memory space
covering 16 Kbytes. This memory space is divided into I/O, RAM, EEPROM, and
boot ROM areas.
5
6
7
2.2 User Mode Memory Map
When the MC68HC805P18 is in the user mode, the 32 bytes of I/O, 192 bytes of
RAM, 128 bytes of EEPROM, 8000 bytes of program EEPROM, 48 bytes of user
page zero EEPROM, and 16 bytes of user vectors EEPROM are all active as
shown in Figure 2-1.
8
9
10
2.3 I/O and Control Registers
Figure 2-2 through Figure 2-4 briefly describe the I/O and control registers at
locations $0000–$001F. Reading unimplemented bits will return unknown states,
and writing unimplemented bits will be ignored.
11
12
13
2.4 RAM
The user RAM consists of 192 bytes (including the stack) at locations $0050
through $010F. The stack begins at address $00FF. The stack pointer can access
64 bytes of RAM from $00FF to $00C0.
14
NOTE
16
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking
from an interrupt or subroutine call.
A
17
18
19
20
MEMORY
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2.5 EEPROM
8
The EEPROM is located at address $0140 and consists of 128 bytes.
Programming the EEPROM can be done by the user on a single byte basis by
manipulating the programming register, located at address $001C. Refer to
SECTION 8 EEPROM for a discussion of the EEPROM.
2
3
4
2.6 User EEPROM
There are 8064 bytes of user EEPROM available, consisting of 8000 bytes at
locations $1FC0 through $3EFF, 48 bytes in page zero locations $0020 through
$004F, and 16 additional bytes for user vectors at locations $3FF0 through $3FFF.
Freescale Semiconductor, Inc...
5
6
This EEPROM can be programmed only in bootloader mode. Refer to 6.2.2
Bootloader Mode for more details.
7
8
9
10
11
12
13
14
A
16
17
18
19
20
MEMORY
2-2
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GENERAL RELEASE SPECIFICATION
$0000
$001F
$0020
$004F
$0050
$00BF
$00C0
$00FF
$010F
Freescale Semiconductor, Inc...
$013F
$0140
$01BF
$01C0
0000
I/O
32 BYTES
$0000
8
0031
0032
USER EEPROM
48 BYTES
I/O REGISTERS
SEE FIGURE 2-2
0079
0080
INTERNAL RAM
192 BYTES
STACK
64 BYTES
UNUSED
48 BYTES
EEPROM
128 BYTES
0191
0192
0255
0271
0272
0319
0320
$001F
UNUSED
7728 BYTES
8127
8128
USER EEPROM
8000 BYTES
$3EFF
$3F00
$3F01
$3F02
16127
MASK OPTION REGISTER
16128
16130
UNUSED
238 BYTES
$3FEF
$3FF0
$3FFF
16367
16368
USER VECTORS EEPROM
16 BYTES
3
4
0447
0448
$1FBF
$1FC0
2
16383
COP CONTROL REGISTER
$3FF0
UNIMPLEMENTED
$3FF1
UNIMPLEMENTED
$3FF2
UNIMPLEMENTED
$3FF3
UNIMPLEMENTED
$3FF4
UNIMPLEMENTED
$3FF5
UNIMPLEMENTED
$3FF6
UNIMPLEMENTED
$3FF7
TIMER VECTOR (HIGH BYTE)
$3FF8
TIMER VECTOR (LOW BYTE)
$3FF9
IRQ VECTOR (HIGH BYTE)
$3FFA
IRQ VECTOR (LOW BYTE)
$3FFB
SWI VECTOR (HIGH BYTE)
$3FFC
SWI VECTOR (LOW BYTE)
$3FFD
RESET VECTOR (HIGH BYTE)
$3FFE
RESET VECTOR (LOW BYTE)
$3FFF
Figure 2-1. MC68HC805P18 User Mode Memory Map
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
MEMORY
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
2
3
4
Freescale Semiconductor, Inc...
5
6
7
8
9
10
PORT A DATA REGISTER
$0000
PORT B DATA REGISTER
$0001
PORT C DATA REGISTER
$0002
PORT D DATA REGISTER
$0003
PORT A DATA DIRECTION REGISTER
$0004
PORT B DATA DIRECTION REGISTER
$0005
PORT C DATA DIRECTION REGISTER
$0006
PORT D DATA DIRECTION REGISTER
$0007
UNIMPLEMENTED
$0008
UNIMPLEMENTED
$0009
SIOP CONTROL REGISTER
$000A
SIOP STATUS REGISTER
$000B
SIOP DATA REGISTER
$000C
UNIMPLEMENTED
$000D
UNIMPLEMENTED
$000E
UNIMPLEMENTED
$000F
UNIMPLEMENTED
$0010
RESERVED
$0011
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
INPUT CAPTURE MOST SIGNIFICANT BIT
$0014
INPUT CAPTURE LEAST SIGNIFICANT BIT
$0015
OUTPUT COMPARE MOST SIGNIFICANT BIT
$0016
OUTPUT COMPARE LEAST SIGNIFICANT BIT
$0017
TIMER MOST SIGNIFICANT BIT
$0018
TIMER LEAST SIGNIFICANT BIT
$0019
ALTERNATE COUNTER MOST SIGNIFICANT BIT
$001A
ALTERNATE COUNTER LEAST SIGNIFICANT BIT
$001B
12
EEPROM PROGRAMMING REGISTER
$001C
A/D CONVERTER DATA REGISTER
$001D
13
A/D CONVERTER CONTROL AND STATUS REGISTER
$001E
RESERVED
$001F
11
14
Figure 2-2. MC68HC805P18 I/O and Control Registers Memory Map
A
16
17
18
19
20
MEMORY
2-4
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GENERAL RELEASE SPECIFICATION
ADDR
$0000
$0001
Freescale Semiconductor, Inc...
$0002
READ
WRITE
REGISTER
W
W
PORT C DATA
PORTC
W
R
$0004
$0008
$0009
4
3
2
1
0
8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
2
0
0
0
0
0
PB7
PB6
PB5
PC7
PC6
PC5
PD7
0
3
R
PORT A DATA DIRECTION
DDRA
$0007
5
R
PORT B DATA
PORTB
$0003
$0006
6
R
PORT A DATA
PORTA
PORT D DATA
PORTD
$0005
7
PORT C DATA DIRECTION
DDRC
PORT D DATA DIRECTION
DDRD
PC3
PC2
PC1
PC0
1
0
0
0
0
PD5
W
PORT B DATA DIRECTION
DDRB
PC4
5
R
W
DDRA7
DDRA6
DDRA5
DDRB7
DDRB6
DDRB5
DDRC7
DDRC6
DDRC5
0
0
R
W
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
1
1
1
1
1
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
R
W
R
DDRD5
W
W
R
UNIMPLEMENTED
$000B
$000C
$000D
$000E
SIOP CONTROL REGISTER
SCR
SIOP STATUS REGISTER
SSR
R
0
0
SPE
W
R
SPIF
0
0
0
0
0
0
0
0
MSTR
DCOL
0
0
W
UNIMPLEMENTED
R
SDR7
SDR6
SDR5
SDR4
SDR3
SDR2
SDR1
W
UNIMPLEMENTED
11
R
SDR0
13
14
R
W
$000F
8
12
W
SIOP DATA REGISTER
SDR
UNIMPLEMENTED
7
10
W
$000A
6
9
R
UNIMPLEMENTED
4
A
R
W
16
UNIMPLEMENTED
RESERVED
17
Figure 2-3. MC68HC805P18 I/O and Control Registers $0000–$000F
18
19
20
MEMORY
Rev. 1.0
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8
ADDR
2
$0010
3
$0011
4
$0012
Freescale Semiconductor, Inc...
5
4
3
2
1
0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
ICF
OCF
TOF
0
0
0
0
0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
OCRH7 OCRH6
OCRH5
OCRH4
OCRH3
OCRH2 OCRH1
OCRH0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
ER1
ER0
LATCH
EERC
EEPGM
AD4
AD3
AD2
AD1
AD0
0
0
CH2
CH1
CH0
W
R
TIMER CONTROL REGISTER
TCR
W
$0013
TIMER STATUS REGISTER
TSR
W
$0014
INPUT CAPTURE MSB
ICRH
$0015
INPUT CAPTURE LSB
ICRL
R
R
W
R
W
R
$0017
OUTPUT COMPARE LSB
OCRL
W
$0018
TIMER MSB
TMRH
W
10
$0019
TIMER LSB
TMRL
11
$001A
12
$001B
ALTERNATE COUNTER LSB
ACRL
13
$001C
EEPROM Programming
Register
W
$001D
A/D CONVERSION DATA
ADC
W
$001E
A/D STATUS AND CONTROL
ADSC
W
RESERVED
R
14
5
R
RESERVED
OUTPUT COMPARE MSB
OCRH
9
6
R
UNIMPLEMENTED
$0016
8
7
W
6
7
READ
WRITE
REGISTER
A
$001F
W
R
R
R
W
ALTERNATE COUNTER MSB
ACRH
R
W
R
W
R
R
R
0
AD7
0
CPEN
AD6
AD5
CC
ADON
W
16
UNIMPLEMENTED
17
RESERVED
Figure 2-4. MC68HC805P18 I/O and Control Registers $0010-$001F
18
19
20
MEMORY
2-6
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8
2
SECTION 3
CENTRAL PROCESSING UNIT
3
4
3.1 Introduction
5
Freescale Semiconductor, Inc...
This section describes the CPU registers.
6
3.2 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt stacking order are
shown in Figure 3-2.
7
8
7
0
A
7
9
INDEX REGISTER
10
PROGRAM COUNTER
11
STACK POINTER
12
0
X
12
0
PC
7
12
0
ACCUMULATOR
0
0
0
0
1
0
1
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
13
14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
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7
8
1
2
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
3
0
1
1
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
PCL
STACK
I
N
T
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
4
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
5
Freescale Semiconductor, Inc...
Figure 3-2. Stacking Order
6
3.2.1 Accumulator (A)
7
The accumulator is a general-purpose 8-bit register used to hold operands and
results of arithmetic calculations or data manipulations.
8
7
A
9
10
0
3.2.2 Index Register (X)
11
The index register is an 8-bit register used for the indexed addressing value to
create an effective address. The index register may also be used as a temporary
storage area.
12
7
13
0
X
14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT
3-2
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3.2.3 Condition Code Register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed, and the fifth bit indicates whether interrupts are masked.
These bits can be individually tested by a program, and specific actions can be
taken as a result of their state. Each bit is explained in the following paragraphs.
I
N
Z
C
Half Carry (H)
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2
3
CCR
H
8
4
5
This bit is set during ADD and ADC operations to indicate that a carry occurred
between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt are masked (disabled). If an
interrupt occurs while this bit is set, the interrupt is latched and processed as
soon as the interrupt bit is cleared.
6
7
8
9
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative.
Zero (Z)
10
11
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit
(ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions and during shifts and rotates.
12
13
14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
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3.2.4 Stack Pointer (SP)
8
The stack pointer contains the address of the next free location on the stack.
During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to location $00FF. The stack pointer is then decremented as data is pushed
onto the stack and incremented as data is pulled from the stack.
2
3
When accessing memory, the seven most significant bits are permanently set to
0000011. These seven bits are appended to the six least significant register bits to
produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the
stack pointer wraps around and loses the previously stored information. A
subroutine call occupies two locations on the stack; an interrupt uses five locations.
4
Freescale Semiconductor, Inc...
5
6
12
0
7
8
7
0
0
0
0
1
0
1
SP
3.2.5 Program Counter (PC)
9
The program counter is a 13-bit register that contains the address of the next byte
to be fetched.
10
12
0
PC
11
12
NOTE
13
The M68HC05 CPU core is capable of addressing a 64-Kbyte
memory map. For this implementation, however, the addressing
registers are limited to an 8-Kbyte memory map.
14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT
3-4
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8
2
SECTION 4
INTERRUPTS
4
4.1 Introduction
The MCU can be interrupted six different ways:
Freescale Semiconductor, Inc...
3
•
Non-maskable software interrupt instruction (SWI)
•
External asynchronous interrupt (IRQ)
•
Input capture interrupt (TIMER)
•
Output compare interrupt (TIMER)
•
Timer overflow interrupt (TIMER)
•
Port A interrupt (if selected via MOR2, bits 0 through 7).
Interrupts cause the processor to save the register contents on the stack and to set
the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is completed.
When the current instruction is completed, the processor checks all pending
hardware interrupts. If interrupts are not masked (I bit in the condition code register
is clear) and the corresponding interrupt enable bit is set, the processor proceeds
with interrupt processing. Otherwise, the next instruction is fetched and executed.
The SWI is executed the same as any other instruction, regardless of the I bit state.
When an interrupt is to be processed, the CPU puts the register contents on the
stack, sets the I bit in the CCR, and fetches the address of the corresponding
interrupt service routine from the vector table at locations $3FF0 through $3FFF. If
more than one interrupt is pending when the interrupt vector is fetched, the
interrupt with the highest vector location shown in Table 4-1 will be serviced first.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the CPU state to be recovered from the
stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occurs during interrupt processing.
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
INTERRUPTS
Rev. 1.0
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Table 4-1. Vector Addresses for Interrupts and Reset
8
2
3
4
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5
6
7
Register
Flag Name
Interrupts
CPU Interrupt
Vector Address
N/A
N/A
Reset
RESET
$3FF3–$3FFF
N/A
N/A
Software
SWI
$3FFC–$3FFD
N/A
N/A
External Interrupt
IRQ
$3FFA–$3FFB
TSR
ICF
Timer Input Capture
TIMER
$3FF8–$3FF9
TSR
OCF
Timer Output Compare
TIMER
$3FF8–$3FF9
TSR
TOF
Timer Overflow
TIMER
$3FF8–$3FF9
N/A
N/A
Unimplemented
N/A
$3FF6–$3FF7
N/A
N/A
Unimplemented
N/A
$3FF4–$3FF5
N/A
N/A
Unimplemented
N/A
$3FF2–$3FF3
N/A
N/A
Unimplemented
N/A
$3FF0–$3FF1
8
9
4.2 Interrupt Types
The interrupts fall into three categories: reset, software, and hardware.
10
4.2.1 Reset Interrupt Sequence
11
The reset function is not in the strictest sense an interrupt; however, it is acted upon
in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or
internally generated RST signal causes the program to vector to its starting
address which is specified by the contents of memory locations $3FFE and $3FFF.
The I bit in the condition code register is also set. The MCU is configured to a
known state during this type of reset as described in SECTION 5 RESETS.
12
13
14
A
4.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is
executed regardless of the state of the I bit in the CCR. As with any instruction,
interrupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address for the SWI instruction is
specified by the contents of memory locations $3FFC and $3FFD.
16
17
18
4.2.3 Hardware Interrupts
19
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all
hardware interrupts (internal and external) are disabled. Clearing the I bit enables
the hardware interrupts. Four hardware interrupts are explained in the following
paragraphs.
20
INTERRUPTS
4-2
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FROM RESET
Y
8
2
IS I BIT
SET?
3
N
IRQ
INTERRUPT?
Y
CLEAR IRQ
REQUEST
LATCH
4
N
TIMER
INTERRUPT?
Y
5
Freescale Semiconductor, Inc...
N
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $3FFC, $3FFD
IRQ: $3FFA-$3FFB
TIMER: $3FF8-$3FF9
6
7
8
9
10
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
11
12
Y
N
RTI
INSTRUCTION?
RESTORE RESISTERS
FROM STACK
CC, A, X, PC
Y
N
EXECUTE INSTRUCTION
13
14
A
Figure 4-1. Interrupt Processing Flowchart
16
17
External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector
flip-flop is latched on the falling edge of IRQ. If either the output from the internal
edge detector flip-flop or the level on the IRQ pin is low, a request is
synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive
only option is selected, the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ pin is ignored. If port A interrupts are
INTERRUPTS
Rev. 1.0
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18
19
20
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GENERAL RELEASE SPECIFICATION
programmed as an option, a port A interrupt will use the same vector. The
interrupt service routine address is specified by the contents of memory
locations $3FFA and $3FFB.
8
2
NOTE
3
The internal interrupt latch is cleared 9 PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore,
another external interrupt pulse could be latched during the IRQ
service routine.
4
Freescale Semiconductor, Inc...
5
6
7
NOTE
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
8
9
10
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 through PA7) to act as other IRQ interrupt sources. These
sources are all combined into a single ORing function to be latched by the IRQ
latch.
11
12
IRQ PIN
13
TO BIH & BIL
INSTRUCTION
SENSING
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
14
A
:
:
:
:
16
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
17
18
VDD
:
:
:
:
IRQ
LATCH
:
R
TO IRQ
PROCESSING
IN CPU
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
19
Figure 4-2. IRQ Function Block Diagram
20
INTERRUPTS
4-4
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Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the
IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only
sensitivity is chosen by a mask option, only the IRQ latch output can activate a
request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ
interrupt sensitive to the following cases:
8
2
1.
Falling edge on the IRQ pin with all enabled port A interrupt pins at a high
level.
3
2.
Falling edge on any enabled port A interrupt pin with all other enabled
port A interrupt pins and the IRQ pin at a high level.
4
If level sensitivity is chosen, the active high state of the IRQ input can also
activate an IRQ request to the CPU to generate the IRQ interrupt sequence.
This makes the IRQ interrupt sensitive to the following cases:
5
6
1.
Low level on the IRQ pin
2.
Falling edge on the IRQ pin with all enabled port A interrupt pins at a high
level
3.
Low level on any enabled port A interrupt pin
8
4.
Falling edge on any enabled port A interrupt pin with all enabled port A
interrupt pins and the IRQ pin at a high level
9
This interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically
cleared by entering the interrupt service routine.
7
10
11
Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port
pins if enabled by individual mask options. With pullup enabled, each port A pin
can activate the IRQ interrupt function and the interrupt operation will be the
same as for inputs to the IRQ pin. Once enabled by mask option, each individual
port A pin can be disabled as an interrupt source if its corresponding DDR bit is
configured for output mode.
12
13
14
A
NOTE
16
The BIH and BIL instructions apply to the output of the logic OR
function of the enabled PA0 through PA7 interrupt pins and the IRQ
pin. The BIH and BIL instructions do not test only the state of the IRQ
pin.
17
18
19
20
INTERRUPTS
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8
NOTE
2
If enabled, the PA0 through PA7 pins will cause an IRQ interrupt only
if these individual pins are configured as inputs.
3
Input Capture Interrupt
4
The input capture interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The input capture interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the input capture interrupt to be
enabled. The interrupt service routine address is specified by the contents of
memory locations $3FF8 and $3FF9.
Freescale Semiconductor, Inc...
5
6
7
Output Compare Interrupt
8
The output compare interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The output compare interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the output compare interrupt to be
enabled. The interrupt service routine address is specified by the contents of
memory locations $3FF8 and $3FF9.
9
10
11
Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The timer overflow interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the timer overflow interrupt to be
enabled. This internal interrupt will vector to the interrupt service routine located
at the address specified by the contents of memory locations $3FF8 and $3FF9.
12
13
14
A
16
17
18
19
20
INTERRUPTS
4-6
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 5
RESETS
3
4
Freescale Semiconductor, Inc...
5.1 Introduction
The MCU can be reset from four sources: one external input and three internal
reset conditions. The RESET pin is an input with a Schmitt trigger as shown in
Figure 5-1. The CPU and all peripheral modules will be reset by the RST signal
which is the logical OR of internal reset functions and is clocked by PH2.
5
6
7
5.2 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt
trigger. The external reset occurs whenever the RESET input is driven below the
lower threshold and remains in reset until the RESET pin rises above the upper
threshold. The upper and lower thresholds are given in SECTION 13
ELECTRICAL SPECIFICATIONS.
TO IRQ
LOGIC
IRQ
D
LATCH
MODE
SELECT
RESET
8
9
10
11
12
13
R
(PULSE WIDTH =4 x E-CLK)
PH2
14
CLOCKED
ONE-SHOT
A
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
VDD
LOW-VOLTAGE
RESET (LVR)
VDD
POWER-ON RESET
(POR)
16
CPU
S
D
LATCH
RST
PH2
Figure 5-1. Reset Block Diagram
TO OTHER
PERIPHERALS
17
18
19
20
RESETS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
5.3 Internal Resets
8
The three internally generated resets are the initial power-on reset (POR), the COP
watchdog timer, and low-voltage reset (LVR) functions.
2
3
5.3.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator to stabilize.
The POR is strictly for power turn-on conditions and should not be used to detect
a drop in the power supply voltage. There is a 4064 PH2 clock cycle oscillator
stabilization delay after the oscillator becomes active.
4
Freescale Semiconductor, Inc...
5
The POR will generate the RST signal and reset the MCU. The POR will also pull
the RESET pin low at the same time, allowing external devices to be reset with the
MCU. If any other reset function is active at the end of this 4064 PH2 clock cycle
delay, the RST signal will remain active until the other reset condition(s) end.
6
7
8
5.3.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (by MOR1, bit 0), the internal COP reset
is generated automatically by a timeout of the COP watchdog timer. This timer is
implemented with an 18-stage ripple counter that provides a time-out period of
65.5 ms when a 4-MHz oscillator is used. The COP watchdog counter is cleared
by writing a logical zero to bit zero at location $3FF0.
9
10
11
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading this location
will return the MSB of the unimplemented user interrupt vector. Writing to this
location will clear the COP watchdog timer.
12
13
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
R
Reset:
—
14
$3FF0
A
16
COPR
—
—
= Unimplemented
—
—
R
—
—
—
= Reserved
Figure 5-2. Unimplemented Vector and
COP Watchdog Timer Register
17
18
19
20
RESETS
5-2
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GENERAL RELEASE SPECIFICATION
5.3.3 Low-Voltage Reset (LVR)
Freescale Semiconductor, Inc...
If the LVR has been enabled via MOR1, the internal LVR reset is generated when
the supply voltage to the VDD pin falls below a nominal 3.80 Vdc. The LVR
threshold is not intended to be an accurate and stable trip point, but is intended to
ensure that the CPU will be held in reset when the VDD supply voltage is below
reasonable operating limits. If the LVR is tripped for a short time, the LVR reset
signal will last at least two cycles of the CPU bus clock, PH2.
The LVR will generate the RST signal which will reset the CPU and other
peripherals. Also, the LVR will establish the mode of operation based on the state
of the IRQ pin at the time the LVR signal ends. If any other reset function is active
at the end of the LVR reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end.
NOTE
The voltage of the IRQ pin must be between 0–VDD volts to stay in
the normal operation mode.
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
RESETS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 6
OPERATING MODES
3
4
Freescale Semiconductor, Inc...
6.1 Introduction
This section describes the user, bootloader, and low-power modes. In addition the
computer operating properly (COP) timer considerations are discussed.
6.2 User Modes
5
6
7
The MC68HC805P18 has two modes of operation available to the user:
8
•
User mode
•
Bootloader mode
9
The mode of operation is determined by the voltages on the IRQ and PD7/TCAP
pins on the rising edge of the external RESET pin. Table 6-1 shows the condition
required to go into each mode.
10
Table 6-1. Operating Mode Conditions
11
RESET
IRQ
TCAP
Mode
0–5 V
0–5 V
User
2 x VDD
5V
Bootloader
12
13
14
6.2.1 User Mode
The user mode allows the MCU to function as a self-contained microcontroller with
maximum use of the pins for on-chip peripheral functions. All address and data
activity occurs within the MCU and is not available externally. User mode is entered
on the rising edge of RESET, if the IRQ pin is within the normal operating voltage
range. In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared
with the analog-to-digital (A/D) subsystem, one 3-bit I/O port shared with the serial
input/output port (SIOP), and a 2-bit I/O port shared with the16-bit timer
subsystem.
A
16
17
18
19
20
OPERATING MODES
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
6.2.2 Bootloader Mode
8
Bootloader mode is entered upon the rising edge of RESET if the IRQ pin is twice
the VDD voltage and the TCAP/PD7 pin is at logic one. In bootloader mode, the
user EEPROM and mask option register (MOR) bytes can be erased and
programmed. Figure 6-1 shows the bootloader circuit. PTC4 determines whether
erasing or programming will occur as shown in Table 6-2.
2
3
4
Table 6-2. Bootloader Functions
5
Freescale Semiconductor, Inc...
PTC4
6
7
Function
0
Bulk Erase/Blank Verify
1
Bulk Erase/Program/Verify
Bulk Erase/Blank Verify
8
To use the bootloader circuit to bulk erase the user EEPROM, follow this
sequence:
9
10
11
12
13
1.
Close RESET switch and PTC4 switch so these pins are held low.
2.
Apply 12 V power to IRQ.
3.
Release RESET.
4.
Programming LED will turn on while bulk erase is occurring.
5.
When bulk erase is finished, programming LED will turn off.
6.
When blank verify is finished, verify LED will turn on.
7.
Close RESET switch.
8.
Remove 12 V from IRQ, then remove power.
14
A
16
17
18
19
20
OPERATING MODES
6-2
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GENERAL RELEASE SPECIFICATION
12 V
27C128
MC14040B
1 KΩ
IRQ
OSC1
PA0
DQ1
A11
Q12
PA1
DQ2
A10
Q11
PA2
DQ3
A9
Q10
PA3
DQ4
A8
Q9
PA4
DQ5
A7
Q8
PA5
DQ6
A6
Q7
PA6
DQ7
A5
Q6
PA7
DQ8
A4
Q5
CE
A3
Q4
OE
A2
Q3
A1
Q2
A0
Q1
8
2
4 MHz
3
OSC2
10 MΩ
Freescale Semiconductor, Inc...
20 pF
20 pF
VDD
10 KΩ
RESET
PC6
PC7
1 µF
A12
A13
5
6
7
8
RST
PC5 (SYNC)
VDD
4
VDD
4.7 KΩ
CLK
9
10
4.7 KΩ
PROG
390 Ω
11
TCAP
PB7
PC1
12
PC2
VDD
VERF
PB6
10 KΩ
390 Ω
13
PC4
14
VDD = 5.0 V
PC3
4.7 KΩ
A
16
17
Figure 6-1. Bootloader Circuit
18
19
20
OPERATING MODES
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
Bulk Erase/Program Verify
8
To use the bootloader circuit to bulk erase, program, and verify the user
EEPROM, follow this sequence:
2
1.
Close RESET switch so RESET is low upon power up.
2.
Open PTC4 switch so PTC4 remains high during reset sequence.
3.
Make sure code to be loaded into user EEPROM is in the external
EPROM (shown as 27C128).
4.
Apply 12 V power to IRQ.
5.
Release RESET.
6
6.
Programming LED will be on during bulk erase and programming. (The
code in the 27C128 will be loaded into the user EEPROM and MOR.)
7
7.
When programming is finished, the programming LED will turn off.
8.
When the verify is finished, verify LED will turn on.
9.
Close RESET switch.
3
4
Freescale Semiconductor, Inc...
5
8
10.
9
10
Remove 12 V from IRQ, then remove power.
NOTE
Bootloader mode is the only mode in which the user can program the
8K user EEPROM and MOR. The 128-byte EEPROM can be
programmed in user mode.
11
12
13
14
A
16
17
18
19
20
OPERATING MODES
6-4
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GENERAL RELEASE SPECIFICATION
6.3 Low-Power Modes
The MC68HC805P18 is capable of running in a low-power mode in each of its
configurations. The WAIT and STOP instructions provide modes that reduce the
power required for the MCU by stopping various internal clocks and/or the on-chip
oscillator. The STOP and WAIT instructions are not normally used if the COP
watchdog timer is enabled (MOR1, bit 0). The stop conversion to halt option
(MOR1, bit 5) is used to modify the behavior of the STOP instruction from stop
mode to halt mode. The flow of the stop, halt, and wait modes is shown in
Figure 6-2.
2
3
4
5
6.4 STOP Instruction
Freescale Semiconductor, Inc...
8
The STOP instruction can result in one of two modes of operation depending on
the option programmed in the mask option register 1. If the stop conversion to halt
option (MOR1,bit 5) is not chosen, the STOP instruction will behave like a normal
STOP instruction in the M68HC805 Family and place the MCU in the stop mode.
If the stop conversion to halt option is chosen, the STOP instruction will behave like
a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in the halt mode.
6.4.1 Stop Mode
6
7
8
9
10
Execution of the STOP instruction (without conversion to halt) places the MCU in
its lowest-power consumption mode. In the stop mode, the internal oscillator is
turned off stopping all internal processing including the COP watchdog timer. The
RC oscillator that feeds the EEPROM and the A/D converter is also stopped.
Execution of the STOP instruction automatically clears the I bit in the condition
code register so that the IRQ external interrupt is enabled. All other registers and
memory remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of the stop mode only by an IRQ external interrupt
(or port A, if selected as an option in the MOR2) or an externally generated reset.
When exiting the stop mode, the internal oscillator will resume after a 4064 PH2
clock cycle oscillator stabilization delay.
11
12
13
14
A
16
17
18
19
20
OPERATING MODES
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
STOP
2
STOP
TO HALT
OPTION?
3
N
4
Freescale Semiconductor, Inc...
5
6
HALT
WAIT
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET START-UP DELAY
STOP RC OSCILLATOR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I-BIT IN CCR
STOP RC OSCILLATOR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I BIT IN CCR
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
LVR OR
EXTERNAL
RESET?
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I BIT IN CCR
Y
N
LVR OR
EXTERNAL
RESET?
7
8
Y
Y
N
IRQ
EXTERNAL
INTERRUPT?
9
N
10
Y
Y
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
END
OF STABILIZATION
DELAY?
TIMER
INTERNAL
INTERRUPT?
Y
COP
INTERNAL
RESET?
1.
2.
A
16
IRQ
EXTERNAL
INTERRUPT?
N
Y
TIMER
INTERNAL
INTERRUPT?
N
Y
RESTART INTERNAL
PROCESSOR CLOCK
14
Y
N
N
LVR OR
EXTERNAL
RESET?
N
N
11
13
Y
N
Y
12
IRQ
EXTERNAL
INTERRUPT?
COP
INTERNAL
RESET?
N
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 6-2. STOP/WAIT Flowcharts
17
18
19
20
OPERATING MODES
6-6
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GENERAL RELEASE SPECIFICATION
NOTE
Execution of the STOP instruction without conversion to halt (via
MOR1) will cause the oscillator to stop, and therefore disable the
COP watchdog timer. If the COP watchdog timer is to be used, the
stop mode should be changed to the halt mode by programming the
appropriate option in MOR1.
8
2
3
4
5
Freescale Semiconductor, Inc...
6.4.2 Halt Mode
Execution of the STOP instruction with the conversion to halt places the MCU in
this low-power mode. Halt mode consumes the same amount of power as wait
mode (both halt and wait modes consume more power than stop mode).
In halt mode the PH2 clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be generated
from the 16-bit timer or a reset to be generated from the COP watchdog timer.
Execution of the STOP instruction automatically clears the I bit in the condition
code register enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt
mode and resume normal operation. The halt mode also can be exited when an
IRQ external interrupt (or port A, if selected as an option in the MOR2) or external
RESET occurs. When exiting the halt mode, the PH2 clock will resume after a
delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the
halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of
the stop mode), which has been free-running (a feature of the wait mode).
6
7
8
9
10
11
12
13
14
NOTE
The halt mode is not intended for normal use. This feature is provided
to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently.
A
16
17
18
19
20
OPERATING MODES
Rev. 1.0
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6.4.3 WAIT Instruction
8
The WAIT instruction places the MCU in a low-power mode which consumes more
power than the stop mode. In wait mode the PH2 clock is halted, suspending all
processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer and reset to be generated from the
COP watchdog timer. Execution of the WAIT instruction automatically clears the I
bit in the condition code register enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
2
3
4
If the 16-bit timer interrupt is enabled it will cause the processor to exit the wait
mode and resume normal operation. The 16-bit timer may be used to generate a
periodic exit from the wait mode. The wait mode may also be exited when an IRQ
or RESET occurs. Note that if port A interrupts (if programmed as an option in the
mask option register 1) will also exit wait mode. However, when exiting the wait
mode, the internal oscillator will not need to wait for 4064 PH2 clock cycles to
stabilize as in the stop and halt modes.
Freescale Semiconductor, Inc...
5
6
7
8
6.5 COP Watchdog Timer Considerations
9
The COP watchdog timer is active in user mode of operation when programmed
as an option in MOR1. Executing the STOP instruction without conversion to halt
(via mask option register1) will cause the COP to be disabled. Therefore, it is
recommended that the STOP instruction be modified to produce halt mode (via
MOR1) if the COP watchdog timer will be enabled.
10
11
Furthermore, it is recommended that the COP watchdog timer be disabled for
applications that will use the halt or wait modes for time periods that will exceed the
COP time-out period.
12
13
COP watchdog timer interactions are summarized in Table 6-3.
14
Table 6-3. COP Watchdog Timer Recommendations
A
IF the following conditions exist:
16
17
18
19
STOP Instruction Mode
Wait Period
THEN the COP Watchdog
Timer should be:
Halt Mode Selected
via MOR1, Bit 5
WAIT Period Less than
COP Time Out
Enable or Disable COP
via MOR1, Bit 0
Halt Mode Selected
via MOR1, Bit 5
WAIT Period More Than
COP Time Out
Disable COP
via MOR1, Bit 0
Stop Mode Selected
via MOR1, Bit 5
Any Length Wait Period
Disable COP
via MOR1, Bit 0
20
OPERATING MODES
6-8
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 7
INPUT/OUTPUT PORTS
3
4
Freescale Semiconductor, Inc...
7.1 Introduction
In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D).
These ports are programmable as either inputs or outputs under software control
of the data direction registers (DDRs). An input-only pin is associated with port D.
5
6
7
7.2 Port A
Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt
system as shown in Figure 7-1. Each port A pin is controlled by the corresponding
bits in a data direction register and a data register. The port A data register is
located at address $0000. The port A data direction register (DDRA) is located at
address $0004. Reset clears the DDRA, thereby initializing port A as an input port.
The port A data register is unaffected by reset.
8
9
10
11
VDD
MOR 2
(PULLUP INHIBIT)
12
READ $0004
13
WRITE $0004
DATA DIRECTION
REGISTER BIT
WRITE $0000
DATA
REGISTER BIT
OUTPUT
I/O
PIN
A
READ $0000
INTERNAL HC05
DATA BUS
14
100 µA
PULLUP
16
17
RESET
(RST)
TO IRQ INTERRUPT
SYSTEM
Figure 7-1. Port A I/O Circuitry
18
19
20
INPUT/OUTPUT PORTS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
7.3 Port B
8
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP
communications subsystem. The port B data register is located at address $0001
and its data direction register (DDR) is located at address $0005. Reset does not
affect the data registers, but clears the DDRs, thereby setting all of the port pins to
input mode. Writing a logic one to a DDR bit sets the corresponding port pin to
output mode (see Figure 7-2).
2
3
4
Port B may be used for general I/O applications when the SIOP subsystem is
disabled. The SPE bit in register SPCR is used to enable/disable the SIOP
subsystem. When the SIOP subsystem is enabled, port B registers are still
accessible to software. Writing to either of the port B registers while a data transfer
is under way could corrupt the data. See SECTION 11 SERIAL INPUT/OUTPUT
PORT for a discussion of the SIOP subsystem.
Freescale Semiconductor, Inc...
5
6
7
READ $0005
8
WRITE $0005
9
WRITE $0001
10
READ $0001
11
RESET
(RST)
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
INTERNAL HC05
DATA BUS
12
Figure 7-2. Port B I/O Circuitry
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
7-2
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GENERAL RELEASE SPECIFICATION
7.4 Port C
Freescale Semiconductor, Inc...
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D
subsystem. The port C data register is located at address $0002 and its data
direction register (DDR) is located at address $0006. Reset does not affect the
data registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a logic one to a DDR bit sets the corresponding port pin to output
mode (see Figure 7-3). Two port C pins, PC0 and PC1, can source and sink a
higher current than a typical I/O pin. See SECTION 13 ELECTRICAL
SPECIFICATIONS regarding current specifications.
Port C may be used for general I/O applications when the A/D subsystem is
disabled. The ADON bit in register ADSC is used to enable/disable the A/D
subsystem. Care must be exercised when using pins PC0–PC2 while the A/D
subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in the
data or DDR registers will produce unpredictable results in the A/D subsystem. See
SECTION 9 ANALOG-TO-DIGITAL CONVERTER.
8
2
3
4
5
6
7
8
READ $0006
WRITE $0006
WRITE $0002
RESET
(RST)
HIGH CURRENT
CAPABILITY, PC0
AND PC1 ONLY
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
9
10
11
READ $0002
INTERNAL HC05
DATA BUS
12
Figure 7-3. Port C I/O Circuitry
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
7.5 Port D
8
Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be replaced with a
buffered OSC2 clock output via MOR1. The port D data register is located at
address $0003 and its data direction register (DDR) is located at address $0007.
Reset does not affect the data registers, but clears the DDRs, thereby setting
PD5/CKOUT to input mode. Writing a one to DDR bit 5 sets PD5/CKOUT to output
mode (see Figure 7-4).
2
3
4
Port D may be used for general I/O applications regardless of the state of the 16-bit
timer. Since PD7 is an input-only line, its state can be read from the port D data
register at any time.
Freescale Semiconductor, Inc...
5
6
READ $0007
7
WRITE $0007
8
WRITE $0003
9
READ $0003
10
RESET
(RST)
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
INTERNAL HC05
DATA BUS
11
Figure 7-4. Port D I/O Circuitry
12
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
7-4
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GENERAL RELEASE SPECIFICATION
7.6 I/O Port Programming
Each pin on ports A through port D (except pin 7 of port D) may be programmed
as an input or an output under software control as shown in Table 7-1, Table 7-2,
Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its
corresponding bit in the associated port data direction register (DDR). A pin is
configured as an output if its corresponding DDR bit is set to a logic one. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic zero.
8
2
3
4
Freescale Semiconductor, Inc...
Table 7-1. Port A I/O Functions
DDRA
I/O Pin Mode
5
Access to DDRA
@ $0004
Access to Data
Register @ $0000
Read/Write
Read
Write
0
Input, High Impedance
DDRA0–DDRA7
I/O Pin
*
1
Output
DDRA0–DDRA7
PA0–PA7
PA0–PA7
*Does not affect input, but stored to data register
6
7
8
9
10
Table 7-2. Port B I/O Functions
DDRB
I/O Pin Mode
Access to DDRA
@ $0005
Access to Data
Register @ $0001
Read/Write
Read
Write
0
Input, High Impedance
DDRB5–DDRB7
I/O Pin
*
1
Output
DDRB5–DDRB7
PB5–PB7
PB5–PB7
*Does not affect input, but stored to data register
11
12
13
14
A
Table 7-3. Port C I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
0
Input, High Impedance
DDRC0–DDRC7
I/O Pin
*
1
Output
DDRC0–DDRC7
PC0–PC7
PC0–PC7
*Does not affect input, but stored to data register
16
17
18
19
20
INPUT/OUTPUT PORTS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
Table 7-4. Port D I/O Functions
8
2
DDRA
3
0
1
4
I/O Pin Mode
Access to DDRA
@ $0007
Accesses to Data
Register @ $0003
Read/Write
Read
Write
Input, High Impedance
DDRD5
I/O Pin
*
Output
DDRD5
PD5/CKOUT
PD5/CKOUT
*Does not affect input, but stored to data register
**PD7 is input-only
Freescale Semiconductor, Inc...
5
6
NOTE
To avoid generating a glitch on an I/O port pin, data should be written
to the I/O port data register before writing a logical one to the
corresponding data direction register.
7
8
9
10
11
12
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
7-6
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 8
EEPROM
3
4
Freescale Semiconductor, Inc...
8.1 Introduction
This section describes the EEPROM which is located at address $0140 and
consists of 128 bytes. Programming the EEPROM can be done by the user on a
single byte basis by manipulating the programming register located at address
$001C.
Also, the mask option register (MOR), which consists of two additional EEPROM
bytes, is discussed.
8.2 EEPROM Programming Register (EEPROG)
5
6
7
8
9
The contents and use of the programming register are discussed here.
10
Bit 7
EEPROG
$001C
Read:
6
5
0
4
3
2
1
Bit 0
ER1
ER0
LATCH
EERC
EEPGM
0
0
0
0
0
0
CPEN
Write:
Reset:
11
12
0
0
0
= Unimplemented
Figure 8-1. EEPROM Programming Register
CPEN — Charge Pump Enable
When set, CPEN enables the charge pump which produces the internal
EEPROM programming voltage. This bit should be set concurrently with the
LATCH bit. The programming voltage will not be available until EEPGM is set.
The charge pump should be disabled when not in use. CPEN is readable and
writable and is cleared by reset.
ER1 and ER0 — Erase Select Bits
ER1 and ER0 form a 2-bit field which is used to select one of three erase modes:
byte, block, or bulk. Table 8-1 shows the modes selected for each bit
configuration. These bits are readable and writable and are cleared by reset.
13
14
A
16
17
18
19
20
EEPROM
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
In byte erase mode, only the selected byte is erased. In block mode, a 32-byte
block of EEPROM is erased. The EEPROM memory space is divided into four
32-byte blocks ($140–$15F, $160–$17F, $180–$19F, $1A0–$1BF), and doing
a block erase to any address within a block will erase the entire block. In bulk
erase mode, the entire 128-byte EEPROM section is erased.
8
2
3
Table 8-1. Erase Mode Select
4
ER1
ER0
Mode
0
0
Program (no Erase)
0
1
Byte Erase
1
0
Block Erase
1
1
Bulk Erase
Freescale Semiconductor, Inc...
5
6
7
LATCH — Latch Bit
8
10
When set, LATCH configures the EEPROM address and data bus for
programming. Writes to the EEPROM array cause the data bus and the address
bus to be latched. This bit is readable and writable, but reads from the array are
inhibited if the LATCH bit is set and a write to the EEPROM space has taken
place.
11
When clear, address and data buses are configured for normal operation. Reset
clears this bit.
9
12
EERC — EEPROM RC Oscillator Control
When this bit is set, the EEPROM section uses the internal RC oscillator instead
of the CPU clock. The RC oscillator is shared with the A/D converter, so this bit
should be set by the user when the internal bus frequency is below 1.5 MHz to
guarantee reliable operation of the EEPROM or A/D converter. After setting the
EERC bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit is
readable and writable. The EERC bit is cleared by reset. The RC oscillator is
disabled while the MCU is in stop mode.
13
14
A
16
EEPGM — EEPROM Programming Power Enable
EEPGM must be written to enable (or disable) the EEPGM function. When set,
EEPGM turns on the charge pump and enables the programming (or erasing)
power to the EEPROM array. When clear, this power is switched off. This will
enable pulsing of the programming voltage to be controlled internally. This bit
can be read at any time, but can only be written to if LATCH = 1. If LATCH is not
set, then EEPGM cannot be set. LATCH and EEPGM cannot both be set with
one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is
cleared. Reset clears this bit.
17
18
19
20
EEPROM
8-2
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GENERAL RELEASE SPECIFICATION
8.3 Programming/Erasing Procedures
To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write
data to the desired address and then set EEPGM for a time, tEPGM.
NOTE
Freescale Semiconductor, Inc...
Any bit should be erased before it is programmed. However, if
write/erase cycling is a concern, the following procedure will
minimize the cycling of each bit in each EEPROM byte.
If PB • EB = 0, then program the new data over the existing data
without erasing it first. If PB • EB ≠ 0, then erase the byte before
programming where PB = byte data to be programmed and
EB = existing EEPROM byte data.
8
2
3
4
5
6
7
8
To erase a byte of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 0 and ER0 = 1,
write to the address to be erased and set EEPGM for a time, tEBYT.
9
To erase a block of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 1 and ER0 = 0,
write to any address in the block, and set EEPGM for a time, tEBLOCK.
10
For a bulk erase, set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any
address in the array, and set EEPGM for a time, tEBULK.
11
To terminate the programming or erase sequence, clear EEPGM, delay for a time
tFPV to allow the program voltage to fall, and then clear LATCH and CPEN to free
up the buses. Following each erase or programming sequence, clear all
programming control bits.
12
13
14
NOTE
Erased/programmed state of the programming EEPROM (128 bytes)
and the user EEPROM (8064 bytes) is opposite. An erased
EEPROM memory location is a logic zero for user EEPROM, while it
is a logic one for programming EEPROM.
A
16
17
18
19
20
EEPROM
Rev. 1.0
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8.4 Mask Option Registers (MOR)
8
The MOR consists of two EEPROM bytes located at $3F00 and $3F01. The MOR
holds the 16 option bits for:
2
3
4
Freescale Semiconductor, Inc...
5
6
•
The SIOP data format, interrupt sensitivity
•
COP enable/disable
•
SIOP clock rate
•
LVR enable/disable
•
Stop conversion to halt, pullup/interrupt enable on port A
•
Clock output option to replace PD5
When in the erased state, the EEPROM cells will read as logic zeros. These
registers are refreshed every 256 µs during power-on reset and every 16 ms after
the part is out of reset (assuming fOSC = 4 MHz).
7
8
9
MOR1
$3F00
10
Read:
Bit 7
6
5
4
3
2
1
0
CLKOUT
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ
COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
11
Figure 8-2. Mask Option Register 1
12
13
MOR2
$3F01
14
Read:
Bit 7
6
5
4
3
2
1
0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Reset:
A
Unaffected by reset
= Unimplemented
Figure 8-3. Mask Option Register 2
16
COPEN — COP enable/disable
17
COPEN may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The COP is disabled (erased state).
1 = The COP is enabled.
18
19
20
EEPROM
8-4
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LEVIRQ — Interrupt request option
LEVIRQ may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state).
1 = The IRQ pin is edge- and level-sensitive.
2
3
LSBF — SIOP MSB or LSB first
LSBF may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first.
Freescale Semiconductor, Inc...
8
4
5
6
SPR1 and SPR0 — SIOP Rate Select Bits
These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode.
Table 8-2. SIOP Clock Rate Selection
SPR1
SPR0
Frequency
0
0
fOSC divided by 16
0
1
fOSC divided by 8
1
0
fOSC divided by 4
1
1
fOSC divided by 2
7
8
9
10
11
12
SWAIT — STOP conversion to WAIT
SWAIT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode.
1 = STOP instruction puts MCU in halt mode.
13
14
A
LVRE — LVR enable/disable
LVRE may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
0 = The LVR is disabled (erased state).
1 = The LVR is enabled.
CLKOUT — CLKOUT enable/disable
CLKOUT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The CLKOUT is disabled (erased state).
1 = The CLKOUT is enabled.
EEPROM
Rev. 1.0
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16
17
18
19
20
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GENERAL RELEASE SPECIFICATION
PA7PU through PA0PU — Port A pullups/interrupt enable/disable
8
These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode.
0 = Port A (bits 0 through 7) pullups/interrupt is disabled (erased state).
1 = Port A (bits 0 through 7) pullups/interrupt is enabled.
2
3
4
Freescale Semiconductor, Inc...
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
EEPROM
8-6
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8
2
SECTION 9
ANALOG-TO-DIGITAL CONVERTER
4
9.1 Introduction
Freescale Semiconductor, Inc...
3
The MC68HC805P18 includes a 4-channel, multiplexed input, 8-bit successive
approximation analog-to-digital (A/D) converter. The A/D subsystem shares its
inputs with port C pins PC3 through PC7.
5
6
7
9.2 Analog Section
The following paragraphs describe the operation and performance of analog
modules within the analog subsystem.
9.2.1 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH supplying the high reference
voltage. Applying an input voltage equal to VREFH produces a conversion result of
$FF (full scale). Applying an input voltage equal to VSS produces a conversion
result of $00. An input voltage greater than VREFH will convert to $FF with no
overflow indication. For ratiometric conversions, VREFH should be at the same
potential as the supply voltage being used by the analog signal being measured
and referenced to VSS.
9.2.2 VREFH
8
9
10
11
12
13
14
The reference supply for the A/D converter shares pin PC7 with port C. The low
reference is tied to the VSS pin internally. VREFH can be any voltage between VSS
and VDD; however, the accuracy of conversions is tested and guaranteed only for
VREFH = VDD.
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.2.3 Accuracy and Precision
8
The 8-bit conversion result is accurate to within ± 1 1/2 LSB, including quantization;
however, the accuracy of conversions is tested and guaranteed only with external
oscillator operation.
2
3
9.2.4 Conversion Process
4
The A/D reference inputs are applied to a precision digital-to-analog converter.
Control logic drives the D/A and the analog output is successively compared to the
selected analog input which was sampled at the beginning of the conversion cycle.
The conversion process is monotonic and has no missing codes.
Freescale Semiconductor, Inc...
5
6
9.3 Digital Section
7
The following paragraphs describe the operation and performance of digital
modules within the analog subsystem.
8
9
9.3.1 Conversion Times
Each input conversion requires 32 PH2 clock cycles, which must be at a frequency
equal to or greater than 1 MHz.
10
11
9.3.2 Internal versus External Oscillator
If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external oscillator), the
internal RC oscillator (approximately 1.5 MHz) must be used for the A/D converter
clock. The internal RC clock is selected by setting the EERC bit in the EEPROG
register.
12
13
14
NOTE
A
The RC oscillator is shared with the EEPROM module. The RC
oscillator is disabled while the MCU is in stop mode.
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
9-2
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When the internal RC oscillator is being used, these limitations apply:
1. Since the internal RC oscillator is running asynchronously with respect to the
PH2 clock, the conversion complete bit (CC) in the A/D status and control
register must be used to determine when a conversion sequence has been
completed.
8
2. Electrical noise will slightly degrade the accuracy of the A/D converter. The
A/D converter is synchronized to read voltages during the quiet period of the
clock driving it. Since the internal and external clocks are not synchronized
the A/D converter occasionally will measure an input when the external clock
is making a transition.
3
3. If the PH2 clock is 1 MHz or greater (for instance, external oscillator 2 MHz
or greater), the internal RC oscillator should be turned off and the external
oscillator used as the conversion clock.
9.3.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four external
analog signals. Port C pins PC3 through PC6 are shared with the inputs to the
multiplexer.
2
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.4 A/D Status and Control Register (ADSC)
8
The ADSC register reports the completion of A/D conversion and provides control
over oscillator selection, analog subsystem power, and input channel selection.
See Figure 9-1.
2
3
Bit 7
4
ADSC
$001E
5
Read:
6
5
R
ADON
0
0
CC
0
= Unimplemented
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3
0
0
2
1
Bit 0
CH2
CH1
CH0
0
0
0
Write:
Reset:
6
4
0
R
0
= Reserved
Figure 9-1. A/D Status and Control Register
7
CC — Conversion Complete
8
This read-only status bit is set when a conversion sequence has completed and
data is ready to be read from the ADC register. CC is cleared when a channel is
selected for conversion, when data is read from the ADC register, or when the
A/D subsystem is turned off. Once a conversion has been started, conversions
of the selected channel will continue every 32 PH2 clock cycles until the ADSC
register is written to again. During continuous conversion operation, the ADC
register will be updated with new data and the CC bit set every 32 PH2 clock
cycles. Also, data from the previous conversion will be overwritten regardless of
the state of the CC bit.
9
10
11
12
Reserved
13
This bit is not used currently. It can be read or written, but does not control
anything.
14
ADON — A/D Subsystem On
A
When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to
stabilize before accurate conversion results can be attained.
16
CH2-CH0 — Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D
converter. Channels 0 through 3 correspond to port C input pins PC6 through
PC3. Channels 4 through 6 are used for reference measurements. In user mode
channel 7 is reserved. If a conversion is attempted with channel 7 selected the
result will be $00. Table 9-1 lists the inputs selected by bits CH0 through CH3.
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
9-4
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GENERAL RELEASE SPECIFICATION
If the ADON bit is set and an input from channels 0 through 4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port C pin an input).
If the port C data register is read while the A/D is on and one of the shared input
channels is selected using bit CH0 through CH2, the corresponding port C pin will
read as a logic zero. The remaining port C pins will read normally. To digitally read
a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5
through 7 must be selected.
Table 9-1. A/D Multiplexer Input
Channel Assignments
Freescale Semiconductor, Inc...
Channel
Signal
0
AD0 — Port C, Bit 6
1
AD1 — Port C, Bit 5
2
AD2 — Port C, Bit 4
3
AD3 — Port C, Bit 3
4
VREFH — Port C, Bit 7
5
(VREFH + VSS)/2
6
VSS
7
Reserved
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.5 A/D Conversion Data Register (ADC)
8
This register contains the output of the A/D converter. See Figure 9-1.
2
3
ADC
$001D
4
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
X
X
X
X
X
X
X
X
Write:
Reset:
5
Freescale Semiconductor, Inc...
Read:
Bit 7
= Unimplemented
Figure 9-2. A/D Conversion Data Register
6
7
9.6 A/D Subsystem During Wait/Halt Modes
The A/D subsystem continues normal operation during wait and halt modes. To
decrease power consumption during wait or halt, the ADON bit in the ADSC
register and the EERC bit in the EEPROG register should be cleared if the A/D
subsystem is not being used.
8
9
10
9.7 A/D Subsystem Operation During Stop Mode
When the stop mode is enabled, execution of the STOP instruction will terminate
all A/D subsystem functions. Any pending conversion is aborted. When the
oscillator resumes operation upon leaving the stop mode, a finite amount of time
passes before the A/D subsystem stabilizes sufficiently to provide conversions at
its rated accuracy. The delays built into the MC68HC805P18 when coming out of
stop mode are sufficient for this purpose. No explicit delays need to be added to
the application software.
11
12
13
14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
9-6
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 10
16-BIT TIMER
4
10.1 Introduction
Freescale Semiconductor, Inc...
3
The MC68HC805P18 MCU contains a single 16-bit programmable timer with an
input capture function and an output compare function. The 16-bit timer is driven
by the output of a fixed divide-by-four prescaler operating from the PH2 clock. The
16-bit timer may be used for many applications including input waveform
measurement, while simultaneously generating an output waveform. Pulse widths
can vary from microseconds to seconds depending on the oscillator frequency
selected. The 16-bit timer is also capable of generating periodic interrupts. See
Figure 10-1.
Because the timer has a 16-bit architecture, each function is represented by two
registers. Each register pair contains the high and low byte of that function.
Generally, accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific timer
function until the low byte is also accessed.
NOTE
The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time
the high and low bytes are accessed.
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
INTERNAL HC05 BUS
8
OUTPUT
COMPARE
2
3
OCRH
BUFFER
FREERUNNING
COUNTER
OCRL
4
TMRH/
ACRH
5
Freescale Semiconductor, Inc...
INPUT
CAPTURE
PH2
CLOCK
ICRH
TMRL/
ACRL
ICRL
÷4
6
7
COMPARE
DETECTOR
8
OVERFLOW
DETECTOR
EDGE
DETECTOR
TCAP
9
10
R
R
TCMP
>
11
R
TIMER
STATUS
REGISTER
12
OCF
TOF
RESET
ICF
13
14
INTERRUPT
GENERATOR
TIMER INTERRUPT
A
OCIE
16
TOIE
ICIE
IEDG
OLVL
TIMER
CONTROL
REGISTER
17
18
19
Figure 10-1. 16-Bit Timer Block Diagram
20
16-BIT TIMER
10-2
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10.2 Timer
Freescale Semiconductor, Inc...
The key element of the programmable timer is a 16-bit free-running counter, or
timer registers, preceded by a prescaler which divides the PH2 clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds when a 4-MHz crystal is
used. The counter is incremented to increasing values during the low portion of the
PH2 clock cycle.
The double byte free-running counter can be read from either of two locations: the
timer registers (TMRH and TMRL) or the alternate counter registers (ACRH and
ACRL). Both locations will contain identical values. A read sequence containing
only a read of the LSB of the counter (TMRL/ACRL) will return the count value at
the time of the read. If a read of the counter accesses the MSB first (TMRH/ACRH),
it causes the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value
remains fixed after the first MSB byte read, even if the MSB is read several times.
The buffer is accessed when reading the counter LSB (TMRL/ACRL), and thus
completes a read sequence of the total counter value. When reading either the
timer or alternate counter registers, if the MSB is read, the LSB must also be read
to complete the read sequence. See Figure 10-2 and Figure 10-3.
TMRH
$0018
Read:
2
3
4
5
6
7
8
9
Bit 7
6
5
4
3
2
1
Bit 0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
10
1
1
1
1
1
1
1
1
11
Bit 7
6
5
4
3
2
1
Bit 0
12
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
1
0
0
Write:
Reset:
TMRL
$0019
8
Read:
13
Write:
Reset:
= Unimplemented
Figure 10-2. Timer Registers (TMRH/TMRL)
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
ACRH
$001A
2
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
1
0
0
Write:
Reset:
3
4
ACRL
$001B
Freescale Semiconductor, Inc...
5
Read:
Write:
Reset:
6
= Unimplemented
7
Figure 10-3. Alternate Counter Registers (ACRH/ACRL)
8
The timer registers and alternate counter registers can be read at any time without
affecting their value. However, the alternate counter registers differ from the timer
registers in one respect: Aread of the timer register MSB can clear the timer
overflow flag (TOF). Therefore, the alternate counter registers can be read at any
time without the possibility of missing timer overflow interrupts due to clearing of
the TOF. See Figure 10-4.
9
10
11
PH2
CLOCK
12
13
14
A
16-BIT
FREE-RUNNING
COUNTER
$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
16
Figure 10-4. State Timing Diagram for Timer Overflow
17
18
19
20
16-BIT TIMER
10-4
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GENERAL RELEASE SPECIFICATION
The free-running counter is initialized to $FFFC during reset and is a read-only
register. During power-on-reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is 16 bits
preceded by a fixed divide-by-four prescaler, the value in the counter repeats every
262,144 PH2 clock cycles (524,288 oscillator cycles). When the free-running
counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) in register
TSR is set. An interrupt can also be enabled when counter rollover occurs by
setting the timer overflow interrupt enable bit (TOIE) in register TCR. See
Figure 10-5.
8
2
3
4
Freescale Semiconductor, Inc...
5
PH2
CLOCK
6
INTERNAL
RESET
16-BIT
FREE-RUNNING
COUNTER
7
$FFFC
$FFFD
$FFFE
RESET
(EXTERNAL
OR OTHER)
$FFFF
8
9
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset.
Figure 10-5. State Timing Diagram for Timer Reset
10
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
10.3 Output Compare
8
The output compare function may be used to generate an output waveform and/or
as an elapsed time indicator. All of the bits in the output compare register pair
OCRH/OCRL are readable and writable and are not altered by the 16-bit timer’s
control logic. Reset does not affect the contents of these registers. If the output
compare function is not utilized, its registers can be used for data storage. See
Figure 10-3.
2
3
4
5
Freescale Semiconductor, Inc...
OCRH
$0016
6
Bit 7
6
5
4
3
2
1
Bit 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
X
X
X
X
X
X
X
X
Bit 7
6
5
4
3
2
1
Bit 0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
7
8
OCRL
$0017
9
Read:
Write:
Reset:
10
Figure 10-6. Output Compare Registers (OCRH/OCRL)
11
The contents of the output compare registers are compared with the contents of
the free-running counter once every four PH2 clock cycles. If a match is found, the
output compare flag bit (OCF) is set and the output level bit (OLVL) is clocked to
the output latch. The values in the output compare registers and output level bit
should be changed after each successful comparison to control an output
waveform or to establish a new elapsed timeout. An interrupt can also accompany
a successful output compare if the output compare interrupt enable bit (OCIE) is
set.
12
13
14
A
After a CPU write cycle to the MSB of the output compare register pair (OCRH),
the output compare function is inhibited until the LSB (OCRL) is written. Both bytes
must be written if the MSB is written. A write made only to the LSB will not inhibit
the compare function. The free-running counter increments every four PH2 clock
cycles. The minimum time required to update the output compare registers is a
function of software rather than hardware.
16
17
The output compare output level bit (OLVL) will be clocked to its output latch
regardless of the state of the output compare flag bit (OCF). A valid output compare
must occur before the OLVL bit is clocked to its output latch (TCMP).
18
19
20
16-BIT TIMER
10-6
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Since neither the output compare flag (OCF) nor the output compare registers are
affected by reset, care must be exercised when initializing the output compare
function. The following procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register (CCR).
2
2. Write the MSB of the output compare register pair (OCRH) to inhibit further
compares until the LSB is written.
3
3. Read the timer status register (TSR) to arm the output compare flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to enable the
output compare function and to clear its flag (and interrupt).
5. Unblock interrupts by clearing the I bit in the CCR.
Freescale Semiconductor, Inc...
8
This procedure prevents the output compare flag bit (OCF) from being set between
the time it is read and the time the output compare registers are updated. A
software example is shown in Figure 10-7.
9B
.
.
B6
BE
B7
B6
BF
.
.
.
XX
XX
16
13
17
.
SEI
.
.
LDA
LDX
STA
LDA
STX
.
.
.
DATAH
DATAL
OCRH
TSR
OCRL
.
BLOCK INTERRUPTS
.
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
Figure 10-7. Output Compare Software Initialization Example
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
10.4 Input Capture
8
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture.
They are used to latch the value of the free-running counter after a defined
transition is sensed by the input capture edge detector.
2
3
NOTE
4
The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
Freescale Semiconductor, Inc...
5
6
The edge that triggers the counter transfer is defined by the input edge bit (IEDG)
in register TCR. Reset does not affect the contents of the input capture registers.
See Figure 10-3.
7
8
9
ICRH
$0014
10
Bit 7
6
5
4
3
2
1
Bit 0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
X
X
X
X
X
X
X
X
Bit 7
6
5
4
3
2
1
Bit 0
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
11
12
ICRL
$0015
13
Read:
Write:
Reset:
Figure 10-8. Input Compare Registers (ICRH/ICRL)
14
A
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the PH2 clock preceding the external
transition (see Figure 10-9). This delay is required for internal synchronization.
Resolution is affected by the prescaler, allowing the free-running counter to
increment once every four PH2 clock cycles.
16
17
The contents of the free-running counter are transferred to the input capture
registers on each proper signal transition regardless of the state of the input
capture flag bit (ICF) in register TSR. The input capture registers always contain
the free-running counter value which corresponds to the most recent input capture.
18
19
20
16-BIT TIMER
10-8
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After a read of the MSB of the input capture register pair (ICRH), counter transfers
are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic
forces the minimum pulse period attainable to be determined by the time required
to execute an input capture software routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones which allow
software to read the LSB of the register pair (ICRL) and perform needed
operations. There is no conflict between reading the LSB (ICRL) and the
free-running counter transfer, since they occur on opposite edges of the PH2 clock.
8
2
3
4
Freescale Semiconductor, Inc...
5
6
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
7
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
TCAP
PIN
INPUT
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER
8
9
10
(SEE NOTE)
11
$????
$FFED
12
INPUT
CAPTURE
FLAG
13
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
Figure 10-9. State Timing Diagram for Input Capture
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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10.5 Timer Control Register (TCR)
8
The timer control (TCR) shown in Figure 10-3 and free-running counter (TMRH,
TMRL, ACRH, and ACRL) registers are the only registers of the 16-bit timer
affected by reset. The output compare port (TCMP) is forced low after reset and
remains low until OLVL is set and a valid output compare occurs.
2
3
4
TCR
$0012
5
Freescale Semiconductor, Inc...
6
5
ICIE
OCIE
TOIE
0
0
0
Read:
4
3
2
0
0
0
1
Bit 0
IEDG
OLVL
X
0
Write:
Reset:
6
Bit 7
0
0
0
= Unimplemented
Figure 10-10. Timer Control Register (TCR)
7
ICIE — Input Capture Interrupt Enable
8
Bit 7, when set, enables input capture interrupts to the CPU. The interrupt will
occur at the same time bit 7 (ICF) in the TSR register is set.
9
OCIE —Output Compare Interrupt Enable
10
Bit 6, when set, enables output compare interrupts to the CPU. The interrupt will
occur at the same time bit 6 (OCF) in the TSR register is set.
11
TOIE — Timer Overflow Interrupt Enable
12
Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The
interrupt will occur at the same time bit 5 (TOF) in the TSR register is set.
13
IEDG — Input Capture Edge Select
14
Bit 1 selects which edge of the input capture signal will trigger a transfer of the
contents of the free-running counter registers to the input capture registers.
Clearing this bit will select the falling edge; setting it selects the rising edge.
A
OLVL — Output Compare Output Level Select
16
Bit 0 selects the output level (high or low) that is clocked into the output compare
output latch at the next successful output compare.
17
18
19
20
16-BIT TIMER
10-10
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10.6 Timer Status Register (TSR)
Reading the timer status register (TSR) satisfies the first condition required to clear
status flags and interrupts. See Figure 10-3. The only remaining step is to read (or
write) the register associated with the active status flag (and/or interrupt). This
method does not present any problems for input capture or output compare
functions.
Freescale Semiconductor, Inc...
However, a problem can occur when using a timer interrupt function and reading
the free-running counter at random times to, for example, measure an elapsed
time. If the proper precautions are not designed into the application software, a
timer interrupt flag (TOF) could unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set, and
8
2
3
4
5
6
2. The LSB of the free-running counter is read, but not for the purpose of
servicing the flag or interrupt.
7
The alternate counter registers (ACRH and ACRL) contain the same values as the
timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any
time without affecting the timer overflow flag (TOF) or interrupt.
8
9
TSR
$0013
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCR
TOF
0
0
0
0
0
X
X
X
0
0
0
0
0
Write:
Reset:
= Unimplemented
10
11
12
Figure 10-11. Timer Status Register (TSR)
13
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been sensed
by the input capture edge detector fed by pin TCAP. This flag and the input
capture interrupt can be cleared by reading register TSR followed by reading the
LSB of the input capture register pair (ICRL).
14
A
16
OCF — Output Compare Flag
Bit 6 is set when the contents of the output compare registers match the
contents of the free-running counter. This flag and the output compare interrupt
can be cleared by reading register TSR followed by writing the LSB of the output
compare register pair (OCRL).
17
18
19
20
16-BIT TIMER
Rev. 1.0
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TOF — Timer Overflow Flag
8
Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This
flag and the timer overflow interrupt can be cleared by reading register TSR
followed by reading the LSB of the timer register pair (TMRL).
2
3
10.7 Timer Operation During Wait/Halt Modes
During wait and halt modes, the 16-bit timer continues to operate normally and may
generate an interrupt to trigger the MCU out of the wait/halt mode.
4
10.8 Timer Operation During Stop Mode
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5
6
When the MCU enters the stop mode, the free-running counter stops counting (the
PH2 clock is stopped). It remains at that particular count value until the stop mode
is exited by applying a low signal to the IRQ pin, at which time the counter resumes
from its stopped value as if nothing had happened. If stop mode is exited via an
external RESET (logic low applied to the RESET pin), the counter is forced to
$FFFC.
7
8
9
If a valid input capture edge occurs at the TCAP pin during stop mode the input
capture detect circuitry will be armed. This action does not set any flags or “wake
up” the MCU, but when the MCU does “wake up” there will be an active input
capture flag (and data) from the first valid edge. If the stop mode is exited by an
external RESET, no input capture flag or data will be present even if a valid input
capture edge was detected during stop mode.
10
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
10-12
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GENERAL RELEASE SPECIFICATION
8
2
SECTION 11
SERIAL INPUT/OUTPUT PORT
3
4
Freescale Semiconductor, Inc...
11.1 Introduction
The simple synchronous serial input/output port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or other
MCUs. The SIOP is implemented as a 3-wire master/slave system with serial clock
(SCK), serial data Input (SDI), and serial data output (SDO). A block diagram of the
SIOP is shown in Figure 11-1.
The SIOP subsystem shares its input/output pins with port B. When the SIOP is
enabled (SPE bit set in register SCR), port B data direction registers (DDR) and
data registers are modified by the SIOP. Although port B DDR and data registers
can be altered by application software, these actions could affect the transmitted
or received data.
5
6
7
8
9
10
HCO5 INTERNAL BUS
11
12
SPE
13
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
BAUD
CONTROL
STATUS
RATE
8-BIT
SDO
SHIFT
REGISTER
$0A
14
7 6 5 4 3 2 1 0
GENERATOR
REGISTER
$0B
REGISTER
$0C
I/O
SDO/PB5
CONTROL
SDI
LOGIC
SDI/PB6
A
16
SCK
PH2 CLOCK
Figure 11-1. SIOP Block Diagram
SCK/PB7
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
11.2 SIOP Signal Format
8
The SIOP subsystem is software configurable for master or slave operation. No
external mode selection inputs are available (such as the slave select pin).
2
3
11.2.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic one during idle periods
between data transfers. The first falling edge of SCK signals the beginning of a
data transfer. At this time the first bit of received data is accepted at the SDI pin
and the first bit of transmitted data is presented at the SDO pin (see Figure 11-2).
Data is captured at the SDI pin on the rising edge of SCK, and the first bit of
transmitted data is presented at the SDO pin. The transfer is terminated upon the
eighth rising edge of SCK.
4
Freescale Semiconductor, Inc...
5
6
7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 6
BIT 7
SDO
8
9
SCK
100 ns
10
100 ns
SDI
BIT 0
11
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
Figure 11-2. SIOP Timing Diagram
12
The master and slave modes of operation differ only by the sourcing of SCK. In
master mode, SCK is driven from an internal source within the MCU. In slave
mode, SCK is driven from a source external to the MCU. The SCK frequency is
programmable via the mask option register 1 (MOR1). Available rates are OSC
divided by 2, 4, 8, or 16.
13
14
A
16
NOTE
17
OSC divided by 2 is four times faster than the standard rate available
on the 68HC05P6.
18
Refer to 8.4 Mask Option Registers (MOR) for a description of available mask
option registers.
19
20
SERIAL INPUT/OUTPUT PORT
11-2
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11.2.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New
data is presented to the SDI pin on the falling edge of SCK. Valid data must be
present at least 100 nanoseconds before the rising edge of SCK and remain valid
for 100 nanoseconds after the rising edge of SCK. See Figure 11-2.
8
2
3
Freescale Semiconductor, Inc...
11.2.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior
to enabling the SIOP, PB5 can be initialized to determine the beginning state.
While the SIOP is enabled, PB5 cannot be used as a standard output since that pin
is connected to the last stage of the SIOP serial shift register. The data can be
transmitted in either MSB first format or the LSB format by programming the
MOR1.
On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin.
The remaining data bits will be shifted out to the SDI pin on subsequent falling
edges of SCK. The SDO pin will present valid data at least 100 nanoseconds
before the rising edge of the SCK and remain valid for 100 nanoseconds after the
rising edge of SCK. See Figure 11-2.
4
5
6
7
8
9
10
11.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR)
located at address $000A, the SIOP status register (SSR) located at address
$000B, and the SIOP data register (SDR) located at address $000C.
11
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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11.3.1 SIOP Control Register (SCR)
8
This register is located at address $000A and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
2
3
Bit 7
SCR
$000A
4
Read:
0
5
4
0
SPE
3
2
1
Bit 0
0
0
0
0
0
0
0
0
MSTR
Write:
Reset:
5
6
0
0
0
0
Freescale Semiconductor, Inc...
= Unimplemented
6
Figure 11-3. SIOP Control Register
7
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the
serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial
clock input in the slave mode or a serial clock output in the master mode. Port
B DDR and data registers can be manipulated as usual (except for PB5);
however, these actions could affect the transmitted or received data.
8
9
10
The SPE bit is readable and writable at any time. Clearing the SPE bit while a
transmission is in progress will 1) abort the transmission, 2) reset the serial bit
counter, and 3) convert the port B/SIOP port to a general-purpose I/O port.
Reset clears the SPE bit.
11
12
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A
transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output
providing a synchronous data clock dependent upon the oscillator frequency.
When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave
modes.
13
14
A
The MSTR bit is readable and writable at any time regardless of the state of the
SPE bit. Clearing the MSTR bit will abort any transfers that may have been in
progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave
mode.
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
11-4
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GENERAL RELEASE SPECIFICATION
11.3.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
SSR
$000B
Read:
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Freescale Semiconductor, Inc...
2
3
4
Write:
Reset:
8
Figure 11-4. SIOP Status Register
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK and
indicates that a data transfer has been completed. It has no effect on any future
data transfers and can be ignored. The SPIF bit is cleared by reading the SSR
followed by a read or write of the SDR. If the SPIF is cleared before the last rising
edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the
SPIF bit.
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access of the SDR
has occurred. The DCOL bit will be set when reading or writing the SDR after
the first falling edge of SCK and before SPIF is set. Reading or writing the SDR
during this time will result in invalid data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed
by a read or write of the SDR. If the last part of the clearing sequence is done
after another transfer has started, the DCOL bit will be set again. Reset clears
the DCOL bit.
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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11.3.3 SIOP Data Register (SDR)
8
This register is located at address $000C and serves as both the transmit and
receive data register. Writing to this register will initiate a message transmission if
the SIOP is in master mode. The SIOP subsystem is not double buffered and any
write to this register will destroy the previous contents. The SDR can be read at any
time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause
invalid data to be transmitted and/or received. Figure 11-3 shows the position of
each bit in the register. This register is not affected by reset.
2
3
4
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5
6
SDR
$000C
7
6
5
4
3
2
1
Bit 0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Read:
Write:
Reset:
8
Bit 7
Unaffected by reset
Figure 11-5. SIOP Data Register
9
10
11
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
11-6
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SECTION 12
INSTRUCTION SET
12.1 Introduction
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This section describes the addressing modes and instruction types.
12.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
12.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent
instructions require no memory address and are one byte long.
12.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
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12.2.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are 3-byte instructions that use direct
addressing to access the operand and relative addressing to specify a branch
destination.
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12.2.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
12.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with
variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
12.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with
variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
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12.2.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with
variable addresses at any location in memory. The CPU adds the unsigned byte in
the index register to the two unsigned bytes following the opcode. The sum is the
conditional address of the operand. The first byte after the opcode is the high byte
of the 16-bit offset; the second byte is the low byte of the offset. These instructions
can address any location in memory.
Freescale Semiconductor, Inc...
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
12.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch condition
is not true, the CPU goes to the next instruction. The offset is a signed, two’s
complement byte that gives a branching range of –128 to +127 bytes from the
address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset because the assembler determines the proper offset and verifies that it
is within the span of the branch.
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12.3 Instruction Types
The MCU instructions fall into five categories:
•
Register/Memory instructions
•
Read-Modify-Write instructions
•
Jump/Branch instructions
•
Bit Manipulation instructions
•
Control instructions
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12.3.1 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
INSTRUCTION SET
12-4
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12.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
12.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is met.
If the test condition is not met, the branch is not performed. All branch instructions
use relative addressing.
Bit test and branch instructions cause a branch based on the state of any readable
bit in the first 256 memory locations. These 3-byte instructions use a combination
of direct addressing and relative addressing. The direct address of the byte to be
tested is in the byte following the opcode. The third byte is the signed offset byte.
The CPU finds the conditional branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition
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(set or clear) is part of the opcode. The span of branching is from –128 to +127 from
the address of the next location after the branch instruction. The CPU also
transfers the tested bit to the carry/borrow bit of the condition code register.
Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
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Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
Branch Never
BRN
Branch if Bit Set
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
INSTRUCTION SET
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12.3.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Instruction
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Clear Bit
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
12.3.5 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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12.4 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕ — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
↕ — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
38
48
58
68
78
dd
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
0
b7
b0
C
b7
— — ↕ ↕ ↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 12-6. Instruction Set Summary
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
INSTRUCTION SET
12-8
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Address
Mode
Opcode
Operand
Cycles
Table 12-6. Instruction Set Summary (Continued)
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Freescale Semiconductor, Inc...
Source
Form
Operation
Description
Effect on
CCR
H I N Z C
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
INSTRUCTION SET
Rev. 1.0
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REL
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Cycles
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect on
CCR
H I N Z C
Mn ← 1
Address
Mode
Operation
Operand
Freescale Semiconductor, Inc...
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
BSET n opr
Set Bit n
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
— — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
— — ↕ ↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — ↕ ↕ 1
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
— — ↕ ↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
— — 0 1 —
— — ↕ ↕ —
INSTRUCTION SET
12-10
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2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC805P18
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GENERAL RELEASE SPECIFICATION
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
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INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC
C dd
C hh ll
D ee ff
ff
C
EC
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD
C dd
D hh ll
D ee ff
ff
D
ED
FD
5
6
7
6
5
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
INH
42
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
PC ← Jump Address
Unconditional Jump
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
— — ↕ ↕ —
X ← (M)
C
0
b7
0
C
b7
— — ↕ ↕
⋅
b0
— — 0 ↕ ↕
b0
X : A ← (X) × (A)
0 — — — 0
INSTRUCTION SET
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Cycles
Negate Byte
(Two’s Complement)
NOP
No Operation
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
30
40
50
60
70
ii
5
3
3
6
5
— — — — —
INH
9D
2
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
2
3
4
5
4
3
39
49
59
69
79
dd
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
Effect on
CCR
Description
H I N Z C
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operand
Operation
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
C
b7
— — ↕ ↕ ↕
b0
ff
ff
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕
INH
80
6
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
C
b7
— — ↕ ↕ ↕
b0
ff
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕ ↕ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
M ← (A)
INSTRUCTION SET
12-12
For More Information On This Product,
Go to: www.freescale.com
MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
Store Index
Register In Memory
— — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
2
3
4
5
4
3
Subtract Memory
Byte from
Accumulator
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Software Interrupt
INH
83
10
TAX
Transfer
Accumulator to
Index Register
— — — — —
INH
97
2
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— ↕ — — —
INH
8F
2
M ← (X)
A ← (A) – (M)
X ← (A)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock
and Enable
Interrupts
(M) – $00
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
INSTRUCTION SET
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
dd
ff
Cycles
— — ↕ ↕ —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
Freescale Semiconductor, Inc...
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
4
3
3
5
4
12-14
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
REL 2
3
BRA
2
5
DIR 1
5
ASR
DIR 1
5
ROR
DIR 1
LSR
DIR 1
5
COM
5
1
3
11
3
INH 1
3
ASRA
INH 1
3
RORA
INH 1
LSRA
INH 1
3
COMA
INH
3
MUL
INH 1
NEGA
4
INH
3
3
INH 2
3
ASRX
INH 2
3
RORX
INH 2
LSRX
INH 2
3
COMX
3
INH 2
NEGX
5
INH
DIR 1
CLR
5
DIR 1
TST
DIR 1
4
INC
5
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
INH 1
CLRA
3
INH 1
TSTA
INH 1
3
INCA
3
INH 1
DECA
INH 1
3
ROLA
INH 1
3
INH 2
3
INH 2
CLRX
3
INH 2
TSTX
INH 2
3
INCX
3
INH 2
DECX
INH 2
3
ROLX
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
NEG
3
DIR
6
6
IX1 1
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
6
IX1 1
DEC
IX1 1
6
ROL
ASR
ROR
LSR
COM
NEG
7
IX
IX
5
IX
5
5
IX
IX 1
5
IX
IX
4
5
IX
IX
5
9
2
1
1
1
1
1
1
1
INH 1
WAIT
INH
2
STOP
INH
SWI
10
INH
RTS
INH
6
RTI
8
INH
2
2
2
2
2
2
2
INH
TXA
2
2
6
MSB
0
4
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
SUB
C
EXT
3
IX2 2
5
IX2 2
6
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
IX2 2
5
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
BIT
5
IX2 2
5
SUB
D
IX2
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
5 Number of Cycles
DIR Number of Bytes/Addressing Mode
4
IX1 1
4
SUB
E
IX1
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
DIR 3
3
SUB
B
DIR
Register/Memory
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
REL 2
2
BSR
2
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
0
2
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
A
IMM
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
INH
2
TAX
9
INH
Control
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
1
IX 1
5
5
1
IX 1
5
ASL/LSL
IX1 1
6
ASR
IX1 1
6
ROR
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
Read-Modify-Write
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
BSET0
1
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
BRCLR7
3
BRSET7
3
BRCLR6
3
BRSET6
3
BRCLR5
3
BRSET5
3
BRCLR4
3
BRSET4
3
BRCLR3
3
BRSET3
3
BRCLR2
3
BRSET2
3
BRCLR1
3
BRSET1
3
BRCLR0
3
BRSET0
0
5
0
MSB
LSB
Branc
Bit
h
Manipulation
DIR
DIR
REL
Table 12-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8
2
SECTION 13
ELECTRICAL SPECIFICATIONS
3
4
13.1 Introduction
Freescale Semiconductor, Inc...
This section contains electrical and timing specifications for the MC68HC805P18.
5
6
13.2 Maximum Ratings
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3 to VDD + 0.3
V
Factory Mode (IRQ Pin Only)
VIN
VSS –0.3 to 2 x VDD
V
I
25
mA
TSTG
–65 to +150
°C
Current Drain Per Pin Excluding VDD and VSS
Storage Temperature Range
NOTE: Voltages referenced to VSS
Operating Temperature Range
MC68HC805P18 (Standard)
MC68HC805P18 (Extended)
MC68HC805P18 (Automotive)
8
9
10
11
13.3 Operating Temperature Range
Rating
7
12
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
–40 to +125
°C
13
14
A
NOTE
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage
higher than maximum-rated voltages to this high-impedance circuit.
For proper operation, it is recommended that VIN and VOUT be
constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of
operation is enhanced if unused inputs are connected to an
appropriate logic voltage level (for instance, either VSS or VDD).
ELECTRICAL SPECIFICATIONS
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
16
17
18
19
20
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.4 Thermal Characteristics
8
2
3
4
Characteristic
Thermal Resistance
Plastic
SOIC
Symbol
Value
Unit
θJA
60
60
°C/W
13.5 Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from:
5
Freescale Semiconductor, Inc...
TJ = TA + (PD × θJA)
6
(1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W.
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
7
8
9
For most applications, PI/O « PINT and can be neglected.
The following is an approximate relationship between PD and TJ (neglecting PI/O):
10
PD = K ÷ (TJ + 273 °C)
11
(2)
Solving equations (1) and (2) for K gives:
12
K = PD × (TA + 273 °C) + θJA × (PD)2
13
where K is a constant pertaining to the particular part. K can be determined from
equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of
K, the values of PD and TJ can be obtained by solving equations (1) and (2)
iteratively for any value of TA.
14
(3)
A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
13-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.6 DC Electrical Characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C)
Freescale Semiconductor, Inc...
Characteristic
8
Symbol
Min
Typ
Max
Unit
Output Voltage
ILoad = 10.0 µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
2
Output High Voltage
(ILoad = –0.8 mA) PA0–PA7, PB5–PB7,
PC0–PC7, PD5/CKOUT
VOH
VDD –0.8
—
—
V
3
Output Low Voltage
(ILoad = 1.6 mA) PA0–PA7, PB5–PB7,
PC0–PC7, PD5/CKOUT
VOL
—
—
0.4
V
4
Input High Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT,
TCAP/PD7, IRQ, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5,
TCAP/PD7, IRQ, RESET, OSC1
VIL
6
VSS
—
0.2 x VDD
V
7
Supply Current
Run
Wait (see Note 3)
Stop (see Note 8)
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Extended)
–40 °C to +125 °C (Automotive
IDD
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT,
TCAP/PD7
—
—
4.75
2.75
7.50
5.00
mA
mA
—
—
—
—
TBD
TBD
TBD
TBD
350
400
500
500
µA
µA
µA
µA
IIL
—
—
±10
µA
RPTA
62
—
102
k
A/D Ports Hi-Z Leakage Current
PC3–PC7
IIL
—
—
±1
µA
Input Current
RESET, IRQ, OSC1
IIN
—
—
±1
µA
COUT
CIN
—
—
—
—
12
8
pF
EEPROM Program/Erase Time (128 Byte Array)
Byte
Block (Erase Only)
Bulk (Erase Only)
—
—
—
2
5
10
10
15
50
Low Voltage Reset Voltage
3.6
3.8
—
I/O Ports Switch Resistance
(Pullup Enabled PA0–PA7)
Capacitance
Ports (as Input or Output)
RESET, IRQ
5
NOTES:
1. All values shown reflect average measurements.
2. Typical vlaues at midpoint of voltage range, 25 °C only.
3. Wait IDD with active systems: Timer, SIOP, and A/D.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc = 4.2 MHz), all
inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V
6. Stop IDD measured with OSC1 = VSS
7. Wait IDD is affected linearly by the OSC2 capacitance.
8. Stop IDD maximum values given with LVR option enabled.
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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8
9
10
11
12
13
14
A
ms
V
16
17
18
19
20
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.7 Active Reset Characteristics
8
2
3
4
Freescale Semiconductor, Inc...
5
8
9
10
11
12
13
14
A
Fall Time
Pulse Width
CLoad
Pullup
0.5 µs
13 ns
2.4 µs
50 pF
10 K
1.0 µs
20 ns
2.7 µs
100 pF
10 K
2.5 µs
20 ns
2.7 µs
250 pF
10 K
NOTE: VDD = 4.5 Vdc, VSS = 0 Vdc, TA = 125 °C
13.8 A/D Converter Characteristics
(VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted)
6
7
Rise Time
Characteristic
Min
Max
Unit
Resolution
8
8
Bits
Absolute Accuracy
(VDD ≥ VREFH > 4.5)
—
± 1 1/2
LSB
VSS
VSS
VREFH
VDD
V
—
—
±1
±1
µA
µA
32
32
tAD*
Conversion Range
VREFH
Input Leakage
AD0, AD1, AD2, AD3
VREFH
Conversion Time
(Includes Sampling Time)
Monotonicity
Comments
Including quantization
A/D accuracy may decrease proportionately as
VREFH is reduced below 4.5
Inherent (Within Total Error)
Zero Input Reading
00
01
Hex
Vin = 0 V
Full-Scale Reading
FE
FF
Hex
Vin = VREFH
Sample Time
12
12
tAD*
Input Capacitance
—
12
pF
VSS
VREFH
V
Analog Input Voltage
*tAD = tcyc if clock source equals MCU
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
13-4
For More Information On This Product,
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MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.9 SIOP Timing
(VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note)
Freescale Semiconductor, Inc...
Number
Characteristic
8
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fSIOP(M)
fSIOP(S)
1
dc
1
1
fOP
1
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
1
—
1
1
tCYC
2
SCK Low Time
tCYC
238
—
ns
3
SDO Data Valid Time
tv
—
200
ns
4
SDO Hold Time
tHO
0
—
ns
5
SDI Setup Time
tS
100
—
ns
6
SDI Hold Time
tH
100
—
ns
2
3
4
5
6
7
NOTES:
1. fOP = fOSC ÷ 2 = 2.1 MHz max; tCYC = 1 ÷ fOP
2. In master mode, the SCK rate is determined by the programmable option in MOR1.
8
9
t2
t1
10
SCK
t5
t6
11
12
SDI
SDI
SDI
t3
SDI
SDI
13
t4
14
SDI
SDI
BIT 7
A
Figure 13-1. SIOP Timing Diagram
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
13.10 OSC Out Timing
8
Characteristic
Symbol
Min
Max
Unit
2
Cycle Time
1*
476
—
ns
Rise Time
4*
3.5
12
ns
3
Fall Time
5*
7.5
27.5
ns
2 and 3*
200
—
ns
4
*Refer to Figure 13-2
Pulse Width
5
(1)
Freescale Semiconductor, Inc...
(2)
6
(3)
OSC OUT
7
8
(4)
9
(5)
Figure 13-2. OSC Out Timing
10
NOTE
11
All timing is shown with respect to 20% and 70% VDD. Maximum rise
and fall times assume 44% duty cycle. Minimum rise and fall times
assume 55% duty cycle
12
13
14
A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
13-6
For More Information On This Product,
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MC68HC805P18
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GENERAL RELEASE SPECIFICATION
13.11 Control Timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note)
Freescale Semiconductor, Inc...
Characteristic
8
Symbol
Min
Max
Unit
Frequency of Operation
Crystal Option
External Clock Option
fOSC
—
dc
4.2
4.2
MHz
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fOP
—
dc
2.1
2.1
MHz
Cycle Time
tCYC
476
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
RESET Pulse Width
tRL
1.5
—
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
*
—
tCYC
tOH, tOL
200
—
ns
A/D On Current Stabilization Time
tADON
—
100
µs
RC Oscillator Stabilization Time (A/D)
tRCON
—
5.0
µs
OSC1 Pulse Width
2
3
* The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service
routine plus 21 tCYC.
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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19
20
NOTE 3
8
11
13-8
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
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3FFE
PCH
3FFE
PCL
3FFF
Figure 13-3. Power-On Reset and External Reset Timing Diagram
NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence.
RESET
13
tRL
3FFE
9
OP
CODE
10
3FFE
7
NEW
PCL
12
NEW PC
6
NEW
PCH
14
NEW PC
5
INTERNAL
DATA
BUS1
3FFF
t
CYC
NEW PC
3
3FFE
4064 tCYC
OP
CODE
NEW PC
2
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
16
DD THRESHOLD (1–2 V TYPICAL)
18
V
A
OSC12
DD
V
17
t
VDDR
Freescale Semiconductor, Inc...
GENERAL RELEASE SPECIFICATION
Freescale Semiconductor, Inc.
8
4
MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8
2
SECTION 14
MECHANICAL SPECIFICATIONS
3
4
Freescale Semiconductor, Inc...
14.1 Introduction
This section provides package dimension drawings for the 28-pin dual in-line (DIP)
or 28-pin small outline (SOIC) packages.
To make sure that you have the latest case outline specifications, contact one of
the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
15
B
14
L
C
N
H
G
F
D
K
M
10
11
12
14.2 28-Pin Dual In-Line Package (Case #710)
A
7
9
Follow Mfax or wwweb on-line instructions to retrieve the current mechanical
specifications.
1
6
8
Worldwide Web (wwweb) at http://design-net.com
28
5
J
°
°
°
°
13
14
A
16
17
18
19
20
MECHANICAL SPECIFICATIONS
Rev. 1.0
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Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
14.3 28-Pin Small Outline Package (Case #751F)
8
-A-
2
28
14X
-B-
3
1
4
P
14
28X D
!
M
R X 45°
C
-T26X
Freescale Semiconductor, Inc...
5
! ! % ! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
6
-T-
G
K
7
F
J
°
°
°
°
8
9
10
11
12
13
14
A
16
17
18
19
20
MECHANICAL SPECIFICATIONS
14-2
For More Information On This Product,
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MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8
2
SECTION 15
ORDERING INFORMATION
3
4
15.1 Introduction
Freescale Semiconductor, Inc...
This section contains instructions for ordering the MC68HC805P18.
5
6
15.2 MC Order Numbers
Table 15-1 shows the MC order numbers for the available package types.
Table 15-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC805P18P (Standard)
0 °C to 70 °C
MC68HC805P18DW (Standard)
0 °C to 70 °C
MC68HC805P18CP (Extended)
–40 °C to +85 °C
MC68HC805P18CDW (Extended)
–40 °C to +85 °C
MC68HC805P18MP (Automotive)
–40 °C to +125 °C
MC68HC805P18MDW (Automotive)
–40 °C to +125 °C
P = Plastic Dual In-Line Package
DW = Small Outline (Wide Body) Package
7
8
9
10
11
12
13
14
A
16
17
18
19
20
ORDERING INFORMATION
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
2
APPENDIX A
EMULATION
3
4
Freescale Semiconductor, Inc...
This appendix discusses the functional differences between the P-series devices.
The MC68HC805P18 can be used to emulate the following devices:
MC68HC05P1A
MC68HC05P7
MC68HC05P2
MC68HC05P7A
MC68HC05P3
MC68HC05P8
MC68HC05P4
MC68HC05P9
MC68HC05P4A
MC68HC705P9
MC68HC05P6
MC68HC05P10
MC68HC705P6
MC68HC05P18
These functional differences will be summarized in:
Table A-1. Elements of Memory
Table A-2. Memory Breakdown by Types
Table A-3. P-Series Features
Table A-4. Mask Options
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
EMULATION
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
Table A-1. Elements of Memory
2
Device
RAM
User ROM
EPROM
EEPROM
User
EEPROM
ROM
Security
3
P1A
128 b
0080-00FF
R 2320 b
0020-004F
0100-08FF*
N
N
N
N
P2
96 b
00A0-00FF
R 3088 b
0020-004F
1300-1EFF
N
N
N
N
P3
128 b
0080-00FF
R 3072 b
0020-004F
0300-0EFF
N
128 b
0100-017F
N
N
705P3
128 b
0080-00FF
N
3072 b
0020-004F
0300-0EFF
128 b
0100-017F
N
N
P4/P4A
176 b
0050-00FF
R 4160 b
0020-004F
0100-10FF
N
N
N
N/Y
P6
176 b
0050-00FF
R 4672 b
0020-004F
0100-10FF*
N
N
N
N
705P6
176 b
0050-00FF
N
4672 b
0020-004F
0100-12FF*
N
N
N
12
P7/P7A
128 b
0080-00FF
R 2112 b
0020-004F
0100-08FF*
N
N
N
N/Y
13
P8
112 b
0090-00FF
R 2064 b
1680-1E7F
N
32 b
0030-004F
N
N
14
P9/P9A
128 b
0080-00FF
R 2112 b
0020-004F
0100-08FF
N
N
N
N/Y
705P9
128 b
0080-00FF
N
2112 b
0020-004F
0100-08FF*
N
N
N
P10
128 b
0080-00FF
R 4160 b
0020-004F
0100-10FF
N
N
N
N
P18
192 b
0050-010F
R 8064 b
0020-004F
1FC0-3EFF
N
128 b
0140-01BF
N
N
805P18
192 b
0050-010F
N
N
128 b
0140-01BF
8064 b
0020-004F
1FC0-3EFF
Y
4
Freescale Semiconductor, Inc...
5
6
7
8
9
10
11
A
16
17
18
19
20
EMULATION
A-2
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MC68HC805P18
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GENERAL RELEASE SPECIFICATION
Table A-2. Memory Breakdown by Types
Range
P1a
P2
P3/
705P3
P4/
P4a
P6
705
P6
P7/
P7a
0020–004F
ROM
ROM
ROM/E
ROM
ROM
ROM
ROM
0030–004F
P9/
705P9
P10
P18
805
P18
ROM/E
ROM
ROM
UEE
RAM
RAM
RAM
0080–008F
RAM
RAM
RAM
RAM
RAM
RAM
0090–009F
RAM
RAM
RAM
RAM
RAM
RAM
00A0–00FF
RAM
RAM
RAM
RAM
RAM
RAM
0100–010F
ROM
EE
ROM
ROM
E
0110–013F
ROM
EE
ROM
ROM
0140–017F
ROM
EE
ROM
0180–01BF
ROM
01C0–02D1
2
3
EE
0050–007F
Freescale Semiconductor, Inc...
P8
8
RAM
RAM
4
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
ROM
ROME
ROM
RAM
RAM
6
E
ROM
ROME
ROM
ROM
E
ROM
ROME
ROM
EE
EE
7
ROM
ROM
E
ROM
ROME
ROM
EE
EE
ROM
ROM
ROM
E
ROM
ROME
ROM
02D2–02FF
ROM
ROM
ROM
E
ROM
ROME
ROM
0300–08FF
ROM
ROME
ROM
ROM
E
ROM
ROME
ROM
0900–0EFF
ROME
RON
ROM
E
ROM
0F00–0FEF
ROM
ROM
ROM
E
ROM
ROM
ROM
E
ROM
ROM
E
RAM
0FF0–10FF
1100–12FF
1300–167F
ROM
1680–1EFF
ROM
1F00
ROM
ROM
1F01–1FBF
ROM
ROM
ROM
1FC0–1FEF
ROM
ROM
ROM
5
8
ROM
9
10
11
12
13
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
1FF0–3EFF
14
ROM
UEE
ROM
UEE
3F00–3F01
UEE
3F02–3FEF
ROM
NOTE: I/O registers are common to all parts so they are not included in the table. There are an additional 16 bytes
of user vectors in the memory map for each device.
E = EPROM
EE = EEPROM
PEE = User EEPROM
A
16
17
18
19
20
EMULATION
Rev. 1.0
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GENERAL RELEASE SPECIFICATION
8
Table A-3. P-Series Features
Devices
Mask Option
MOR
A/D
LVR
High Current
P1A
Y
N
N
N
Y
P2
Y
N
N
N
N
P3/705P3
Y/N
N/Y
N
N
N
P4/P4A
Y
N
N
N
N/Y
P6/705P6
Y/N
N/Y
Y
N
N
P7/P7A
Y
N
N
N
N/Y
P8
Y
N
Y
N
N
P9/705P9/P9A
Y/N/Y
N/Y/N
Y
N
N/N/Y
P10
Y
N
N
N
N
P18/805P18
Y/N
N/Y
Y
Y
Y
2
3
4
Freescale Semiconductor, Inc...
5
6
7
8
9
Table A-4. Mask Options
10
Devices
XTAL/RC
SIOP
Clock Rate
SIOP
MSB/LSB
Port A
PU/INT
STOP
to HALT
11
P1A
Y
N
N
Y
Y
P2
Y
N
N
N
N
P3
N
N
N
N
N
P4/P4A
Y
N
Y
N/Y
N/Y
P6
Y
Y
Y
N
Y
P7/P7A
Y
N
Y
N/Y
N/Y
P8
N
N
N
N
N
P9/P9A
N
N
Y
N/Y
N/Y
P10
Y
N
Y
Y
N
P18
N
Y*
Y
Y
Y
12
13
14
A
16
17
* The MC68HC05P18 and MC68HC805P18 have selectable clock rates that are four times as fast as the
MC68HC05P6 selectable rates.
18
19
20
EMULATION
A-4
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MC68HC805P18
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
$0F
Read:
Bit 7
6
5
4
3
2
1
Bit 0
0
1
0
0
1
0
OPTCOP
OPTIRQ
2
Write:
Reset:
Unaffected by reset
3
4
Freescale Semiconductor, Inc...
Figure A-1. MC68HC705P3 Mask Option Register
$900
Read:
8
Bit 7
6
5
4
3
2
1
Bit 0
—
RC
SWAIT
SPR1
SPR0
LSBF
IRQ
COP
5
6
Write:
Reset:
7
Unaffected by reset
8
Figure A-2. MC68HC705P6 Mask Option Register
9
$900
Read:
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
SIOP
IRQ
COP
Write:
10
11
Reset:
Unaffected by reset
12
Figure A-3. MC68HC705P9 Mask Option Register
Read:
13
Bit 7
6
5
4
3
2
1
Bit 0
CLKOUT
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ
COPEN
MOR1
Write:
Reset:
Read:
Unaffected by reset
A
16
Bit 7
6
5
4
3
2
1
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
17
18
MOR2
Write:
Reset:
14
Unaffected by reset
Figure A-4. MC68HC805P18 Mask Option Register
EMULATION
Rev. 1.0
For More Information On This Product,
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19
20
Freescale Semiconductor, Inc...
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Home Page:
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claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
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68HC805P18GRS/D
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