Preliminary NJU6645 16-CHARACTER 6-LINE LCD DRIVER with JAPANESE KANJI ROM ! GENERAL DESCRIPTION The NJU6645 is a 16-character 6-line (16x16dots size Japanese Kanji) or 96 x 256 dots LCD driver with Japanese Kanji ROM. It contains 8-bit parallel or serial interface, instruction decoder, character generator ROM/RAM, common and segment drivers, bleeder resistor and voltage booster. The NJU6645 supports the character font of JIS level-1 and level-2, non-kanji and half-size character and symbol. It is suitable for the low operation voltage and low power applications by low operating voltage 2.4 to 3.6V. ! PACKAGE OUTLINE NJU6645CJ ! FEATURES ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 16-character 6-line Kanji Character Display or 96 x 256 dots Graphic Display LCD controller driver LCD Driver Output : 96-common x 256-segment + 2-icon com 8-bit Parallel Interface Serial Interface Display Data RAM 1,536 bits at Full-size 96 Characters Character Generator ROM :JIS Level-1 Kanji 16 x 16 dots 2,965 fonts :JIS Level-2 Kanji 16 x 16 dots 3,388 fonts :JIS Non-Kanji 16 x 16 dots 524 fonts :Half Size Display 8 x 16 dots 256 fonts Character Generator RAM 24,576 bits 8 x 16 dots 192 fonts Icon Display RAM 512 bits Maximum 512 icons Duty Ratio 1/18, 1/34, 1/50, 1/66, 1/82, 1/98 (Programmable) Bias Ratio 1/4 ~ 1/11 (Programmable) Common and Segment driver Location order Select Function (Programmable) Common Wiring Select Function Useful Instruction Set RE Flag Set, Status Read, Display Clear, Cursor Home, Display Control, Stand-by, Cursor Control, Display / Entry Mode, Scroll Start Line, Scroll Start Row, Display Start Line, Display Duty Ratio, N-line inversion, Driver Output Control, Oscillation Control, Discharge, Boost Level, Bias Ratio, Electrical Volume, Power Control, RAM Address Set, Address Shift, RAM Data Writing / Reading Built-in Voltage Boost 2 to 6-time Built-in Electrical Volume 128-step Oscillation Circuit External Resistor Required Built-in Bleeder Resistor Operating Voltage +2.4 to 3.6V LCD Driving Voltage +4.5 to 17.0V Operation Temperature Range -40 to +85°C C-MOS Technology (P-sub ) Package Outline Bump Chip Ver.2009-05-20 -1- 261:DUMMY85 262:DUMMY86 263:DUMMY87 264:COM48 265:COM49 311:COM95 312:COMMK1 313:DUMMY88 315:DUMMY90 ! PAD ALIGNMENT 314:DUMMY89 Preliminary NJU6645 ALI_B1 ALI_A2 316:DUMMY91 260:DUMMY84 317:DUMMY92 259:DUMMY83 318:DUMMY93 258:DUMMY82 319:SEG255 257:C5- 320:SEG254 256:C5- X Y TOP VIEW NJU6645 Chip Size Chip Thickness Bump Size Bump Material -2- : 14.16mm x 3.16mm (T.B.D.) : 625µm±25µm : 31µm x 130µm : Au 632:DUMMY102 631:DUMMY101 630:DUMMY100 628:COM0 Chip Center Pad Pitch Bump Height 629:COMMK0 1:DUMMY1 ALI_A1 582:COM46 2:DUMMY2 577:DUMMY96 ALI_B2 581:COM47 3:DUMMY3 576:DUMMY95 580:DUMMY99 4:TESTOUT 575:DUMMY94 579:DUMMY98 5:DUMMY4 574:SEG0 578:DUMMY97 573:SEG1 : X=0µm, Y=0µm : 50µm pitch : 17.5µm(Typ.) Ver.2009-05-20 Preliminary NJU6645 Alignment Mark 70µm - Type A Center Coordinates : ALI_A1 (X, Y) = (-6682, -1447) : ALI_A2 (X, Y) = (6682, -1447) 70µm - Type B 110µm Center Coordinates : ALI_B1 (X, Y) = (6710, 1427) : ALI_B2 (X, Y) = (-6710, 1427) 70µm Ver.2009-05-20 -3- NJU6645 Preliminary ! PAD COORDINATES 1 PAD No. PAD name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DUMMY1 DUMMY2 DUMMY3 TESTOUT DUMMY4 DUMMY5 SEL68 DUMMY6 VPUP DUMMY7 PS DUMMY8 VPUP DUMMY9 CSEL DUMMY10 DUMMY11 RSTb RSTb DUMMY12 DUMMY13 CSb CSb DUMMY14 DUMMY15 RS RS DUMMY16 VPDN DUMMY17 WRb/RW WRb/RW DUMMY18 DUMMY19 RDb/E RDb/E DUMMY20 VPUP DUMMY21 D0 D0 DUMMY22 DUMMY23 D1 D1 DUMMY24 DUMMY25 D2 D2 DUMMY26 -4- X= µm -6475 -6425 -6375 -6325 -6275 -6225 -6175 -6125 -6075 -6025 -5975 -5925 -5875 -5825 -5775 -5725 -5675 -5625 -5575 -5525 -5475 -5425 -5375 -5325 -5275 -5225 -5175 -5125 -5075 -5025 -4975 -4925 -4875 -4825 -4775 -4725 -4675 -4625 -4575 -4525 -4475 -4425 -4375 -4325 -4275 -4225 -4175 -4125 -4075 -4025 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DUMMY27 D3 D3 DUMMY28 DUMMY29 D4 D4 DUMMY30 DUMMY31 D5 D5 DUMMY32 DUMMY33 D6/SCL D6/SCL DUMMY34 DUMMY35 D7/SDA D7/SDA DUMMY36 OSC2 OSC2 DUMMY37 VDD VDD VDD VDD VDD VDD DUMMY38 OSC1 OSC1 DUMMY39 VSS VSS VSS VSS VSS VSS DUMMY40 DUMMY41 VLCD VLCD VLCD VLCD VLCD VLCD DUMMY42 DUMMY43 V1 -3975 -3925 -3875 -3825 -3775 -3725 -3675 -3625 -3575 -3525 -3475 -3425 -3375 -3325 -3275 -3225 -3175 -3125 -3075 -3025 -2975 -2925 -2875 -2825 -2775 -2725 -2675 -2625 -2575 -2525 -2475 -2425 -2375 -2325 -2275 -2225 -2175 -2125 -2075 -2025 -1975 -1925 -1875 -1825 -1775 -1725 -1675 -1625 -1575 -1525 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 Ver.2009-05-20 Preliminary NJU6645 ! PAD COORDINATES 2 PAD No. PAD name 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 V1 V1 V1 V1 DUMMY44 DUMMY45 V2 V2 V2 V2 V2 DUMMY46 DUMMY47 V3 V3 V3 V3 V3 DUMMY48 DUMMY49 V4 V4 V4 V4 V4 DUMMY50 DUMMY51 VREG VREG VREG VREG VREG DUMMY52 DUMMY53 VREF VREF VREF VREF DUMMY54 DUMMY55 VBA VBA VBA VBA DUMMY56 DUMMY57 VSS VSS VSS VSS Ver.2009-05-20 X= µm -1475 -1425 -1375 -1325 -1275 -1225 -1175 -1125 -1075 -1025 -975 -925 -875 -825 -775 -725 -675 -625 -575 -525 -475 -425 -375 -325 -275 -225 -175 -125 -75 -25 25 75 125 175 225 275 325 375 425 475 525 575 625 675 725 775 825 875 925 975 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 VSS VSS DUMMY58 DUMMY59 VOUT VOUT VOUT VOUT VOUT VOUT DUMMY103 DUMMY104 VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT DUMMY60 DUMMY61 VEE VEE VEE VEE VEE VEE DUMMY62 DUMMY63 C1+ C1+ C1+ C1+ C1+ C1+ DUMMY64 DUMMY65 C1C1C1C1C1C1DUMMY66 DUMMY67 C2+ C2+ C2+ C2+ C2+ 1025 1075 1125 1175 1225 1275 1325 1375 1425 1475 1525 1575 1625 1675 1725 1775 1825 1875 1925 1975 2025 2075 2125 2175 2225 2275 2325 2375 2425 2475 2525 2575 2625 2675 2725 2775 2825 2875 2925 2975 3025 3075 3125 3175 3225 3275 3325 3375 3425 3475 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -5- NJU6645 Preliminary ! PAD COORDINATES 3 PAD No. PAD name 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 C2+ DUMMY68 DUMMY69 C2C2C2C2C2C2DUMMY70 DUMMY71 C3+ C3+ C3+ C3+ C3+ C3+ DUMMY72 DUMMY73 C3C3C3C3C3C3DUMMY74 DUMMY75 C4+ C4+ C4+ C4+ C4+ C4+ DUMMY76 DUMMY77 C4C4C4C4C4C4DUMMY78 DUMMY79 C5+ C5+ C5+ C5+ C5+ C5+ DUMMY80 -6- X= µm 3525 3575 3625 3675 3725 3775 3825 3875 3925 3975 4025 4075 4125 4175 4225 4275 4325 4375 4425 4475 4525 4575 4625 4675 4725 4775 4825 4875 4925 4975 5025 5075 5125 5175 5225 5275 5325 5375 5425 5475 5525 5575 5625 5675 5725 5775 5825 5875 5925 5975 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 DUMMY81 C5C5C5C5C5C5DUMMY82 DUMMY83 DUMMY84 DUMMY85 DUMMY86 DUMMY87 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 6025 6075 6125 6175 6225 6275 6325 6375 6425 6475 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1352 -1302 -1252 -1202 -1152 -1102 -1052 -1002 -952 -902 -852 -802 -752 -702 -652 -602 -552 -502 -452 -402 -352 -302 -252 -202 -152 -102 -52 -2 48 98 148 198 248 298 348 398 448 498 548 598 Ver.2009-05-20 Preliminary NJU6645 ! PAD COORDINATES 4 PAD No. PAD name 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COMMK1 DUMMY88 DUMMY89 DUMMY90 DUMMY91 DUMMY92 DUMMY93 SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 SEG248 SEG247 SEG246 SEG245 SEG244 SEG243 SEG242 SEG241 SEG240 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 Ver.2009-05-20 X= µm 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6525 6475 6425 6375 6325 6275 6225 6175 6125 6075 6025 5975 5925 5875 5825 5775 5725 5675 5625 5575 5525 5475 5425 5375 5325 5275 5225 5175 5125 5075 5025 4975 4925 4875 4825 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 648 698 748 798 848 898 948 998 1048 1098 1148 1198 1248 1298 1348 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 SEG199 SEG198 SEG197 SEG196 SEG195 SEG194 SEG193 SEG192 SEG191 SEG190 SEG189 SEG188 SEG187 SEG186 SEG185 SEG184 SEG183 SEG182 SEG181 SEG180 SEG179 SEG178 SEG177 SEG176 SEG175 SEG174 4775 4725 4675 4625 4575 4525 4475 4425 4375 4325 4275 4225 4175 4125 4075 4025 3975 3925 3875 3825 3775 3725 3675 3625 3575 3525 3475 3425 3375 3325 3275 3225 3175 3125 3075 3025 2975 2925 2875 2825 2775 2725 2675 2625 2575 2525 2475 2425 2375 2325 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 -7- NJU6645 Preliminary ! PAD COORDINATES 5 PAD No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 -8- PAD name SEG173 SEG172 SEG171 SEG170 SEG169 SEG168 SEG167 SEG166 SEG165 SEG164 SEG163 SEG162 SEG161 SEG160 SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153 SEG152 SEG151 SEG150 SEG149 SEG148 SEG147 SEG146 SEG145 SEG144 SEG143 SEG142 SEG141 SEG140 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 X= µm 2275 2225 2175 2125 2075 2025 1975 1925 1875 1825 1775 1725 1675 1625 1575 1525 1475 1425 1375 1325 1275 1225 1175 1125 1075 1025 975 925 875 825 775 725 675 625 575 525 475 425 375 325 275 225 175 125 75 25 -25 -75 -125 -175 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 -225 -275 -325 -375 -425 -475 -525 -575 -625 -675 -725 -775 -825 -875 -925 -975 -1025 -1075 -1125 -1175 -1225 -1275 -1325 -1375 -1425 -1475 -1525 -1575 -1625 -1675 -1725 -1775 -1825 -1875 -1925 -1975 -2025 -2075 -2125 -2175 -2225 -2275 -2325 -2375 -2425 -2475 -2525 -2575 -2625 -2675 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 Ver.2009-05-20 Preliminary NJU6645 ! PAD COORDINATES 6 PAD No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 Ver.2009-05-20 PAD name SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 X= µm -2725 -2775 -2825 -2875 -2925 -2975 -3025 -3075 -3125 -3175 -3225 -3275 -3325 -3375 -3425 -3475 -3525 -3575 -3625 -3675 -3725 -3775 -3825 -3875 -3925 -3975 -4025 -4075 -4125 -4175 -4225 -4275 -4325 -4375 -4425 -4475 -4525 -4575 -4625 -4675 -4725 -4775 -4825 -4875 -4925 -4975 -5025 -5075 -5125 -5175 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DUMMY94 DUMMY95 DUMMY96 DUMMY97 DUMMY98 DUMMY99 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 -5225 -5275 -5325 -5375 -5425 -5475 -5525 -5575 -5625 -5675 -5725 -5775 -5825 -5875 -5925 -5975 -6025 -6075 -6125 -6175 -6225 -6275 -6325 -6375 -6425 -6475 -6525 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1348 1298 1248 1198 1148 1098 1048 998 948 898 848 798 748 698 648 598 548 498 448 398 348 298 248 -9- NJU6645 Preliminary ! PAD COORDINATES 7 PAD No. PAD name 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMMK0 DUMMY100 DUMMY101 DUMMY102 - 10 - X= µm -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 198 148 98 48 -2 -52 -102 -152 -202 -252 -302 -352 -402 -452 -502 -552 -602 -652 -702 -752 -802 -852 -902 -952 -1002 -1052 -1102 -1152 -1202 -1252 -1302 -1352 Ver.2009-05-20 Preliminary NJU6645 ! LCD DISPLAY EXAMPLE - Mix display (Full-size / Half-size / Graphics) Ver.2009-05-20 - 11 - Preliminary NJU6645 ! BLOCK DIAGRAM Display Counter N-line Inversion Oscillator Circuit Timing Generator Character Generator RAM(CGRAM) 24,576-bit Icon Display RAM (MKRAM) 512-bit Common Driver OSC1 OSC2 Character Generator ROM (Full-size FCGROM) 2M-bit (Half-size HCGROM) 32k-bit 256-bit Shift Register RSTb Reset Circuit Data Register Full/Half/ODD/EVEN Discrimination Circuit Segment Driver Graphics Counter 98-bit Shift Register Display Data RAM(DD RAM) 1,536-bit Data Register Instruction Register Interface Instruction Decoder Address Counter PS SEL68 CSb RS WRb/RW RDb/E D7/SDA D6/SCL D5~D0 CSEL TESTOUT VDD VSS VPUP VPDN Attribute, Cursor, Inversion Reference Voltage VBA VOUT VREG VREF + - + Gain Control C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VEE E.V.R. Boost Level Register + - VLCD + - V1 + - V2 + - V3 + - V4 E.V.R. Register Voltage Booster VDCOUT - 12 - Ver.2009-05-20 COM0~ COM95, COMM0, COMM1 SEG0~ SEG255 Preliminary NJU6645 ! TERMINAL DESCRIPTION No. SYMBOL I/O 74 to 79 VDD Power 84 to 89, 147 to 152 141 to 144 135 to 138 128 to 132 VSS Power VBA VREF VREG Output Input Output 172 to 177 VEE Power 155 to 160 VOUT Power 163 to 169 VDCOUT Output 92 to 97 100 to 104 107 to 111 114 to 118 VLCD V1 V2 V3 121 to 125 V4 9,13,38 VPUP Power/ Output 29 VPDN Power/ Output 180 to 185 188 to 193 196 to 201 204 to 209 212 to 217 220 to 225 228 to 233 236 to 241 244 to 249 252 to 257 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5- Output 81,82 OSC1 Input 71,72 OSC2 Input 18,19 RSTb Input 15 CSEL Input Ver.2009-05-20 Power/ Output FUNCTION Power Supply (Logic, I/F) VDD=2.4 to 3.6V GND (Logic, I/F, High voltage) VSS=0V Reference-Voltage Generator Output Voltage Regulator Input Voltage Regulator Output Voltage Booster Input VEE is normally connected to VDD. High Voltage Power Supply Input (External supply) Input of LCD power supply circuit. Voltage Booster Output Output of voltage booster circuit. LCD Bias Voltages When the internal LCD power supply is used, internal LCD bias voltages (VLCD and V1~V4) are activated by the “Power Control” instruction. Stabilizing capacitors are required between each bias voltage and VSS. When the external LCD power supply is used, LCD bias voltages are externally supplied on VLCD, V1, V2, V3 and V4 individually, with the following relation maintained : VSS<V4<V3<V2<V1<VDD VPUP is internally connected to VDD to fix SEL68 or PS or CSEL to “H” if necessary, and cannot be used as main power supply. VPUP should be open if not used. VPDN is internally connected to VSS to fix SEL68 or PS or CSEL to “L” if necessary, and cannot be used as main GND. VPDN should be open if not used. Capacitor Connection for Voltage Booster Resistor Connection for Oscillation Circuit When the internal oscillator is used, connect OSC1 and VDD with an external resistor. And fix OSC2 to “H” or “L”. External Clock Input When the internal oscillator is not used, input external clock to OSC2 and leave OSC1 open. Reset Active “L” COM Output Select “L” : Both sides wiring “H” : Comb wiring - 13 - Preliminary NJU6645 No. SYMBOL I/O 11 PS Input 7 SEL68 Input 22,23 CSb Input 26,27 RS Input 31,32 WRb/RW Input 35,36 RDb/E Input 68,69 64,65 60,61 56,57 52,53 48,49 44,45 40,41 D7/SDA D6/SCL D5 D4 D3 D2 D1 D0 Input/ Output - 14 - FUNCTION Parallel / Serial Interface Mode Select “L” : Serial Interface “H” : Parallel Interface *In the serial interface mode (PS=”L”) D5 to D0 should be fixed to “H” or “L”. MPU Mode Select Parallel Interface (PS=”H”) “L” : 80-series “H” : 68-series Serial Interface (PS=”L”) Not used. SEL68 should be fixed to “H” or “L”. Chip Select Active “L” Register Select This signal interprets transferred data as display data or instruction. “L” : Instruction “H” : Display Data 80-series MPU Interface (PS=”H”, SEL68=”L”) Data Write (WRb) Signal Active “L” 68-series MPU Interface (PS=”H”, SEL68=”H”) Data Read or Write (RW) Signal “L” : Write “H” : Read Serial Interface (PS=”L”) Data Read or Write (RW) Signal 80-series MPU Interface (PS=”H”, SEL68=”L”) Data Read (RDb) Signal Active “L” 68-series MPU Interface (PS=”H”, SEL68=”H”) Enable Signal Active “H” Serial Interface (PS=”L”) Not used. RDb/E should be fixed to “H” or “L”. Parallel Interface (PS=”H”) In the parallel interface mode (PS=“H”), D7 to D0 are connected to 8-bit bi-directional MPU bus. D7 to D0 : 8-bit Bi-directional Bus Serial Interface (PS=”L”) D7 : Serial Data (SDA) D6 : Serial Clock (SCL) D5 to D0 should be fixed to “H” or “L”. Ver.2009-05-20 Preliminary No. SYMBOL SEG0~ 319 to 574 SEG255 264 to 311, COM0~ 581 to 628 COM95 COMMK0, 629,312 COMMK1 4 TESTOUT - Ver.2009-05-20 DUMMYx I/O Output Output Output Output - NJU6645 FUNCTION Segment Drivers Segment drivers output an one level from VLCD, V2, V3 and VSS. Common Drivers Common drivers output an one level from VLCD, V1, V4 and VSS. Common Drivers for Icons For Testing Dummy PAD Dummy x is normally open. - 15 - Preliminary NJU6645 ! FUNCTION DESCRIPTION (1) MPU INTERFACE (1-1) Selection of Parallel / Serial Interface Mode The PS selects a parallel or a serial interface mode, as shown in Table 1. Table 1 Selection of Parallel / Serial Interface Mode PS I/F Mode CSb RS RDb CSb RS RDb H Parallel I/F CSb RS L Serial I/F Note) “-“ : Fix to ”H” or ”L” WRb WRb WRb SEL68 SEL68 - SDA SCL SDA SCL Data D7~D0 - (1-2) Data Recognition The data from MPU is interpreted as display data or instruction according to the combination of the RS, RDb and WRb(RW) signals, as shown in Table 2. Table 2 Data Recognition Function Read Instruction Write Instruction Read Display Data Write display Data - 16 - RS 0 0 1 1 68-series RW 1 0 1 0 80-series RDb WRb 0 1 1 0 0 1 1 0 Serial RW 1 0 1 0 Ver.2009-05-20 Preliminary NJU6645 (1-3) Selection of MPU Mode In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 3. Table 3 Selection of MPU Mode SEL68 MPU Mode H 68-series MPU L 80-series MPU CSb CSb CSb RS RS RS RDb E RDb WRb RW WRb Data D7~D0 D7~D0 When the CSb signal is “H”, the interface is reset. The data of one character is processed by writing two times. In the DDRAM data writing, CSb is required to change to “H” once every two times. Because, it is recognized as upper 1-byte after CSb is changed from “H” to “L”. The data is latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the 68-series MPU mode. In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after writing display data or instruction. Therefore a dummy data is read out by the 1st “Display Data Read” instruction. After that, the display data is read out from a specified address by the 2nd instruction. When the RS switches, it should be CSb="H". • 80-series parallel data transmission (PS=”H”, SEL68=”L”) <Write> RS (Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte. CSb WRb D7~D0 (Data bus direction) <Read> Input RS CSb RDb D7~D0 1st reading out is dummy. (Data bus direction) Input Output Input Output Input Output Input The data bus is output at CSb=”L” and RDb=”L”. Ver.2009-05-20 - 17 - Preliminary NJU6645 • 68-series parallel data transmission (PS=”H”, SEL68=”H”) <Write> RS RW (Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte. CSb E D7~D0 (Data bus direction) <Read> Input RS RW CSb E D7~D0 1st reading out is dummy. (Data bus direction) Input Output Input Output Input Output Input The data bus is output at RW=”H”, CSb=”L” and E=”H”. - 18 - Ver.2009-05-20 Preliminary NJU6645 (1-4) Serial Interface The serial interface is transmitted with 5-line. While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is inactive (CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized. The data is interpreted as writes or reads according to the RS. 8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,…, and D0, and converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on the SDA is interpreted as display data or instruction according to the RS. When the CSb signal is “H”, the interface is reset. The data of 1-character is processed by writing 2-byte. In the DDRAM data writing, CSb is required to change to “H” once every 2-bytes. Because, it is recognized as 1-byte after CSb is changed from “H” to “L”. Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. In the read mode, selected address RAM data is read out after 1-dummy as for parallel interface. When the RS and RW switches, it should be CSb="H". Ver.2009-05-20 - 19 - Preliminary NJU6645 • Serial data transmission (PS=”L”) <Write> RW (Data bus direction) Input The data bus is Input at RW=”L”. RS (Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte. CSb SCL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDA <Read> RW (Data bus direction) Output Input The data bus is output at RW=”H” and CSb=”L”. RS CSb SCL - 20 - DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDA Ver.2009-05-20 Preliminary NJU6645 (2) ADDRESS COUNTER The NJU6645 has the address counter of 12-bit for read/write of RAM data. The address is set by "RAM address set" instruction. In case of the RDM=”0”, the address is incremented after the RAM data writing and reading. In case of the RDM=”1”, the address is incremented only after the RAM data writing. The address doesn't change after the RAM data reading. The address shifts as follows within range of the address DDRAM, MKRAM, and CGRAM. The DDRAM address shifts in each line. DDRAM (1-line) DDRAM (2-line) DDRAM (3-line) DDRAM (4-line) DDRAM (5-line) DDRAM (6-line) MKRAM CGRAM : (000)H → (001)H → --- → (01F)H → (000)H : (020)H → (021)H → --- → (03F)H → (020)H : (040)H → (041)H → --- → (05F)H → (040)H : (060)H → (061)H → --- → (07F)H → (060)H : (080)H → (081)H → --- → (09F)H → (080)H : (0A0)H → (0A1)H → --- → (0BF)H → (0A0)H : (100)H → (101)H → --- → (13F)H → (100)H : (200)H → (201)H → --- → (DFF)H → (200)H The address is shifted to +1 or -1 by "address shift (ARL)" instruction. When ARL="0" is input, whenever it is input the address is shifted -1. When ARL="1" is input, whenever it is input the address is shifted +1. The address shifts as follows within range of the address DDRAM, MKRAM and CGRAM. DDRAM (1-line) DDRAM (2-line) DDRAM (3-line) DDRAM (4-line) DDRAM (5-line) DDRAM (6-line) MKRAM CGRAM Ver.2009-05-20 : (000)H ↔ (001)H ↔ --- ↔ (01F)H ↔ (000)H : (020)H ↔ (021)H ↔ --- ↔ (03F)H ↔ (020)H : (040)H ↔ (041)H ↔ --- ↔ (05F)H ↔ (040)H : (060)H ↔ (061)H ↔ --- ↔ (07F)H ↔ (060)H : (080)H ↔ (081)H ↔ --- ↔ (09F)H ↔ (080)H : (0A0)H ↔ (0A1)H ↔ --- ↔ (0BF)H ↔ (0A0)H : (100)H ↔ (101)H ↔ --- ↔ (13F)H ↔ (100)H : (200)H ↔ (201)H ↔ --- ↔ (DFF)H ↔ (200)H - 21 - Preliminary NJU6645 (3) DATA RAM (3-1) RAM Address Map Display Data RAM (DDRAM), Character Generator RAM(CGRAM), and Icon Data RAM(MKRAM) are stored at the following addresses. The address is set in the address counter by "RAM address set" instruction. RAM Address Map BEH BFH C0H FEH FFH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * DDRAM address (1 address = 11-bit) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * MKRAM address (1 address = 7-bit) D0 * * * * * * * * * * * * * * * * * * * * * * * ----- 3EH 3FH 40H --- RAM ADDRESS – LOWER 8bit 00H 01H 02H 03H EH FH D2 D1 DH D4 D3 ----- D7 D6 D5 D1 D0 D3 D2 D6 D5 D4 D0 D7 D5 D4 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D10 D9 D3 D2 D1 RAM ADDRESS – UPPER 4bit 1H 2H 0H * * * * * * * * * * * * * * CGRAM address (1 address = 8-bit) --- DDRAM (Display Data RAM) --- MKRAM (Icon RAM) --- CGRAM (Character Generator RAM) * : Invalid Data - 22 - Ver.2009-05-20 * * * * * * * * * * * * * * * * * * * * * * * Preliminary NJU6645 (3-2) DDRAM Display Data RAM (DDRAM) is RAM that memorizes the attribute display data, data for the capital letters and small letters distinction, and the character-code data. RAM address uses "000H" ~ "0BFH ". The RAM Capacity has 192 addresses of 11-bit/address. At this time, the full-size data is using 2 addresses for a character, and the half-size data is using one address for a character. In the DDRAM address and the position where the panel is displayed, there are relations of the following. Correspondence of display position on panel and DDRAM address (SEL1=”0", SEL2=”0") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 000 020 040 060 080 0A0 001 021 041 061 081 0A1 2-digit 002 022 042 062 082 0A2 003 023 043 063 083 0A3 3-digit 004 024 044 064 084 0A4 005 025 045 065 085 0A5 4-digit 006 026 046 066 086 0A6 007 027 047 067 087 0A7 5-digit 008 028 048 068 088 0A8 6-digit 7-digit 8-digit 009 00A 00B 00C 00D 00E 029 02A 02B 02C 02D 02E 049 04A 04B 04C 04D 04E 069 06A 06B 06C 06D 06E 089 08A 08B 08C 08D 08E 0A9 0AA 0AB 0AC 0AD 0AE 00F 02F 04F 06F 08F 0AF 9-digit 010 030 050 070 090 0B0 011 031 051 071 091 0B1 10-digit 012 032 052 072 092 0B2 013 033 053 073 093 0B3 11-digit 014 034 054 074 094 0B4 015 035 055 075 095 0B5 12-digit 016 036 056 076 096 0B6 017 037 057 077 097 0B7 13-digit 018 038 058 078 098 0B8 019 039 059 079 099 0B9 14-digit 01A 01B 03A 03B 05A 05B 07A 07B 09A 09B 0BA 0BB 15-digit 01C 03C 05C 07C 09C 0BC 01D 03D 05D 07D 09D 0BD 16-digit 01E 03E 05E 07E 09E 0BE 01F 03F 05F 07F 09F 0BF Correspondence of display position on panel and DDRAM address (SEL1=”1", SEL2=”0") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 0A0 080 060 040 020 000 0A1 081 061 041 021 001 2-digit 0A2 082 062 042 022 002 0A3 083 063 043 023 003 3-digit 0A4 084 064 044 024 004 0A5 085 065 045 025 005 4-digit 0A6 086 066 046 026 006 0A7 087 067 047 027 007 5-digit 0A8 088 068 048 028 008 6-digit 7-digit 8-digit 0A9 0AA 0AB 0AC 0AD 0AE 089 08A 08B 08C 08D 08E 069 06A 06B 06C 06D 06E 049 04A 04B 04C 04D 04E 029 02A 02B 02C 02D 02E 009 00A 00B 00C 00D 00E 0AF 08F 06F 04F 02F 00F 9-digit 0B0 090 070 050 030 010 0B1 091 071 051 031 011 10-digit 0B2 092 072 052 032 012 0B3 093 073 053 033 013 11-digit 0B4 094 074 054 034 014 0B5 095 075 055 035 015 12-digit 0B6 096 076 056 036 016 0B7 097 077 057 037 017 13-digit 0B8 098 078 058 038 018 0B9 099 079 059 039 019 14-digit 0BA 0BB 09A 09B 07A 07B 05A 05B 03A 03B 01A 01B 15-digit 0BC 09C 07C 05C 03C 01C 0BD 09D 07D 05D 03D 01D 16-digit 0BE 09E 07E 05E 03E 01E 0BF 09F 07F 05F 03F 01F Correspondence of display position on panel and DDRAM address (SEL1=”0", SEL2=”1") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 01F 03F 05F 07F 09F 0BF 2-digit 3-digit 4-digit 01E 01D 01C 01B 01A 019 03E 03D 03C 03B 03A 039 05E 05D 05C 05B 05A 059 07E 07D 07C 07B 07A 079 09E 09D 09C 09B 09A 099 0BE 0BD 0BC 0BB 0BA 0B9 018 038 058 078 098 0B8 5-digit 017 037 057 077 097 0B7 016 036 056 076 096 0B6 6-digit 015 035 055 075 095 0B5 014 034 054 074 094 0B4 7-digit 013 033 053 073 093 0B3 012 032 052 072 092 0B2 8-digit 011 031 051 071 091 0B1 010 030 050 070 090 0B0 9-digit 10-digit 11-digit 12-digit 00F 00E 00D 00C 00B 00A 009 02F 02E 02D 02C 02B 02A 029 04F 04E 04D 04C 04B 04A 049 06F 06E 06D 06C 06B 06A 069 08F 08E 08D 08C 08B 08A 089 0AF 0AE 0AD 0AC 0AB 0AA 0A9 008 028 048 068 088 0A8 13-digit 007 027 047 067 087 0A7 006 026 046 066 086 0A6 14-digit 005 025 045 065 085 0A5 004 024 044 064 084 0A4 15-digit 003 023 043 063 083 0A3 002 022 042 062 082 0A2 16-digit 001 021 041 061 081 0A1 000 020 040 060 080 0A0 Correspondence of display position on panel and DDRAM address (SEL1=”1", SEL2=”1") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 0BF 09F 07F 05F 03F 01F 2-digit 3-digit 4-digit 0BE 0BD 0BC 0BB 0BA 0B9 09E 09D 09C 09B 09A 099 07E 07D 07C 07B 07A 079 05E 05D 05C 05B 05A 059 03E 03D 03C 03B 03A 039 01E 01D 01C 01B 01A 019 0B8 098 078 058 038 018 5-digit 0B7 097 077 057 037 017 0B6 096 076 056 036 016 6-digit 0B5 095 075 055 035 015 0B4 094 074 054 034 014 7-digit 0B3 093 073 053 033 013 0B2 092 072 052 032 012 8-digit 0B1 091 071 051 031 011 0B0 090 070 050 030 010 9-digit 10-digit 11-digit 12-digit 0AF 0AE 0AD 0AC 0AB 0AA 0A9 08F 08E 08D 08C 08B 08A 089 06F 06E 06D 06C 06B 06A 069 04F 04E 04D 04C 04B 04A 049 02F 02E 02D 02C 02B 02A 029 00F 00E 00D 00C 00B 00A 009 0A8 088 068 048 028 008 13-digit 0A7 087 067 047 027 007 0A6 086 066 046 026 006 14-digit 0A5 085 065 045 025 005 0A4 084 064 044 024 004 15-digit 0A3 083 063 043 023 003 0A2 082 062 042 022 002 16-digit 0A1 081 061 041 021 001 0A0 080 060 040 020 000 Note) The DDRAM is not initialized after the power supply turns on, therefore it is necessary to execute the "Display Clear instruction" at first. Ver.2009-05-20 - 23 - Preliminary NJU6645 (3-3) CGRAM The character generator RAM (CG RAM) stores any kinds of character pattern written by the user program to display user’s original character pattern. RAM address uses "200H" to "DFFH". The CG RAM is able to store character of 5 x 8 dot for 4 kinds. Data "1" correspond to selection as a display, and Data "0" correspond to non-selection as a display. When the character pattern stored in CGRAM is displayed, "0100H" to “015FH" of the character-code is written in DDRAM. The following tables show the relation between the CGRAM address, data, and the displayed pattern. Correspondence of character code and CGRAM address “0100” CG Address “0110” CG Address CG CG CG CG - 24 - “0105” “0106” “0107” “0108” “0109” “010A” “010B” “010C” “010D” “010E” “010F” “0111” “0112” “0113” “0114” “0115” “0116” “0117” “0118” “0119” “011A” “011B” “011C” “011D” “011E” “011F” “0121” “0122” “0123” “0124” “0125” “0126” “0127” “0128” “0129” “012A” “012B” “012C” “012D” “012E” “012F” “0131” “0132” “0133” “0134” “0135” “0136” “0137” “0138” “0139” “013A” “013B” “013C” “013D” “013E” “013F” “0141” “0142” “0143” “0144” “0145” “0146” “0147” “0148” “0149” “014A” “014B” “014C” “014D” “014E” “014F” A00 A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 AB0 AC0 AD0 AE0 AF0 B00 B10 B20 B30 B40 B50 B60 B70 B80 B90 BA0 BB0 BC0 BD0 BE0 BF0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : A0F A1F A2F A3F A4F A5F A6F A7F A8F A9F AAF ABF ACF ADF AEF AFF B0F B1F B2F B3F B4F B5F B6F B7F B8F B9F BAF BBF BCF BDF BEF BFF “0150” Address “0104” 800 810 820 830 840 850 860 870 880 890 8A0 8B0 8C0 8D0 8E0 8F0 900 910 920 930 940 950 960 970 980 990 9A0 9B0 9C0 9D0 9E0 9F0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 80F 81F 82F 83F 84F 85F 86F 87F 88F 89F 8AF 8BF 8CF 8DF 8EF 8FF 90F 91F 92F 93F 94F 95F 96F 97F 98F 99F 9AF 9BF 9CF 9DF 9EF 9FF “0140” Address “0103” 600 610 620 630 640 650 660 670 680 690 6A0 6B0 6C0 6D0 6E0 6F0 700 710 720 730 740 750 760 770 780 790 7A0 7B0 7C0 7D0 7E0 7F0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 60F 61F 62F 63F 64F 65F 66F 67F 68F 69F 6AF 6BF 6CF 6DF 6EF 6FF 70F 71F 72F 73F 74F 75F 76F 77F 78F 79F 7AF 7BF 7CF 7DF 7EF 7FF “0130” Address “0102” 400 410 420 430 440 450 460 470 480 490 4A0 4B0 4C0 4D0 4E0 4F0 500 510 520 530 540 550 560 570 580 590 5A0 5B0 5C0 5D0 5E0 5F0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 40F 41F 42F 43F 44F 45F 46F 47F 48F 49F 4AF 4BF 4CF 4DF 4EF 4FF 50F 51F 52F 53F 54F 55F 56F 57F 58F 59F 5AF 5BF 5CF 5DF 5EF 5FF “0120” Address “0101” 200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 20F 21F 22F 23F 24F 25F 26F 27F 28F 29F 2AF 2BF 2CF 2DF 2EF 2FF 30F 31F 32F 33F 34F 35F 36F 37F 38F 39F 3AF 3BF 3CF 3DF 3EF 3FF “0151” “0152” “0153” “0154” “0155” “0156” “0157” “0158” “0159” “015A” “015B” “015C” “015D” “015E” “015F” C00 C10 C20 C30 C40 C50 C60 C70 C80 C90 CA0 CB0 CC0 CD0 CE0 CF0 D00 D10 D20 D30 D40 D50 D60 D70 D80 D90 DA0 DB0 DC0 DD0 DE0 DF0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : C0F C1F C2F C3F C4F C5F C6F C7F C8F C9F CAF CBF CCF CDF CEF CFF D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F DAF DBF DCF DDF DEF DFF Ver.2009-05-20 Preliminary NJU6645 Relation between the CGRAM address, data, and the displayed pattern Character Code =”0100” (DDRAM Data) D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Upper Address 8bit=23H D5 Upper Address 8bit=22H D6 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Character Code =”0101” (DDRAM Data) Upper Address 8bit=21H D7 Lower Address 4bit Upper Address 8bit=20H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- Character Code =”0110” (DDRAM Data) D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 --- --- D5 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 --- D6 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Upper Address 8bit=41H D7 Lower Address 4bit Upper Address 8bit=40H Note) The CGRAM is not initialized after the power supply turns on, therefore it is necessary to write data into CGRAM before display on. Ver.2009-05-20 - 25 - NJU6645 Preliminary (3-4) MKRAM The icon display generator RAM (MK RAM) is RAM that stores 512 output ON/OFF settings. RAM address uses "100H" to "13FH". By storing data in this RAM, ON/OFF of each icon is set. Data "1" correspond to selection as a display, and Data "0" correspond to non-selection as a display. Correspondence of SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”0") 0 : 7 MK COM0 MK COM1 SEG 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 --- SEG248 SEG249 SEG250 SEG251 SEG252 SEG253 SEG254 SEG255 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 --- D7 D6 D5 D4 D3 D2 D1 D0 Correspondence of SEG/COM terminals and each bit of MKRAM address (SEL1=”0", SEL2=”0”) MK COM0 Address=100H Address=101H Address=102H Address=103H --- Address=11FH MK COM1 Address=120H Address=121H Address=122H Address=123H --- Address=13FH Note) The MKRAM is not initialized after the power supply turns on, therefore it is necessary to write data into CGRAM before display on. Note) Correspondence to the SEG/COM terminals are changed by the “Driver Output Control instruction” (SEL1, SEL2). Refer to “(9) COMMON SHIFT DIRECTION / SEGMENT OUTPUT DIRECTION” for details. Note) When the "Display Control instruction" is ALLON="1", display is all ON regardless of the content of RAM. (3-5) FCGROM (Full-size font ROM) Full-size font character generator ROM (FCGROM) generates 16 x 16 dots character pattern represented in 14-bit character codes. The NJU6645 has the Full-size font pattern of 8,128-font such as the JIS level-1, level-2 and non-kanji. Refer to “(14) Full-size / Half-size Font Mix Display” for the correspondence of the JIS code and the character code set to DDRAM. (3-6) HCGROM (Half-size font ROM) Half-size font character generator ROM (FCGROM) generates 8 x 16 dots character pattern represented in 8-bit character codes. The NJU6645 has the Half-size font pattern of 256-font. Refer to “(14) Full-size / Half-size Font Mix Display” for the correspondence of the character code set to DDRAM. - 26 - Ver.2009-05-20 Preliminary NJU6645 D5 D1 D0 D1 D0 D1 D2 D0 D0 D6 D1 D7 D2 D2 0 D3 D3 0 D4 D4 0 0 D6 Half-size character code 8bit D5 0 0 D3 2nd byte Half-size discrimination code D7 P1 Input Data Attribute 1 Attribute P0 0 1st byte D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 (3-7) Correspondence of the JIS Code, Input Data, RAM Data and RAM Address (3-7-1) Write Data to DDRAM (i) Half-size font character The half-size data becomes the data of one character by the input data of 2-byte, and it is stored at one RAM address. When the lower 6-bit of 1st byte is all “0”, it is recognized as half-size data. The attribute data is allocated in upper 2-bit in the 1st input byte. When the half-size font, “1” is stored in the MSB of RAM data as full-size/half-size discrimination bit. D2 D3 D4 D5 D6 Character code 8bit D7 1 DDRAM DDRAM address Full/ D10 Half Attribute P1 D9 1 Attribute D8 P0 0 ALL”0” → D10=”1” n Note) When the full-size character is overwritten by half-size character, the character is displayed unexpected. Therefore, when the full-size character is overwritten by half-size character, it must write two character's equivalent or rewrite all character. - Prohibited matter (1) In the 32nd half-size character of each line (right edge) prohibit overwriting the full-size character. (2) In the only half left of full-size character prohibit overwriting the half-size character. (3) In the only half right of full-size character prohibit overwriting the half-size (full-size) character. Ver.2009-05-20 - 27 - Preliminary NJU6645 D0 D1 D2 D3 D1 D0 D1 D0 D1 D4 D8 D4 D2 D5 D5 D2 D6 D6 D2 D7 D7 D3 D8 D0 D3 D9 D1 1 ODD/EVEN D9 D12 D7 D3 D13 D8 D10 Attribute 1 Attribute P0 0 2nd byte D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D4 D11 D10 D5 Full-size character code 14bit D6 P1 D10 1st byte Input data D4 D5 D6 D7 D0 D1 D2 D3 D11 D12 D4 D10 D13 D5 JIS code lower 7bit D2 D14 D6 0 D3 D15 JIS code upper 7bit D7 0 JIS code D4 D5 D6 D7 (ii) Full-size font character The full-size data becomes the data of 1-character by the input data of 2-byte, and it is stored at two RAM address. The attribute data is allocated in upper 2-bit in the 1st input byte. When the full-size font, “0” is stored in the MSB of RAM data as Full-size/half-size discrimination bit. And, “0” or “1” is stored in the 2nd bit of RAM as 1st byte/2nd byte discrimination data. (1st bit : “0”, 2nd bit : “1”) The character code is 14-bit stuffed into the lower bit excluding 1-bit (code : ”0”) and 9-bit (code : ”0”) of JIS codes (16-bit). The relation between each bit allocation of JIS code and input data and the RAM is as follows. In case of 2nd byte → D9=”1” In case of 1st byte → D9=”0” DDRAM address - 28 - n D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D4 D3 D5 D6 D7 Character code lower 8bit 0 Full/ Half 0 D8 D9 D10 D11 D12 D13 Character code upper 6bit 0 P0 Attribute 1 Attribute 0 P1 0 ODD/EVEN D9 DDRAM 0 Full/ Half Except for ALL”0” → D10=”0” n+1 Ver.2009-05-20 Preliminary NJU6645 When the DDRAM is written, the address is incremented as follows once a 1-byte in case of the full-size data, and once a 2-byte in case of the half-size data. 0 0 P1 P0 0 D13 D12 D11 D10 D9 D8 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 P1 P0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 P1 P0 D7 D6 D5 D4 D3 D2 D1 D0 P1 P0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 --- 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DDRAM Full-size character data 5th byte 6th byte 0 0 P1 P0 0 D13 D12 D11 D10 D9 D8 Input data Half-size character data 3rd byte 4th byte P1 P0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Full-size character data 1st byte 2nd byte n n+1 n+2 n+3 n+4 DDRAM address --- The data is recognized without fail as the first byte, immediately after CSb becomes “L”. Therefore, when the DDRAM data is written, it is necessary to make CSb = ”H” after it finishes writing the 2nd byte. CSb RS WRb D7~D0 n n+1 n+2 mth character data Address Set n n+3 n+4 m+1th character data n+5 m+2th character data (3-7-2) Write Data to CGRAM The CGRAM has 8-bit per an address, and the input value is stored in each bit as follows. The address is incremented once a 1-byte at the data writing. Relation between the interface, RAM data, and RAM address, in the CGRAM data writing CGRAM address Ver.2009-05-20 D1 D2 D3 D4 D5 D6 D0 D0 D1 D2 D3 D4 D5 D6 D7 D7 D1 D0 D0 D2 3rd byte D1 D3 D5 D4 201H D2 D3 D4 D5 D7 D1 D6 D6 D7 D0 D0 2nd byte D1 D2 D3 D4 200H D2 D3 D4 D6 D5 D5 D6 RAM data D7 Input data D7 1st byte --- --- 202H - 29 - Preliminary NJU6645 (3-7-3) Write Data to MKRAM The CGRAM has 8-bit per an address, and the input value is stored in each bit as follows. The address is incremented once a 1-byte at the data writing. Relation between the interface, RAM data, and RAM address, in the MKRAM data writing 100H D1 D2 D3 D4 D5 D6 D7 D0 D0 D1 D2 D3 D4 D5 D6 D7 D1 D0 D0 D2 3rd byte D1 D3 D4 D5 D6 D7 101H D2 D3 D4 D5 D6 D7 D1 D0 D0 D2 D3 D4 2nd byte D1 D2 D3 D5 D6 MKRAM address D4 D5 D6 RAM data D7 Input data D7 1st byte --- --- 102H (3-7-4) Write to Instruction Register The instruction set is stored in the internal instruction register by the 8-bit input in the state of RS=”0”, RW=”0”. The instruction code is applied to the item corresponding to the RE register set beforehand. Refer to "(20) Instruction table" for the correspondence of input data and the instruction. Write to instruction Register D0 D1 D2 D3 D4 D5 D6 D7 Instruction data - 30 - D0 D3 D3 D0 D4 D4 D1 D5 D5 D1 D6 D6 Instruction discrimination D2 D7 Instruction register D2 Input data D7 Instruction code Instruction register Ver.2009-05-20 Preliminary NJU6645 (3-8) Read Data from RAM The data is read out from DDRAM, CGRAM, and MKRAM. When reading data from the RAM, it is necessary to read after the address setting. The dummy reading is necessary right after the address setting. After read out, the address is incremented automatically according to the entry mode. (Note) When the DDRAM data reading, CSb should be changed to "H" once every 2-byte. CSb RS WRb RDb D7~D0 n Address Set n n+1 n+2 Dummy read n+3 n+4 Data read (3-8-1) Read Data from DDRAM The DDRAM reading discriminates whether the content of the DDRAM data is full-size/half-size, and is output by an input and the same format. The data is recognized without fail as the 1st byte, immediately after CSb becomes “L”. Therefore, when the DDRAM data is read, it is necessary to make CSb = ”H” after it finishes reading the 2nd byte. (i) Half-size font character When the content of DDRAM data is half-size character code, the address data of one address is divided 2-byte. And after read the 2nd byte, the address is incremented according to the entry mode. The 3rd to 8th bit in 1st byte is all output “0”. DDRAM address Ver.2009-05-20 D0 D1 D2 D3 D4 D5 D0 D3 0 D1 D4 0 D6 D5 0 D7 D6 0 1st byte D2 P0 D7 P1 P0 0 1 Output data 0 DDRAM P1 n 2nd byte - 31 - Preliminary NJU6645 (ii) Full-size font character When the content of DDRAM data is full-size character code, the address data of 1-address is read by 1-byte. And after read, the address is incremented according to the entry mode. D5 D4 D3 D2 D1 D0 D0 D6 D1 D7 0 D5 D3 1 D6 1st byte D4 0 D7 D8 D9 D11 D8 D10 D12 D9 P0 D12 0 P1 D13 D13 0 P0 D11 0 Output data n+1 D10 DDRAM P1 n D2 DDRAM address 2nd byte (3-8-2) Read Data from CGRAM and MKRAM The CGRAM and MKRAM read the address data of one address by 1-byte as follows. And after read, the address is incremented according to the entry mode. D0 D1 D2 D3 --- 2nd byte D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 n+2 D2 D3 D5 D6 D7 D0 D1 1st byte D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 n+1 D2 D3 D4 D5 D6 D7 Output data n D4 CGRAM address D3 D4 D5 D6 RAM data D7 Relation between the interface, RAM data, and RAM address, in the CGRAM and MKRAM data reading --- 3rd byte (3-9) Status Read The status reading is output to the following bits. The dummy reading is not necessary for the status reading. However, the dummy reading is necessary for the status reading at the serial interface. - 32 - D0 D1 Display line on now D2 D3 D4 Display row on now D5 D6 Output data D7 Busy flag Status Read Ver.2009-05-20 Preliminary NJU6645 Correspondence Table of Character code and JIS code (ROM version “00”) - 0000 ~ 00FF : Half-size character code (256-character) - 0100 ~ 015F : CGRAM character code (96-character) - 10A1 ~ 3A7F : Full-size character code (8064-character) Note) Refer to "Correspondence Table of Half-size character code and Character pattern" for the half-size character. Ver.2009-05-20 - 33 - NJU6645 - 34 - Preliminary Ver.2009-05-20 Preliminary Ver.2009-05-20 NJU6645 - 35 - NJU6645 - 36 - Preliminary Ver.2009-05-20 Preliminary Ver.2009-05-20 NJU6645 - 37 - NJU6645 - 38 - Preliminary Ver.2009-05-20 Preliminary Ver.2009-05-20 NJU6645 - 39 - NJU6645 - 40 - Preliminary Ver.2009-05-20 Preliminary Ver.2009-05-20 NJU6645 - 41 - NJU6645 - 42 - Preliminary Ver.2009-05-20 Preliminary Ver.2009-05-20 NJU6645 - 43 - NJU6645 Preliminary Correspondence Table of Half-size character code and Character pattern (ROM version “00”) - 44 - Ver.2009-05-20 Preliminary NJU6645 (4) FULL SCREEN REVERSE DISPLAY FUNCTION This function reverses the full character and graphic display part except the icon display part. It is possible to reverse display easily without the RAM rewriting by this function. The cursor and the attribute display part are reversed too. The icon part doesn't change. Character/graphic part is reversed. Ver.2009-05-20 - 45 - NJU6645 Preliminary (5) CURSOR CONTROL The method of displaying the cursor has 3-kind that are the reversing blink (BW=”1”) and the underline blinks of 16th row (C=”1”) and the black blink (B=”1"). The “LC” register is possible to switch the cursor display of 1-character corresponding to the DDRAM address set in the address counter and the cursor display of the entire line including the setting address. (5-1) Character Cursor (5-1-1) Underline <C=”1”, LC=”0”, B=”0”, BW=”0”> The underline is displayed to the 16th row. When there is ON data in the 16th row, the data displays the logical add with original data. Cursor (5-1-2) Reverse Blink <C=”1”, LC=”0”, B=”0”, BW=”1”> The character at the cursor position is blinking with the reversing display. And then, the reversing switches at every 32-frame cycle. It alternately displays at every 32-frame cycle. (5-1-3) Black Blink <C=”1”, LC=”0”, B=”1”, BW=”0”> The character at the cursor position is blinking with the black pattern display. The blinking switches the all black pattern and the character pattern at every 32-frame cycle. It alternately displays at every 32-frame cycle. - 46 - Ver.2009-05-20 Preliminary NJU6645 (5-2) Line Cursor (5-2-1) Line Unit Underline <C=”1”, LC=”1”, B=”0”, BW=”0”> The 16th row of the line including the DDRAM address setting in the address counter is all ON. When there is character data, the data displays the logical add. Line Unit Underline (5-2-2) Line Unit Reverse <C=”1”, LC=”1”, B=”0”, BW=”1”> The line including the DDRAM address setting in the address counter is reversed display. Line Unit Reverse (5-2-3) Line Unit White Blink <C=”1”, LC=”1”, B=”1”, BW=”0”> The line including the DDRAM address setting in the address counter is blinking with the white pattern display. The blinking switches the all white pattern and the character data at every 32-frame cycle. Line Unit White Blink Ver.2009-05-20 - 47 - Preliminary NJU6645 (6) DISPLAY ATTRIBUTE SETTING NJU6645 is set the Reverse Display, the White Blink Display and the Reverse Blink Display by the display attribute code of each character in 2-bit. This display is applied in matrix unit of the 16 x 16 dots in the full-size data and the 8 x 16 dots in the half-size data. The White Blink Display and the Reverse Blink Display are switching at every 32-frame cycle. < Relation between the input data at the data writing to DDRAM and the bit > The attribute code of full-size / half-size character is allocated the 1st bit and 2nd bit in the 1st byte. When the DDRAM data is written, it is necessary to select the attribute code of this bit and to input the attribute of each character. D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Attribute 0 Half-size attribute code Half-size character code 8bit P1 P0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Full-size character code 14bit P1 P0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Attribute 0 Attribute 1 2nd byte D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 2nd byte [Half-size character data] 1st byte Attribute 1 [Full-size character data] 1st byte < Correspondence of the attribute code and the display status > The display status changes according to the following tables. P1 0 0 1 1 - 48 - P0 0 1 0 1 Display Status Normal Reverse White blink Reverse blink Ver.2009-05-20 Preliminary NJU6645 < Example of display when the display attribute is selected > (i) Reverse <Full-size character display> <Half-size character display> (ii) White blink It alternately displays at every 32-frame cycle. (iii) Reverse blink It alternately displays at every 32-frame cycle. Ver.2009-05-20 - 49 - Preliminary NJU6645 (7) RELATION BETWEEN ATTRIBUTE, BLINK and FULL SCREEN REVERSE DISPLAY The attribute display, the cursor display, and full screen reverse display are sequentially processed as shown in the following figures. The period that the data of various blinks is converted is reversed in the attribute display processing block and the cursor display processing block. Therefore, when the part where the attribute of the blink was selected and the cursor position of the blink overlap, the attribute display and the cursor display are alternately displayed. The full screen reverse display reverses the data after the attribute display processing and the cursor display processing are done. CGROM,CGRAM Period A is Active 32-flame Counter Setting OFF Reverse Reverse blink White blink Attribute processing block Processing Content Reversing all bits. (INV) Reversing all bits at period A. (INV) Changing to the OFF data in all bits at period A. (NOR) Setting OFF Underline Black blink Reverse blink Underline(Line unit) White blink(Line unit) Reverse(Line unit) Cursor processing block Period B is Active Full screen reverse processing block Period B = Period A Setting OFF Reverse Display Data Processing Content Changing to the all ON data in 16th row. (OR) Changing to the ON data in all bits at period B. (OR) Reversing all bits at period B. (INV) Changing to the all ON data in 16th row within the line. (OR) Changing to the OFF data in all bits within the line at period B. (NOR) Reversing all bits within the line. (INV) Processing Content Reversing all bits. (INV) < Method of display when attribute selection overlaps with cursor display > Attribute Cursol ABCDE FG OFF Underline Black blink Nomal + Reverse blink Underline (Line unit) White blink (Line unit) Reverse (Line unit) - 50 - ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG Attribute + Cursol display = = = = = ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG = ABCDE FG = ABCDE FG Ver.2009-05-20 Preliminary Attribute Cursol ABCDE FG OFF Reverse attribute selection part Underline Black blink + Reverse Reverse blink Underline (Line unit) White blink (Line unit) Reverse (Line unit) Attribute ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG Attribute + Cursol display = = = = = OFF ABCDE FG = ABCDE FG = ABCDE FG Black blink Reverse blink + Reverse blink Underline (Line unit) White blink (Line unit) Reverse (Line) ABCDE FG ABCDE FG ABCDE FG ABCDE FG = = = ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG ABCDE FG = ABCDE FG = Ver.2009-05-20 ABCDE FG ABCDE FG ABCDE FG ABCDE FG = Underline ABC E FG ABCDE FG Attribute + Cursol display ABCDE FG ABCDE FG Reverse blink attribute selection part ABCDE FG ABCDE FG ABCDE FG = Cursol ABCDE FG NJU6645 ABCDE FG ABCDE FG ABCDE FG - 51 - Preliminary NJU6645 Attribute Cursol ABCDE FG AB OFF Attribute + Cursol display ABCDE FG ABCDE FG = FG White blink attribute selection part Underline ABCDE FG = ABCDE FG Black blink White blink + Reverse blink Underline (Line unit) White blink (Line unit) Reverse (Line) ABCDE FG ABCDE FG ABCDE FG ABCDE FG = = = AB FG ABCDE FG AB FG ABCDE FG AB FG ABCDE FG AB FG ABCDE FG = ABCDE FG = - 52 - AB FG ABCDE FG AB FG ABCDE FG ABDDD F G Ver.2009-05-20 Preliminary NJU6645 (8) COMMON DRIVER OUTPUT SWITCHING The common output order of NJU6645 is selected by CSEL terminal (Both sides wiring or Comb wiring). When the CSEL="L", the COM0 to 47 connects on the upper half of the panel and the COM48 to 95 connects on the lower half. When the CSEL="H", the COM is divided by 16, that is connected to the panel by the comb pattern. < Wiring image > (i) CSEL=”L” Both sides wiring mode COMMK0 COM0 : : : COM47 Panel (CSEL=”L”) COM47 : : COM0 COMMK0 NJU6645 COM48 : : : COM95 COMMK1 COMMK1 COM95 : : COM48 (ii) CSEL=”H” Comb wiring mode COMMK0 COM0 : COM15 COM16 : COM31 COM32 : COM47 Panel (CSEL=”H”) COM64 : COM79 COM80 : COM95 COMMK1 COM47 : : COM0 COMMK0 Ver.2009-05-20 COM48 : COM63 NJU6645 COMMK1 COM95 : : COM48 - 53 - NJU6645 Preliminary (9) COMMON SHIFT DIRECTION / SEGMENT OUTPUT DIRECTION The direction of COM scan and SEG output of the dot matrix part and icon part is changed by "Driver Output Control" instruction (SEL1, SEL2). The output data of SEG and COM changes as follows. COMMK0 COM0 COM1 COM data COM output terminal COM94 COM95 COMMK1 COMMK0 COM0 COM1 COM output terminal COM94 COM95 COMMK1 COMMK0 COM0 COM1 COM data COMMK0 COM0 COM1 COM output direction switching < SEL1=”0" > COM94 COM95 COMMK1 COM94 COM95 COMMK1 < SEL1=”1" > SEG0 SEG1 SEG2 SEG output terminal SEG253 SEG254 SEG255 SEG data SEG253 SEG254 SEG255 SEG0 SEG1 SEG2 SEG output direction switching < SEL2=”0" > SEG0 SEG1 SEG2 SEG output terminal - 54 - SEG253 SEG254 SEG255 SEG data SEG253 SEG254 SEG255 SEG0 SEG1 SEG2 < SEL2=”1" > Ver.2009-05-20 Preliminary NJU6645 The correspondence of the display position on the panel and the DDRAM address is changed as follows. SEL1=”0”, SEL2=”0" The correspondence of the display position on the panel and the DDRAM address (SEL1=”0", SEL2=”0") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 000 020 040 060 080 0A0 001 021 041 061 081 0A1 2-digit 002 022 042 062 082 0A2 003 023 043 063 083 0A3 3-digit 004 024 044 064 084 0A4 005 025 045 065 085 0A5 4-digit 006 026 046 066 086 0A6 007 027 047 067 087 0A7 5-digit 008 028 048 068 088 0A8 6-digit 7-digit 009 00A 00B 00C 029 02A 02B 02C 049 04A 04B 04C 069 06A 06B 06C 089 08A 08B 08C 0A9 0AA 0AB 0AC 00D 02D 04D 06D 08D 0AD 8-digit 00E 02E 04E 06E 08E 0AE 00F 02F 04F 06F 08F 0AF 9-digit 010 030 050 070 090 0B0 011 031 051 071 091 0B1 10-digit 012 032 052 072 092 0B2 013 033 053 073 093 0B3 11-digit 014 034 054 074 094 0B4 015 035 055 075 095 0B5 12-digit 016 036 056 076 096 0B6 017 037 057 077 097 0B7 13-digit 018 038 058 078 098 0B8 019 039 059 079 099 0B9 14-digit 01A 01B 03A 03B 05A 05B 07A 07B 09A 09B 0BA 0BB 15-digit 01C 03C 05C 07C 09C 0BC 01D 03D 05D 07D 09D 0BD 16-digit 01E 03E 05E 07E 09E 0BE 01F 03F 05F 07F 09F 0BF COM0 COM1 SEG0 SEG1 SEG254 SEG255 COM94 COM95 SEL1=”1”, SEL2=”0" The correspondence of the display position on the panel and the DDRAM address (SEL1=”1", SEL2=”0") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 0A0 080 060 040 020 000 0A1 081 061 041 021 001 2-digit 0A2 082 062 042 022 002 0A3 083 063 043 023 003 3-digit 0A4 084 064 044 024 004 0A5 085 065 045 025 005 4-digit 0A6 086 066 046 026 006 0A7 087 067 047 027 007 5-digit 0A8 088 068 048 028 008 6-digit 7-digit 0A9 0AA 0AB 0AC 089 08A 08B 08C 069 06A 06B 06C 049 04A 04B 04C 029 02A 02B 02C 009 00A 00B 00C 0AD 08D 06D 04D 02D 00D 8-digit 0AE 08E 06E 04E 02E 00E 0AF 08F 06F 04F 02F 00F 9-digit 0B0 090 070 050 030 010 0B1 091 071 051 031 011 10-digit 0B2 092 072 052 032 012 0B3 093 073 053 033 013 11-digit 0B4 094 074 054 034 014 0B5 095 075 055 035 015 12-digit 0B6 096 076 056 036 016 0B7 097 077 057 037 017 13-digit 0B8 098 078 058 038 018 0B9 099 079 059 039 019 14-digit 0BA 0BB 09A 09B 07A 07B 05A 05B 03A 03B 01A 01B 15-digit 0BC 09C 07C 05C 03C 01C 0BD 09D 07D 05D 03D 01D 16-digit 0BE 09E 07E 05E 03E 01E 0BF 09F 07F 05F 03F 01F COM0 COM1 SEG0 SEG1 SEG254 SEG255 COM94 COM95 Ver.2009-05-20 - 55 - Preliminary NJU6645 SEL1=”0”, SEL2=”1" The correspondence of the display position on the panel and the DDRAM address (SEL1=”0", SEL2=”1") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 01F 03F 05F 07F 09F 0BF 2-digit 3-digit 4-digit 01E 01D 01C 01B 01A 019 03E 03D 03C 03B 03A 039 05E 05D 05C 05B 05A 059 07E 07D 07C 07B 07A 079 09E 09D 09C 09B 09A 099 0BE 0BD 0BC 0BB 0BA 0B9 018 038 058 078 098 0B8 5-digit 017 037 057 077 097 0B7 016 036 056 076 096 0B6 6-digit 015 035 055 075 095 0B5 014 034 054 074 094 0B4 7-digit 013 033 053 073 093 0B3 012 032 052 072 092 0B2 8-digit 011 031 051 071 091 0B1 010 030 050 070 090 0B0 9-digit 10-digit 11-digit 12-digit 00F 00E 00D 00C 00B 00A 009 02F 02E 02D 02C 02B 02A 029 04F 04E 04D 04C 04B 04A 049 06F 06E 06D 06C 06B 06A 069 08F 08E 08D 08C 08B 08A 089 0AF 0AE 0AD 0AC 0AB 0AA 0A9 008 028 048 068 088 0A8 13-digit 007 027 047 067 087 0A7 006 026 046 066 086 0A6 14-digit 005 025 045 065 085 0A5 004 024 044 064 084 0A4 15-digit 003 023 043 063 083 0A3 002 022 042 062 082 0A2 16-digit 001 021 041 061 081 0A1 000 020 040 060 080 0A0 COM0 COM1 SEG0 SEG1 SEG254 SEG255 COM94 COM95 SEL1=”1”, SEL2=”1" The correspondence of the display position on the panel and the DDRAM address (SEL1=”1", SEL2=”1") 1-digit 1-line 2-line 3-line 4-line 5-line 6-line 0BF 09F 07F 05F 03F 01F 2-digit 3-digit 4-digit 0BE 0BD 0BC 0BB 0BA 0B9 09E 09D 09C 09B 09A 099 07E 07D 07C 07B 07A 079 05E 05D 05C 05B 05A 059 03E 03D 03C 03B 03A 039 01E 01D 01C 01B 01A 019 0B8 098 078 058 038 018 5-digit 0B7 097 077 057 037 017 0B6 096 076 056 036 016 6-digit 0B5 095 075 055 035 015 0B4 094 074 054 034 014 7-digit 0B3 093 073 053 033 013 0B2 092 072 052 032 012 8-digit 0B1 091 071 051 031 011 0B0 090 070 050 030 010 9-digit 10-digit 11-digit 12-digit 0AF 0AE 0AD 0AC 0AB 0AA 0A9 08F 08E 08D 08C 08B 08A 089 06F 06E 06D 06C 06B 06A 069 04F 04E 04D 04C 04B 04A 049 02F 02E 02D 02C 02B 02A 029 00F 00E 00D 00C 00B 00A 009 0A8 088 068 048 028 008 13-digit 0A7 087 067 047 027 007 0A6 086 066 046 026 006 14-digit 0A5 085 065 045 025 005 0A4 084 064 044 024 004 15-digit 0A3 083 063 043 023 003 0A2 082 062 042 022 002 16-digit 0A1 081 061 041 021 001 0A0 080 060 040 020 000 COM0 COM1 - 56 - SEG254 SEG255 SEG0 SEG1 COM94 COM95 Ver.2009-05-20 Preliminary NJU6645 The correspondence of the SEG/COM terminals and the MKRAM address is changed as follows. The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”0") 0 : 7 MK COM0 MK COM1 SEG 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”1", SEL2=”0") 0 : 7 MK COM0 MK COM1 SEG 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”1") 0 : 7 MK COM0 MK COM1 SEG 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255 11F 11E 11D 11C 11B 11A 119 118 117 116 115 114 113 112 111 110 10F 10E 10D 10C 10B 10A 109 108 107 106 105 104 103 102 101 100 13F 13E 13D 13C 13B 13A 139 138 137 136 135 134 133 132 131 130 12F 12E 12D 12C 12B 12A 129 128 127 126 125 124 123 122 121 120 The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”1", SEL2=”1") 0 : 7 MK COM0 MK COM1 SEG 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255 13F 13E 13D 13C 13B 13A 139 138 137 136 135 134 133 132 131 130 12F 12E 12D 12C 12B 12A 129 128 127 126 125 124 123 122 121 120 11F 11E 11D 11C 11B 11A 119 118 117 116 115 114 113 112 111 110 10F 10E 10D 10C 10B 10A 109 108 107 106 105 104 103 102 101 100 Ver.2009-05-20 - 57 - NJU6645 Preliminary (10) PARTIAL DISPLAY The partial display is executed by combining the Display Duty Ratio instruction "DN2, 1, 0" with the Display Start Position instruction "DST2, 1, 0". This function reduces the LCD driving voltage and the power consumption when the duty set low like the clock display of stand-by. 1 2 3 4 5 6 Display Duty Ratio = 6th line Display Area 1 2 3 4 5 6 Non-display Area Display Area 1 2 Display Duty Ratio = 2nd line Display Start Position = 3rd line Non-display Area When the Display Start Position is set to the 3rd line, the character data of the first line of the DDRAM address is displayed from the 3rd line (33 to 48 rows). When the Display Duty Ratio is set to the 2nd line, the duty corresponds to 2-line (16 rows x 2 + 2 rows of icon part). - 58 - Ver.2009-05-20 Preliminary NJU6645 (11) VERTICAL SMOOTH SCROLL NJU6645 is executed to the vertical smooth scroll display of 1-dot unit by combining the Scroll Start Row with the Scroll Start Line. The display scroll is set by the “Scroll Start Line” instruction (0,1,2,3,4, and 5-line scroll) at the unit of line (16-dot units). The display scroll is set by the “Scroll Start Row” instruction (0,1,2, --- 14, and 15-dot scroll) at the 1 dot unit. The display shifts to the upside only the amount of “Scroll Start Line” + “Scroll Start Row”. When it is made to scroll by Display Duty Ratio = 6-line, the display that pushed outside the screen appears from the other side. < Example of smooth scroll display > (i) Scroll Start Line = ”0-line” Scroll Start Row = “0-dot” (ii) Scroll Start Line = ”0-line” Scroll Start Row = “8-dot” 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (iii) Scroll Start Line = ”1-line” Scroll Start Row = “0-dot” (iv) Scroll Start Line = ”2-line” Scroll Start Row = “8-dot” Ver.2009-05-20 - 59 - NJU6645 Preliminary < Example of 4-dot smooth scroll display > When the scroll operation to above by 4-dot of the 5-line display, the sequence and the panel image are shown below. Display Duty Ratio = 5-line (RE, DB7~0) = (0 1001 0001) No scroll Display ON (0 0010 0001) 4-dot Scroll (0 0111 0100) 4-dot Scroll 8-dot Scroll (0 0111 1000) 8-dot Scroll 12-dot Scroll (0 0111 1100) 12-dot Scroll 0-dot Scroll (0 0111 0000) 1-line Scroll (0 0110 0001) 16-dot Scroll (1-line Scroll) It is necessary to update the display data in DDRAM or CGRAM of 6th line. 4-dot Scroll (0 0111 0100) 20-dot Scroll (1-line + 4-dot Scroll) 8-dot Scroll (0 0111 1000) 24-dot Scroll (1-line + 8-dot Scroll) 12-dot Scroll (0 0111 1100) 28-dot Scroll (1-line + 12-dot Scroll) 0-dot Scroll (0 0111 0000) 32-dot Scroll (2-line Scroll) 2-line Scroll (0 0110 0010) - 60 - Ver.2009-05-20 Preliminary NJU6645 (12) N-LINE INVERSION NJU6645 sets the number of inversion line of the alternating signal for LCD to the optional values from 2 ~ 98. 2nd line --1st line Icon 2nd line Icon 1st line 96th line 95th line 3rd line 2nd line --1st line Icon 2nd line Icon 1st line 95th line 3rd line 2nd line 1st line --- 96th line < Setting example > - N-line inversion = 98-line Frame Inversion Inversion Inversion 98-line 98-line 4th line 3rd line 2nd line --1st line Icon 2nd line Icon 1st line 5th line 4th line 3rd line 2nd line 1st line --- 96th line - N-line inversion = 2-line Frame Inversion Inversion Inversion 2-line Ver.2009-05-20 2-line 2-line Inversion Inversion Inversion 2-line 2-line 2-line 2-line - 61 - NJU6645 Preliminary (13) DISPLAY MODE NJU6645 sets the 3 kinds display mode by the SPR and GR instructions. (13-1) Character Mode (SPR="0”, GR=”0”) In the character mode, the font pattern that uses the CGROM and CGRAM is displayed. The font pattern is displayed at the position that corresponds to the DDRAM address by the character code written in DDRAM. - 62 - Ver.2009-05-20 Preliminary NJU6645 (13-2) Graphics Mode (SPR="0”, GR=”1”) In the graphics mode, the graphics of maximum 256x96 dots is displayed by using only CGRAM. At this time, the relation between the CGRAM address and the position of display is shown in the following tables. Because all CGRAM is used for graphics, it is not possible to use it as a user font. Besides, the setting of “Scroll Start Line” and “Scroll Start Row” instructions is not reflected in the graphics mode. Correspondence of display position on panel and CGRAM address. (In the graphics mode) 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 30F 31F 32F 33F 34F 35F 36F 37F 38F 39F 3AF 3BF 3CF 3DF 3EF 3FF 500 510 520 530 540 550 560 570 580 590 5A0 5B0 5C0 5D0 5E0 5F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 50F 51F 52F 53F 54F 55F 56F 57F 58F 59F 5AF 5BF 5CF 5DF 5EF 5FF 700 710 720 730 740 750 760 770 780 790 7A0 7B0 7C0 7D0 7E0 7F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 70F 71F 72F 73F 74F 75F 76F 77F 78F 79F 7AF 7BF 7CF 7DF 7EF 7FF 900 910 920 930 940 950 960 970 980 990 9A0 9B0 9C0 9D0 9E0 9F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 90F 91F 92F 93F 94F 95F 96F 97F 98F 99F 9AF 9BF 9CF 9DF 9EF 9FF B00 B10 B20 B30 B40 B50 B60 B70 B80 B90 BA0 BB0 BC0 BD0 BE0 BF0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ B0F B1F B2F B3F B4F B5F B6F B7F B8F B9F BAF BBF BCF BDF BEF BFF D00 D10 D20 D30 D40 D50 D60 D70 D80 D90 DA0 DB0 DC0 DD0 DE0 DF0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F DAF DBF DCF DDF DEF DFF --- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Address Lower 4bit 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Address Lower 4bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 20F 21F 22F 23F 24F 25F 26F 27F 28F 29F 2AF 2BF 2CF 2DF 2EF 2FF 400 410 420 430 440 450 460 470 480 490 4A0 4B0 4C0 4D0 4E0 4F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 40F 41F 42F 43F 44F 45F 46F 47F 48F 49F 4AF 4BF 4CF 4DF 4EF 4FF 600 610 620 630 640 650 660 670 680 690 6A0 6B0 6C0 6D0 6E0 6F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 60F 61F 62F 63F 64F 65F 66F 67F 68F 69F 6AF 6BF 6CF 6DF 6EF 6FF 800 810 820 830 840 850 860 870 880 890 8A0 8B0 8C0 8D0 8E0 8F0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 80F 81F 82F 83F 84F 85F 86F 87F 88F 89F 8AF 8BF 8CF 8DF 8EF 8FF A00 A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 AB0 AC0 AD0 AE0 AF0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ A0F A1F A2F A3F A4F A5F A6F A7F A8F A9F AAF ABF ACF ADF AEF AFF C00 C10 C20 C30 C40 C50 C60 C70 C80 C90 CA0 CB0 CC0 CD0 CE0 CF0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ C0F C1F C2F C3F C4F C5F C6F C7F C8F C9F CAF CBF CCF CDF CEF CFF Address Upper 8bit Address Upper 8bit Address Upper 8bit Address Upper 8bit --- Address Upper 8bit Address Upper 8bit Address Upper 8bit Address Upper 8bit --- --- --Ver.2009-05-20 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh - 63 - NJU6645 Preliminary (13-3) Superimpose mode (SPR="1”, GR=”*”) The superimpose mode overlaps and displays the character mode and the graphics mode. The displayed data is a logical addition of the character mode data and the graphics mode data. Because all CGRAM is used for graphics, it is not possible to use it as a user font. Besides, the setting of “Scroll Start Line” and “Scroll Start Row” instructions is reflected only in the character part, and not reflected in the graphics part. - 64 - Ver.2009-05-20 Preliminary NJU6645 (14) FULL-SIZE and HALF-SIZE MIXED DISPLAY NJU6645 displays from the left end of the screen with mixing the full-size character (16 x 16 dots) and the half-size character (8 x 16 dots). The distinction between full-size and half-size is decided by 1st bit of DDRAM data writing of the 2-byte format. In case of the “0”, it is the full-size character. In case of the “1”, it is the half-size character. 1-character of the full-size character is composed of two DDRAM addresses, and 1-character of the half-size character is composed of one DDRAM address. The corresponding example of that input data, DDRAM data, and display are shown below. Half-size"1" Full-size" " Half-size"2" (Attribute=Reverse) Full-size" " Input Data 0 0 0 0 0 0 0 0 RAM Address RAM Data 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 000 0 0 0 0 0 0 0 1 001 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 0 002 0 1 0 0 0 0 0 0 003 0 0 0 0 0 0 1 0 004 0 0 1 0 0 0 1 1 0 1 1 1 1 1 0 0 005 Panel Display Note) When the Full-size character is written to the half-size address of the end of line, the character is displayed unexpected. The number of writing characters must become just 32-character at half-size by 1-line. Ver.2009-05-20 - 65 - NJU6645 Preliminary (15) RESET FUNCTION The reset function initializes the LSI by setting the RSTb terminal to "L". The reset operation is always required after the power supply is turned on. The reset status is as follows. Item RE Flag : 1st page Address Counter : DDRAM left end of the 1st line Dot Matrix Display : OFF Icon Display : OFF Full Screen Reverse Display : OFF Standby mode : OFF Cursor Display : OFF Line Cursor Setting : OFF Blink Setting : OFF Reverse Cursor Setting : OFF Display Mode : Character Mode Read Modify Write Mode : OFF Scroll Start Line : 1st line Scroll Start Row : 1st row Display Start Line : 1st line Display Duty Ratio : 6-line N-line Inversion : 98 Driver Output Control : Forward Direction Internal Oscillation / External Clock : Internal OSC Internal Capacitance Adjust : Reference Value Discharge : OFF Voltage Boost Circuit : OFF Internal Power Circuit : OFF Boost Level : No Boost Bias Ratio: 1/11 Bias Electrical Volume : Low (Minimum value) Register RE AC D M REV HALT C LC B BW SPR / GR RDM SSN2,1,0 SSL3,2,1,0 DST2,1,0 DN2,1,0 NL6,5,4,3,2,1,0 SEL1,SEL2 INTCK OC2,1,0 DIS DCON AMPON VU2,1,0 BS3,2,1,0 EV6,5,4,3,2,1,0 Initial Value 0 000h 0 0 0 0 0 0 0 0 0/0 0 0,0,0 0,0,0,0 0,0,0 0,0,0 1,1,0,0,0,0,1 0,0 0 0,0,0 0 0 0 0,0,0 0,0,0,0 0,0,0,0,0,0,0 Note) After the resetting, the DDRAM, CGRAM, and MKRAM are not initialized. After the data is written, it is necessary to turn on the display. - 66 - Ver.2009-05-20 Preliminary NJU6645 (16) OSCILLATION CIRCUIT NJU6645 is equipped with the CR oscillation circuit with the external resistor used, and generates internal clocks used for the display timing. The generating method of the clock selects by the internal oscillation or external clock. When the internal oscillation circuit is used, connect OSC1 and VDD with an external resistor. At this time, it is necessary to fix the OSC2 to "H" or "L". The internal capacity value of the internal oscillation circuit is set by the instruction (0.7/0.8/0.9/1/1.1/1.2/1/3 times.). The oscillation frequency is adjusted by setting the internal capacity value. When the external clock is used, INTCK=”1” and the external clock is supplied from the OSC2. At this time, the OSC1 opens. < Using Internal Oscillation > < Using External Clock > VDD 47kΩ OSC1 OPEN OSC2 “H” or “L” External Clock OSC1 OSC2 (17) POWER SUPPLY CIRCUIT (17-1) LCD power supply The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage converter consists of the reference voltage generator, the voltage regulator with EVR and the LCD bias voltage generator. If the internal LCD power supply doesn't have enough capability to drive the particular LCD panel, use the external LCD power supply. Otherwise, it may affect display quality. The configuration of the LCD power supply is arranged by setting the D1 (AMPON) and D0 (DCON) bits of the “Power Control” instruction. For this configuration, the internal LCD power supply can be partially used in combination with an external supply voltage, as shown below. DCON AMPON 0 0 1 0 1 1 Voltage Booster Inactive Inactive Active Voltage Converter Inactive Active Active External Supply Voltage Note VOUT, VLCD, V1, V2, V3, V4 VOUT VDCOUT is supplied to VOUT. *1, 3 *2, 3 - Note 1) No internal LCD power supply is used. The LCD bias voltages are externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VREF, VREG and VEE are open. Note 2) Only the voltage converter is used. The VOUT is externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5- and VEE are open. The reference voltage is supplied on the VREF. Note 3) The following relation among each LCD bias voltages must be maintained. VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS Ver.2009-05-20 - 67 - Preliminary NJU6645 (17-2) Voltage booster The internal voltage booster generates up to 6xVEE voltage. The boost level is selected from 2x, 3x, 4x, 5x or 6x by setting the D2 to D0 (VU2 to VU0) bits of the “Boost Level” instruction. VDCOUT terminal and VOUT terminal are connected on the outside and used. The boost voltage VDCOUT must not exceed 17.0V, otherwise the voltage stress may cause a permanent damage to the LSI. Boost Voltage VDCOUT = VEE x N [V] ( N : Boost Level =2~6 ) VDCOUT=16.8V VDCOUT=9.9V VEE=3.3V VEE=2.8V VSS=0V VSS=0V 3-time Boost 6-time Boost - External Capacitor Connection of Voltage Booster 6-time Boost C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VOUT VDCOUT VSS 4-time Boost C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VOUT VDCOUT VSS - 68 - 5-time Boost C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VOUT + + + + + VDCOUT VSS + 3-time Boost + + + + C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VOUT VDCOUT VSS + + + + + 2-time Boost + + + C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VOUT VDCOUT VSS + + Ver.2009-05-20 Preliminary NJU6645 (17-3) Reference voltage generator The reference voltage generator produces the reference voltage. Reference Voltage : VBA = 0.75 x VEE When using the internal LCD power supply, connect the VBA and the VREF, or supply 0.75xVEE or lower voltage on the VREF. When using an external LCD power supply, the VBA should be open. (17-4) Voltage regulator The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is multiplied to obtain the VREG voltage, and its multiple (boost level) is set by the D2 to D0 (VU2 to VU0) bits of the “Boost Level” instruction. The formula is shown below. VREG = VREF x N [V] ( N : Boost Level = 2~6 ) (17-5) Electrical variable Resistor (EVR) The EVR is used to fine-tune the V LCD voltage to optimize display contrast. The EVR value is controlled in 128 steps by setting the D3 to D0 (DV6 to DV0) bits of the “EVR Control” instruction. The formula is shown below. VLCD = 0.5 x VREG + M(VREG –0.5VREG) / 127 [V] ( M : EVR Value = 0 to 127) Ver.2009-05-20 - 69 - Preliminary NJU6645 (17-6) LCD bias circuit The suitable bias is set by the bias register (BS3 to 0) according to the display duty. When the VLCD voltage is close to minimum (nearly equal: 4.5V), it is recommended not to use it because there is a possibility of not operating in 1/11 bias setting. VLCD R + - VLCD R + - + - V1 R + - V2 7R V3 R + - V4 R + - + - V1 R + - V2 6R V3 R + - V4 R + - <1/11 Bias> VLCD R + + - V1 R + - V2 5R V3 R + - V4 R + - <1/10 Bias> + - VLCD R + - V1 R V2 3R + - V3 R + + - V4 R + - VLCD + - V1 R V2 2R + - V3 R + + - V4 R VLCD R + - V1 R 0.5R + - V4 R + <1/8 Bias> VLCD + - V1 R V2 1.5R + - V3 R + + - V4 R <1/5.5 Bias> VLCD R + - V1 R V2 + - V2 V3 R + - V3 R + - V4 R + - V4 R + - - 70 - V3 R + - + - + - <1/4.5 Bias> + - V2 4R R <1/6 Bias> + - + - V1 R <1/9 Bias> R <1/7 Bias> VLCD R + - <1/4 Bias> LCD Bias Circuit + - VLCD R + - V1 R V2 R + - V3 R + + - V4 R <1/5 Bias> Note) R = Reference resistor Ver.2009-05-20 Preliminary NJU6645 (17-7) Discharge circuit The LSI incorporates a discharge circuit for the VLCD and V1 to V4 and for the VOUT. The VLCD and V1 to V4 are discharged by setting "1" at the D0 (DIS) bit of the "Discharge ON/OFF" instruction or the reset by the RESb. Be sure to turned off the internal or external LCD power supply when this instruction is executed, otherwise it may function as a current load and affect an operating current. Refer to “(r) Discharge ON/OFF”. (17-8) Power ON/OFF To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power supply. In addition to the following discussions, refer to “(21) TYPICAL INSTRUCTION SEQUENCES”. (i) Power ON/OFF in using external LCD supply -Power ON First “VDD and VEE ON”, next “Reset by RSTb”, then “External LCD power supply ON”. When using only external VOUT, first “VDD ON”, next “Reset by RSTb”, then “External VOUT ON”, as well. -Power OFF First “Reset by RSTb or “HALT” instruction” to isolate external LCD bias voltage, next “VDD OFF”. For more safety, placing a resistor in series on the VLCD line (or the VOUT line in using only the external VOUT) is recommended. That resistance is usually between 50Ω and 100Ω. (ii) Power ON/OFF in using internal LCD supply -Power ON First “VDD and VEE ON”, next “Reset by RSTb”, then “Internal LCD power supply ON”. Be sure to execute the “Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be turned on instantly. -Power OFF First “Reset by RSTb or “HALT” instruction”, next “VDD and VEE OFF”. If using different power sources for the VDD and the VEE individually, the VEE must be turned off after the reset or the “HALT”. After that, the VDD can be turned off, waiting until the LCD bias voltages (VLCD, V1, V2, V3 and V4) drop below the threshold level of LCD pixels. Ver.2009-05-20 - 71 - Preliminary NJU6645 - External Components for LCD Power Supply Using Only Internal LCD Power Supply (6x boost) VDD VDD VDD VEE VSS CA1 VBA VSS CA3 VSS Using Only External LCD Power Supply CA3 VSS CA1 CA1 CA1 CA1 CA1 CA1 VDD VEE VSS VBA VREF VREF VREG VREG C1- C1- C1+ C1+ C2- C2- C2+ C2+ C3- C3- C3+ C3+ C4C4+ C4- NJU6645 C4+ C5+ C5+ CA2 CA2 CA2 CA2 VSS CA2 Reference Values CA1 CA2 CA3 VDCOUT VOUT CA1 VLCD V1 VLCD VSS VOUT VLCD V1 V3 V1 External Power V2 Circuit V3 V4 V4 V4 V2 NJU6645 C5- C5- VDCOUT CA1 VSS VSS V2 V3 CA2 CA2 CA2 CA2 1.0 to 4.7µF 1.0 to 2.2µF 0.1µF VSS VSS VSS VSS Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the particular application. Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. - 72 - Ver.2009-05-20 Preliminary Using Internal LCD Power Supply Without Reference Voltage Generator (2) (6x boost) Using Internal LCD Power Supply Without Reference Voltage Generator (1) (6x boost) VDD CA1 VDD VDD VEE VSS Thermistor VREG CA3 VSS CA1 C1- VSS CA1 CA1 C2+ C3- CA1 C3+ C4- CA1 C4+ NJU6645 CA1 C5- CA1 VREG CA3 VSS C2- CA1 CA1 C5+ VDCOUT CA1 VSS CA2 CA2 CA2 CA2 VSS CA2 Reference Values CA1 CA2 CA3 VOUT C1C1+ C2C2+ C3C3+ C4C4+ NJU6645 C5C5+ VDCOUT CA1 VSS VOUT VLCD CA2 VLCD V1 CA2 V1 V2 CA2 V2 V3 CA2 V3 V4 VSS VREF C1+ CA1 VDD VEE VBA VSS VREF VSS CA1 VBA VSS NJU6645 VSS CA2 V4 1.0 to 4.7µF 1.0 to 2.2µF 0.1µF Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the particular application. Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. Ver.2009-05-20 - 73 - Preliminary NJU6645 Using Internal LCD Power Supply Without Voltage Booster VDD CA1 VDD VEE VSS VBA VSS CA3 VREF CA3 VREG VSS VSS C1C1+ C2C2+ C3C3+ C4C4+ NJU6645 C5C5+ External Power Circuit VDCOUT CA1 CA2 CA2 CA2 CA2 VSS Reference Values CA1 CA2 CA3 VOUT VLCD V1 V2 V3 CA2 V4 1.0 to 4.7µF 1.0 to 2.2µF 0.1µF Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the particular application. Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. - 74 - Ver.2009-05-20 Preliminary NJU6645 (18) COMMON DRIVERS AND SEGMENT DRIVERS The LSI includes 256-segment drivers and 98-common drivers. 2 out of 98-common drivers are assigned to the COMMK0 and COMMK1 for an icon display. The common drivers generates LCD driving waveforms formed on the VLCD, V1, V4 and VSS levels. The segment drivers generates waveforms formed on the VLCD, V2, V3 and VSS levels. (19) LCD DRIVING WAVEFORMS 98 COM0 Ver.2009-05-20 2 3 4 5 98 1 2 3 4 5 98 1 COM0 VLCD V1 V2 V3 V4 VSS COM1 VLCD V1 V2 V3 V4 VSS SEG0 VLCD V1 V2 V3 V4 VSS SEG1 VLCD V1 V2 V3 V4 VSS SEG2 SEG1 SEG0 COM1 1 - 75 - Preliminary NJU6645 (20) INSTRUCTION Instruction Tables (1/2) Instruction Code RE RS RW a RAM Data Write b RAM Data Read * * 1 1 0 1 c Status Read * 0 1 D7 D6 D5 D4 D3 D2 D1 DDRAM, CGRAM, MKRAM Data D0 NF2 NF1 NF0 LF3 LF2 LF1 Description - DDRAM, CGRAM, MKRAM Data BF Default LF0 - BF: Busy Flag NF: Display Line at present LF: Display Row at present * : Don’t care Instruction Code Default RE RS RW D7 D6 D5 D4 D3 D2 D1 D0 d Display Clear 0 0 0 0 0 0 0 0 0 0 1 - e Cursor Home 0 0 0 0 0 0 1 0 0 0 1 - f 0 0 0 0 0 1 0 M D 000 0 0 0 0 0 1 1 Display Control g Standby ALL REV ON * * h Cursor Display 0 0 0 0 1 0 0 BW B i Display / Entry Mode 0 0 0 0 1 0 1 * SPR Scroll Start Line Scroll Start Row Display Start Line Display Duty Ratio N-line Inversion (Upper) n N-line Inversion (Lower) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 o Driver Output Control 0 0 0 1 1 0 0 p Oscillation Control 0 0 0 1 1 0 1 q RE Flag * 0 0 1 1 1 1 j k l m * HALT LC C GR RDM Description Writing the half-size space code “0020h” into all DDRAM. Setting the DDRAM address “000h" into address counter. Setting the DDRAM address “000h" into address counter. Initialization the Scroll Start Line and the Scroll Start Row. ALLON: All pixels ON/OFF REV: Full Screen Reverse Display ON/OFF M: Icon Display ON/OFF D: Dot Matrix Display ON/OFF 0 0000 000 BW: Reverse Cursor B: Blink LC: Line Cursor C: Cursor SPR: Superimpose Mode GR: Graphics Mode RDM: Read Modify Write * SSN2 SSN1 SSN0 000 0000 * DST2 DST1 DST0 000 * DN2 DN1 DN0 000 SSL3 SSL2 SSL1 SSL0 * NL6 NL5 NL4 NL3 NL2 NL1 NL0 * * SEL1 SEL2 INT OC2 OC1 OC0 CK * * * RE 110 0001 00 0000 0 SEL1: COM Shift Direction Set SEL2: SEG Output Direction Set INTCK: Internal OSC / External Clock OC2,1,0: Internal Capacitance Adjust RE Flag Set * : Don’t care - 76 - Ver.2009-05-20 Preliminary NJU6645 Instruction Tables (2/2) Instruction r s t Discharge Boost Level Bias Ratio Electrical Volume (Upper) u Electrical Volume (Lower) Code RE RS RW D7 D6 D5 D4 D3 D2 D1 * * D0 DIS 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 * * 1 0 0 0 0 1 1 1 0 0 0 1 0 0 EV3 EV2 EV1 EV0 AMP DC ON ON VU2 VU1 VU0 BS3 BS2 BS1 BS0 * * EV6 EV5 EV4 0 000 0000 0 0 0 1 0 1 RAM Address Set 1 w RAM Address Set 2 RAM Address Set 3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 AD3 AD2 AD1 AD0 1 AD7 AD6 AD5 AD4 0 AD11 AD10 AD9 AD8 x Address Shift 1 0 0 1 0 0 1 ARL - Maker Test 1 Maker Test 2 y Maker Test 3 Maker Test 4 Maker Test 5 q RE Flag 1 1 1 1 1 * 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 TS3 TS2 TS1 TS0 1 TS7 TS6 TS5 TS4 0 TS11 TS10 TS9 TS8 1 * * TS13 TS12 0 TSM3TSM2TSM1 TSM0 1 * * * RE 0 * VU2,1,0: Boost Level 0000 1 * Description 000 v Power Control * * Default 00 0000 0000 0000 AMPON: Internal Operational Amplifier ON/OFF DCON: Voltage Boost Circuit ON/OFF RAM Address 4bit (AD3 to AD0) RAM Address 4bit (AD7 to AD4) RAM Address 4bit (AD11 to AD8) ARL=”0” Address -1 ARL=”1” Address +1 Maker Test Instruction (Not used usually.) RE Flag Set * : Don’t care Ver.2009-05-20 - 77 - Preliminary NJU6645 < Instruction Descriptions > (a) RAM Data Write The "RAM Data Write" instruction writes display data on a specified address. The address is incremented automatically by "Display / Entry Mode” instruction. RE * RS 1 RW 0 D7 D6 D5 D4 D3 WRITE DATA D2 D1 D0 (b) RAM Data Read The "RAM Data Read" instruction reads out display data from a specified address. The address is incremented automatically by "Display / Entry Mode” instruction. RE * - 78 - RS 1 RW 1 D7 D6 D5 D4 D3 READ DATA D2 D1 D0 Ver.2009-05-20 Preliminary NJU6645 (c) Status Read The "Status Read" instruction reads out the busy flag (BF) that indicates the internal operation and the line / row that displayed at present. The BF="1" indicates that internal operation is in progress. When the BF="1", the next instruction is disabled. Check the busy flag status (BF="0") before the next write operation. RE * RS 0 - Busy Flag Read BF 0 1 RW 1 D7 BF D6 NF2 D5 NF1 D3 LF3 D2 LF2 D1 LF1 D0 LF0 Internal Operation Instruction is enable Operating (Instruction is disabled) - Display Line Read NF 000 001 010 011 100 101 110 111 Display Line 1st line 2nd line 3rd line 4th lint 5th line 6th line - - Display Row Read LF 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Display Row 1st row 2nd row 3rd row 4th row 5th row 6th row 7th row 8th row 9th row 10th row 11th row 12th row 13th row 14th row 15th row 16th row Ver.2009-05-20 D4 NF0 - 79 - Preliminary NJU6645 (d) Display Clear When the "Display Clear" instruction is executed, the Half-size space code "0020h" is written into every DD RAM address, the DD RAM address "000h" is set into the address counter. The MK RAM / CG RAM data is unchanged. RE 0 RS 0 RW 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 (e) Cursor Home When the "Cursor Home" instruction is executed, the DD RAM address "000h" is set into the address counter. The Scroll Start Line and the Scroll Start Row are set to default. The DD RAM contents are unchanged. RE 0 (f) RS 0 RW 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 Display Control The "Display Control" instruction controls the Dot Matrix Display ON/OFF, the Icon Display ON/OFF, the Full Screen Reverse Display ON/OFF and All Pixels ON/OFF. The Icon Display ON/OFF and the Dot Matrix Display ON/OFF are controlled separately. When the M=”0” and D=”0”, common / segment drivers are turning OFF and output VSS level. RE 0 RS 0 - All Pixels ON/OFF ALLON 0 1 RW 0 D7 0 D6 0 D5 1 D4 0 D3 D2 ALLON REV D1 M D0 D Display Normal display All ON display (Both dot matrix and Icon display) - Full Screen Reverse Display ON/OFF REV Display 0 Normal display 1 Full screen reverse display - Icon Display ON/OFF M 0 1 - Dot Matrix Display ON/OFF D 0 1 - 80 - Icon Display OFF ON Dot Matrix Display OFF ON Ver.2009-05-20 Preliminary NJU6645 (g) Standby The "Standby" instruction controls the Standby mode ON/OFF. RE 0 RS 0 RW 0 D7 0 HALT 0 1 D6 0 D5 1 D4 1 D3 * D2 * D1 * D0 HALT Function OFF (Normal mode) ON (Standby mode) During the standby ON, operating current is down to the standby level. The internal state of the LSI in the standby mode is listed below. - Internal oscillator and internal LCD power supply are halted. - All segment and common drivers are fixed at VSS level. - External clock to the OSC2 cannot be accepted. - Voltage booster is halted. - Display data in the DDRAM and data in the instruction registers are being maintained. - VLCD, V1, V2, V3 and V4 are in high impedance. In the standby ON sequence, execute the "Display OFF" prior to the "Standby ON". In the standby OFF sequence, execute the "Standby OFF" prior to the "Display ON". If the "Standby ON/OFF" instruction is executed during the "Display ON", unexpected pixels may be turned on instantly. (h) Cursor Display The "Cursor Display" instruction controls the Cursor ON/OFF, the Line Cursor ON/OFF and display method. RE 0 RS 0 BW * 0 0 1 1 0 0 1 1 Ver.2009-05-20 RW 0 B * 0 1 0 1 0 1 0 1 D7 0 LC * 0 0 0 0 1 1 1 1 D6 1 D5 0 D4 0 D3 BW D2 B D1 LC C 0 1 1 1 1 1 1 1 1 Display State Cursor OFF Underline cursor (Character unit) Black blink cursor (Character unit) Reverse blink cursor (Character unit) Inhibited Underline cursor (Line unit) White blink cursor (Line unit) Reverse cursor (Line unit) Inhibited D0 C - 81 - Preliminary NJU6645 (i) Display Mode / Entry Mode The "Display Mode / Entry Mode" instruction controls the Display Mode and Entry Mode. RE 0 RS 0 - Display Mode SPR 0 0 1 RW 0 D6 1 GR 0 1 * - Read Modify Write Mode RDM 0 1 (j) D7 0 D5 0 D4 1 D3 * D2 SPR D1 GR D0 RDM Display state Character Mode Graphics Mode Superimpose Mode Function OFF (Auto increment in writing and reading display data) ON (Auto increment in writing display data only) Scroll Start Line The "Scroll Start Line" instruction controls the Display Line from COM0 output. RE 0 SSN2 0 0 0 0 1 1 1 - 82 - RS 0 RW 0 SSN1 0 0 1 1 0 0 1 D7 0 SSN0 0 1 0 1 0 1 * D6 1 D5 1 D4 0 D3 * D2 SSN2 D1 SSN1 D0 SSN0 Scroll Start Line 1st line 2nd line 3rd line 4th line 5th line 6th line Inhibited Ver.2009-05-20 Preliminary NJU6645 - Example of Display Ver.2009-05-20 SSN=”000” (Default) 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 SSN=”001” 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 SSN=”010” 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 SSN=”011” 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 SSN=”100” 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 SSN=”101” 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 - 83 - Preliminary NJU6645 (k) Scroll Start Row The "Scroll Start Row" instruction controls number of the Scroll Start Row. RE 0 RS 0 SSL3 0 0 0 0 RW 0 SSL2 0 0 0 0 D7 0 SSL1 0 0 1 1 D6 1 D5 1 SSL0 0 1 0 1 D4 1 D3 SSL3 1 D1 SSL1 D0 SSL0 Scroll Start Row 1st row 2nd row 3rd row 4th row : : 1 D2 SSL2 : : 1 1 16th row - Example of Display SSL3 to 0=0 SSL3 to 0=1 SSL3 to 0=2 --- SSL3 to 0=14 SSL3 to 0=15 (Under Character) --- (l) Display Start Line The "Display Start Line" instruction controls the Display Start Line. The displayed data of the 1st line shifts to the setting line. RE 0 DST2 0 0 0 0 1 1 1 - 84 - RS 0 RW 0 DST1 0 0 1 1 0 0 1 D7 1 DST0 0 1 0 1 0 1 * D6 0 D5 0 D4 0 D3 * D2 DST2 D1 DST1 D0 DST0 Display Start Line 1st line 2nd line 3rd line 4th line 5th line 6th line Inhibited Ver.2009-05-20 Preliminary NJU6645 - Example of Display Ver.2009-05-20 DST=”000” (Default) 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 DST=”001” 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 DST=”010” 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 DST=”011” 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 DST=”100” 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 DST=”101” 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 - 85 - Preliminary NJU6645 (m) Display Duty Ratio The "Display Duty Ratio" instruction controls the number of display line, and is used to carry out the partial display. RE 0 RS 0 DN2 0 0 0 0 1 1 1 RW 0 DN1 0 0 1 1 0 0 1 D7 1 D6 0 DN0 0 1 0 1 0 1 * D5 0 D4 1 D3 * D2 DN2 D1 DN1 D0 DN0 Display Line (Duty) 6-line (1/98 Duty) 5-line (1/82 Duty) 4-line (1/66 Duty) 3-line (1/50 Duty) 2-line (1/34 Duty) 1-line (1/18 Duty) Inhibited (n) N-line Inversion The "N-line Inversion" instruction controls the number of inversion line. The setting range are 2 to 98 lines, and is alternated by setting (N+1). RE 0 RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 * D2 NL6 D1 NL5 D0 NL4 RE 0 RS 0 RW 0 D7 1 D6 0 D5 1 D4 1 D3 NL3 D2 NL2 D1 NL1 D0 NL0 NL3 0 0 0 0 NL2 0 0 0 0 NL6 0 0 0 0 NL5 0 0 0 0 NL4 0 0 0 0 NL1 0 0 1 1 NL0 0 1 0 1 : 1 1 1 1 0 0 0 0 : 0 0 0 0 0 1 1 1 1 : 1 - 86 - 1 1 1 Inversion Line Inhibited 2 3 4 97 98 Inhibited Ver.2009-05-20 Preliminary NJU6645 (o) Driver Output Control The "Driver Output Control" instruction controls the SEG / COM driver output direction. RE 0 RS 0 RW 0 D7 1 D6 1 D5 0 D4 0 SEL1 0 1 Function COM scan forward direction COM scan backward direction SEL2 0 1 Function SEG output forward direction SEG output backward direction D3 * D2 * D1 SEL1 D0 SEL2 (p) Oscillation Control The "Oscillation Control" instruction controls the system clock type and the internal capacitance of internal oscillation circuits. The frame frequency is adjusted by internal capacitance setting. When the frame frequency is set by this instruction, make sure what is the best setting in the particular application. RE 0 RS 0 RW 0 D7 1 INTCK 0 1 OC2 0 0 0 0 1 1 1 1 D6 1 D5 0 D4 1 D3 INTCK D2 OC2 D1 OC1 D0 OC0 Function Internal oscillation circuit External oscillation input OC1 0 0 1 1 0 0 1 1 OC0 0 1 0 1 0 1 0 1 Internal Capacitance Reference capacitance 0.7 x Reference capacitance 0.8 x Reference capacitance 0.9 x Reference capacitance 1.1 x Reference capacitance 1.2 x Reference capacitance 1.3 x Reference capacitance Inhibited (q) RE Flag Set The "RE Flag Set" instruction controls the access to the expanded register. When it accesses each instruction, it is necessary to set the RE flag in advance. RE * Ver.2009-05-20 RS 0 RW 0 D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 RE - 87 - Preliminary NJU6645 (r) Discharge Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VLCD, V1, V2, V3, V4 and VSS. This instruction prevents the unknown display at the power supply off. RE 1 RS 0 RW 0 D7 0 DIS 0 1 (s) D6 0 D5 0 D4 0 D3 * D2 * D1 * D0 DIS D3 * D2 VU2 D1 VU1 D0 VU0 D3 BS3 D2 BS2 D1 BS1 D0 BS0 Function Discharge OFF Discharge ON Boost Level The "Boost Level" instruction controls the level of Voltage Boost Circuit.. RE 1 RS 0 VU2 0 0 0 0 1 1 1 1 (t) RW 0 VU1 0 0 1 1 0 0 1 1 D7 0 D6 0 VU0 0 1 0 1 0 1 0 1 D5 0 D4 1 Boost Level 1 time (No boost) 2 times 3 times 4 times 5 times 6 times Inhibited Bias Ratio The "Bias Ratio" instruction controls the Bias Ratio. RE 1 RS 0 RW 0 BS3 0 0 0 0 0 0 0 0 1 1 1 BS2 0 0 0 0 1 1 1 1 0 0 0 1 1 D7 0 D6 0 BS1 0 0 1 1 0 0 1 1 0 0 1 BS0 0 1 0 1 0 1 0 1 0 1 0 1 1 D4 0 Bias Ratio 1/11 1/10 1/9 1/8 1/7 1/6 1/5.5 1/5 1/4.5 1/4 Inhibited : - 88 - D5 1 Ver.2009-05-20 Preliminary NJU6645 (u) Electrical Volume The "Electrical Volume" instruction adjusts VLCD to optimize display contrast. The voltage divided into 127 is set. The setting order requires upper byte first. RE 1 RS 0 RW 0 D7 0 D6 0 D5 1 D4 1 D3 * D2 EV6 D1 EV5 D0 EV4 RE 1 RS 0 RW 0 D7 0 D6 1 D5 0 D4 0 D3 EV3 D2 EV2 D1 EV1 D0 EV0 EV3 0 0 EV2 0 0 EV6 0 0 EV5 0 0 EV4 0 0 EV1 0 0 EV0 0 1 Output Voltage Low : : : 1 1 1 1 1 1 1 1 1 1 1 1 0 1 High This instruction is finally effective when both upper and lower bytes are transmitted in order to prevent high VLCD. The setting order is upper byte first, then lower byte. Note) When the electrical volume setting is changed to wide range at keeping display on, there is possibility that the unknown display appears. In this case, add waiting time and change the electrical volume value gradually. < Example of the changing from EV=80 to EV=110 at keeping display on > EV=80 → Wait (~ms) → EV=90 → Wait (~ms) → EV=100 → Wait (~ms) → EV=110 * The wait time and electrical volume setting range is different depending on the capacitance value of V1 to V4 and the panel size. Please make sure what is the best setting in the particular application. (v) Power Control RE 1 RS 0 RW 0 D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 AMPON DCON AMPON : This instruction controls ON/OFF of the operational amplifier parts of the internal power supply circuits (Voltage regulator, electrical variable resistor, and voltage converter). AMPON 0 1 DCON : This instruction controls Internal Voltage Booster ON/OFF, DCON 0 1 Ver.2009-05-20 Function Internal operational amplifier OFF Internal operational amplifier ON Function Voltage booster OFF Voltage booster ON - 89 - Preliminary NJU6645 (w) RAM Address Set The "RAM Address Set" instruction specifies the DDRAM, CGRAM, and MKRAM address. The RAM address should set lower 4-bit (AD3 to AD0) at first. This instruction is finally effective when upper 4-bit (AD11 to AD8) are transmitted. RE 1 RS 0 RW 0 D7 0 D6 1 D5 1 D4 0 D3 AD3 D2 AD2 D1 AD1 D0 AD0 RE 1 RS 0 RW 0 D7 0 D6 1 D5 1 D4 1 D3 AD7 D2 AD6 D1 AD5 D0 AD4 RE 1 RS 0 RW 0 D7 1 D6 0 D5 0 D4 0 D3 AD11 D2 AD10 D1 AD9 D0 AD8 (x) Address Shift The "Address Shift" instruction controls increment (+1) or decrement (-1) of the address. The address moves whenever this instruction is executed. RE 1 RS 0 RW 0 D7 1 ARL 0 1 D6 0 D5 0 D4 1 D3 * D2 * D1 * D0 ARL Function Address –1 Address +1 (y) Maker Test This instruction is using for device testing mode. Please do not use this instruction usually. - 90 - RE 1 RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 * D2 * D1 * D0 * RE 1 RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 * D1 * D0 * Ver.2009-05-20 Preliminary NJU6645 (21) TYPICAL INSTRUCTION SEQUENCE (21-1) Initialization Sequence in Using Internal LCD Power Supply Power ON (VDD, VEE) (*1) WAIT(*2) Reset (RSTb terminal) WAIT(*3) Refer to (15)RESET FUNCTION -------------------- Instruction Code ------------------- ----- Setting Example ----- Display Clear D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 RE Flag 1 1 1 1 * * * 1 RE=”1” Boost Level 0 0 0 1 * 1 0 1 6 times boost Bias Ratio 0 0 1 0 0 0 0 0 1/11 bias Electrical Volume (Upper) 0 0 1 1 * 1 0 0 EV=“1,0,0,0,0,0,0” Electrical Volume (Lower) 0 1 0 0 0 0 0 0 Power Control 0 1 0 1 * * 0 1 Voltage booster ”ON” 0 1 0 1 * * 1 1 Internal operational amplifier ”ON” Display clear WAIT(*4) Power Control WAIT(*5) End *1 *2 *3 *4 *5 If different power sources are applied to the VDD and the VEE, turn ON the VDD first. Wait until the VDD and VEE are stabilized. Wait 1.5ms or more. Wait until the VDCOUT (VOUT) is stabilized. Wait until the VLCD and V1 to V4 are stabilized. Ver.2009-05-20 - 91 - NJU6645 Preliminary (21-2) Initialization Sequence in Using External LCD Power Supply Power ON (VDD) WAIT(*1) Reset (RSTb terminal) Refer to (15)RESET FUNCTION WAIT(*2) External Power Supply ON WAIT(*3) Display Clear -------------------- Instruction Code ------------------D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 ----- Setting Example ----- Display clear End *1 *2 *3 - 92 - Wait until the VDD is stabilized. Wait 1.5ms or more. Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized. Ver.2009-05-20 Preliminary NJU6645 (21-3) Display Data Write Sequence Operational Status -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 1 RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1st line DDRAM address Set (000h) RAM Data Write * * * * * * * * 1st line writing RAM Data Write * * * * * * * * RE=”1” DDRAM data Repeating 2nd to 5th line RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 6th line DDRAM address set (0A0h) RAM Data Write * * * * * * * * 6th line DDRAM data writing RAM Data Write * * * * * * * * RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 MKRAM address set (100h) RAM Data Write * * * * * * * * MKRAM data writing RAM Data Write * * * * * * * * RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 CGRAM address set (200h) RAM Data Write * * * * * * * * CGRAM Data Writing RAM Data Write * * * * * * * * RE Flag 1 1 1 1 * * * 0 RE=”0” Display Control 0 0 1 0 0 0 1 1 Dot matrix display “ON” Icon display ”ON” Data Display Ver.2009-05-20 - 93 - NJU6645 Preliminary (21-4) Power OFF Sequence in Using Internal LCD Power Supply Operational Status -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 0 Display Control 0 0 1 0 0 0 0 0 Display ”OFF" Standby 0 0 1 1 * * * 1 Standby ”ON” RE Flag 1 1 1 1 * * * 1 RE=”1” Discharge 0 0 0 0 * * * 1 Discharge ”ON” RE=”0” WAIT(*1) Power OFF (VEE) Power OFF (VDD) *1 Wait until the discharge is completed. (21-5) Power OFF Sequence in Using External LCD Power Supply Operational Status -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 0 Display Control 0 0 1 0 0 0 0 0 Display ”OFF" Standby 0 0 1 1 * * * 1 Standby ”ON” RE Flag 1 1 1 1 * * * 1 RE=”1” Discharge 0 0 0 0 * * * 1 Discharge ”ON” RE=”0” External Power OFF WAIT(*1) Power OFF (VEE) Power OFF (VDD) *1 - 94 - Wait until the discharge is completed. Ver.2009-05-20 Preliminary NJU6645 (21-6) Partial Display Sequence [Example : Display Duty Ratio = 2-line (1/34 Duty), Display Start Line = 3rd line] Operational Status -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 0 Display Control 0 0 1 0 0 0 0 0 Display ”OFF" RE Flag 1 1 1 1 * * * 1 RE=”1” Power Control 0 1 0 1 * * 0 0 Voltage booster ”OFF” Internal operational amplifier ”OFF” Boost Level 0 0 0 1 * 0 1 0 3 times boost Bias Ratio 0 0 1 0 0 1 0 1 1/6 bias Electrical Volume (Upper) 0 0 1 1 * 1 0 0 EV=“1,0,0,0,0,0,0” Electrical Volume (Lower) 0 1 0 0 0 0 0 0 Power Control 0 1 0 1 * * 0 1 Voltage booster ”ON” 0 1 0 1 * * 1 1 Internal operational amplifier ”ON” RE Flag 1 1 1 1 * * * 0 RE=”0” Display Start line 1 0 0 0 * 0 1 0 3rd line Display Duty Ratio 1 0 0 1 * 1 0 0 2-line (1/34Duty) Display Control 0 0 1 0 0 0 1 1 Dot matrix display “ON” Icon display ”ON” RE=”0” WAIT(*1) WAIT(*2) Power Control WAIT(*3) Partial Display *1 *2 *3 Wait until the discharge is completed. Wait until the VDCOUT (VOUT) is stabilized. Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized. Refer to (10) PARTIAL DISPLAY . Ver.2009-05-20 - 95 - NJU6645 Preliminary (21-7) Smooth Scroll Display Sequence [Example : 5-line display, 4-dot scroll] 5-line display, Display ON -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 0 Scroll Start Row 0 1 1 1 0 1 0 0 4-row scroll Scroll Start Row 0 1 1 1 1 0 0 0 8-row scroll Scroll Start Row 0 1 1 1 1 1 0 0 12-row scroll Scroll Start Row Scroll Start Line 0 0 1 1 1 1 1 0 0 * 0 0 0 0 0 1 0-row scroll 1-line scroll RE Flag 1 1 1 1 * * * 1 RE=”1” RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1st line DDRAM address set (000h) RAM Data Write * * * * * * * * 1st line writing RAM Data Write * * * * * * * * RE Flag 1 1 1 1 * * * 0 RE=”0” Scroll Start Row 0 1 1 1 0 1 0 0 4-row scroll Scroll Start Row 0 1 1 1 1 0 0 0 8-row scroll Scroll Start Row 0 1 1 1 1 1 0 0 12-row scroll Scroll Start Row Scroll Start Line 0 0 1 1 1 1 1 0 0 * 0 0 0 1 0 0 0-row scroll 2-line scroll RE=”0” DDRAM data Refer to (11) VERTICAL SMOOTH S SCROLL. - 96 - Ver.2009-05-20 Preliminary NJU6645 (21-8) Superimpose Mode Display Sequence [Example : Character display on 2nd ~ 5th line] Operational Status -------------------- Instruction Code ------------------- ----- Setting Example ----- RE Flag D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 0 Display / Entry Mode 0 1 0 1 * 1 0 0 Superimpose mode RE Flag 1 1 1 1 * * * 1 RE=”1” RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2nd line DDRAM address set (020h) RAM Data Write * * * * * * * * 2nd line DDRAM data writing RAM Data Write * * * * * * * * RE=”0” Repeating 3rd to 4th line RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 5th line DDRAM address set (080h) RAM Data Write * * * * * * * * 5th line DDRAM data writing RAM Data Write * * * * * * * * RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 CGRAM address set (200h) RAM Data Write * * * * * * * * CGRAM data writing RAM Data Write * * * * * * * * RE Flag 1 1 1 1 * * * 0 RE=”0” Display Control 0 0 1 0 0 0 1 1 Dot matrix display “ON” Icon display ”ON” Data Display Refer to (13-3) Superimpose Mode. Ver.2009-05-20 - 97 - NJU6645 Preliminary ! ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage (1) Operating Temperature Storage Temperature *1 *2 SYMBOL VDD VEE VOUT, VDCOUT VREG VLCD V1, V2, V3, V4 VI CONDITION VSS=0V Common Ta=+25°C TERMINAL VDD VEE VOUT, VDCOUT VREG VLCD V1, V2, V3, V4 Topr Tstg Bump Chip RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to VLCD+0.3 -0.3 to VDD+0.3 UNIT V V V V V V V -40 to +85 °C -55 to +125 °C If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. The order of turning on the power supply should turn on VDD earlier than other power supplies. When the power supply is turned off, that requires turning off VDD at the last. ! RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Operating Voltage *1 *2 *3 *4 *5 *6 *7 - 98 - SYMBOL VDD1 VDD2 VEE VLCD VOUT VDCOUT VREG VREF TERMINAL VDD VEE VLCD VOUT VDCOUT VREG VREF MIN 2.4 2.4 2.4 4.5 1.8 TYP - MAX UNIT 3.6 V 3.6 V 3.6 V 17.0 V 17.0 V 17.0 V VOUTx0.9 V 3.6 V NOTE *1 *2 *3 *4 *5 *6 Applied to the condition when the reference voltage generator (VBA) is not used. (VSS common) Applied to the condition when the reference voltage generator (VBA) is used. (VSS common) Applied to the condition when the voltage booster is used. The following relation among the LCD bias voltages must be maintained. VSS<V4<V3<V2<V1<VLCD≤VOUT When the voltage booster is used, there is possibility that the VDCOUT is changing by the ITO resistance and the panel load. The setting of the VREG voltage is recommended to become a voltage that is lower than the lowest value of the changing VOUT. Relation : VREF < VEE must be maintained. To stabilize the LSI operation, place decoupling capacitors between VDD and VSS, between VEE and VSS, between VBA and VSS, between VREF and VSS, between VREG and VSS, between VLCD and VSS, and between V1 to V4 and VSS. Ver.2009-05-20 Preliminary NJU6645 ! DC CHARACTERISTICS VDD=+2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C SYM PARAMETER BOL “H” Level Input Voltage VIH “L” Level Input Voltage VIL “H” Level Output Voltage VOH “L” Level Output Voltage VOL Input Leakage Current ILI Output Leakage Current ILO RON1 Driver ON-resistance RON2 Oscillation Frequency fOSC Voltage Booster VOUT Output Voltage Operating Current (1) Operating Current (2) Operating Current (3) Operating Current (4) VBA Output Voltage VREG Output Voltage LCD Bias Voltages *1 *2 *3 *4 *5 *6 *7 *8 *9 CONDITION IOH=-0.1mA IOL= 0.1mA VI=VSS or VDD VI=VSS or VDD |∆VON|=0.5V, VLCD=10V |∆VON|=0.5V, VLCD=6V VDD=3V, Ta=25°C, Rf=47kΩ N-time boost (N=2 to 6) RL=500kΩ (VDCOUT-VSS) Ta=25°C, 6-time boost, All pixels ON, IDD1 VEE=2.4V, VREF=1.8V Ta=25°C, 5-time boost, All pixels ON, IDD2 VEE=3.0V, VREF=2.25V Ta=25°C, 4-time boost, All pixels ON, IDD3 VEE=3.6V, VREF=2.7V ISTB Ta=25°C, CSb=VDD, HALT="1” VEE=2.4 to 3.6V VBA MIN TYP MAX 0.8VDD VSS VDD-0.2 -1 -1 0.82 NxVEE x0.95 1 2 1 VDD 0.2VDD 0.2 1 1 2 4 1.18 V V V V µA µA kΩ kΩ MHz *1 *1 *2 *2 *3 *4 - - V *7 - 1.5 3.6 mA - 1.5 3.6 mA - 1.5 3.6 mA 10 (0.75VEE)x (0.75VEE)x 0.75VEE 0.98 1.02 (VREFxN)x VEE=2.4 to 3.6V (VREFxN)x (VREFxN) VREG 1.05 N-time boost (N=2 to 6) 0.95 VLCD VEE=3.0V, VREF=2.25V, -0.1 +0.1 VOUT=15V, Bias=1/4 to 1/11, V1 -0.1 +0.1 Electrical Volume=MAX., DCON=”0”, V2 -0.1 +0.1 Display OFF, No-load, AMPON=”1”, V3 -0.1 +0.1 Boost Level=5-time V4 -0.1 +0.1 UNIT NOTE *5 *6 *8 µA *9 V *10 V *11 V V V V V D7 to D0, CSb, RS, WRb, RDb, SEL68, PS, CSEL, and RSTb terminals. D7 to D0 terminals. D7 to D0, CSb, RS, WRb, RDb, SEL68, PS, CSEL, RSTb, and OSC2 terminals. D7 to D0 in high impedance. SEG0 to SEG255, COM0 to COM95, and COMMK0 to COMMK1 terminals. This parameter defines the resistance between each COM/SEG and each LCD bias (VLCD, V1, V2, V3, V4). 0.5V difference / 1/11 LCD bias Oscillation frequency of using the internal oscillation circuit. (OS2, OS1, OS0) = ”0, 0, 0” VDCOUT terminal. This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used. N-time boost (N=2 to 6). VEE=2.4V to 3.6V / Electrical Volume : Max = “1, 1, 1, 1, 1, 1, 1” / 1/11 LCD Bias / 1/98 Duty / No-load on COM/SEG / RL=500kΩ between VDCOUT and VSS / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1” VSS terminal. This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used, and the no accessing from MPU. Electrical Volume : Max = “1, 1, 1, 1, 1, 1, 1” / All pixels ON or Checker Flag Display / No-load on COM/SEG / VDD=VEE / VREF=0.75VEE / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1” / NL6 to 0=”1, 1, 0, 0, 0, 0, 1” (98-line) / 1/98 Duty / Ta=25°C VDD terminal. Internal oscillator is halted. / CSb=VDD (No active) / No-load Ver.2009-05-20 - 99 - NJU6645 Preliminary *10 VBA terminal. VBA=VREF / Boost Level (N)=”1” / DCON=”0” / VOUT=13.5V *11 VREG terminal. VEE=2.4V to 3.6V / VOUT=17V / 1/11 LCD Bias / 1/98 Duty / Electrical Volume : Max = “1, 1, 1, 1, 1, 1, 1” / Checker Flag Display / No-load on COM/SEG / Boost Level (N)=”2 to 6” / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”0” / AMPON=”1” / NL6 to 0=”1, 1, 0, 0, 0, 0, 1” (98-line) - 100 - Ver.2009-05-20 Preliminary NJU6645 ! OSCILLATION FREQUENCY AND FRAME FREQUENCY OSCILLATOR /EXTERNAL CLOCK Using Internal Oscillator Using External Clock Ver.2009-05-20 DISPLAY DUTY (1/D) 98 82 66 50 34 18 fOSC/(128xD) fOSC/(128xD) fOSC/(128xD) fOSC/((128xD)/2) fOSC/((128xD)/3) fOSC/((128xD)/6) fCK/(128xD) fCK/(128xD) fCK/(128xD) fCK/((128xD)/2) fCK/((128xD)/3) fCK/((128xD)/6) - 101 - NJU6645 Preliminary ! AC CHARACTERISTICS (1) Write Operation (Parallel Interface / 80-series MPU) tRSS8 tRSH8 RS tWCS8 CSb WRb tCSH8 tCSS8 tWRLW8 tWRHW8 tDS8 tDH8 D7 to D0 tCYC8 PARAMETER SYMBOL CONDITION RS Hold Time tRSH8 RS Setup Time tRSS8 CSb Hold Time tCSH8 CSb Setup Time tCSS8 CSb ”H” Level Pulse Width tWCS8 System Cycle Time tCYC8 Enable ”L” Level Pulse Time tWRLW8 Enable ”H” Level Pulse Time tWRHW8 Data Setup Time tDS8 Data Hold Time tDH8 Note) Each timing is specified based on 20% and 80% of VDD. - 102 - MIN. 30 30 30 30 180 180 80 80 70 40 (VDD=2.4 to 3.6V, Ta=-40 to +85°C) MAX. UNIT TERMINAL ns RS ns ns CSb ns ns ns WRb ns ns ns D7 to D0 ns Ver.2009-05-20 Preliminary (2) Read Operation (Parallel Interface / 80-series MPU) tRSS8 NJU6645 tRSH8 RS tWCS8 CSb tCSH8 tCSS8 tWRLR8 RDb tWRHR8 tRDH8 D7 to D0 tRDD8 tCYC8 PARAMETER SYMBOL CONDITION RS Hold Time tRSH8 RS Setup Time tRSS8 CSb Hold Time tCSH8 CSb Setup Time tCSS8 CSb ”H” Level Pulse Width tWCS8 System Cycle Time tCYC8 Enable ”L” Level Pulse Time tWRLR8 Enable ”H” Level Pulse Time tWRHR8 Read Data Delay Time tRDD8 CL=15pF Read Data Hold Time tRDH8 Note) Each timing is specified based on 20% and 80% of VDD. Ver.2009-05-20 MIN. 40 40 40 40 140 250 120 120 0 (VDD=2.4 to 3.6V, Ta=-40 to +85°C) MAX. UNIT TERMINAL ns RS ns ns CSb ns ns ns RDb ns ns 110 ns D7 to D0 ns - 103 - NJU6645 Preliminary (3) Write Operation (Parallel Interface / 68-series MPU) tRSS6 tRSH6 RS tWCS6 CSb tCSH6 tCSS6 RW (WRb) E (RDb) tEHW6 tELW6 tDS6 tDH6 D7 to D0 tCYC6 PARAMETER SYMBOL CONDITION RS Hold Time tRSH6 RS Setup Time tRSS6 CSb Hold Time tCSH6 CSb Setup Time tCSS6 CSb ”H” Level Pulse Width tWCS6 System Cycle Time tCYC6 Enable ”L” Level Pulse Time tELW6 Enable ”H” Level Pulse Time tEHW6 Data Setup Time tDS6 Data Hold Time tDH6 Note) Each timing is specified based on 20% and 80% of VDD. - 104 - MIN. 30 30 30 30 180 180 80 80 70 40 (VDD=2.4 to 3.6V, Ta=-40 to +85°C) MAX. UNIT TERMINAL ns RS ns ns CSb ns ns ns E ns ns ns D7 to D0 ns Ver.2009-05-20 Preliminary (4) Read Operation (Parallel Interface / 68-series MPU) tRSS6 NJU6645 tRSH6 RS tWCS6 CSb tCSH6 tCSS6 RW (WRb) tEHR6 E (RDb) tELR6 tRDH6 D7 to D0 tRDD6 tCYC6 PARAMETER SYMBOL CONDITION RS Hold Time tRSH6 RS Setup Time tRSS6 CSb Hold Time tCSH6 CSb Setup Time tCSS6 CSb ”H” Level Pulse Width tWCS6 System Cycle Time tCYC6 Enable ”L” Level Pulse Time tELR6 Enable ”H” Level Pulse Time tEHR6 Read Data Delay Time tRDD6 CL=15pF Read Data Hold Time tRDH6 Note) Each timing is specified based on 20% and 80% of VDD. Ver.2009-05-20 MIN. 40 40 40 40 140 250 120 120 0 (VDD=2.4 to 3.6V, Ta=-40 to +85°C) MAX. UNIT TERMINAL ns RS ns ns CSb ns ns ns E ns ns 110 ns D7 to D0 ns - 105 - Preliminary NJU6645 (5) Serial Interface RS tAAS tAHS tAAS tAHS RW CSb tCSS tCYCS tSHW SCL tDSS SDA Input Input or Output Input Input or Output Output tSLW Input Input Input or Output Output Output Input or Output Input tSOD Output PARAMETER SYMBOL CONDITION Serial Clock Cycle tCYCS SCL ”H” Level Pulse Width tSHW SCL ”L” Level Pulse Width tSLW Address Setup Time tASS Address Hold Time tAHS Data Setup Time tDSS Data Hold Time tDHS Serial Data Delay Time tSOD CSb – SCL Time tCSS CSb Hold Time tCSH CSb “H” Level Pulse Width tWCSS Note) Each timing is specified based on 20% and 80% of VDD. - 106 - tWCSS tDHS tSOD SDA Output tCSH MIN. 160 75 75 35 35 35 35 35 35 75 (VDD=2.4 to 3.6V, Ta=-40 to +85°C) MAX. UNIT TERMINAL ns SCL ns ns ns RS / RW ns ns SDA ns 40 ns SDA ns ns CSb ns Ver.2009-05-20 Preliminary NJU6645 ! External Clock Input Timing OSC2 0.5VDD fCP PARAMETER SYMBOL External Clock Operating Frequency fCP External Clock Duty duty MIN. 35 (VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C) MAX. CONDITION UNIT 1.18 OSC2 MHz 65 % ! Reset Input Timing tRW RSTb tR Internal circuit status PARAMETER Reset Time RSTb “L” Level Pulse Width Ver.2009-05-20 During reset SYMBOL tR tRW MIN. 1.5 End of reset (VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C) MAX. CONDITION UNIT 0.5 µs ms - 107 - Preliminary NJU6645 ! APPLICATION CIRCUIT (1) Microprocessor Interface Example (i) 80 type MPU 2.4 to 3.6V VCC A0 A1~A7 (80 type MPU) IORQb D0~D7 RDb WRb RESb RS 7 Decoder 8 GND VDD CSb NJU6645 D0~D7 RDb WRb RSTb VSS Reset input (ii) 68 type MPU 2.4 to 3.6V VCC A0 A1~A15 15 (68 type MPU) VMA D0~D7 E R/W RESb GND RS Decoder 8 VDD CSb NJU6645 D0~D7 RDb(E) WRb(R/W) RSTb VSS Reset input (iii) Serial Interface 2.4 to 3.6V VCC A0 A1~A7 (CPU) RS 7 Decoder - 108 - NJU6645 SDA SCL RSTb PORT1 PORT2 RESb GND CSb VDD Reset input VSS Ver.2009-05-20 Preliminary NJU6645 (2) Connection with Panel Display (i) SEL1=”0”, SEL2=”0” SEG255 COM47 : : COM0 COMMK0 SEG0 ABCDEFG HIJKLMN OPQRSTU VWXYZ NJU6645 TOP VIEW COMMK1 COM95 : : COM48 (ii) SEL1=”1”, SEL2=”1” SEG0 COMMK1 COMMK0 NJU6645 TOP VIEW SEG255 COM48 : : COM95 COM0 : : COM47 ABCDEFG HIJKLMN OPQRSTU VWXYZ Ver.2009-05-20 - 109 - NJU6645 Preliminary (iii) SEL1=”1”, SEL2=”0” COMMK0 SEG255 NJU6645 BOTTOM VIEW SEG0 COM0 : : COM47 COM48 : : COM95 COMMK1 ABCDEFG HIJKLMN OPQRSTU VWXYZ (iv) SEL1=”0”, SEL2=”1” COM95 : : COM48 - 110 - SEG255 COMMK1 SEG0 ABCDEFG HIJKLMN OPQRSTU VWXYZ NJU6645 BOTTOM VIEW COM47 : : COM0 COMMK0 Ver.2009-05-20 Preliminary NJU6645 ! COG WIRING EXAMPLE COG 80type Parallel CSEL="L" Using Internal OSC Using Voltage Boost Using Internal OP-amp NJU6645 C5N C5P C4N C4P C3N C3P C2N C2P C1N C1P VEE VDCOUT VOUT *When the voltage booster is used, VDCOUT terminal and VOUT terminal should be not connect at ITO of inside panel, and it requires to connect at outside of COG. VSS VBA VREF VREG V4 V3 V2 V1 VLCD VSS OSC1 VDD OSC2 D7 D6 D5 D4 D3 D2 D1 D0 VPUP RDB WRB VPDN RS CSB RSTB CSEL VPUP PS VPUP SEL68 TESTOUT Ver.2009-05-20 - 111 - NJU6645 Preliminary [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 112 - Ver.2009-05-20