PHILIPS NE5537N Sample-and-hold amplifier Datasheet

Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DESCRIPTION
PIN CONFIGURATIONS
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kΩ load. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
FE and N Packages
V+ 1
8
LOGIC
OFFSET ADJUST 2
7
LOGIC REFERENCE
INPUT 3
6
Ch
V– 4
5
OUTPUT
D1 Package
INPUT
1
14 V
OS ADJ
NC
2
13 NC
V–
3
12 V+
NC
4
11 LOGIC
NC
5
10 LOGIC REFERENCE
NC
6
9
NC
7
8
Ch
FEATURES
• Operates from ±5V to ±18V supplies
• Hold leakage current 6pA @ TJ = 25°C
• Less than 4µs acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5mV typical hold step at CH=0.01µF
• Low input offset: 1MV (typical)
• 0.002% gain accuracy with RL=2kΩ
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
OUTPUT
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
30k
5
–
INPUT
LOGIC
3
OUTPUT
+
8
–
7
LOGIC
REFERENCE
300
+
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
August 31, 1994
884
TEMPERATURE RANGE
ORDER CODE
DWG #
0 to +70°C
NE5537N
0404B
0 to +70°C
NE5537D
0175D
-55°C to +125°C
SE5537FE
0404B
853-1044 13721
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
±18
V
N package
1160
mW
D package
1090
mW
FE package
780
mW
SE5537
-55 to +125
°C
NE5537
0 to +70
°C
-65 to +150
°C
VS
Voltage supply
PD
Maximum power dissipation
TA=25°C (still-air)1
TA
Operating ambient temperature range
TSTG
Storage temperature range
VIN
Input voltage
Equal to supply voltage
Logic to logic reference differential voltage2
+7, -30
Output short circuit duration
TSOLD
V
Indefinite
Hold capacitor short circuit duration
10
s
Lead soldering temperature (10sec max)
300
°C
NOTES:
1. Derate above 25°C at the following rates:
FE package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply
voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below
the positive supply and 3V above the negative supply.
August 31, 1994
885
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DC ELECTRICAL CHARACTERISTICS1
SYMBOL
PARAMETER
TEST CONDITIONS
SE5537
Min
TJ=25°C
VOS
Max
1
3
5
25
Min
UNIT
Typ
Max
2
7
mV
10
mV
50
nA
100
nA
0.01
%
0.02
%
Input offset voltage4
Full temperature range
5
TJ=25°C
IBIAS
NE5537
Typ
10
Input bias current4
Full temperature range
75
Input impedance
TJ=25°C
1010
1010
Gain error
TJ=25°C
0.002 0.007
0.004
Ω
-10V≤VIN≤10V, RL=2kΩ
-11.5V≤VIN≤11.5V,
RL=10kΩ
Full temperature range
Feedthrough attenuation
ratio at 1kHz
Output impedance
TJ=25°C, CH=0.01µF
0.02
86
TJ=25°C, “HOLD” mode
96
0.5
Full temperature range
“HOLD” Step2
ICC
Supply current4
80
2
90
0.5
4
dB
4
Ω
6
TJ=25°C, CH=0.01µF, VOUT=0
0.5
2.0
1.0
2.5
mV
TJ=25°C
4.5
6.5
4.5
7.5
mA
TJ=25°C
2
10
2
10
µA
TJ=25°C “hold” mode3
6
50
6
100
pA
VOUT=10V,
CH=1000pF
4
4
µs
Logic and logic reference
input current
Leakage current into hold
capacitor4
Acquisition time to 0.1%
SVRR
CH=0.01µF
20
20
µs
Hold capacitor charging
current
VIN-VOUT=2V
5
5
mA
Supply voltage rejection
ratio
VOUT=0V
80
110
80
110
dB
Differential logic threshold
TJ=25°C
0.8
1.4
0.8
1.4
2.4
2.4
V
NOTES:
1. Unless otherwise specified, the following conditions apply: Unit is in “sample” mode. VS=±15V, TJ=25°C, -11.5V≤VIN≤11.5V, CH=0.01µF, and
RL=2kΩ. Logic reference voltage=0V and logic voltage=2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor
value.
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. These parameters guaranteed over a supply voltage range of ±5 to ±18V.
August 31, 1994
886
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current
Output Short-Circuit Current
Gain Error
30
INPUT VOLTAGE — OUTPUT VOLTAGE (mV)
25
28
20
26
CURRENT (mA)
CURRENT (nA)
15
10
5
0
24
SOURCING
22
20
SINKING
18
16
–5
14
–10
–15
–50
12
–25
0
25
50
75
100
125
10
–50
150
JUNCTION TEMPERATURE (°C)
–25
0
25
50
75
100
125
1
TJ = 25°C
RL = 2kΩ
SAMPLE MODE
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
150
–15
–10
–5
0
5
10
15
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Leakage Current Into
Hold Capacitor
Hold Step
10
100
2
VOUT = 0
HOLD MODE
1
CURRENT (nA)
1
10–1
10–2
0.1
1000pF
0.01µF
0.1µF
10–3
–50
1µF
–25
25
50
75
Acquisition Time
TJ = 100°C
1.4
1.2
1
TJ = 25°C
0.8
0.6
TJ = –55°C
0.4
0.2
0
–15
150
VIN = 0 TO ±10V
225
200
1%
175
TIME (ns)
10
0.1%
150
V+ = V– = 15V
∆VIN – 10V
NEGATIVE
INPUT
STEP
125
25
HOLD CAPACITOR (µF)
5
10
15
POLYPROPYLENE
AND POLYSTYRENE
TIME CONSTANT
1
MYLAR
TIME
CONSTANT
POLYPROPYLENE
AND POLYSTYRENE
HYSTERSIS
0.1
0
–50
0
10
POSITIVE
INPUT
STEP
50
0.1
MYLAR
HYSTERESIS
∆VOUT ≤ 1mV
75
0.01
–5
Capacitor Hysteresis
100
100
0.01%
100
–10
INPUT VOLTAGE (V)
250
TJ = 25°C
August 31, 1994
125
1.6
Aperture Time
1
1000
0.001
100
1.8
JUNCTION TEMPERATURE (°C)
HOLD CAPACITOR
TIME ( µ s)
0
FINAL SAG (mV)
HOLD STEP (mV)
TJ = 25°C
10
NORMALIZED HOLD STEP AMPLITUDE
VS = ±15V
V+ = V– = 15V
0.01
100pF
Hold Step vs Input Voltage
–25
0
25
50
75
100 125 150
JUNCTION TEMPERATURE (°C)
887
0.1
1
10
SAMPLE TIME (ms)
100
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Dynamic Sampling Error
100
Output Droop Rate
Hold Settling Time
100
330pF
2
1.8
10–1
0.01µF
0.033µF
0.1µF
0.03µF
3300pF
1000pF
TJ = 85°C
10–2
10–3
–10
TIME ( µ S)
±1
1.4
∆ V/ ∆ T (V/SEC)
ERROR (mV)
10
V+ = V– = 15V
SETTLING TO 1mV
1.6
1.2
1
0.8
0.6
TJ = 25°C
0.4
0.2
1
10
100
10–4
100pF
1000
1000pF
70
–5
60
–10
50
40
30
20
10
1M
0
10M
50
75 100 125 150
160
TJ = 25°C
V+ = V– = 15V
VOUT = 0V
140
120
140
100
POSITIVE
SUPPLY
80
NEGATIVE
SUPPLY
60
120
100
“HOLD” MODE
80
60
40
40
20
20
0
100
10k
100k
1M
–130
–120
–110
Ch = 0.1µF
V+ = V– = 15V
VIN = 10VP-P
V7,8 = 0
TJ = 25°C
–100
Ch = 0.01µF
–90
–80
Ch = 1000pF
–70
–60
–50
10
100
1k
10k
FREQUENCY (Hz)
888
10
100
1k
10k
FREQUENCY (Hz)
Feedthrough Rejection
Ratio (Hold Mode)
1
SAMPLE MODE
0
1k
FREQUENCY (Hz)
RATIO (dB)
25
Output Noise
160
FREQUENCY (Hz)
August 31, 1994
0
JUNCTION TEMPERATURE (°C)
Hz)
80
0
REJECTION (dB)
5
100k
0
–50 –25
1µF
Power Supply Rejection
INPUT TO OUTPUT PHASE DELAY (DEG)
GAIN—INPUT TO OUTPUT (dB)
Phase and Gain
(Input-to-Output, Small-Signal)
10k
0.1µF
HOLD CAPACITOR
INPUT SLEW RATE (V/ms)
1k
0.01µF
NOISE (nV/
–100
0.1
100k
1M
100k
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
Gain Error —
The ratio of output voltage swing to input voltage swing in the
sample mode expressed as a percent difference.
SAMPLE-AND-HOLD
For many years designers have used the sample-and-hold (or
track-and-hold) to operate on analog information in a time frame
which is expedient.
Hold Mode Droop —
The output voltage change per unit of time while in hold. Commonly
specified in V/s, µV/µs or other convenient units.
By sampling a segment of the information and holding it until the
proper timing for converting to some form of control signal or
readout, the designer maintains certain freedom in performing
predetermined manipulative functions. Therefore, the
sample-and-hold can be defined as a “selective analog memory
cell”.
Hold Mode Feedthrough —
The percentage of an input sinusoidal signal that is measured at the
output of a sample-hold when it’s in hold mode.
Hold Settling Time —
The time required for the output to settle within 1mV of final value
after the “HOLD” logic command.
The memory is volatile and will also decay with time.
When using the sample-and-hold method for evaluating signal
information, the designer is given the added feature of eliminating
outside noise elements. With the analog-to-digital converter
products available today, the “DC memory” of the sample-and-hold
can be easily converted to digital format and further incorporated
into microprocessor-based systems.
Hold Step —
The voltage step at the output of the sample-and-hold when
switching from sample mode to hold mode with a steady (DC)
analog input voltage. Logic swing is 5V.
Parametric evaluation of the sample-and-hold will be discussed in
the following paragraphs.
Sample-to-Hold Offset Error —
The difference in output voltage between the time the switch starts
to open, and the time when the output has settled completely. It is
caused by charge being transferred to the hold capacitor switch as it
opens.
DEFINITION OF TERMS
Slew Rate —
The fastest rate at which the sample-and-hold output can change
(specified in V/µs).
Acquisition Time —
The time required to acquire a new analog input voltage with an
output step of 10V. Note that acquisition time is not just the time
required for the output to settle, but also includes the time required
for all internal nodes to settle so that the output assumes the proper
value when switched to the hold mode.
Threshold Level —
That level which causes the switch control to change state.
Aperture Delay Time —
The time elapsed from the hold command to the opening of the
switch.
BASIC BLOCK DIAGRAM
The basic circuit concept of the sample-and-hold circuit incorporates
the use of two (2) operational amplifiers and a switch control
mechanism (which determines sample, hold or track conditions).
Aperture Jitter —
Also called “aperture uncertainty time”, it is the time variation or
uncertainty with which the switch opens, or the time variation in
aperture delay.
The block diagram of the NE5537 is a closed loop, non-inverting
unity gain sample-and-hold system. The input buffer amplifier
supplies the current necessary to charge the hold capacitor, while
the output buffer amplifier closes the loop so that the output voltage
is identical to the input voltage (with consideration for input offset
voltage, offset current, and temperature variations which are
common to all sample-and-hold circuits, be they monolithic, hybrid
or modular).
Aperture Time —
The delay required between “HOLD” command and an input analog
transition, so that the transition does not affect the held output.
Bandwidth —
The frequency at which the gain is down 3dB from its DC value. It’s
measured in sample (track) mode with a small-signal sine wave that
doesn’t exceed the slew rate limit.
When the sampling switch is open (in the hold mode), the clamping
diodes close the loop around the input amplifier to keep it from being
overdriven into saturation.
Dynamic Sampling Error —
The error introduced into the hold output due to a changing analog
input at the time the hold command is given. Error is expressed in
mV with a given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
The switch control is driven by external logic levels via a timing
sequence remote from the sample-and-hold device (See Figure 1).
The switch control has a floating reference (Pin 7), referred to as the
logic reference which makes the sample-and-hold device compatible
to several types of external logic signals (TTL, PMOS, and CMOS).
The switching device operates at a threshold level of 1.4V.
Effective Aperture Delay —
The time difference between the hold command and the time at
which the input signal is at the held voltage.
Figure of Merit —
The ratio of the available charging current during sample mode to
the leakage current during hold mode.
August 31, 1994
889
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DATA ACQUISITION SYSTEMS
V+
1
ANALOG INPUT
4
3
7
SAMPLE 5V
HOLD 0V
LOGIC
INPUT
As mentioned earlier, the designer may wish to operate on several
different segments of an “analog” signal; however, he is limited by
the fact that only one analog-to-digital converter channel is available
to him. Figure 3 shows the means by which a multiplexing system
may be accomplished.
V–
8
5
6
OUTPUT
Ch
APPLICATION HINTS
Figure 1. Typical Connection
Hold Capacitor
The switch mechanism is on (sampling an information stream) when
the logic level is high (Pin 8 is 1.4V higher than Pin 7) and presents
a load of 5µA to the input logic signal. The analog sampled signal is
amplified, stored (in the external holding capacitor), and buffered. At
the end of the sampling period, the internal switch mechanism turns
off (switch opens) and the “stored analog memory” information on
the external capacitor (Pin 6) is loaded down by an operational
amplifier connected in the unity gain non-inverting configuration.
This input impedance of this amplifier is effectively:
R
where R
A significant source of error in an accurate sample-and-hold circuit
is dielectric absorption in the hold capacitor. A mylar cap, for
instance, may “sag back” up to 0.2% after a quick change in voltage.
A long “soak” time is required before the circuit can be put back in
the hold mode with this type of capacitor. Dielectrics with very low
hysteresis are polystyrene, polypropylene, and teflon. Other types
such as mica and polycarbonate are not nearly as good. Ceramic is
unusable with >1% hysteresis. The advantage of polypropylene over
polystyrene is that it extends the maximum ambient temperature
from 85°C to 100°C. The hysteresis relaxation time constant in
polystyrene, for instance, is 10-50ms. If A-to-D conversion can be
made within 1ms, hysteresis error will be reduced by a factor of ten.
= RIN (AOL) / (1 + 1/A)
= Effective input impedance
RIN = Open-loop input impedance
AOL = Open-loop gain
A
DC ZEROING
= AC loop gain
DC zeroing is accomplished by connecting the offset adjust pin to
the wiper of a 1kΩ potentiometer which has one end tied to V+ and
the other end tied through a resistor to ground. The resistor should
be selected to give 0.6mA through the 1kΩ potentiometer.
Therefore, the higher the open-loop gain of the second operational
amplifier, the larger the effective loading on the capacitor. The larger
the load, the lower the “leakage” current and the better the droop
characteristics.
Sampling Dynamic Signals
In actuality, the amplifiers are designed with special leakage current
cancellation circuits along with FET input devices. The leakage
current cancellation circuits give better high temperature operation.
(Remember that the FET amplifiers double in required bias current
for every 10 degree increase in junction temperature.)
Sampling errors due to moving (changing) input signals are of
significant concern to designers employing sample-and-hold circuits.
There exist finite phase delays through the sample-and-hold circuit
causing an input-output phase of differential for moving signals. In
addition, the series protection resistor (300Ω to Pin 6 of the NE5537)
will add an RC time constant, over and above the slew rate limitation
of the input buffer/current drive amplifier. This means that at the
moment the “HOLD” command arrives, the hold capacitor voltage
may be somewhat different from the actual analog input. The effect
of these delays is opposite to the effect created by delays in the
logic which switches the circuit from sample to hold. For example,
consider an analog input of 20 VP-P at 10kHz. Maximum dV/dt is
0.6V/µs. With no analog phase delay and 100ns logic delay, one
could expect up to (0.1µs) (0.6V/µs) =60mV error if the “HOLD”
signal arrived near maximum dV/dt of the input. A positive-going
input would give a ±60mV error. Now assume a 1MHz (3dB)
bandwidth for the overall analog loop. This generates a phase delay
of 160ns. If the hold capacitor sees this exact delay, then error due
to analog delay will be (0.16µs) (0.6V/µs)=-96mV (analog) for a total
of -36mV. To add to the confusion, analog delay is proportional to
hold capacitor value, while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help estimate
errors.
Sampling time for the NE5537 is less than 10µs (measured to 0.1%
of input signal). Leakage current is 6pA at a rate output load of 2kΩ.
BASIC APPLICATIONS
Multiplying DAC
As depicted in the block diagram of Figure 2, the sample-and-hold
circuit is used to supply a “variable” reference to the digital-to-analog
converter. As the input reference varies, the output will change in
accordance with Equation 1, shown in Figure 2.
Varying the input signal reference level can aid the system in
performing both compression and expansion operations. The
multiplying DACs used are the Philips Semiconductors NE/SE5008;
however, if the rate of change of the reference variation is kept slow
enough, a microprocessor-compatible DAC can be incorporated,
such as the NE5018 or the NE5020.
August 31, 1994
890
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
5k
5k
VIN
NE5537
5008/DAC-08
530
VOUT
+VREFIN
D0-D7
NOTE:
1
V
V IN x
(20 D 0 2 1D 1 2 7D 7) Equation 1
OUT
256
Figure 2. Multiplying DAC Application
SD5000
NE5537
ANALOG INPUT 1
D0
A/D
CONVERTER
CONTROL 1
ANALOG INPUT 2
D7
CONTROL 2
SUCCESSIVE APPROXIMATION
(NE5034, NE5037)
or INTEGRATING TYPE ADC
ANALOG INPUT 3
CONTROL 3
ANALOG INPUT 4
CONTROL 4
SUBSTRATE
Figure 3. Analog Data Multiplexing
A curve labeled “Aperture Time” has been included for sampling
SPECIAL NOTES
conditions where the input is steady during the sampling period, but
1. Not all definitions herein defined are measured parametrically for
may experience a sudden change nearly coincident with the “HOLD”
the NE5537, but are legitimate terms used in sample-and-hold
command. This curve is based on a 1mV error fed into the output.
systems.
A second curve, “Hold Settling Time,” indicates the time required for
the output to settle to 1mV after the “HOLD” command.
2. Reference should be made to Design Engineering, Volumes 23
(Nov. 8, 1978), 25 (Dec. 6, 1978) and 26 (Dec. 20, 1978) for
articles written by Eugene Zuch of Datel Systems, Inc., for a
further discussion of sample-and-hold circuits.
Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier is put
into the hold mode. To minimize this problem, board layout should
keep logic lines as far as possible from the analog input. Grounded
guarding traces may also be used around the input line, especially if
it is driven from a high impedance source. Reducing high amplitude
logic signals to 2.5V will also help.
3. Reference also made to National Semiconductor Corporation’s
Special Functions Data Book (1976).
Logic signals also couple to the hold capacitor. This hold capacitor
should be guarded by a PC card trace connected to the
sample-and-hold output. This will also minimize board leakage.
August 31, 1994
891