Qimonda HYB25D128800CC-6 128-mbit double-data-rate sdram Datasheet

February 2007
HYB25D128160C[E/F/T]
HYB25D128400C[C/E/T]
HYB25D128800C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
DDR SDRAM
Internet Data Sheet
Rev. 1.6
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
HYB25D128160C[E/F/T], HYB25D128400C[C/E/T]
Revision History: 2007-02, Rev. 1.6
Page
Subjects (major changes since last revision)
All
Adapted internet edition
5
Added HYB25D128800CE-7 and HYB25D128800CT-5
Previous Revision : 2006-09, Rev. 1.51
All
Qimonda update
Previous Revision : 2006-02, Rev. 1.5
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-U5AN-6TI1
2
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter contains features and the description.
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
VDD = 2.5 V ± 0.2 V (DDR266A, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
P(G)-TFBGA-60 package with 3 depopulated rows (8 × 12 mm2)
P(G)-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
Speed Grade
max. Clock Frequency
–5
–6
–7
Unit
Component
DDR400B
DDR333
DDR266A
—
Module
PC3200-3033
PC2700–2533
PC2100-2033
—
200
166
—
MHz
166
166
143
MHz
133
133
133
MHz
@CL3
@CL2.5
@CL2
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
fCK3
fCK2.5
fCK2
3
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of
DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 128-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-bank
DRAM.
The 128-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
128-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for
Writes.
The 128-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
4
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Informationfor non RoHS Compliant Products
Part Number1)
Org.
CAS-RCDClock
RP Latencies (MHz)
CAS-RCD-RP Clock
Latencies
(MHz)
Speed
Package
HYB25D128160CT–5
×16
3-3-3
2.5-3-3
DDR400B
P-TSOPII-66-2 —
HYB25D128800CT–5
×8
HYB25D128800CT–6
×8
HYB25D128160CT–6
×16
HYB25D128400CT–7
×4
200
166
Note2)
—
2.5-3-3
166
2-3-3
133
DDR333
—
—
143
DDR266A
—
P-FBGA-60-12 —
HYB25D128800CC–5
×8
3-3-3
200
2.5-3-3
166
DDR400B
HYB25D128400CC–6
×4
2.5-3-3
166
2-3-3
133
DDR333
HYB25D128800CC–6
×8
—
—
TABLE 3
Order Information for RoHS Compliant Products
Part Number1)
Org.
CAS-RCD-RP
Latencies
Clock CAS-RCD-RP
(MHz) Latencies
Clock
(MHz)
Speed
HYB25D128160CE–5
×16
3-3-3
200
166
DDR400B PG-TSOPII-66-1 —
HYB25D128800CE–5
×8
2.5-3-3
Package
Note2)
—
HYB25D128800CF–5
PG-FBGA-60-19 —
HYB25D128160CE–6
×16
HYB25D128400CE–6
×4
—
HYB25D128800CE–6
×8
—
2.5-3-3
166
2-3-3
HYB25D128800CF–6
133
DDR333
PG-TSOPII-66-1 —
PG-FBGA-60-19 —
HYB25D128400CE–7
×4
HYB25D128800CE–7
×8
143
DDR266A PG-TSOPII-66-1 —
—
1) HYB: designator for memory components 25D: DDR SDRAMs at VDDQ = 2.5 V 128: 128-Mbit density 400/800/160: Product variations ×4,
×8 and ×16 C: Die revision C T/E/C: Package type TSOP and FBGA L: Low power version (available on request) - these components are
specifically selected for low IDD6 Self Refresh currents -5/6/7/7F/8: speed grade - see Table 2
2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
5
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2.
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
G2, 45
CK
I
SSTL
Clock Signal
G3, 46
CK
I
SSTL
Complementary Clock Signal
H3, 44
CKE
I
SSTL
Clock Enable
H7, 23
RAS
I
SSTL
Row Address Strobe
G8, 22
CAS
I
SSTL
Column Address Strobe
G7, 21
WE
I
SSTL
Write Enable
H8, 24
CS
I
SSTL
Chip Select
Bank Address Bus 2:0
Clock Signals
Control Signals
Address Signals
J8, 26
BA0
I
SSTL
J7, 27
BA1
I
SSTL
K7, 29
A0
I
SSTL
L8, 30
A1
I
SSTL
L7, 31
A2
I
SSTL
M8, 32
A3
I
SSTL
M2, 35
A4
I
SSTL
L3, 36
A5
I
SSTL
L2, 37
A6
I
SSTL
K3, 38
A7
I
SSTL
K2, 39
A8
I
SSTL
J3, 40
A9
I
SSTL
K8, 28
A10
I
SSTL
AP
I
SSTL
J2, 41
A11
I
SSTL
H2, 42
A12
I
SSTL
Address Signal 12
Note: 256 Mbit or larger dies
NC
NC
—
Note: 128 Mbit or smaller dies
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based dies
NC
NC
—
Note: 512 Mbit or smaller dies
F9, 17
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Address Bus 11:0
6
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signal 3:0
Data Signals ×4 organization
B7, 5
DQ0
I/O
SSTL
D7, 11
DQ1
I/O
SSTL
D3, 56
DQ2
I/O
SSTL
B3, 62
DQ3
I/O
SSTL
Data Strobe ×4 organisation
E3, 51
DQS
I/O
SSTL
Data Strobe
I
SSTL
Data Mask
Data Signal 7:0
Data Mask ×4 organization
F3, 47
DM
Data Signals ×8 organization
A8, 2
DQ0
I/O
SSTL
B7, 5
DQ1
I/O
SSTL
C7, 8
DQ2
I/O
SSTL
D7, 11
DQ3
I/O
SSTL
D3, 56
DQ4
I/O
SSTL
C3, 59
DQ5
I/O
SSTL
B3, 62
DQ6
I/O
SSTL
A2, 65
DQ7
I/O
SSTL
Data Signal
Data Strobe ×8 organisation
E3, 51
DQS
I/O
SSTL
Data Strobe
I
SSTL
Data Mask
Data Signal 15:0
Data Mask ×8 organization
F3, 47
DM
Data Signals ×16 organization
A8, 2
DQ0
I/O
SSTL
B9, 4
DQ1
I/O
SSTL
B7, 5
DQ2
I/O
SSTL
C9, 7
DQ3
I/O
SSTL
C7, 8
DQ4
I/O
SSTL
D9, 10
DQ5
I/O
SSTL
D7, 11
DQ6
I/O
SSTL
E9, 13
DQ7
I/O
SSTL
E1, 54
DQ8
I/O
SSTL
D3, 56
DQ9
I/O
SSTL
D1, 57
DQ10
I/O
SSTL
C3, 59
DQ11
I/O
SSTL
C1, 60
DQ12
I/O
SSTL
B3, 62
DQ13
I/O
SSTL
B1, 63
DQ14
I/O
SSTL
A2, 65
DQ15
I/O
SSTL
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
7
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Strobe ×16 organization
E3, 51
UDQS
I/O
SSTL
Data Strobe Upper Byte
E7, 16
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×16 organization
F3, 47
UDM
I
SSTL
Data Mask Upper Byte
F7, 20
LDM
I
SSTL
Data Mask Lower Byte
VREF
A9, B2, C8, D2, VDDQ
AI
—
I/O Reference Voltage
PWR
—
I/O Driver Power Supply
A7, F8, M3, M7, VDD
1, 18, 33
PWR
—
Power Supply
A1, B8, C2, D8, VSSQ
E2, 6, 12, 52,
58, 64
PWR
—
Power Supply
VSS
PWR
—
Power Supply
A2, 65
NC
NC
—
Not Connected
Note: ×4 organization
A8, 2
NC
NC
—
Not Connected
Note: ×4 organization
B1, 63
NC
NC
—
Not Connected
Note: ×8 and ×4 organisation
B9, 4
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C1, 60
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C3, 59
NC
NC
—
Not Connected
Note: ×4 organization
C7, 8
NC
NC
—
Not Connected
Note: ×4 organization
C9, 7
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D1, 57
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D9, 10
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E1, 54
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
Power Supplies
F1, 49
E8, 3, 9, 15, 55,
61
F2, 34
Not Connected
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
8
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
E7, 16
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E9, 13
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
F7, 20
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
F9, 14, 17, 19,
25,43, 50, 53
NC
NC
—
Not Connected
Note: ×16,×8 and ×4 organization
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
9
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
FIGURE 1
Pin Configuration P-TFBGA-60 Top View
6331
.#
633
.#
6$$1
.#
!
6$$
.#
6$$1
6331
$1
633
$1
"
$1
6331
.#
.#
6$$1
6331
.#
#
.#
6$$1
.#
.#
.#
6$$1
$1
$
$1
6331
.#
.#
6331
$13
%
.#
6$$1
62%&
633
$-
&
.#
6$$
#+
#+
'
7%
.#!
#+%
(
!
!
!
!
6$$
$1
6$$1
$1
"
$1
6331
.#
6331
$1
#
$1
6$$1
.#
.#
6$$1
$1
$
$1
6331
.#
.#
.#
6331
$13
%
.#
6$$1
.#
.#!
62%&
633
$-
&
.#
6$$
.#!
#!3
#+
#+
'
7%
#!3
2!3
#3
.#!
#+%
(
2!3
#3
*
"!
"!
!
!
*
"!
"!
!
+
!
!!0
!
!
+
!
!!0
!
!
,
!
!
!
!
,
!
!
!
633
-
6$$
!
!
633
-
6$$
!
X
X
6331
$1
633
!
6$$
$1
6$$1
$1
6$$1
$1
"
$1
6331
$1
$1
6331
$1
#
$1
6$$1
$1
$1
6$$1
$1
$
$1
6331
$1
$1
6331
5$13
%
,$13
6$$1
$1
62%&
633
5$-
&
,$-
6$$
.#!
#+
#+
'
7%
#!3
(
2!3
#3
.#! #+%
!
!
*
"!
"!
!
!
+
!
!!0
!
!
,
!
!
!
633
-
6$$
!
X
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
10
-00$
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
FIGURE 2
Pin Configuration P-TSOPII-66-1
X
X
X 6$$
6$$
6$$
633
633
633
.#
$1
$1
$1
$1
.#
6$$1
6$$1
6$$1
6331
6331
6331
.#
.#
$1
$1
.#
.#
$1
$1
$1
$1
$1
$1
6331
6331
6331
6$$1
6$$1
6$$1
.#
.#
$1
$1
.#
.#
.#
$1
$1
$1
$1
.#
6$$1
6$$1
6$$1
6331
6331
6331
.#
.#
$1
$1
.#
.#
$1
$1
$1
$1
$1
$1
6331
6331
6331
6$$1
6$$1
6$$1
.#
.#
$1
$1
.#
.#
.#
.#
.#
.#
.#
.#
6$$1
6$$1
6$$1
6331
6331
6331
.#
.#
,$13
5$13
$13
$13
.#
.#
.#
6$$
62%&
62%&
62%&
.# ! .# ! .# !
6$$
6$$
.#
.#
.#
633
633
633
.#
.#
,$-
5$-
$-
$-
7%
7%
7%
#+
#+
#+
#!3
#!3
#!3
#+
#+
#+
2!3
2!3
2!3
#+%
#+%
#+%
#3
#3
#3
.#
.#
"!
.#
.#
.#
.# ! .# ! .# !
"!
.#
"!
!
!
!
"!
"!
"!
!
!
!
!!0
!!0
!!0
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
6$$
6$$
6$$
633
633
633
-00$
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
11
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
3
Functional Description
%$
%$
$
$
$
$
$
$
$
$
&/
02'(
$
$
%7
$
$
$
%/
03%/
TABLE 7
MR Mode Register Definition (BA[1:0] = 00B)
Field
Bits
Type1)
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B 2
010B 4
011B 8
BT
3
w
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
Sequential
1B
Interleaved
CL
[6:4]
w
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B 2
011B 3
101B 1.5
Note: DDR200 components only
110B 2.5
MODE [11:7] w
Operating Mode
Note: All other bit combinations are RESERVED.
00000B
00010B
Normal Operation without DLL Reset
Normal Operation with DLL Reset
1) w=write
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
12
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 8
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
13
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
EMR
Extended Mode Register Definition
BA1
BA0
0
1
A11
A10
A9
(BA[1:0] = 01B)
A8
A7
A6
A5
A4
MODE
reg. addr
w
A3
A2
A1
A0
DS
DLL
w
w
TABLE 9
Extended Mode Register Definition (BA[1:0] = 01B)
Field
Bits
Type1)
Description
DLL
0
w
DLL Status
Enabled
0B
1B
Disabled
DS
1
w
Drive Strength
0B
Normal
1B
Weak
MODE
[11:2]
w
Operating Mode
Note: All other bit combinations are RESERVED.
0000000000B Normal Operation
1) w=write
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
14
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 10
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Note
Deselect (NOP)
H
X
X
X
X
NOP
1)2)
No Operation (NOP)
L
H
H
H
X
NOP
1)2)
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1)4)
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1)4)
Burst Terminate
L
H
H
L
X
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1)7)8)
Mode Register Set
L
L
L
L
Op-Code
MRS
1)9)
1)
2)
3)
4)
5)
6)
7)
8)
9)
CKE is HIGH for all commands shown except Self Refresh.VREF must be maintained during Self Refresh operation.
Deselect and NOP are functionally interchangeable.
BA0-BA1 provide bank address and A0-A11 provide row address.
BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the
Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to the selected Mode
Register).
TABLE 11
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
15
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 12
Truth Table 2: Clock Enable (CKE)
Current State
CKE n-1
CKEn
Command n
Action n
Note
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
1)
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
2)
Power Down
L
L
X
Maintain Power-Down
—
Power Down
L
H
Deselect or NOP
Exit Power-Down
—
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
—
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
—
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
—
—
H
H
See Table 13
—
—
1) VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
16
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 13
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State
CS
RAS
CAS
WE
Command
Action
Note
Any
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
to 6)
L
L
H
H
Active
Select and activate row
to 6)
L
L
L
H
AUTO REFRESH
—
to 7)
L
L
L
L
MODE REGISTER
SET
—
to 7)
L
H
L
H
Read
Select column and start Read burst
to 6), 8)
L
H
L
L
Write
Select column and start Write burst
to 6), 8)
L
L
H
L
Precharge
Deactivate row in bank(s)
to 6), 9)
Read (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
to 6), 8)
L
L
H
L
Precharge
Truncate Read burst, start Precharge
to 6), 9)
L
H
H
L
BURST
TERMINATE
BURST TERMINATE
to 6), 10)
Write (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
to 6), 8), 11)
L
H
L
L
Write
Select column and start Write burst
to 6), 8)
Idle
Row Active
to 6), 9), 11)
Truncate Write burst, start Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12 and after tXSNR/tXSRD has been met (if the previous state
L
L
H
L
Precharge
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge
command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active
command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with
registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
according to Table 14.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with
registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
17
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 14
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE
Command
Action
Note
Any
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
Idle
X
X
X
X
Any Command
Otherwise Allowed to
Bank m
—
1) to 6)
Row Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7)
L
H
L
L
Write
Select column and start Write burst
1) to 7)
L
L
H
L
Precharge
—
1) to 6)
Read (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7)
L
L
H
L
Precharge
—
1) to 6)
Write (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 8)
L
H
L
L
Write
Select column and start new Write burst
1) to 7)
L
L
H
L
Precharge
—
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7), 9)
L
H
L
L
Write
Select column and start Write burst
1) to 7), 10)
L
L
H
L
Precharge
—
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7)
L
H
L
L
Write
Select column and start new Write burst
1) to 7)
L
L
H
L
Precharge
—
1) to 6)
Read (With Auto
Precharge)
Write (With Auto
Precharge)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if
the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, w. Auto
Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, w. Auto Precharge disabled,
and has not yet terminated or been terminated. Read w. Auto Precharge Enabled: See 10). Write w. Auto Precharge Enabled: See 10).
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 15.
10) A Write command may be applied after the completion of data output.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
18
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 15
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
WRITE w/AP
Read or Read w/AP
1 + (BL/2) + tWTR
Write to Write w/AP
BL/2
Read w/AP
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Minimum Delay with Concurrent Auto Unit
Precharge Support
Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
CL (rounded up) + BL/2
Precharge or Activate
1
19
tCK
tCK
tCK
tCK
tCK
tCK
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
4
Electrical Characteristics
This chapter lists the electrical characteristics.
4.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 16
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Note/ Test
Condition
Min.
Typ.
Max.
—
VDDQ +
V
—
Voltage on I/O pins relative to VSS
VIN, VOUT
–0.5
Voltage on inputs relative to VSS
–1
—
+3.6
V
—
–1
—
+3.6
V
—
Storage temperature (plastic)
VIN
VDD
VDDQ
TA
TSTG
Power dissipation (per SDRAM component)
Short circuit output current
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
0.5
–1
—
+3.6
V
—
0
—
+70
°C
—
-55
—
+150
°C
—
PD
—
1.5
—
W
—
IOUT
—
50
—
mA
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated
circuit.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
20
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Input Capacitance: CK, CK
Delta Input Capacitance
Input Capacitance: All other input-only pins
Symbol
CI1
CdI1
CI2
Values
Unit
Note/
Test Condition
Min.
Typ.
Max.
1.5
—
2.5
pF
P(G)-TFBGA-60 1)
2.0
—
3.0
pF
P(G)-TSOPII-66
—
—
0.25
pF
—
1.5
—
2.5
pF
P(G)-TFBGA-60
2.0
—
3.0
pF
P(G)-TSOPII-66
Delta Input Capacitance: All other input-only
pins
CdIO
—
—
0.5
pF
—
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
—
4.5
pF
P(G)-TFBGA-60 2)
4.0
—
5.0
pF
P(G)-TSOPII-66
Delta Input/Output Capacitance: DQ, DQS,
DM
CdIO
—
—
0.5
pF
—
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only. VDDQ = VDD =
2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
21
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 18
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Unit Note1) / Test Condition
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz
0
—
0
V
—
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDQ / 2
– 50 mV
VDDQ / 2
VDDQ / 2
V
fCK ≤ 166 MHz 4)
fCK > 166 MHz
VREF – 0.04
—
VREF + 0.04
V
5)
VIH(DC)
Input Low (Logic0) Voltage
VIL(DC)
Input Voltage Level, CK and VIN(DC)
VREF + 0.15
—
V
—
–0.3
—
V
—
–0.3
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
—
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
—
VDDQ + 0.6
V
6)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
—
1.4
—
7)
Input Leakage Current
II
–2
—
2
µA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
VDD
VDD
VDDQ
VDDQ
VSS,
VSSQ
VREF
VREF
VTT
Input High (Logic1) Voltage
CK Inputs
+ 50 mV
8)9)
IOZ
–5
—
5
µA
Output High Current, Normal IOH
Strength Driver
—
—
–16.2
mA
VDDQ
VOUT = 1.95 V
16.2
—
—
mA
VOUT = 0.35 V
Output Leakage Current
Output Low Current, Normal
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2)
3)
4)
5)
6)
7)
8)
9)
IOL
DQs are disabled; 0 V ≤ VOUT ≤
DDR400 conditions apply for all clock frequencies above 166 MHz
Under all conditions, VDDQ must be less than or equal to VDD.
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Inputs are not recognized as valid until VREF stabilizes.
Values are shown per component
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
22
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
4.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 3 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification
for DDR components.
FIGURE 3
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Ω
Output
(VOUT)
Timing Reference Point
30 pF
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
23
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 19
AC Operating Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
1)
2)
3)
4)
5)
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Values
Min.
Max.
VREF + 0.31
—
VREF – 0.31
0.7
VDDQ + 0.6
0.5 × VDDQ – 0.5 × VDDQ+
—
0.2
Unit
Note1)/ Test
Condition
V
2)3)
V
—
V
4)
V
5)
0.2
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ TA ≤ 70 °C
Input slew rate = 1 V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 20
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
IDD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VILMAX; tCK = tCKMIN
IDD2P
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
IDD2F
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current:CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control IDD2Q
inputs stable at ≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once IDD4R
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; tCK = tCKMIN; IOUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once IDD4W
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; tCK = tCKMIN
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
24
IDD5
IDD6
IDD7
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 21
IDD Specification
–5
–6
–7
DDR400B
DDR333
DDR266A
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
70
90
60
75
50
65
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
1)
Unit
Note / Test Condition
mA
×4/×8 2)3)
75
90
65
75
55
65
mA
×16
80
100
70
85
65
75
mA
×4/×8
95
110
80
95
70
85
mA
×16
4
5
3.5
4.5
3
4
mA
—
30
36
25
30
20
24
mA
—
20
28
17
24
15
21
mA
—
13
18
11
15
9
13
mA
—
38
45
32
38
28
36
mA
×4/×8
43
54
36
45
30
40
mA
×16
85
100
70
85
60
70
mA
×4/×8
100
120
85
100
70
85
mA
×16
90
105
75
90
65
75
mA
×4/×8
100
130
90
110
75
90
mA
×16
140
190
120
160
100
140
mA
—
1.4
2.8
1.4
2.8
1.4
2.8
mA
Standard version 4)
—
—
1.1
1.1
1.1
1.1
mA
Low power version 5)
210
250
180
215
140
170
mA
×4/×8
210
250
180
215
140
170
mA
×16
1) Test conditions for typical values: VDD = 2.5 V ( DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum
values: VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
5) L: Low power version (available on request)
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
25
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 22
AC Timing - Absolute Specifications
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
DQ and DM input hold time
DQ and DM input pulse width (each
input)
Symbol
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
—
5
8
6
12
ns
CL = 3.0
6
12
6
12
ns
CL = 2.5
7.5
12
7.5
12
ns
CL = 2.0
tCL
tDAL
0.45
0.55
0.45
0.55
tCK
tCK
tDH
tDIPW
0.4
—
0.45
—
ns
—
1.75
—
1.75
—
ns
—
tAC
tCH
tCK
(tWR/tCK)+(tRP/tCK)
(tWR/tCK)+(tRP/tCK)
—
6)
DQS output access time from CK/CK tDQSCK
–0.5
+0.5
–0.6
+0.6
ns
—
tDQSL,H
0.35
—
0.35
—
tCK
—
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
—
+0.40
—
+0.40
ns
TFBGA
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
—
+0.40
—
+0.45
ns
TSOPII
Write command to 1st DQS latching
transition
tDQSS
0.72
1.25
0.75
1.25
tCK
—
DQ and DM input setup time
tDS
tDSH
0.4
—
0.45
—
ns
—
0.2
—
0.2
—
tCK
—
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
—
Clock Half Period
tHP
tHZ
min. (tCL, tCH)
—
min. (tCL, tCH)
—
ns
—
—
+0.7
–0.7
+0.7
ns
7)
tIH
0.6
—
0.75
—
ns
DQS input low (high) pulse width
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Data-out high-impedance time from
CK/CK
Address and control input hold time
Control and Addr. input pulse width
(each input)
tIPW
Address and control input setup time tIS
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
fast slew rate
8)
0.7
—
0.8
—
ns
slow slew rate
2.2
—
2.2
—
ns
9)
0.6
—
0.75
—
ns
fast slew rate
0.7
—
0.8
—
ns
slow slew rate
26
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
Data-out low-impedance time from
CK/CK
tLZ
–0.7
+0.7
–0.7
+0.7
ns
—
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
—
DQ/DQS output hold time
tQH
tQHS
tHP –tQHS
—
tHP –tQHS
—
ns
—
—
+0.50
—
+0.50
ns
TFBGA
—
+0.50
—
+0.55
ns
TSOPII
Data hold skew factor
tRAP
tRAS
tRC
tRCD
—
tRCD
—
ns
—
40
70E+3
42
70E+3
ns
—
55
—
60
—
ns
—
tRCD
tREFI
tRFC
15
—
18
—
ns
—
—
15.6
—
15.6
µs
10)
65
—
72
—
ns
—
tRP
tRPRE
tRPST
tRRD
15
—
18
—
ns
—
0.9
1.1
0.9
1.1
—
0.40
0.60
0.40
0.60
tCK
tCK
10
—
12
—
ns
—
Write preamble
0.25
—
0.25
—
tCK
—
Write preamble setup time
0
—
0
—
ns
11)
0.40
0.60
0.40
0.60
tCK
12)
15
—
15
—
ns
—
2
—
1
—
tCK
—
75
—
75
—
ns
—
200
—
200
—
tCK
—
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh
command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
tWPRE
tWPRES
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit self-refresh to non-read
tXSNR
—
command
Exit self-refresh to read command
tXSRD
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
27
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
TABLE 23
AC Timing - Absolute Specifications
Parameter
Symbol
–7
Unit
Note1)/ Test
Condition
DDR266A
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery + precharge time
DQ and DM input hold time
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (DQS and associated DQ signals)
DQS-DQ skew (DQS and associated DQ signals)
st
Write command to 1 DQS latching transition
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock Half Period
Data-out high-impedance time from CK/CK
Address and control input hold time
Control and Addr. input pulse width (each input)
Address and control input setup time
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
tAC
tCH
tCK
tCL
tDAL
tDH
tDIPW
tDQSCK
tDQSL,H
tDQSQ
tDQSQ
tDQSS
tDS
tDSH
tDSS
tHP
tHZ
tIH
tIPW
tIS
tLZ
tMRD
tQH
28
Min.
Max.
–0.75
+0.75
ns
2)3)4)5)
0.45
0.55
tCK
—
7.5
12
ns
CL = 3.0
7.5
12
ns
CL = 2.5
7.5
12
ns
CL = 2.0
0.45
0.55
—
(tWR/tCK)+(tRP/tCK)
tCK
tCK
0.5
—
ns
—
1.75
—
ns
—
–0.75
+0.75
ns
—
0.35
—
tCK
—
—
+0.5
ns
TFBGA
—
+0.5
ns
TSOPII
0.75
1.25
tCK
—
0.5
—
ns
—
0.2
—
—
0.2
—
tCK
tCK
min. (tCL, tCH)
—
ns
—
—
+0.75
ns
7)
0.9
—
ns
6)
—
fast slew rate
8)
1.0
1.1
ns
slow slew rate
2.2
—
ns
9)
0.9
—
ns
fast slew rate
1.0
—
ns
slow slew rate
–0.75
+0.75
ns
—
2
—
tCK
—
tHP –tQHS
—
ns
—
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
–7
Unit
Note1)/ Test
Condition
DDR266A
Min.
Max.
—
+0.75
ns
TFBGA
Data hold skew factor
tQHS
—
+0.75
ns
TSOPII
Active to Autoprecharge delay
tRAP
tRAS
tRC
tRCD
tREFI
tRCD or tRASmin
—
ns
—
45
120E+3
ns
—
65
—
ns
—
20
—
ns
—
—
15.6
µs
10)
tRFC
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
tXSNR
tXSRD
75
—
ns
—
20
—
ns
—
0.9
1.0
0.60
tCK
tCK
—
0.40
15
—
ns
—
0.25
—
tCK
—
0
—
ns
11)
0.40
0.60
tCK
12)
15
—
ns
—
1
—
tCK
—
75
—
ns
—
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
—
Exit self-refresh to read command
200
—
tCK
—
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
29
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
5
Package Outlines
There are two package types used for this product family each in lead-free and lead-containing assembly:
• P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package
TABLE 24
TFBGA Common Package Properties (non-green/green)
Description
Size
Units
Ball Size
0.460
mm
Recommended Landing Pad
0.350
mm
Recommended Solder Mask
0.450
mm
FIGURE 4
Package Outline of P(G)-TFBGA-60 (non-green/green)
[ 0$
;
%
$
[ 0
$;
&
0
$;
0
,1
&
¡ “ [
¡ 0 $ %
&
¡ 0
& 6($7 ,1
*3
/$1(
$0
DU NLQ J%DOOVLGH
$0
DU NLQ J&K LSVLGH D GVZ
LWKRXW%DOO
'X PP
\ 3
%DG8
Q LW0
DUNLQJ %80
0LGGOHR I3
D FN D JHV(
GJHV
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
*3$
30
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
• P-TSOPII: Plastic Thin Small Outline Package Type II
FIGURE 5
›
X ›
-!8
)NDEX -ARKING
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
-!8
›
›
›
›
P(G)-TSOPII-66 (Plastic Thin Small Outline Package Type II)
'08
31
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Pin Configuration P-TFBGA-60 Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline of P(G)-TFBGA-60 (non-green/green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P(G)-TSOPII-66 (Plastic Thin Small Outline Package Type II). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
32
10
11
23
30
31
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Informationfor non RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Order Information for RoHS Compliant Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MR Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Extended Mode Register Definition (BA[1:0] = 01B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 18
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
33
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
34
Internet Data Sheet
Edition 2007-02
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com