INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4043B MSI Quadruple R/S latch with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4043B MSI Quadruple R/S latch with 3-state outputs DESCRIPTION The HEF4043B is a quadruple R/S latch with 3-state outputs with a common output enable input (EO). Each latch has an active HIGH set input (S0 to S3), an active HIGH reset input (R0 to R3) and an active HIGH 3-state output (O0 to O3). When EO is HIGH, the state of the latch output (On) can be determined from the function table below. When EO is LOW, the latch outputs are in the high impedance OFF-state. EO does not affect the state of the latch. Fig.2 Pinning diagram. The high impedance off-state feature allows common busing of the outputs. HEF4043BP(N): 16-lead DIL; plastic (SOT38-1) HEF4043BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4043BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING EO common output enable input S0 to S3 set inputs (active HIGH) R0 to R3 reset inputs (active HIGH) O0 to O3 3-state buffered latch outputs FUNCTION TABLE INPUTS OUTPUT On EO Sn Rn L X X Z H L H L H H X H H L L latched Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state immaterial Z = high impedance state Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4043B MSI Fig.4 Logic diagram (one latch). Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification HEF4043B MSI Quadruple R/S latch with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays Rn → On HIGH to LOW 5 10 tPHL 15 Sn → On LOW to HIGH 5 10 tPLH 15 Output transition times 5 10 HIGH to LOW 15 LOW to HIGH 10 tTHL 5 90 180 ns 63 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 65 135 ns 38 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 15 35 ns 7 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL EO → On 5 45 90 ns HIGH 10 20 35 ns tTLH 3-state propagation delays Output disable times LOW tPHZ 15 10 25 ns 5 50 100 ns 20 40 ns 15 10 25 ns 5 25 50 ns 10 tPLZ Output enable times EO → On HIGH LOW 10 tPZH 15 30 ns 15 10 25 ns 5 40 80 ns 20 45 ns 15 35 ns 10 tPZL 15 Minimum Sn pulse width; HIGH Minimum Rn pulse width; HIGH 5 10 15 ns 20 10 ns 15 16 8 ns 5 30 15 ns 20 10 ns 16 8 ns 10 15 January 1995 tWSH 30 tWRH 4 see also waveforms Fig.5 Philips Semiconductors Product specification HEF4043B MSI Quadruple R/S latch with 3-state outputs VDD V TYPICAL FORMULA FOR P (µW) 5 1100 fi + ∑(foCL) × VDD2 dissipation per 10 4400 package (P) 15 11 400 fi + ∑(foCL) × VDD2 fi + ∑(foCL) × VDD2 Dynamic power where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑(foCL) = sum of outputs VDD = supply voltage (V) Fig.5 Waveforms showing minimum Sn and Rn pulse widths. APPLICATION INFORMATION An example of application for the HEF4043B is: • Four-bit storage with output enable January 1995 5