Etron EM658160TS-7 4m x 16 ddr synchronous dram (sdram) Datasheet

EtronTech
EM658160
4M x 16 DDR Synchronous DRAM (SDRAM)
Etron Confidential
(Rev. 1.1 Jan./2002)
Features
Pin Assignment (Top View)
•
•
•
•
•
•
•
•
Fast clock rate: 300/285/250/200/166/143/125MHz
Differential Clock CK & /CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 1M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- /CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
• Individual byte write mask control
• DM Write Latency = 0
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 64ms
• Precharge & active power down
• Power supplies: VDD = 3.3V ± 0.3V
VDDQ = 2.5V ± 0.2V
• Interface: SSTL_2 I/O Interface
• Package: 66 Pin TSOP II, 0.65mm pin pitch
Ordering Information
Part Number
Frequency
Package
EM658160TS-3.3
300MHz
EM658160TS-3.5
285MHz
TSOP II
TSOP II
EM658160TS-4
250MHz
TSOP II
EM658160TS-5
200MHz
TSOP II
EM658160TS-6
166MHz
TSOP II
EM658160TS-7
143MHz
TSOP II
EM658160TS-8
125MHz
TSOP II
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
1
2
3
4
5
6
7
8
9
10
11
12
56
55
54
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
51
50
49
UDQS
NC
VREF
19
20
48
47
46
VSS
UDM
NC
LDM
/WE
A2
A3
VDD
59
58
57
DQ14
DQ13
VDDQ
16
17
18
LDQS
NC
VDD
A10/AP
A0
A1
62
61
60
VSS
DQ15
VSSQ
DQ8
NC
VSSQ
13
14
15
NC
BS0
BS1
65
64
63
53
52
NC
VDDQ
/CAS
/RAS
/CS
66
21
22
23
24
25
26
27
28
29
30
31
32
33
45
44
43
42
41
40
39
38
37
36
35
34
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Overview
The EM658160 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 64
Mbits. It is internally configured as a quad 1M x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and /CK.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The EM658160
provides programmable Read or Write burst lengths of 2,
4, 8, full page.
An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. The refresh functions, either
Auto or Self Refresh are easy to use. In addition,
EM658160 features programmable DLL option. By
having a programmable mode register and extended
mode register, the system can choose the most suitable
modes to maximize its performance. These devices are
well suited for applications requiring high memory
bandwidth, result in a device particularly well suited to
high performance main memory and graphics
applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
4Mx16 DDR SDRAM
EM658160
Block Diagram
Row Decoder
Column Decoder
1MX16
CELL ARRAY
(BANK #0)
Sense Amplifier
DLL
CLOCK
BUFFER
CK
/CK
CONTROL
SIGNAL
GENERATOR
CKE
/CS
/RAS
/CAS
/WE
COMMAND
DECODER
MODE
REGISTER
Row Decoder
Sense Amplifier
1MX16
CELL ARRAY
(BANK #1)
Column Decoder
COLUMN
COUNTER
A10/AP
Row Decoder
Column Decoder
ADDRESS
BUFFER
A0
A11
BS0
BS1
1MX16
CELL ARRAY
(BANK #2)
Sense Amplifier
REFRESH
COUNTER
Sense Amplifier
Row Decoder
DATA
STROBE
BUFFER
LDQS,
UDQS
DQ
BUFFER
h
DQ0
DQ15
1MX16
CELL ARRAY
(BANK #3)
Column Decoder
LDM, UDM
Etron Confidential
2
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Pin Descriptions
Table 1. Pin Details of EM658160
Symbol
Type
Description
CK, /CK
Input
Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and /CK increment the internal burst
counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
BS0, BS1
Input
Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7with A10 defining
Auto Precharge).
/CS
Input
Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when /CS is sampled HIGH. /CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
/RAS
Input
Row Address Strobe: The /RAS signal defines the operation commands in
conjunction with the /CAS and /WE signals and is latched at the positive edges of CK.
When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the /WE signal.
When the /WE is asserted "HIGH," the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the /WE is asserted
"LOW," the Precharge command is selected and the bank designated by BS is
switched to the idle state after the precharge operation.
/CAS
Input
Column Address Strobe: The /CAS signal defines the operation commands in
conjunction with the /RAS and /WE signals and is latched at the positive edges of CK.
When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is started
by asserting /CAS "LOW." Then, the Read or Write command is selected by asserting
/WE "HIGH " or LOW"."
/WE
Input
Write Enable: The /WE signal defines the operation commands in conjunction with
the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
Input /
UDQS
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and /CK. The I/Os are byte-maskable during Writes.
UDM
DQ0 - DQ15
Etron Confidential
3
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
VDD
Supply
Power Supply: +3.3V ±0.3V
VSS
Supply
Ground
VDDQ
Supply
DQ Power: +2.5V ±0.2V. Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VREF
Supply
Reference Voltage for Inputs: +0.5*VDDQ
NC
-
Etron Confidential
No Connect: These pins should be left unconnected.
4
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKEn-1 CKEn
DM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE
Idle(3)
H
X
X
V
BankPrecharge
Any
H
X
X
V
L
PrechargeAll
Any
H
X
X
X
BankActivate
Row address
L
L
H
H
X
L
L
H
L
H
X
L
L
H
L
Column
address
(A0 ~ A7)
L
H
L
L
L
H
L
L
Column
address
(A0 ~ A7)
L
H
L
H
L
H
L
H
Write
Active(3)
H
X
X
V
L
Write and AutoPrecharge
Active(3)
H
X
X
V
H
Read
Active(3)
H
X
X
V
L
Read and Autoprecharge
Active(3)
H
X
X
V
H
Mode Register Set
Idle
H
X
X
OP code
L
L
L
L
Extended MRS
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
Burst Stop
(SelfRefresh)
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Power Down Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
X
X
(PowerDown)
Data Write/Output Enable
Active
H
X
L
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Etron Confidential
5
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
•
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 2, 4, 8.
•
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode.
Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8.
A3
Addressing Mode
0
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table.
Data n
0
1
2
3
4
5
6
7
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
2 words
Burst Length
4 words
8 words
Full Page (Even starting address)
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in the following table.
Data n
Column Address
Burst Length
Data 0
A7
A6
A5
A4
A3
A2
A1
A0
Data 1
A7
A6
A5
A4
A3
A2
A1
A0#
Data 2
A7
A6
A5
A4
A3
A2
A1# A0
Data 3
A7
A6
A5
A4
A3
A2
A1# A0#
Data 4
A7
A6
A5
A4
A3
A2# A1
A0
Data 5
A7
A6
A5
A4
A3
A2# A1
A0#
Data 6
A7
A6
A5
A4
A3
A2# A1# A0
Data 7
A7
A6
A5
A4
A3
A2# A1# A0#
Etron Confidential
6
4 words
8 words
Rev. 1.1
Jan. 2002
EtronTech
•
•
•
EM658160
4Mx16 DDR SDRAM
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the
first read data. The minimum whole value of CAS Latency depends on the frequency of CK.
The minimum whole value satisfying the following formula must be programmed into this field.
tCAC(min) ≤ CAS Latency X tCK
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
1
0
2 clocks
0
1
1
3 clocks
1
0
1
Reserved
1
1
0
2.5 clocks
1
1
1
Reserved (3.5 clocks)
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
A7
Test Mode
0
0
Normal mode
1
0
DLL Reset
X
1
Test mode
( BS0, BS1)
BS1
BS0
An ~ A0
RFU
0
MRS Cycle
RFU
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
BS1
BS0
A11~ A1
A0
RFU
1
RFU
0
DLL Enable
RFU
1
RFU
1
DLL Disable
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Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Absolute Maximum Rating
Symbol
Item
Rating
Unit
Note
VIN, VOUT
Input, Output Voltage
- 0.3~ VDD + 0.3
V
1
VDD, VDDQ
Power Supply Voltage
- 0.3~3.6
V
1
TOPR
Operating Temperature
0~70
°C
1
TSTG
Storage Temperature
- 55~150
°C
1
TSOLDER
Soldering Temperature (10s)
260
°C
1
PD
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (Ta = 0 ~ 70 °C)
Symbol
Min.
Max.
Unit
Power Supply Voltage
Parameter
VDD
3.0
3.6
V
Power Supply Voltage (for I/O Buffer)
VDDQ
2.3
2.7
V
Input Reference Voltage
VREF
1.15
1.35
V
Termination Voltage
VTT
VREF - 0.04
VREF + 0.04
V
Input High Voltage (DC)
VIH (DC)
VREF + 0.18
VDDQ + 0.3
V
Input Low Voltage (DC)
VIL (DC)
-0.3
VREF – 0.18
V
Input Voltage Level, CLK and CLK#
inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Different Voltage, CLK and CLK#
inputs
VID (DC)
-0.36
VDDQ + 0.6
V
II
-5
5
µA
Output leakage current
IOZ
-5
5
µA
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2 mA
Output Low Voltage
VOL
VTT – 0.76
V
IOL = +15.2 mA
Input leakage current
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Rev. 1.1
Note
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25 °C)
Symbol
CIN
CI/O
Parameter
Min.
Max.
Unit
Input Capacitance (except for CK pin)
2.5
5
pF
Input Capacitance (CK pin)
2.5
4
pF
DQ, DQS, DM Capacitance
4
6.5
pF
Note: These parameters are periodically sampled and are not 100% tested.
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3, Ta = 0~70 °C)
Max.
Parameter
Operation Current
(one bank active)
Operation Current
(one bank active)
Precharge Powerdown Standby Current
Idel Standby Current
Symbol
IDD0
250/240/230/220/190/180/160
IDD1
Burst = 2, tRC = min, CL = 3
IOUT = 0mA, Active-Read-Precharge
320/300/260/250/220/210/200
IDD2P
IDD2N
IDD3P
Active Standby
Current
IDD3N
Operation Current
(Read)
IDD4R
Operation Current
(Write)
IDD4W
Self Refresh Current
Etron Confidential
UNIT
tRC = min, tCK = min
Active-precharge
Active Power-down
Standby Current
Auto Refresh Current
- 3.3/3.5/4/5/6/7/8
IDD5
IDD6
CKE ≤ VIL(max), tCK = min,
All banks idle
CKE ≥ VIH(min), CS# ≥ VIH(min),
tCK = min
All banks ACT, CKE ≤ VIL(max),
tCK = min
One bank; Active-Precharge,
tRC = tRAS(max), tCK = min
Burst = 2, CL = 3, tCK = min,
IOUT = 0mA
Burst = 2, CL = 3, tCK = min
tRC(min)
80/80/80/65/65/60/55
170/160/150/130/110/100/90
80/80/80/65/65/60/55
180/170/160/155/145/140/135
mA
330/310/270/250/220/200/180
330/310/270/250/220/200/180
190/180/170/155/145/140/135
CKE ≤ 0.2v
2
9
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3 ± 0.3 V, Ta = 0~70 °C)
- 3.3/3.5/4/5/6/7/8
Symbol
Parameter
Min.
Max.
Unit
tRC
Row cycle time
44/44/44/55/60/70/80
ns
tRFC
Refresh row cycle time
56/56/56/70/84/91/96
ns
tRAS
Row active time
32/32/32/40/42/49/56
tRCD
/RAS to /CAS Delay
12/12/12/15/18/21/24
ns
tRP
Row precharge time
12/12/12/15/18/21/24
ns
tRRD
Row active to Row active delay
6.6/7/8/10/12/14/16
ns
twR
Write recovery time
2
tCK
tCDLR
Last data in to Read command
2.5tCK-tDQSS
tCK
tCCD
Col. Address to Col. Address delay
1
tCK
tCK
Clock cycle time
120000
CL*=3
3.3/3.5/4/5/6/7/8
15
CL*=2.5
5/5/5.5/6/7.5/8/9
15
CL*=2
6/6/7/8/9/10/11
15
ns
ns
tCH
Clock high level width
0.45
0.55
tCK
tCL
Clock low level width
0.45
0.55
tDQSCK DQS-out access time from CK,/CK
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8
0.6/0.6/0.6/0.7/0.7/0.75/0.8
tCK
ns
tAC
Output access time from CK,/CK
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8
0.6/0.6/0.6/0.7/0.7/0.75/0.8
ns
tDQSQ
DQS-DQ Skew
-0.5/-0.5/-0.5/-0.5/-0.5/-0.5/-0.6
0.5/0.5/0.5/0.5/0.5/0.5/0.6
ns
tRPRE
Read preamble
0.9
1.1
tCK
tRPST
Read postamble
0.4
0.6
tCK
tDQSS
CK to valid DQS-in
0.75
1.25
tCK
tWPRES DQS-in setup time
0.4/0.4/0.4/0.4/0.45/0.5/0.55
ns
tWPREH DQS-in hold time
0.4/0.4/0.4/0.4/0.45/0.5/0.55
ns
tWPST
DQS write postamble
0.4
0.6
tCK
tDQSH
DQS in high level pulse width
0.4
0.6
tCK
tDQSL
DQS in low level pulse width
0.4
0.6
tIS
Address and Control input setup time
1.1
tCK
ns
tIH
Address and Control input hold time
1.1
ns
tMRD
Mode register set cycle time
1
tDS
DQ & DM setup time to DQS
0.4/0.4/0.4/0.4/0.45/0.5/0.55
tCK
ns
tDH
DQ & DM hold time to DQS
0.4/0.4/0.4/0.4/0.45/0.5/0.55
ns
tQH
Output DQS valid window
0.3
tPDEX
Power down exit time
tCK
ns
tXSA
Self refresh exit to active
command delay
Self refresh exit to read
command delay
tXSR
Etron Confidential
tIS+1tCK
tIS+2tCK
12/12/11/11/10/10/10
tCK
200
tCK
10
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. Power-up sequence is described in Note 6.
5. A.C. Test Conditions
SSTL_2 Interface
Reference Level of Output Signals (VRFE)
0.5 * VDDQ
Output Load
Reference to the Under Output Load (A)
Input Signal Levels
VREF+0.35 V / VREF-0.35 V
Input Signals Slew Rate
1 V/ns
Reference Level of Input Signals
0.5 * VDDQ
0.5*VDDQ
25 Ω
25 Ω
Output
30pF
SSTL_2 A.C. Test Load
6.
Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and
maintain CKE “LOW”. Power applied to VDDQ the same time as VTT and VREF.
2) After power-up, No-Operation of 200 µ−seconds minimum is required.
3) Start clock and keep CKE “HIGH” to maintain either No-Operation or Device Deselect at the input.
4) Issue EMRS – enable DLL.
5) Issue MRS – reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are
needed for DLL lock)
6) Precharge all banks of the device.
7) Two or more Auto Refresh commands.
8) Issue MRS – Initialize device operation.
Etron Confidential
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Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Timing Waveforms
Figure 1. AC Parameters for Read Timing (Burst Length=4, CAS Latency=2.5)
tCH
tCL
tCK
CK
/CK
t IS
CMD
tIH
Read
t IS
tIH
ADDR
/CS
tDQSQ
tRPST
tRPRE
DQS
Preamble
Postamble
tAC
DQ
Etron Confidential
D0
12
D1
D2
D3
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 2. AC Parameters for Write Timing (Burst Length=4)
CK
/CK
CMD
Write
ADDR
/CS
DQ
D0
D1
D2
D3
tDH
tWPRES
tDS
tDQSS
tDSH
tDSL
tWPST
DQS
Preamble
Etron Confidential
Postamble
13
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Figure 3. Read Command to Output Data Latency (Burst Length=2)
CK
/CK
CMD
Read
CL=2
DQ
DA0
DA1
Postamble
DQS
Preamble
CL=2.5
DQ
DA0
DA1
Postamble
DQS
Preamble
CL=3
DQ
DA0
DA1
Postamble
DQS
Preamble
Etron Confidential
14
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 4. Read Followed by Write (Burst Lenth=4, CAS Latency=3)
CK
/CK
tRRD
tRCDR
Activate
Read
CMD
Write
ACT
ADDR
Row/Bank0
Col/Bank0 Rol/Bank1
Col/Bank0
/CS
DQ
DQS
D0
D1
D2
D3
Preamble
Postamble
Etron Confidential
15
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 5. Write followed by Read (Burst Lenth=4, CAS Latency=3)
CK
/CK
tWTR
CMD
Write
Read
ADDR
Col
Col
/CS
DQ
D0 D1 D2
D0 D1
D3
D2 D3
DQS
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Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Figure 6. Precharge Termination of a Burst Read (Burst Length=4, CAS Latency=3)
CK
/CK
Precharge
CMD
ADDR
ACT
Read
Col
Bank
Bank
/CS
tRP
DQ
DQS
D0
D1
Preamble
Postamble
Etron Confidential
17
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Figure 7. Precharge Termination of a Burst Write (Burst Length=4)
CK
/CK
tRC
Activate
Write
Precharge
Activate
CMD
ADDR
Row/Bank
Col/Bank
Row/Bank
Row/Bank
/CS
tRCD
tWR
DQM
tRP
tDS
tQDH
tRAS
DQ
D0
D1
masked by DQM
DQS
Etron Confidential
Preamble
Postamble
18
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 8. Auto Precharge after Read Burst (CAS Latency=3)
CK
/CK
tRP
BL=2
CMD
Auto Precharge
ReadA
ACT
D0 D1
DQ
tRP
Auto Precharge
BL=4
CMD
ACT
ReadA
DQ
D0 D1 D2
D3
tRP
Auto Precharge
BL=8
CMD
ACT
ReadA
DQ
Etron Confidential
D0
D1 D2
D3 D4 D5 D6
D7
19
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 9. Auto Precharge after Write Burst
CK
/CK
BL=2
WriteA
Auto Precharge
ACT
CMD
tWR
D0
DQ
tRP
D1
Preamble
DQS
BL=4
Postamble
WriteA
Auto Precharge
ACT
CMD
tWR
D0 D1 D2
DQ
tRP
D3
Preamble
DQS
BL=8
Postamble
Auto Precharge
WriteA
ACT
CMD
tWR
DQ
D0 D1 D2 D3
D4 D5
tRP
D6 D7
Preamble
DQS
Postamble
Etron Confidential
20
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 10. Read Terminated By Burst Stop (Burst Length=8)
CK
/CK
CMD
Read
BST
Col
ADDR
/CS
CL=3
DQ
D0
D1
D2
D3
DQS
Etron Confidential
21
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Figure 11. Read Terminated by Read (Burst Length=4, CAS Latency=3)
CK
/CK
tCCD
CMD
Read
Read
ADDR
Col A
Col B
/CS
DA0
DQ
DA1
DB0
DB1
DB2
DB3
DQS
Etron Confidential
22
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 12. Mode Register Set Command
CK
/CK
tRP
1 clk
MRS
CMD
ACT
Precharge
Row
ADDR
MRS Data
/CS
Etron Confidential
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Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
Figure 13. Active / Precharge Power Down Mode
CK
/CK
tPDEX
t IS
CKE
Any
Command
CMD
Activate /
Precharge
Note 1,2
Note:
1. All banks should be in idle state prior to entering precharge power down mode.
2. One of the banks should be in active state prior to entering active power down mode.
Etron Confidential
24
Rev. 1.1
Jan. 2002
EtronTech
4Mx16 DDR SDRAM
EM658160
Figure 14. Self Refresh Entry and Exit Cycle
CK
/CK
Self Refresh Enter
CMD
Auto
Refresh
NOP
tRC
CKE
t IS
Self Refresh Exit
tRC is required before any command can be applied,
and 200 cycles of clk are required before a READ
command can be applied.
Etron Confidential
25
Rev. 1.1
Jan. 2002
EtronTech
EM658160
4Mx16 DDR SDRAM
66 Pin TSOP II Package Outline Drawing Information
Units: mm
22.22 0.13
66
0.125
+ 0.085
- 0.005
0.5 0.1
10.16 0.13
11.76 0.20
0.8 TYP
34
1.00 0.10
1.20 MAX
33
1
0~8
0.10 MAX
Etron Confidential
0.65 TYP
0.30 0.08
0.05 MIN
0.71 TYP
26
0.25 TYP
Rev. 1.1
Jan. 2002