A4938 3-Phase Brushless DC Motor Pre-Driver Features and Benefits Description ▪ Drives 6 N-channel MOSFETs ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Hall element inputs ▪ PWM current limiting ▪ Dead time protection ▪ FG outputs ▪ Standby mode ▪ Lock detect protection ▪ Overvoltage protection The A4938 is a complete 3-phase brushless DC (BLDC) motor pre-driver, supplying direct, high-current gate drive of an all N-channel power MOSFET 3-phase bridge. The device has three Hall-element inputs, a sequencer for commutation control, fixed off-time pulse width modulation (PWM) current control, and locked-rotor detection. Output current is scaled by the capability of the external MOSFETs. Locked rotor detection delay is set by an external capacitor on the CLD terminal. The ENABLE, DIR, and BRAKEZ inputs can be used to control motor speed, position, and torque. Motor speed can be determined using the FG1 output. Package: 28-contact QFN (ET package) The external MOSFETS can be PWMed using an external signal on the PWM input, or using the internal PWM current regulator. In either case, the A4938 synchronous rectification feature reduces power dissipation by turning on the appropriate MOSFETs during current decay. The Hall elements can be inexpensive types, when used with noise filtering to prevent false commutation signals. The A4938 provides a regulated 5.0 V supply to power the three Hall elements. Internal circuit protection includes thermal Approximate Scale 1:1 Continued on the next page… Typical Application 0.1 μF 0.1 μF 0.1 μF 2 kΩ CLD HBIAS CP1 CP2 VCP VBB VIN GHA SA GLA M OVP VIN System Control Logic A4938 FG BRAKEZ ENABLE DIR GHB SB GLB GHC SC GLC SENSE GND HA+ HA– HB+ HB– HC+ HC– A4938-DS 0.1 μF A4938 3-Phase Brushless DC Motor Pre-Driver Description (continued) shutdown with hysteresis, undervoltage lockout, and dead time protection. Special power-up sequencing is not required. Operating temperature range is –40°C to 85°C. The A4938 is supplied in a 5 mm × 5 mm, 28-terminal QFN package with exposed thermal pad. This small footprint package is lead (Pb) free with 100% matte tin leadframe plating. Selection Guide Part Number A4938EETTR-T Packing Package 1500 pieces per reel 5 mm x 5 mm, 0.90 mm nominal height QFN Absolute Maximum Ratings Characteristics Load Supply Voltage Symbol Notes VBB Motor Phase Output SX tw < 500 ns Hall Input VHx DC Logic Input Voltage Range VIN Unit 38 V –3 V –0.3 to 7 V –0.3 to 7 V Operating Ambient Temperature TA –40 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –40 to 150 ºC Storage Temperature Range E Rating Thermal Characteristics Characteristics Symbol Package Thermal Resistance, Junction RθJA to Ambient Package Thermal Resistance, Junction RθJP to Exposed Pad *For additional information, refer to the Allegro website. Test Conditions* 4-layer PCB based on JEDEC standard Rating Unit 32 ºC/W 2 ºC/W Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4938 3-Phase Brushless DC Motor Pre-Driver Functional Block Diagram 0.1 μF CLD Lock Detect CP1 CP2 0.1 μF FG1 VCP Charge Pump 0.1 μF HBIAS 2 kΩ 0.1 μF VBB VREG HA+ VIN HALL OVP HA- HB+ HALL VCP Communication Logic VREG GHA SA HB- GHB SB GLB Gate Drive HC+ HALL HCVREG GHC SC GLC Control Logic FG1 GLA BRAKEZ System Logic VREG DIR RSENSE SENSE 200 mV ENABLE OVP VIN GND Terminal List Number Name 1 HA+ 2 HA - 3 4 5 6 Description Number Name Description Hall input A 15 GLB Low side gate drive B Hall input A 16 GLA Low side gate drive A HB+ Hall input B 17 GHC High side gate drive C HB - Hall input B 18 SC HC+ Hall input C 19 GHB HC- Hall input C 20 SB 7 GND Ground 21 GHA 8 HBIAS Hall bias power supply output 22 SA 9 CP1 Charge pump capacitor terminal 23 FG1 10 CP2 Charge pump capacitor terminal 24 OVP Logic input – OVP selection 11 VBB Supply voltage 25 CLD Locked rotor detect timing capacitor 12 VCP Reservoir capacitor terminal 26 DIR 13 SENSE Sense resistor connection 27 ENABLE Logic input – external PWM control 14 GLC Low side gate drive C 28 BRAKEZ Logic input – motor brake (active low) High side source connection C High side gate drive B High side source connection B High side gate drive A High side source connection A FG 1 output Logic input – motor direction Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4938 3-Phase Brushless DC Motor Pre-Driver ELECTRICAL CHARACTERISTICS* Valid at TA= 25°C, VBB = 24 V, unless noted otherwise Characteristics Symbol Supply Voltage Range VBB Motor Supply Current IBB Test Conditions Operating Min. Typ. Max. Unit 8.5 – 30 V fPWM < 30 kHz, CLOAD = 1000 pF – 5 6 mA Charge pump on, outputs disabled, Standby mode – 2.4 3.2 mA HBIAS VHBIAS 4.7 5.0 5.3 V HBIAS Current Limit IHBIASlim 0 mA ≤ IHBIAS ≤ 24 mA 35 – – mA VIN(1) 2 – – V VIN(0) – – 0.8 V OVP pin pull-up to HBIAS – 100 – kΩ ENABLE, BRAKEZ, DIR pins pull-up to HBIAS – 50 – kΩ Control Logic Logic Input Voltage Logic Input Pull-Up RIN(PU) Input Pin Glitch Reject tGLITCH ENABLE Standby Pulse Propagation Delay tdENABLE ENABLE pin 350 500 650 ns DIR, BRAKEZ pins 700 1000 1300 ns To outputs off 2.1 3 3.9 ms tdHBIAS CHBIAS = 0.1 μF – 15 25 μs High-Side Gate Drive Output VGS(H) Relative to VBB, IGATE = 2 mA 7 – – V Low-Side Gate Drive Output VGS(L) IGATE = 2 mA 4.5 – – V GH = GL = 4 V 20 30 – mA HBIAS Wake-up Delay, Standby Mode Gate Drive Gate Drive Current (Sourcing) IGate Gate Drive Pull Down Resistance RGate 10 28 40 Ω Dead Time tdead 700 1000 1300 ns Current Limit Input Threshold VREF 180 200 220 mV Fixed Off-Time tOFF 18 25 37 μs TJTSD 155 170 185 °C Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis TJTSDhys VBB UVLO Enable Threshold VBBUV VBB UVLO Hysteresis VCP UVLO Lock Detect Duration – 20 – °C 6.20 7 7.85 V 0.4 0.75 1 V Relative to VBB 4.6 – 6 V C = 0.1 μF 1.5 2 2.5 s OVP = GND, VBB rising 15.5 16 16.5 V OVP = open, VBB rising 28.5 29 29.5 V – 2 – V Rising VBB VBBUVhys VCPUV tlock VBB Overvoltage Threshold VBBOV VBB Overvoltage Hysteresis VOVOhys Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4938 3-Phase Brushless DC Motor Pre-Driver ELECTRICAL CHARACTERISTICS* (continued) Valid at TA= 25°C, VBB = 24 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit Hall Logic Hall Input Current IHALL Common Mode Input Range VCMR AC Input Voltage Range VHALL Hall Thresholds Vth Hall Threshold Hysteresis VHYS Pulse Reject Filter tpulse VIN = 0.2 to 3.5 V –1 0 1 μA 0.2 – 2.0 V 60 – – mVp-p Difference between Hall inputs at transitions – +10,–10 – mV TJ = 25°C 10 20 30 mV TJ = –40°C to 125°C 5 20 40 mV – 2 – μs FG FG Output Saturation Voltage FG Leakage Current VFG(sat) IFG = 2 mA – – 0.5 V IFGlkg VFG = 5 V – – 1 μA *Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. Specifications throughout the allowed operating temperature range are guaranteed by design and characterization. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4938 3-Phase Brushless DC Motor Pre-Driver Logic States Table (See timing charts, below) X = Don’t Care (can be 1 or 0), Z = high impedance Inputs Condition HA HB HC DIR BRAKEZ ENABLE + – + 1 1 0 A Forward Reverse Chop Resulting Pre-Driver Outputs GHA GLA GHB GLB GHC GLC HI LO LO HI LO A B C LO HI LO Z B + – – 1 1 0 HI LO LO LO LO HI HI Z LO C + + – 1 1 0 LO LO HI LO LO HI Z HI LO D – + – 1 1 0 LO HI HI LO LO LO LO HI Z E – + + 1 1 0 LO HI LO LO HI LO LO Z HI F – – + 1 1 0 LO LO LO HI HI LO Z LO HI A + – + 0 1 0 LO HI HI LO LO LO LO HI Z F + – – 0 1 0 LO HI LO LO HI LO LO Z HI E + + – 0 1 0 LO LO LO HI HI LO Z LO HI D – + – 0 1 0 HI LO LO HI LO LO HI LO Z C – + + 0 1 0 HI LO LO LO LO HI HI Z LO B – – + 0 1 0 LO LO HI LO LO HI Z HI LO A + – + X 1 If 1 for <3 ms LO HI LO HI LO LO LO LO Z F + – – X 1 If 1 for <3 ms LO HI LO LO LO HI LO Z LO E + + – X 1 If 1 for <3 ms LO LO LO HI LO HI Z LO LO D – + – X 1 If 1 for <3 ms LO HI LO HI LO LO LO LO Z C – + + X 1 If 1 for <3 ms LO HI LO LO LO HI LO Z LO B Fault – – + X 1 If 1 for <3 ms LO LO LO HI LO HI Z LO LO – – – X X X LO LO LO LO LO LO Z Z Z + + + X X X LO LO LO LO LO LO Z Z Z LO HI LO HI LO HI LO LO LO LO LO LO LO LO LO Z Z Z Brake X X X X 0 If 0, or if 1 for < 3 ms Standby X X X X X If 1 for >3 ms DIR = 1 = Forward A Motor Output B C D DIR = 0 = Reverse E A F HA HA HB HB HC HC FG1 FG1 SA SA SB SB SC SC F E D C B Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4938 3-Phase Brushless DC Motor Pre-Driver Power-up and Standby Modes Timing Diagram VBB VBBUV Charge Pump HBIAS Voltage tdENABLE 3 ms Standby Mode Turn off Hall Bias Supply ENABLE Outputs Enabled Outputs Disabled Outputs Enabled Power-up and Standby Modes Timing Diagram VBB VBBUV VBB+7.5 V VCPUV Charge Pump 7.5 V VHBIAS HBIAS Voltage ENABLE PWM Outputs Enabled Outputs Disabled Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4938 3-Phase Brushless DC Motor Pre-Driver Functional Description Current Regulation Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the full bridge are turned on, current increases in the motor winding until it reaches a value, ITRIP , given by: ITRIP = 200 mV / RSENSE provide the blanking function. The blanking timer is reset when ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or an ENABLE on triggers the blanking function. The duration is fixed at 1.5 μs. Synchronous Rectification When a PWM-off cycle is . When ITRIP is reached, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off-time period. Enable Logic The ENABLE pin allows external PWM. ENABLE low turns on the selected sink-source pair. ENABLE high switches off the appropriate drivers and the load current decays. If ENABLE is held low, the current will rise until it reaches the level set by the internal current control circuit. Typically PWM frequency is in the 20 to 30 kHz range. If the ENABLE high pulse width exceeds 3 ms, the gate outputs are disabled. The Enable logic is summarized in the following table: ENABLE Pin Outputs Outputs State 0 On Drive 1 Source chopped Slow decay with synchronous rectification 1 for > 3 ms typical Off Disable Fixed Off-Time The A4938 fixed off-time is set to 25 μs nominal. PWM Blank Timer When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source Enable latch, the sense comparator is blanked. The blanking timer runs after the off-time counter, to triggered, either by an ENABLE chop command or by an internal fixed off-time cycle, load current recirculates. The A4938 synchronous rectification feature turns on the appropriate MOSFETs during the current decay, and effectively shorts out the body diodes with the low RDS(on) driver. This lowers power dissipation significantly and can eliminate the need for external Schottky diodes. Brake Mode A logic low on the BRAKEZ pin activates Brake mode. A logic high allows normal operation. Braking turns on all three sink drivers, effectively shorting out the motor-generated BEMF. The BRAKEZ input overrides the ENABLE input and also the Lock Detect function. It is important to note that the internal PWM current control circuit does not limit the current when braking, because the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF / RLOAD. Care should be taken to insure that the maximum ratings of the A4938 are not exceeded in the worse case braking situation: high speed and high inertial load. HBIAS Function This function provides a power supply of 5.0 V, current-limited to 35 mA. This reference voltage is used to power the logic sections of the A4938 and also to power the external Hall elements. Standby Mode To prevent excessive power dissipation due to the current draw of the external Hall elements, Standby mode turns off the HBIAS output voltage. Standby mode is triggered by Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4938 3-Phase Brushless DC Motor Pre-Driver holding ENABLE high for longer than 3 ms. Note that the state Lock Detect Function The IC will evaluate a locked rotor of BRAKEZ does not affect Standby mode. condition under either of these two different conditions: Charge Pump The internal charge pump is used to generate a • The FG1 signal is not consistently changing. supply above VBB to drive the high-side MOSFETs. The voltage • The proper commutation sequence is not being followed. The motor can be locked in a condition in which it toggles between two specific Hall device states. on the VCP pin is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Fault Shutdown In the event of a fault due to excessive junction temperature, or due to low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition is removed. At power-up the UVLO circuit disables the drivers. Overvoltage Protection VBB is monitored to determine if a hazardous voltage is present due to the motor generator pumping-up the supply bus. When the voltage exceeds VBBOV , the synchronous rectification feature is disabled. Connecting OVP to Both of these fault conditions are allowed to persist for a period of time, tlock. The value of tlock is set by capacitor connected to the CLD pin. CLD produces a triangle waveform (1.67 V peak-topeak) with a frequency linearly related to the capacitor value. tlock is defined as 127 cycles of this triangle waveform, or: tlock = CLD × 20 s/μF After the wait time, tlock , has expired, the outputs are disabled, and the fault is latched. GND sets VBBOV to 16 V typically, and leaving OVP open sets These fault conditions are latched and can only be cleared by any one of the following actions: VBBOV to 29 V typically. • Rising or falling edge on the DIR pin Overtemperature Protection If die temperature exceeds • VBB UVLO threshold exceeded (during power-up cycle) approximately 170°C, the Thermal Shutdown function will dis- • ENABLE pin held high for > tlock / 2 able the outputs until the internal temperature falls below the threshold hysteresis. Hall State Reporting The FG1 pin is an open drain output that changes state at each transition of an external Hall element. The Lock Detect function can be disabled by connecting CLD to GND. When the A4938 is in Brake mode, the Lock Detect counter is disabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4938 3-Phase Brushless DC Motor Pre-Driver ET Package, 28-Contact QFN 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown +0.20 0.55 –0.10 A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10