TI AMC1100DUB Fully-differential isolation amplifier for energy metering Datasheet

AMC1100
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Fully-Differential Isolation Amplifier for Energy Metering
Check for Samples: AMC1100
FEATURES
DESCRIPTION
•
The AMC1100 is a precision isolation amplifier with
an output separated from the input circuitry by a
silicon dioxide (SiO2) barrier that is highly resistant to
magnetic interference. This barrier has been certified
to provide galvanic isolation of up to 4250 VPEAK,
according to UL1577 and IEC60747-5-2. Used in
conjunction with isolated power supplies, this device
prevents noise currents on a high common-mode
voltage line from entering the local ground and
interfering with or damaging sensitive circuitry.
1
2
•
•
•
•
•
•
•
•
•
•
•
±250-mV Input Voltage Range Optimized for
Shunt Resistors
Very Low Nonlinearity: 0.075% max at 5 V
Low Offset Error: 1.5 mV max
Low Noise: 3.1 mVRMS typ
Low High-Side Supply Current:
8 mA max at 5 V
Input Bandwidth: 60 kHz min
Fixed Gain: 8 (0.5% Accuracy)
High Common-Mode Rejection Ratio: 108 dB
Low-Side Operation: 3.3 V
Certified Galvanic Isolation:
– UL1577 and IEC60747-5-2 Approved
– Isolation Voltage: 4250 VPEAK
– Working Voltage: 1200 VPEAK
– Transient Immunity: 2.5 kV/µs min
Typical 10-Year Lifespan at Rated Working
Voltage (see Application Report SLLA197)
Fully Specified Over the Extended Industrial
Temperature Range
The AMC1100 input is optimized for direct connection
to shunt resistors or other low voltage level signal
sources. The excellent performance of the device
enables accurate current and voltage measurement
in energy-metering applications. The output signal
common-mode voltage is automatically adjusted to
either the 3-V or 5-V low-side supply.
The AMC1100 is fully specified over the extended
industrial temperature range of –40°C to +105°C and
is available in the SMD-type, gullwing-8 package.
APPLICATIONS
•
Shunt Resistor Based Current Sensing in:
– Energy Meters
– Green Energy
– Power Measurement Applications
VDD1
VDD2
5V
2.55 V
0V
VINP
VOUTP
VINN
VOUTN
2V
250 mV
3.3 V
1.29 V
GND1
2V
GND2
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
AMC1100
SBAS562 – APRIL 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or visit the device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over the operating ambient temperature range, unless otherwise noted.
Supply voltage, VDD1 to GND1 or VDD2 to GND2
Analog input voltage at VINP, VINN
VALUE
UNIT
–0.5 to 6
V
GND1 – 0.5 to VDD1 + 0.5
V
Input current to any pin except supply pins
±10
mA
Maximum junction temperature, TJ Max
Electrostatic discharge (ESD)
ratings,
all pins
(1)
+150
°C
Human body model (HBM)
JEDEC standard 22, test method A114-C.01
±2500
V
Charged device model (CDM)
JEDEC standard 22, test method C101
±1000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
AMC1100
THERMAL METRIC (1)
DUB (SOP)
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
75.1
θJCtop
Junction-to-case (top) thermal resistance
61.6
θJB
Junction-to-board thermal resistance
39.8
ψJT
Junction-to-top characterization parameter
27.2
ψJB
Junction-to-board characterization parameter
39.4
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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REGULATORY INFORMATION
VDE AND IEC
UL
Certified according to IEC 60747-5-2
Recognized under 1577 component recognition program
File number: 40016131
File number: E181974
IEC 60747-5-2 INSULATION CHARACTERISTICS
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
VIORM
VPR
TEST CONDITIONS
VALUE
UNIT
1200
VPEAK
Qualification test: after input/output safety test subgroup
2/3 VPR = VIORM × 1.2, t = 10 s, partial discharge < 5 pC
1140
VPEAK
Qualification test: method A, after environmental tests
subgroup 1, VPR = VIORM × 1.6, t = 10 s, partial discharge
< 5 pC
1920
VPEAK
100% production test: method B1, VPR = VIORM × 1.875,
t = 1 s, partial discharge < 5 pC
2250
VPEAK
Qualification test: t = 60 s
4250
VPEAK
Qualification test: VTEST = VISO, t = 60 s
4250
VPEAK
100% production test: VTEST = 1.2 x VISO, t = 1 s
5100
VPEAK
VIO = 500 V at TS
> 109
Ω
2
°
Maximum working insulation voltage
Input-to-output test voltage
VIOTM
Transient overvoltage
VISO
Insulation voltage per UL
RS
Insulation resistance
PD
Pollution degree
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. I/O
circuitry failure can allow low resistance to either ground or supply and, without current limiting, dissipate sufficient power to
overheat the die and damage the isolation barrier, thus potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of
a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages and
is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then
the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER
IS
Safety input, output, or supply current
TC
Maximum-case temperature
TEST CONDITIONS
MIN
TYP
θJA = 246°C/W, VIN = 5.5 V, TJ = +150°C, TA = +25°C
MAX
UNIT
10
mA
+150
°C
IEC 61000-4-5 RATINGS
PARAMETER
VIOSM
Surge immunity
TEST CONDITIONS
1.2-μs or 50-μs voltage surge and 8-μs or 20-μs current surge
VALUE
UNIT
±6000
V
IEC 60664-1 RATINGS
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
Material group
SPECIFICATION
II
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 400 VRMS
I-III
Rated mains voltage < 600 VRMS
I-III
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PACKAGE CHARACTERISTICS (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance
through air
L(I02)
Minimum external tracking (creepage)
Shortest terminal-to-terminal distance
across package surface
7
CTI
Tracking resistance
(comparative tracking index)
DIN IEC 60112 and VDE 0303 part 1
> 400
V
Minimum internal gap
(internal clearance)
Distance through insulation
0.014
mm
RIO
Isolation resistance
7
mm
mm
Input to output, VIO = 500 V, all pins on
each side of the barrier tied together to
create a two-terminal device, TA < +85°C
> 1012
Ω
Input to output, VIO = 500 V,
+85°C ≤ TA < TA max
> 1011
Ω
CIO
Barrier capacitance input to output
VI = 0.5 VPP at 1 MHz
1.2
pF
CI
Input capacitance to ground
VI = 0.5 VPP at 1 MHz
3
pF
(1)
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific
application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting
pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal
according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves or ribs on the
PCB are used to help increase these specifications.
ELECTRICAL CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +105°C and are within the specified voltage range, unless
otherwise noted. Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Maximum input voltage before
clipping
VINP – VINN
Differential input voltage
VINP – VINN
±320
–250
mV
+250
-0.16
VCM
Common-mode operating range
VOS
Input offset voltage
–1.5
±0.2
+1.5
mV
TCVOS
Input offset thermal drift
–10
±1.5
+10
µV/K
CMRR
Common-mode rejection ratio
CIN
Input capacitance to GND1
CIND
Differential input capacitance
3.6
pF
RIN
Differential input resistance
28
kΩ
60
100
kHz
–0.5
±0.05
+0.5
%
–1
±0.05
+1
%
4.5 V ≤ VDD2 ≤ 5.5 V
–0.075
±0.015
+0.075
%
2.7 V ≤ VDD2 ≤ 3.6 V
–0.1
±0.023
+0.1
%
VIN from 0 V to 5 V at 0 Hz
VIN from 0 V to 5 V at 50 kHz
VINP or VINN
Small-signal bandwidth
VDD1
mV
V
108
dB
95
dB
3
pF
OUTPUT
Nominal gain
GERR
Gain error
TCGERR
Gain error thermal drift
Nonlinearity
8
Initial, at TA = +25°C
±56
Nonlinearity thermal drift
Output noise
PSRR
Power-supply rejection ratio
Rise-and-fall time
4
ppm/K
2.4
ppm/K
VINP = VINN = 0 V
3.1
mVRMS
vs VDD1, 10-kHz ripple
80
dB
vs VDD2, 10-kHz ripple
61
dB
0.5-V step, 10% to 90%
3.66
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6.6
µs
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ELECTRICAL CHARACTERISTICS (continued)
All minimum and maximum specifications are at TA = –40°C to +105°C and are within the specified voltage range, unless
otherwise noted. Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5-V step, 50% to 10%, unfiltered output
1.6
3.3
µs
0.5-V step, 50% to 50%, unfiltered output
3.15
5.6
µs
0.5-V step, 50% to 90%, unfiltered output
5.26
9.9
µs
OUTPUT (continued)
VIN to VOUT signal delay
CMTI
Common-mode transient
immunity
VCM = 1 kV
Output common-mode voltage
ROUT
2.5
3.75
kV/µs
2.7 V ≤ VDD2 ≤ 3.6 V
1.15
1.29
1.45
V
4.5 V ≤ VDD2 ≤ 5.5 V
2.4
2.55
2.7
V
Short-circuit current
20
mA
Output resistance
2.5
Ω
POWER SUPPLY
VDD1
High-side supply voltage
4.5
5.0
5.5
VDD2
Low-side supply voltage
2.7
5.0
5.5
IDD1
High-side supply current
5.4
8
mA
IDD2
Low-side supply current
3.8
6
mA
PDD1
High-side power dissipation
PDD2
Low-side power dissipation
2.7 V < VDD2 < 3.6 V
4.5 V < VDD2 < 5.5 V
V
V
4.4
7
mA
27.0
44.0
mW
2.7 V < VDD2 < 3.6 V
11.4
21.6
mW
4.5 V < VDD2 < 5.5 V
22.0
38.5
mW
PIN CONFIGURATION
DUB PACKAGE
SOP-8
(TOP VIEW)
VDD1
1
8
VDD2
VINP
2
7
VOUTP
VINN
3
6
VOUTN
GND1
4
5
GND2
PIN DESCRIPTIONS
PIN NAME
PIN NO
FUNCTION
GND1
4
Power
High-side analog ground
DESCRIPTION
GND2
5
Power
Low-side analog ground
VDD1
1
Power
High-side power supply
VDD2
8
Power
Low-side power supply
VINN
3
Analog input
Inverting analog input
Noninverting analog input
VINP
2
Analog input
VOUTN
6
Analog output
Inverting analog output
VOUTP
7
Analog output
Noninverting analog output
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TYPICAL CHARACTERISTICS
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
INPUT OFFSET
vs HIGH-SIDE SUPPLY VOLTAGE
INPUT OFFSET
vs LOW-SIDE SUPPLY VOLTAGE
2
2
1.5
1.5
1
1
Input Offset (mV)
Input Offset (mV)
VDD2 = 2.7 V to 3.6 V
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
4.75
5
VDD1 (V)
5.25
−2
2.7
5.5
3
3.3
3.6
VDD2 (V)
Figure 1.
Figure 2.
INPUT OFFSET
vs LOW-SIDE SUPPLY VOLTAGE
INPUT OFFSET
vs TEMPERATURE
2
2
1.5
1
1
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
CMRR (dB)
Input Offset (mV)
1.5
4.75
5
VDD2 (V)
5.25
−2
−40 −25 −10
5.5
COMMON-MODE REJECTION RATIO
vs INPUT FREQUENCY
INPUT CURRENT
vs INPUT VOLTAGE
40
120
30
110
20
100
90
80
110 125
−10
−20
60
−30
100
95
0
70
1
10
Input Frequency (kHz)
80
10
−40
−400
Figure 5.
6
20 35 50 65
Temperature (°C)
Figure 4.
130
50
0.1
5
Figure 3.
Input Current (µA)
Input Offset (mV)
VDD2 = 4.5 V to 5.5 V
−300
−200
−100
0
100
Input Voltage (mV)
200
300
400
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
INPUT BANDWIDTH
vs TEMPERATURE
GAIN ERROR
vs HIGH-SIDE SUPPLY VOLTAGE
120
1
0.8
0.6
0.4
100
Gain Error (%)
Input Bandwidth (kHz)
110
90
80
0.2
0
−0.2
−0.4
−0.6
70
−0.8
60
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
−1
4.5
110 125
5.25
Figure 8.
GAIN ERROR
vs LOW-SIDE SUPPLY VOLTAGE
GAIN ERROR
vs LOW-SIDE SUPPLY VOLTAGE
1
0.6
0.4
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1
2.7
3
3.3
VDD2 = 4.5 V to 5.5 V
0.8
0.6
−1
4.5
3.6
VDD2 (V)
4.75
5
VDD2 (V)
Figure 9.
Figure 10.
GAIN ERROR
vs TEMPERATURE
NORMALIZED GAIN
vs INPUT FREQUENCY
1
5.25
5.5
10
0
0.6
−10
Normalized Gain (dB)
0.8
0.4
0.2
0
−0.2
−0.4
−20
−30
−40
−50
−0.6
−60
−0.8
−70
−1
−40 −25 −10
5.5
1
VDD2 = 2.7 V to 3.6 V
Gain Error (%)
Gain Error (%)
5
VDD1 (V)
Figure 7.
0.8
Gain Error (%)
4.75
5
20 35 50 65
Temperature (°C)
80
95
110 125
−80
1
Figure 11.
10
100
Input Frequency (kHz)
500
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
OUTPUT PHASE
vs INPUT FREQUENCY
OUTPUT VOLTAGE
vs INPUT VOLTAGE
0
5
−30
4.5
−60
VOUTP
VOUTN
4
Output Voltage (V)
Output Phase (°)
−90
−120
−150
−180
−210
−240
3.5
3
2.5
2
1.5
−270
1
−300
0.5
−330
−360
1
10
100
Input Frequency (kHz)
0
−400
1000
−200
−100
0
100
Input Voltage (mV)
200
Figure 13.
Figure 14.
OUTPUT VOLTAGE
vs INPUT VOLTAGE
NONLINEARITY
vs HIGH-SIDE SUPPLY VOLTAGE
3.6
3.3
−300
300
400
0.1
VDD2 = 2.7 V to 3.6 V
VOUTP
VOUTN
3
0.08
0.06
2.4
Nonlinearity (%)
Output Voltage (V)
2.7
2.1
1.8
1.5
1.2
0.04
0.02
0
−0.02
−0.04
0.9
−0.06
0.6
−0.08
0.3
0
−400
−300
−200
−100
0
100
Input Voltage (mV)
200
300
−0.1
4.5
400
NONLINEARITY
vs LOW-SIDE SUPPLY VOLTAGE
NONLINEARITY
vs LOW-SIDE SUPPLY VOLTAGE
5.5
0.1
VDD2 = 2.7 V to 3.6 V
0.06
0.06
0.04
0.04
0.02
0
−0.02
−0.04
0.02
0
−0.02
−0.04
−0.06
−0.06
−0.08
−0.08
3
3.3
3.6
VDD2 = 4.5 V to 5.5 V
0.08
Nonlinearity (%)
Nonlinearity (%)
5.25
Figure 16.
0.1
8
5
VDD1 (V)
Figure 15.
0.08
−0.1
2.7
4.75
−0.1
4.5
VDD2 (V)
5
VDD2 (V)
Figure 17.
Figure 18.
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4.75
5.25
5.5
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
NONLINEARITY
vs INPUT VOLTAGE
NONLINEARITY
vs TEMPERATURE
0.1
0.1
VDD2 = 3 V
VDD2 = 5 V
0.06
0.06
0.04
0.04
0.02
0
−0.02
−0.04
0.02
0
−0.02
−0.04
−0.06
−0.06
−0.08
−0.08
−0.1
−250 −200 −150 −100 −50
0
50 100
Input Voltage (mV)
150
200
−0.1
−40 −25 −10
250
5
20 35 50 65
Temperature (°C)
80
95
Figure 19.
Figure 20.
OUTPUT NOISE DENSITY
vs FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs RIPPLE FREQUENCY
2600
100
2400
90
2200
80
2000
70
PSRR (dB)
Noise (nV/sqrt(Hz))
0.08
Nonlinearity (%)
Nonlinearity (%)
0.08
1800
1600
1400
50
40
30
1000
20
800
10
1
10
100
VDD1
VDD2
60
1200
600
0.1
110 125
0
1
Frequency (kHz)
10
Ripple Frequency (kHz)
Figure 21.
Figure 22.
OUTPUT RISE AND FALL TIME
vs TEMPERATURE
FULL-SCALE
STEP RESPONSE
100
10
Output Rise/Fall Time (µs)
9
8
500 mV/div
7
6
5
4
200 mV/div
3
2
500 mV/div
1
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 23.
Time (2 ms/div)
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
OUTPUT COMMON-MODE VOLTAGE
vs LOW-SIDE SUPPLY VOLTAGE
OUTPUT SIGNAL DELAY TIME vs TEMPERATURE
10
5
8
Signal Delay (µs)
7
6
5
4
3
2
1
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
VDD2 rising
VDD2 falling
Output Common−Mode Voltage (V)
50% to 10%
50% to 50%
50% to 90%
9
4
3
2
1
0
3.5
110 125
3.7
3.8
3.9
4
4.1
VDD2 (V)
4.2
Figure 25.
Figure 26.
OUTPUT COMMON-MODE VOLTAGE
vs TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
5
4.3
4.4
4.5
8
VDD2 = 2.7 V to 3.6 V
VDD2 = 4.5 V to 5.5 V
Output Common−Mode Voltage (V)
3.6
IDD1
IDD2
7
Supply Current (mA)
4
3
2
6
5
4
3
2
1
1
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
0
4.5
110 125
4.75
5
Supply Voltage (V)
Figure 27.
Figure 28.
LOW-SIDE SUPPLY CURRENT
vs LOW-SIDE SUPPLY VOLTAGE
SUPPLY CURRENT
vs TEMPERATURE
8
5.25
5.5
8
7
7
6
6
Supply Current (mA)
IDD2 (mA)
VDD2 = 2.7 V to 3.6 V
5
4
3
2
1
0
2.7
5
4
3
2
1
3
3.3
3.6
0
−40 −25 −10
VDD2 (V)
Figure 29.
10
IDD1
IDD2
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 30.
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THEORY OF OPERATION
INTRODUCTION
The differential analog input of the AMC1100 is a switched-capacitor circuit based on a second-order modulator
stage that digitizes the input signal into a 1-bit output stream. The device compares the differential input signal
(VIN = VINP – VINN) against the internal reference of 2.5 V using internal capacitors that are continuously
charged and discharged with a typical frequency of 10 MHz. With the S1 switches closed, CIND charges to the
voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then both
S2 switches close. CIND discharges to approximately AGND + 0.8 V during this phase. Figure 31 shows the
simplified equivalent input circuitry.
VDD1
GND1
GND1
CINP = 3 pF
3 pF
400 W
VINP
S1
S2
AGND + 0.8 V
Equivalent
Circuit
VINP
CIND = 3.6 pF
S1
400 W
VINN
RIN = 28 kW
S2
VINN
AGND + 0.8 V
3 pF
CINN = 3 pF
GND1
RIN =
GND1
1
fCLK · CDIFF
GND1
(fCLK = 10 MHz)
Figure 31. Equivalent Input Circuit
The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for
current sensing. However, there are two restrictions on the analog input signals, VINP and VINN. If the input
voltage exceeds the range AGND – 0.5 V to AVDD + 0.5 V, the input current must be limited to 10 mA to prevent
the implemented input protection diodes from damage. In addition, the device linearity and noise performance
are ensured only when the differential analog input voltage remains within ±250 mV.
The isolated digital bit stream is processed by a third-order analog filter on the low-side and presented as a
differential output of the device.
The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity, as described in
application report SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity (available for download at
www.ti.com).
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AMC1100
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APPLICATION INFORMATION
CURRENT MEASUREMENT
A typical operation of the AMC1100 is a current-measurement application, as shown in Figure 32. Measurement
of the current through the phase of a power line is done via the shunt resistor RSHUNT (in this case, a two-terminal
shunt). For better performance, the differential signal is filtered using RC filters (components R2, R3, and C2).
Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In this case, care should be taken
when choosing the quality of these capacitors; mismatch in values of these capacitors leads to a common-mode
error at the modulator input.
Isolation
Barrier
Phase
TMC320
C/F28xxx
R1
Device
1
C1
0.1 mF
R2
12 W
RSHUNT
R3
12 W
C2(1)
330 pF
C3
10 pF
(optional)
(1)
VDD1
VDD2
14
(1)
2
VINP
VOUTP
13
C5(1)
0.1 mF R
C
3
C4
10 pF
(optional)
4
VINN VOUTN
GND1
GND2
11
ADC
R
9
Place these capacitors as close as possible to the AMC1100.
Figure 32. Typical Application Diagram for the AMC1100
The high-side power supply for the AMC1100 (VDD1) is derived from the system supply. For lowest cost, a
Zener diode can be used to limit the voltage to 5 V ± 10%. A 0.1-µF decoupling capacitor is recommended for
filtering this power-supply path. This capacitor (C1 in Figure 32) should be placed as close as possible to the
VDD1 pin for best performance. If better filtering is required, an additional 1-µF to 10-µF capacitor can be used.
For higher power efficiency, a step-down converter can be used (such as the TPS62120) to generate the
AMC1100 supply voltage.
The floating ground reference (GND1) is derived from the end of the shunt resistor, which is connected to the
negative input of the AMC1100 (VINN). If a four-terminal shunt is used, the inputs of the AMC1100 are
connected to the inner leads while GND1 is connected to one of the outer shunt leads. The differential input of
the AMC1100 ensures accurate operation even in noisy environments.
The differential output of the AMC1100 can either directly drive an analog-to-digital converter (ADC) input or can
be further filtered before being processed by the ADC.
12
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As shown in Figure 33, it is recommended to place the bypass and filter capacitors as close as possible to the AMC1100 to ensure best performance.
Top View
12 W
SMD 0603
To Shunt
12 W
SMD 0603
330 pF
SMD
0603
LEGEND
Top layer; copper pour and traces
VDD1
VDD2
VINP
VOUTP
0.1 mF
SMD
1206
0.1mF
0.1 mF
SMD
1206
Device
VINN
VOUTN
GND1
GND2
To Filter or ADC
SMD
1206
Clearance area.
Keep free of any
conductive materials.
High-side area
Controller-side area
Via
Figure 33. AMC1100 Layout Recommendation
To maintain the isolation barrier and the common-mode transient immunity (CMTI) of the device, the distance between the high-side ground (GND1) and
the low-side ground (GND2) should be kept at maximum; that is the entire area underneath the device should be kept free of any conducting materials.
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AMC1100
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VOLTAGE MEASUREMENT
The AMC1100 can also be used for isolated voltage measurement applications, as shown in a simplified way in
Figure 34. In such applications, usually a resistor divider (R1 and R2 in Figure 34) is used to match the relatively
small input voltage range of the AMC1100. R2 and the AMC1100 input resistance (RIN) also create a resistance
divider that results in additional gain error. With the assumption that R1 and RIN have a considerably higher value
than R2, the resulting total gain error can be estimated using Equation 1:
R
GERRTOT = GERR + 2
RIN
Where GERR = device gain error.
(1)
L1
R1
R2
RIN
L2
Figure 34. Voltage Measurement Application
14
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ISOLATION GLOSSARY
Creepage Distance: The shortest path between two conductive input-to-output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance: The shortest distance between two conductive input-to-output leads measured through air (line of
sight).
Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that
supplies the primary circuit electric power.
Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate
isolated source.
Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive insulation surface degradation by small localized sparks. Such
sparks result from a surface film of a conducting contaminant breaking on the insulation. The resulting break in
the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated.
These sparks often cause carbonization on insulation material and lead to a carbon track between points of
different potential. This process is known as tracking.
Insulation:
Operational insulation—Insulation needed for correct equipment operation.
Basic insulation—Insulation to provide basic protection against electric shock.
Supplementary insulation—Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation—Insulation comprising both basic and supplementary insulation.
Reinforced insulation—A single insulation system that provides a degree of protection against electric shock
equivalent to double insulation.
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AMC1100
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Pollution Degree:
Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on
device performance.
Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation is to be expected.
Pollution Degree 3—Conductive pollution, or dry nonconductive pollution that becomes conductive because of
condensation, occurs. Condensation is to be expected.
Pollution Degree 4—Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category—This section is directed at insulation coordination by identifying the transient overvoltages
that may occur, and by assigning four different levels as indicated in IEC 60664.
1. Signal Level: Special equipment or parts of equipment.
2. Local Level: Portable equipment, etc.
3. Distribution Level: Fixed installation.
4. Primary Supply Level: Overhead lines, cable systems.
Each category should be subject to smaller transients than the previous category.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
AMC1100DUB
ACTIVE
SOP
DUB
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
AMC1100DUBR
ACTIVE
SOP
DUB
8
350
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
AMC1100DUBR
Package Package Pins
Type Drawing
SOP
DUB
8
SPQ
350
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
10.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.01
5.85
16.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1100DUBR
SOP
DUB
8
350
358.0
335.0
35.0
Pack Materials-Page 2
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