ADVANCE INFORMATION IDT71L024 LOW POWER 3V CMOS SRAM 1 MEG (128K x 8-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The IDT71L024 is a 1,048,576-bit very low-power Static RAM organized as 128K x 8. It is fabricated using IDT’s highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for low-power memory needs. It uses a 6-transistor memory cell. All input and output signals of the IDT71L024 are LVTTLcompatible and operation is from a single extended-range 3.3V supply. This extended supply range makes the device ideally suited for unregulated battery-powered applications. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71L024 is packaged in a JEDEC standard 32-pin TSOP Type I. 128K x 8 Organization Wide Operating Voltage Range: 2.7V to 3.6V Speed Grades: 70ns, 100ns Low Operating Power: 25mA (max) Low Standby Power: 5µA (max) Low-Voltage Data Retention: 1.5V (min) Available in 32-pin, 13.4mm x 8mm Type I TSOP package FUNCTIONAL BLOCK DIAGRAM A0 • • • ADDRESS DECODER • • • 1,048,576-BIT MEMORY ARRAY A16 I/O0 – I/O7 • 8 I/O CONTROL 8 8 WE OE CS1 CONTROL LOGIC CS2 3778 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES 1997 Integrated Device Technology, Inc. MAY 1997 DSC-3967/- 1 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP (I) OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 3778 drw 02 TSOP TOP VIEW TRUTH TABLE(1) CS1 CS2 OE PIN DESCRIPTIONS WE I/O0-I/O7 Function H X X X High-Z Deselected - Standby X L X X High-Z Deselected - Standby L H L H DATAOUT Read L H X L DATAIN Write L H H H High-Z Outputs Disabled NOTE: 1.H = VIH, L = VIL, X = Don't care. 3778 tbl 02 A0 – A16 Address Inputs Input CS1 Chip Select Input CS2 Chip Select Input WE OE Write Enable Input Output Enable Input I/O0 - I/O7 Data Input/Output VDD Power Pwr VSS Ground Gnd I/O 3778 tbl 01 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 6 pF CI/O I/O Capacitance VOUT = 3dV 7 pF NOTE: 3778 tbl 06 1. This parameter is guaranteed by device characterization, but not production tested. 2 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Com’l. and Ind'l. Unit VTERM(2) Terminal Voltage with Respect to VSS –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to VSS –0.5 to VDD+0.5V V °C TBIAS Temperature Under Bias –55 to +125 TSTG Storage Temperature RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Temperature VSS VDD Commercial 0°C to +70°C 0V 2.7V to 3.6V -40°C to +85°C 0V 2.7V to 3.6V Industrial –55 to +125 °C PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA NOTES: 3778 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. Input, Output,and I/O terminals; 4.6V maximum. 3778 tbl 04 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter VDD Supply Voltage VSS Ground VIH Input High Voltage VIL Min. Typ. Max. Unit 2.7 3.0 3.6 V 0 0 0 V 2.0 — VDD+0.3(1) V — 0.8 V (2) Input Low Voltage –0.3 NOTE: 3778 tbl 05 1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –1.5V for pulse width less than 5ns, once per cycle. DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 3.6V, Commercial and Industrial Temperature Ranges Symbol Min. Max. Unit |ILI| Input Leakage Current Parameter VDD = Max., VIN = VSS to VDD Test Conditions — 1 µA |ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD — 1 µA VOH Output High Voltage IOH = –1mA, VDD = Min. 2.4 — V VOL Output Low Voltage IOL = 2mA, VDD = Min. — 0.4 V 3778 tbl 07 DC ELECTRICAL CHARACTERISTICS(1, 2) VDD = 2.7 to 3.6V, VLC = 0.2V, VHC = VDD–0.2V, Commercial and Industrial Temperature Ranges Symbol ICC2 Parameter Dynamic Operating Current Typ.(5) Max. Unit -70 ns — 25 mA -100 ns — 18 — 5 mA µA Test Conditions CS1 = VLC, CS2 = VHC, Outputs Open, VDD = 3.6V, f = fMAX (3) ICC Static Operating Current CS1 = VLC, CS2 = VHC, Outputs Open, WE = VHC, VDD = 3.6V, f = 0(4) ISB1 Standby Supply Current CS1 and CS2 = VHC, or CS2 = VLC, -40 to 85°C — 10 Outputs Open, VDD = 3.6V 0 to 70°C — 5 40°C — 2 25°C — 1 NOTES: 1. All values are maximum guaranteed values. 2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests. 3. fMAX = 1/tRC (all address inputs are cycling at fMAX). 4. f = 0 means no address input lines are changing . 5. Typical conditions are VDD = 3.0V and specified temperature. 3778 tbl 08 3 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (VLC = 0.2V, VHC = VDD - 0.2V) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit — V VDR VCC for Data Retention — 1.5 — ICCDR Data Retention Current 1) CS1 ≥ VHC and CS2 ≥ VHC — <1 5 µA tCDR(3) Chip Deselect to Data Retention Time or 2) CS2 ≤ VLC 0 — — ns tR(3) Operation Recovery Time tRC(2) — — NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. ns 3778 tbl 09 LOW VDD DATA RETENTION WAVEFORM DATA RETENTION MODE VDD 2.7V 2.7V VDR ≥ 1.5V tCDR CS VIH tR VIH VDR 3778 drw 05 AC TEST LOAD AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load VDD GND to 2.5V 3070Ω DATA OUT See Figure 1 3778 tbl 10 50pF* 3150Ω 3778 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load 4 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6V, All Temperature Ranges) Symbol Parameter 71L024L70 71L024L100 Min. Max. Min. Max. Units Read Cycle tRC Read Cycle Time 70 — 100 — ns tAA Address Access Time — 70 — 100 ns Chip Select Access Time — 70 — 100 ns tCLZ Chip Select Low to Output in Low-Z 10 — 10 — ns tCHZ(1) Chip Select High to Output in High-Z — 25 — 30 ns tOE Output Enable Low to Output Valid — 35 — 50 ns tACS (1) (1) Output Enable Low to Output in Low-Z 5 — 5 — ns tOHZ(1) Output Enable High to Output in High-Z — 25 — 30 ns tOH Output Hold from Address Change 10 — 15 — ns tWC Write Cycle Time 70 — 100 — ns tAW Address Valid to End of Write 65 — 80 — ns tCW Chip Select Low to End of Write 65 — 80 — ns tAS Address Set-up Time 0 — 0 — ns tWR Address Hold from End of Write 0 — 0 — ns tWP Write Pulse Width 55 — 70 — ns tDW Data Valid to End of Write 30 — 40 — ns tDH Data Hold Time 0 — 0 — ns tOW(1) Write Enable High to Output in Low-Z 5 — 5 — ns tWHZ(1) Write Enable Low to Output in High-Z — 25 — 30 tOLZ Write Cycle NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. ns 3778 tbl 11 5 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1(1) t RC ADDRESS t AA OE t OE t OLZ CS1 (5) CS2 t ACS (3) t OHZ (5) t CLZ (5) DATA OUT t CHZ (5) HIGH IMPEDANCE DATA OUT VALID 3778 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID 3778 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected; CS1 is LOW and CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 5) tWC ADDRESS tAW CS1 tCW CS2 tWR tWP (7) tAS (3) WE tWHZ DATAOUT (6) tOW HIGH IMPEDANCE (4) (4) tDH tDW DATAIN tCHZ (6) (6) DATAIN VALID 3778 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS1 AND CS2 CONTROLLED TIMING)(1,2,5) tWC ADDRESS tAW CS1 CS2 tAS tWR tCW (3) WE tDW DATAIN tDH DATAIN VALID 3778 drw 10 NOTES: 1. WE or CS1 must be HIGH, or CS2 must be LOW during all address transitions. 2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state. 7. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 7 IDT71L024 LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 71L024 Device Type L XXX XX X Power Speed Package Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PZ 8mm x 13.4mm TSOP Type I 70 100 Speed in nanoseconds 3778 drw 11 8