SMPS MOSFET
PD - 95472A
IRFB18N50KPbF
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency
Circuits
l Lead-Free
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
ID
0.26Ω
17A
500V
Benefits
l Low Gate Charge Qg results in Simple Drive Requirement
l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness
l Fully Characterized Capacitance and Avalanche Voltage
and Current
l Low RDS(on)
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
Mounting Torque, 6-32 or M3 screw
Max.
Units
17
11
68
220
1.8
± 30
7.8
-55 to + 150
A
W
W/°C
V
V/ns
300
°C
10
N
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
370
17
22
mJ
A
mJ
Typ.
Max.
Units
–––
0.50
–––
0.56
–––
58
°C/W
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
1
02/03/06
IRFB18N50KPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
500 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.59 ––– V/°C Reference to 25°C, I D = 1mA
––– 0.26 0.29
Ω
VGS = 10V, ID = 10A
3.0
––– 5.0
V
VDS = V GS, ID = 250µA
––– ––– 50
µA VDS = 500V, VGS = 0V
––– ––– 250
µA
VDS = 400V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
6.4
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
22
60
45
30
2830
330
38
3310
93
155
Max. Units
Conditions
–––
S
VDS = 50V, ID = 10A
120
ID = 17A
34
nC
VDS = 400V
54
VGS = 10V, See Fig. 6 and 13
–––
VDD = 250V
–––
ID = 17A
ns
–––
RG = 7.5Ω
–––
VGS = 10V,See Fig. 10
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 2.5mH, RG = 25Ω,
IAS = 17A,
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
17
––– –––
showing the
A
G
integral reverse
68
––– –––
S
p-n junction diode.
––– ––– 1.5
V
TJ = 25°C, IS = 17A, VGS = 0V
––– 520 780
ns
TJ = 25°C, IF = 17A
––– 5.3 8.0
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C
ISD ≤ 17A, di/dt ≤ 376A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2
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IRFB18N50KPbF
100
100
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
TOP
10
1
0.1
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
5.0V
0.01
10
5.0V
1
0.1
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 150°C
0.001
0.01
0.1
1
10
100
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
100.00
TJ = 150°C
ID, Drain-to-Source Current(Α)
0.1
10.00
1.00
TJ = 25°C
0.10
VDS = 100V
20µs PULSE WIDTH
0.01
5.0
6.0
7.0
8.0
9.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10.0
3.0
ID = 17A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFB18N50KPbF
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance(pF)
10000
Ciss
1000
Coss
100
Crss
VGS , Gate-to-Source Voltage (V)
20
100000
16
8
4
0
10
100
V DS= 400V
V DS= 250V
V DS= 100V
12
10
1
ID = 17A
1000
0
30
60
90
120
150
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 150 ° C
ID , Drain Current (A)
100
10
TJ = 25 ° C
1
10us
100us
10
1ms
10ms
1
0.1
0.2
V GS = 0 V
0.5
0.8
1.1
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
0.1
1.4
TC = 25 °C
TJ = 150 °C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFB18N50KPbF
20
VGS
ID , Drain Current (A)
RD
V DS
RG
15
D.U.T.
+
- VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10
Fig 10a. Switching Time Test Circuit
5
VDS
90%
0
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response(Z thJC )
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
PDM
0.01
t1
t2
0.001
0.00001
Notes:
1. Duty factor D =t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
EAS , Single Pulse Avalanche Energy (mJ)
IRFB18N50KPbF
750
ID
7.6A
11A
BOTTOM 17A
TOP
600
15V
450
D.U.T
RG
300
DRIVER
L
VDS
+
- VDD
IAS
20V
tp
150
A
0.01Ω
Fig 12c. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
Starting T J, Junction Temperature ( ° C)
Fig 12a. Maximum Avalanche Energy
Vs. Drain Current
V(BR)DSS
tp
I AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFB18N50KPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFB18N50KPbF
TO-220AB Package Outline
(Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/06
8
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