TI1 DS125BR111RTWR Low power 12.5 gbps 1-lane linear repeater with equalization Datasheet

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DS125BR111
SNLS430C – OCTOBER 2012 – REVISED AUGUST 2014
DS125BR111 Low Power 12.5 Gbps 1-Lane Linear Repeater
with Equalization
1 Features
3 Description
•
•
•
•
The DS125BR111 is an extremely low power high
performance repeater/redriver designed to support 1lane carrying high speed interface up to 12.5 Gbps.
The receiver's continuous time linear equalizer
(CTLE) provides a boost of 3-10 dB at 6 GHz in each
channel. When operating in SAS-3 or PCIe Gen-3
applications, the DS125BR111 preserves transmit
signal characteristics allowing the host controller and
the end point to negotiate transmit equalizer
coefficients. Transparency to the link training protocol
maximizes the flexibility of the physical placement of
the device within the interconnect and improves
overall channel performance.
1
•
•
•
•
Low 65 mW/Channel (typ) Power Consumption
Supports Link Training
Supports Out-of-Band (OOB) Signaling
Advanced Signal Conditioning I/O
– Receive CTLE up to 10 dB at 6 GHz
– Linear Output Driver
– Output Voltage Range over 1200 mV
Programmable via Pin Selection, EEPROM, or
SMBus Interface
Single Supply Voltage: 2.5 V or 3.3 V
−40°C to 85°C Operating Temperature Range
Flow-thru Pinout in 4 mm × 4 mm 24-pin Leadless
WQFN Package
The programmable settings can be applied easily via
pins, software (SMBus or I2C), or loaded via an
external EEPROM. In EEPROM mode, the
configuration information is automatically loaded on
power up, which eliminates the need for an external
microprocessor or software driver.
2 Applications
•
•
•
SAS-1/2/3 and SATA-1/2/3
PCI Express 1/2/3
Other Proprietary Interfaces up to 12.5 Gbps
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS125BR111
WQFN (24)
4.00mm x 4.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
DS125BR111
INA+
INA-
OUTA+
OUTAINB+
INB-
OUTB+
OUTBVDD
AD0/EQA0
Address
straps (pull-up
or pull-down)
1 N
AD1/EQA1
ENSMB
AD2/EQB1
SMBus
Slave
Mode(1)
3.3V
AD3/EQB0
4.7 N
4.7 N
RES
SD_TH
VDD
SDA/VODA_DB(2)
SCL/VODB_DB(2)
To system
SMBus
READEN/VOD_SEL
VIN
2.5 V
Mode(4)
VDD_SEL
DONE/RXDET
PWDN(3)
2.5V
10F
(1x)
(1)
(2)
(3)
(4)
(5)
1F
(1x)
0.1F
(2x)
Normal
operation
VDD
(DAP) GND(5)
Schematic requires different connections for SMBus Master Mode and Pin Mode
SMBus signals need to be pulled up elsewhere in the system
PWDN pin can alternatively be driven by a control device (i.e. FPGA)
Schematic requires different connections for 3.3 V mode
A minimum of 4 vias are recommended for proper thermal and electrical performance
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS125BR111
SNLS430C – OCTOBER 2012 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
6
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Electrical Characteristics — Serial Management Bus
Interface .................................................................. 10
7.7 Timing Requirements .............................................. 10
7.8 Typical Characteristics ............................................ 12
8
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
13
14
14
17
24
Application and Implementation ........................ 32
9.1 Application Information............................................ 32
9.2 Typical Application ................................................. 34
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1 Trademarks ........................................................... 38
12.2 Electrostatic Discharge Caution ............................ 38
12.3 Glossary ................................................................ 38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2014) to Revision C
•
Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application
and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
Changes from Revision A (January 2014) to Revision B
•
2
Page
Changed Features ................................................................................................................................................................. 1
Changes from Original (April 2013) to Revision A
•
Page
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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6 Pin Configuration and Functions
PWDN
SCL/VODB_DB
SDA/VODA_DB
ENSMB
EQB1/AD2
EQB0/AD3
6
5
4
3
2
1
24 Pin
Package RTW
Top View
OUTA+
7
24
INA+
OUTA-
8
23
INA-
AD1/EQA1
9
22
VDD
AD0/EQA0
10
21
VDD
INB+
11
20
OUTB+
INB-
12
19
OUTB-
13
14
15
16
17
18
RES
SD_TH
VIN
VDD_SEL
VOD_SEL / READEN
RXDET / DONE
SMBUS AND
CONTROL
The center DAP on the package bottom is the only device GND connection. This pad must be connected to
GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DIFFERENTIAL HIGH SPEED I/O
INB+, INB-
11, 12
I
Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination
resistor connects INB+ to VDD and INB- to VDD when enabled by RXDET control logic.
AC coupling required on high-speed I/O
OUTB+,
OUTB-
20, 19
O
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
INA+, INA-
24, 23
I
Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination
resistor connects INA+ to VDD and INA- to VDD when enabled by RXDET control logic.
AC coupling required on high-speed I/O
7, 8
O
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
OUTA+,
OUTA-
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
CONTROL PINS — SHARED (LVCMOS)
ENSMB
3
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) enable Pin
Tie 1 kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBus Mode)
Tie 1 kΩ to GND = Pin Mode
ENSMB = Float or 1 (SMBus MODEs)
SCL
SDA
AD0-AD3
5
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
SMBus clock input Pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
4
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA Pin is enabled. Data input or open drain output. External pullup required as per SMBus protocol (typically in the 2 kΩ to 5 kΩ range). This pin is 3.3 Vtolerant.
10, 9, 2, 1
I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these Pins are the user set SMBus slave
address inputs.
READEN
17
I, LVCMOS
ENSMB = Float: When using an External EEPROM, a logic low on this pin starts the load
from the external EEPROM
ENSMB = 1: When using SMBus Slave Mode the VOD_SEL/READEN pin must be tied Low
for the AD[3:0] to be active. If this pin is tied High or Floated an address of 0xB0 will be used
for the DS125BR111.
DONE
18
O, LVCMOS
When using an External EEPROM (ENSMB = Float), Valid Register Load Status Output
HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0
EQB0
10
1
I, 4-LEVEL,
LVCMOS
EQA0 and EQB0 control the level of equalization of the A/B directions. The Pins are defined
as EQx0 only when ENSMB is de-asserted (low). When ENSMB goes high the SMBus
registers provide independent control of each channel. See Table 4.
EQA1
EQB1
9
2
I, 4-LEVEL,
LVCMOS
EQA1 and EQB1 are not used in the DS125BR111 design. These pins should always be tied
to GND.
VODA_DB
4
I, 4-LEVEL,
LVCMOS
VODA_DB controls the CHA output amplitude dynamic range, for SAS and PCIe applications
it should be held Low. The Pin is defined as VODA_DB only when ENSMB is de-asserted
(low). When ENSMB goes high the SMBus registers provide control of each channel, pin 4 is
converted to SDA. See Table 5.
VODB_DB
5
I, 4-LEVEL,
LVCMOS
VODB_DB controls the CHB output amplitude dynamic range, for SAS and PCIe applications
it should be held Low. The Pin is defined as VODB_DB only when ENSMB is de-asserted
(low). When ENSMB goes high the SMBus registers provide control of each channel, pin 5 is
converted to SCL. See Table 5.
SD_TH
14
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold. This detection threshold is for system debug
only and does not control the high speed datapath.
See Table 3.
VOD_SEL
17
I, 4-LEVEL,
LVCMOS
VOD_SEL controls the low frequency ratio of input voltage to output voltage amplitude. See
Table 5.
I, 4-LEVEL,
LVCMOS
The RXDET Pin controls the receiver detect function. Depending on the input level, a 50 Ω or
> 50 kΩ termination to the power rail is enabled. In a SAS/SATA system RXDET should be
set to a Logic "1" state to keep the termination always enabled.
The RXDET pin only controls the RXDET function in PIN MODE. PCIe applications
which require SMBus Mode functionality must utilize a specific register write
sequence documented in PCIe Applications . If this sequence is not utilized, SMBus
configuration modes will default the input terminations to active (50 Ω). See Table 2 .
RXDET
4
18
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
RES
13
I, 4-LEVEL,
LVCMOS
VDD_SEL
16
I, FLOAT
PWDN
6
I, LVCMOS
Reserved:
This input must be left Floating.
Controls the internal regulator
Float = 2.5 V mode
Tie GND = 3.3 V mode
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 2.
POWER (See Figure 11)
VIN
15
Power
In 3.3 V mode, feed 3.3 V to VIN
In 2.5 V mode, leave floating.
VDD
21, 22
Power
Power supply pins CML/analog
2.5 V mode, connect to 2.5 V
3.3 V mode, decouple each VDD pin with 0.22 µF cap to GND
GND
DAP
Power
Ground pad (DAP - die attach pad).
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage (VDD - 2.5 V)
-0.5
+2.75
V
Supply Voltage (VIN - 3.3 V)
-0.5
+4.0
V
LVCMOS Input/Output Voltage
-0.5
+4.0
V
CML Input Voltage
-0.5
VDD + 0.5
V
CML Input Current
-30
+30
mA
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
Tsolder
Lead Temperature Range Soldering (4 sec.) (1)
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
MIN
MAX
UNIT
-40
125
°C
260
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (2)
-5000
5000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (3)
-1250
1250
V
For soldering specifications: See application note SNOA549.
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage (2.5 V mode)
2.375
2.5
2.625
V
Supply Voltage (3.3 V mode)
3.0
3.3
3.6
V
Ambient Temperature
-40
25
+85
°C
SMBus (SDA, SCL)
3.6
V
Supply Noise up to 50 MHz (1)
100
mVp-p
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
7.4 Thermal Information
DS125BR111
THERMAL METRIC (1)
RTW
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
35.0
RθJC(top)
Junction-to-case (top) thermal resistance
34.0
RθJB
Junction-to-board thermal resistance
13.4
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
13.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.3
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
60
mA
7
13
mA
2.5
2.625
V
POWER
IDD
VDD
Current Consumption
VODx_DB = 0, EQ = 0,
VOD_SEL = 1,
RXDET = 1, PWDN = 0
VIN = 2.625 or 3.6 V
Power Down Current Consumption
PWDN = 1
Integrated LDO Regulator
VIN = 3.0 - 3.6 V
2.375
LVCMOS / LVTTL DC SPECIFICATIONS
Vih25
High Level Input Voltage
2.5 V Supply Mode
1.7
VDD
V
Vih33
High Level Input Voltage
3.3 V Supply Mode
1.7
VIN
V
Vil
Low Level Input Voltage
0
0.7
V
Voh
High Level Output Voltage
(DONE pin)
Ioh = −4 mA
Vol
Low Level Output Voltage
(DONE pin)
Iol = 4 mA
Iih
Input High Current (PWDN pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Iil
Input Low Current (PWDN pin)
2.0
V
0.4
V
-15
+15
µA
VIN = 3.6 V,
LVCMOS = 0 V
-15
+15
µA
Input High Current with internal
resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
+20
+80
µA
Input Low Current with internal
resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 0 V
-160
-40
µA
4-LEVEL INPUT DC SPECIFICATIONS
Iih
Iil
Vth
Threshold 0 / R
0.40
VDD = 2.5 V (2.5 V supply mode)
Internal LDO Disabled
See Table 1 for details
Threshold R / Float
Threshold Float / 1
Threshold 0 / R
1.25
0.55
VIN = 3.3 V (3.3 V supply mode)
Internal LDO Enabled
See Table 1 for details.
Threshold R / Float
Threshold Float / 1
V
2.1
1.65
V
2.7
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-diff
RX Differential return loss
SDD11 10 MHz
-19
SDD11 2 GHz
-14
SDD11 6-11.1 GHz
-8
dB
RLRX-cm
RX Common mode return loss
0.05 - 5 GHz
ZRX-dc
RX DC common mode impedance
Tested at VDD = 2.5 V
40
50
60
Ω
ZRX-diff-dc
RX DC differential mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
VRX-signal-det-diff-
Signal detect assert level
SD_TH = F (float),
0101 pattern at 12 Gbps
50
mVp-p
Signal detect de-assert level
SD_TH = F (float),
0101 pattern at 12 Gbps
37
mVp-p
20% to 80% of differential output
voltage
40
ps
20% to 80% of differential output
voltage
0.01
UI
pp
VRX-idle-det-diff-pp
-10
dB
HIGH SPEED OUTPUTS
TTX-RISE-FALL
Transmitter rise/fall time
TRF-MISMATCH
Transmitter rise/fall mismatch
(1)
(2)
(1)
(2)
Rise / Fall time measurements will vary based on EQ setting, Input Amplitude, and input edge rate.
Mismatch between rise time and fall time for a given channel.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RLTX-DIFF
TX Differential return loss
RLTX-CM
TX Common mode return loss
ZTX-DIFF-DC
DC differential TX impedance
MIN
TYP
MAX
UNIT
SDD22 10 MHz - 2 GHz
-15
SDD22 5.5 GHz
-12
SDD22 11.1 GHz
-10
dB
0.05 - 5 GHz
-10
dB
100
Ω
20
mA
ITX-SHORT
Transmitter short circuit current limit
VTX-CM-DC-
Absolute delta of DC common mode
voltage during L0 and electrical idle
100
mV
Absolute delta of DC common mode
voltage between TX+ and TX-
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINEDELTA
Total current, output shorted to
VDD or GND
dB
HIGH SPEED OUTPUTS
VTX-diff1-pp
Output Voltage Differential Swing
Differential measurement with
OUTx+ and OUTx-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
VODx_DB = 0 dB,
VID = 600 mVp-p
VOD = 001'b (0.7*VID)
440
500
550
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTx+ and OUTx-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
VODx_DB = 0 dB,
VID = 1000 mVp-p
VOD = 001'b (0.7*VID) (3)
630
700
740
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTx+ and OUTx-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
VODx_DB = 0 dB,
VID = 600 mVp-p
VOD = 111'b (1.05*VID) (3)
570
650
740
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTx+ and OUTx-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
VODx_DB = 0 dB,
VID = 1000 mVp-p
VOD = 111'b (1.05*VID) (3)
800
1010
1215
mVp-p
TTX-IDLE-DATA
Time to transition to valid differential
signal after idle
VID = 1.0 Vp-p, 3 Gbps
0.04
ns
TTX-DATA-IDLE
Time to transition to idle after
differential signal
VID = 1.0 Vp-p, 3 Gbps
0.70
ns
TPD
Differential Propagation Delay
EQ = Level 1 to Level 4
70
ps
VTX-diff2-pp
VTX-diff3-pp
VTX-diff4-pp
(3)
8
The output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level and the frequency content.
The DS125BR111 repeater is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support handshake
negotiation link training.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EQUALIZATION
DJE1
Residual Deterministic Jitter at 6 Gbps
Input: 5” Differential Stripline,
5mil trace width, FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x01,
VOD = 111'b, VODx_DB = 0 dB
0.06
UI
DJE2
Residual Deterministic Jitter at 12 Gbps Input: 5” Differential Stripline,
5mil trace width, FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x01,
VOD = 111'b, VODx_DB = 0 dB
0.12
UI
RJADD1
Additive Random Jitter
(4)
Evaluation Module (EVM) only,
FR4,
VID = 0.8 Vp-p,
PRBS7, EQ = 0x00,
VOD = 111'b, VODx_DB = 0 dB
< 300
fs RMS
RJADD2
Additive Random Jitter
(4)
Input: 10" Differential Stripline,
5 mil trace width, FR4,
VID = 0.8 Vp-p,
PRBS7, EQ = 0x03,
VOD = 111'b, VODx_DB = 0 dB
< 400
fs RMS
(4)
Additive random jitter is given in RMS value by the following equation: RJADD = √[(Output Jitter)2 - (Input Jitter)2] . The typical source
input jitter for these measurements is 150 fs RMS.
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7.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
Output Low Voltage
VDD
Nominal Bus Voltage
IIH-pin
Input Leakage Per Device pin
IIL-pin
Input Leakage Per Device pin
SDA or SCL, IOL = 1.25 mA
0.8
V
2.1
3.6
V
0
0.36
V
2.375
3.6
V
+20
+150
µA
-160
-40
µA
(1) (2)
CI
Capacitance for SDA and SCL
See
<5
pF
RTERM
External Termination Resistance
pull to VDD = 2.5 V ± 5% OR 3.3 V
± 10%
Pullup VDD = 3.3 V (1) (2) (3)
2000
Ω
Pullup VDD = 2.5 V (1) (2) (3)
1000
Ω
(1)
(2)
(3)
Typical value.
Recommended maximum capacitance load per bus segment is 400 pF.
Maximum termination voltage should be identical to the device supply voltage.
7.7 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
kHz
520
kHz
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
(1)
280
400
tFALL
SCL or SDA Fall Time
Read operation
RPU = 4.7 kΩ, Cb < 50 pF
60
ns
tRISE
SCL or SDA Rise Time
Read operation
RPU = 4.7 kΩ, Cb < 50 pF
140
ns
tF
Clock/Data Fall Time
See (2)
300
ns
tR
Clock/Data Rise Time
See (2)
1000
ns
(1)
(2)
The external EEPROM device address byte must be 0xA0 and capable of 1 MHz operation at 2.5 V and 3.3 V.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
80%
VOD = [Out+ - Out-]
80%
0V
20%
tRISE
20%
tFALL
Figure 1. Output Rise And Fall Transition Time
10
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IN
0V
tPLHD
tPHLD
OUT
0V
Figure 2. Propagation Delay Timing Diagram
+
IN
0V
DATA
tIDLE-DATA
tDATA-IDLE
+
OUT
0V
DATA
IDLE
IDLE
Figure 3. Transmit Idle-Data and Data-Idle Response Time
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tF
tHD:DAT
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
ST
SP
Figure 4. SMBus Timing Parameters
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7.8 Typical Characteristics
1.4
1.4
VID = 0.6Vpp
VID = 0.6Vpp
VID = 0.8Vpp
VID = 1.0Vpp
VID = 1.2Vpp
VID = 0.8Vpp
1.3
1.3
VID = 1.0Vpp
Output Differential Voltage (Vpp)
Output Differential Voltage (Vpp)
VID = 1.2Vpp
1.2
1.1
1
0.9
0.8
0.7
1.2
1.1
1
0.9
0.8
0.7
0.6
-40
-15
10
35
60
0.6
2.325
85
2.5
2.675
VDD (V)
Temperature (C)
C001
C003
Test Conditions
Data Rate/Test Pattern:
1.5625 Gbps /
101010 Repeating Pattern
VOD:
Level 6
EQ:
Level 1
VOD_DB:
000'b
VDD:
2.5 V
Test Conditions
Data Rate/Test Pattern:
1.5625 Gbps /
101010 Repeating Pattern
VOD:
Level 6
EQ:
Level 1
VOD_DB:
000'b
Temperature:
25°C
Figure 5. Typical VOD vs. VDD
Figure 6. Typical VOD vs. Temperature
1.4
Level 1
Level 2
Output Differential Voltage (Vpp)
1.2
Level 3
Level 4
Level 5
1
Level 6
0.8
0.6
0.4
0.2
0.2
0.4
0.6
0.8
1
1.2
1.4
Input Differential Voltage (Vpp)
C005
Test Conditions
Data Rate/Test Pattern:
1.5625 Gbps / 101010 Repeating Pattern
EQ:
Minimum
VOD_DB:
000'b
Temperature:
25°C
VDD:
2.5 V
Figure 7. Typical VOD Level vs. VID
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8 Detailed Description
8.1 Overview
The DS125BR111 compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The
DS125BR111 operates in 3 modes: pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; please refer to
SMBus Master Mode for additional information.
8.2 Functional Block Diagram
A Channel
Term
RXDET
Signal
Detect
INA+
EQ
INA-
OUTA+
Predriver
Driver
OUTA-
ENSMB
EQA[1:0]
VODA_DB
VOD_SEL
READEN
DONE
AD[3:0]
SCL
SDA
Internal voltage
regulator
Digital Core and SMBus Registers
PWDN
VDD_SEL
VIN
B Channel
ENSMB
EQB[1:0]
VODB_DB
VOD_SEL
Signal
Detect
OUTB+
Predriver
Driver
OUTB-
Term
RXDET
INB+
EQ
INB-
Figure 8. Channel A/B Datapath
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Functional Block Diagram (continued)
8.2.1 Functional Datapath Blocks
The DS125BR111 datapath is designed to provide transparency for Rx-Tx training in SAS-3, PCIe Gen3, and
other standards. The datapath includes input continuous time linear equalization coupled with a linear driver. This
combination has a high level of transparency, achieving greater drive distance in applications which utilize Rx-Tx
training.
The DS125BR111 datapath is optimized to work as a transparent driver and a transparent receiver. The typical
DS125BR111 system placement breaks a long transmission line into two pieces. This often leads to one short
and one long piece. While the DS125BR111 can be placed anywhere in the channel, to maximize channel
extension placement with some attenuation on the DS125BR111 inputs works best. Refer to Application and
Implementation for more application information regarding device placement.
8.3 Feature Description
The 4-level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control
settings when ENSMB=0. There is an internal 30 kΩ pull-up and a 60 kΩ pull-down connected to the package
Pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level.
Using the 1 kΩ pull-up, 1 kΩ pull-down, no connect, and 20 kΩ pull-down provide the optimal voltage levels for
each of the four input states.
Table 1. 4–Level Control Pin Settings
LEVEL
SETTING
0
RESULTING PIN VOLTAGE
3.3 V MODE
2.5 V MODE
Tie 1 kΩ to GND
0.10 V
0.08 V
1/3 x VDD
R
Tie 20 kΩ to GND
1/3 x VIN
Float
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1 kΩ to VIN or VDD
VIN - 0.05 V
VDD - 0.04 V
Typical 4-Level Input Thresholds
• Level 1 - 2 = 0.16 * VIN or VDD
• Level 2 - 3 = 0.5 * VIN or VDD
• Level 3 - 4 = 0.83 * VIN or VDD
In order to minimize the startup current associated with the integrated 2.5 V regulator the 1 kΩ pull-up / pull-down
resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or
more 1 kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500 Ω
resistor is a good way to save board space.
8.4 Device Functional Modes
8.4.1 Pin Control Mode
When in Pin mode (ENSMB = 0), equalization can be selected via pins for each side independently. For
PCIe applications, the RXDET pin provides automatic and manual control for input termination (50 Ω or > 50
kΩ). The receiver electrical signal detect threshold is also adjustable via the SD_TH pin. The signal detect
status can only be used for system debug.
8.4.2 SMBus Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, and termination disable
features are all programmable on a individual channel basis. Upon assertion of ENSMB = 1, the EQx, VOD,
and VODx_DB functions revert to register control immediately. The EQx pins are converted to AD0-AD3
SMBus address inputs. SD_TH remains active unless their respective registers are written to and the
appropriate override bit is set, in which case it is ignored until ENSMB is driven low (Pin mode). On power-up
or when ENSMB is driven low all registers are reset to their default state. If PWDN is asserted while ENSMB
is high, the registers retain their current state.
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Device Functional Modes (continued)
Equalization settings accessible via the Pin controls were chosen to meet the needs of most high speed
applications. If ongoing adjustment is needed, equalization settings can be accessed via the SMBus
registers. Each input has a total of 4 possible equalization settings. The tables show the 4 settings when the
device is in Pin mode. When using SMBus mode, the equalization, VOD and VOD_DB levels are set by
registers.
The 4-level input Pins utilize a resistor divider to help set the 4 valid levels and provide a wide range of
control settings when ENSMB = 0. There is an internal 30 kΩ pull-up and a 60 kΩ pull-down connected to the
package pin. These resistors, together with the external resistor connection combine to achieve the desired
voltage level. Using the 1 kΩ pull-up, 1 kΩ pull-down, no connect, and 20 kΩ pull-down provide the optimal
voltage levels for each of the four input states.
Table 2. RX-Detect Settings
PWDN
(Pin 6)
RXDET
(Pin 18)
SMBus REG
0x0E and 0X15[3:2]
INPUT
TERMINATION
0
0
00'b
Hi-Z
Tie 20 kΩ
to GND
0
01'b
RECOMMENDE
D USE
COMMENTS
Manual RX-Detect, input is high impedance
mode
Pre Detect: Hi-Z
Post Detect: 50 Ω
Auto RX-Detect, outputs test every 12 ms for
600 ms then stops; termination is Hi-Z until RX
detection; once detected input termination is 50
Ω
PCIe only
Reset function by pulsing PWDN high for 5 µs
then low again
0
Float
(PCIe
Default)
0
1
(SAS
Default)
1
10'b
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe only
11'b
50 Ω
All Others
Auto RX-Detect, outputs test every 12 ms until
detection occurs; termination is Hi-Z until RX
detection; once detected input termination is 50
Ω
Manual RX-Detect, input is 50 Ω
X
Power down mode, input is Hi-Z, output drivers
are disabled
High Impedance
Used to reset RX-Detect State Machine when
held high for 5 µsec
When SMBus is used to control the DS125BR111 in a PCIe application, a specific register write sequence
detailed in PCIe Applications is required on power-up to properly enable and control the RX_Detect process.
Table 3. Signal Detect Status Threshold Level (1) (2)
(1)
(2)
SD_TH
(Pin 14)
SMBus REG BIT [3:2] and [1:0]
3 Gbps
12 Gbps
3 Gbps
12 Gbps
0
10
18
75
14
55
R
01
12
40
8
22
F (default)
00
15
50
11
37
1
11
16
58
12
45
[3:2] ASSERT LEVEL (mVp-p)
[1:0] DE-ASSERT LEVEL (mVp-p)
VDD = 2.5 V, 25°C, 11 00 11 00 pattern at 3 Gbps and 101010 pattern at 12 Gbps
Signal Detect Threshold (SD_TH) is for debugging purposes only, outputs are enabled unless the channel is set to PWDN
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8.4.3 Signal Conditioning Settings
Table 4. Equalizer Settings
EQUALIZATION BOOST RELATIVE TO DC
Level
EQx1
EQx0
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
5 GHz
dB at
6 GHz
1
0
0
xxxx xx00 = 0x00
2.1
2.5
2.7
2.9
3.0
2
0
R
xxxx xx01 = 0x01
4.0
5.1
6.4
6.8
7.4
3
0
Float
xxxx xx10 = 0x02
5.5
7.0
8.3
8.6
8.9
4
0
1
xxxx xx11 = 0x03
6.8
8.3
9.5
9.6
9.8
(1)
Suggested Use (1)
SAS-3
For SAS3 applications the best performance is achieved with Equalization Level 4. For non SAS applications, optimal EQ setting should
be determined via simulation and prototype verification.
Table 5. Output Voltage Pin Settings
Channel B Level
VOD_SEL
VID Vp-p
VODx_DB
Setting (1)
VOD Vp-p
0
0
1.0
0
0.65
0
1.0
0
0.70
3
3
R
1.0
0
0.83
5
5
Float
1.0
0
0.91
7
7
1
1.0
0
1.05
Channel A Level
1
(1)
16
The VOD output amplitude is set with the VOD_SEL Pin. For SAS-3 and PCIe operation the VOD_DB level is typically left at 0 dB
(SMBus control = 000'b) in order to keep the output dynamic range as large as possible. VOD_DB settings other than 0 dB or 000'b will
decrease the output dynamic range and act to limit the output VOD. When operating in Pin Mode in a SAS3 environment it is
recommended to use VOD_SEL = 1.
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8.5 Programming
The DS125BR111 device supports reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS125BR111 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines.
• Maximum EEPROM size is 8 kbits (1024 x 8-bit).
• Set ENSMB = Float — enable the SMBus master mode.
• The external EEPROM device address byte must be 0xA0 and capable of 1 MHz operation at 2.5 V and 3.3
V supply.
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
The VOD_SEL/READEN pin must be tied Low for the AD[3:0] to be active. If this pin is tied High or Floated
an address of 0xB0 will be used for the DS125BR111.
When tying multiple DS125BR111 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
• Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for 4 devices. The first device in the sequence must be address 0xB0, subsequent devices
must follow the address order listed below.
– U1: AD[3:0] = 0000 = 0xB0,
– U2: AD[3:0] = 0001 = 0xB2,
– U3: AD[3:0] = 0010 = 0xB4,
– U4: AD[3:0] = 0011 = 0xB6
• Use a pull-up resistor on SDA and SCL; typical value = 2 kΩ - 5 kΩ
• Daisy-chain READEN (Pin 17) and DONE (Pin 18) from one device to the next device in the sequence so that
they do not compete for the EEPROM at the same time.
1. Tie READEN of the 1st device in the chain (U1) to GND
2. Tie DONE of U1 to READEN of U2
3. Tie DONE of U2 to READEN of U3
4. Tie DONE of U3 to READEN of U4
5. Optional: Tie DONE output of U4 to a LED to show the devices have been loaded successfully
Below is an example using the default register values of a 2 kbit (256 x 8-bit) EEPROM in hex format for the
DS125BR111 device. The first 3 bytes of the EEPROM always contain a header common and necessary to
control initialization of all devices connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If
CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from the CRC location,
to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration
data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the
DS125BR111 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is
necessary to properly address the EEPROM. There are 37 bytes of data size for each DS125BR111 device.
:2000000000001000000407002FED4002FED4002FAD4002FAD400005F5A8005F5A8005F5A15
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
Note: The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).
Note: Default register values. These should be changed as indicated in the datasheet to support PCIe and
SAS/SATA
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Table 6. EEPROM Register Map - Single Device With SAS Values
EEPROM Address Byte
Description
Value
0
00
Description
Value
1
00
Description
Value
2
00
Description
3
SMBus Register
Value
00
Description
4
SMBus Register
Value
00
Description
5
SMBus Register
Value
04
Description
6
SMBus Register
Value
07
Description
7
SMBus Register
Value
00
Description
8
SMBus Register
Value
2F
Description
9
SMBus Register
Value
18
ED
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
CRC EN
Address Map
Present
EEPROM > 256
Bytes
RES
DEVICE
COUNT[3]
DEVICE
COUNT[2]
DEVICE
COUNT[1]
DEVICE
COUNT[0]
0
0
0
0
0
0
0
0
RES
RES
RES
RES
RES
RES
RES
RES
0
0
0
0
0
0
0
0
Max EEPROM
Burst size[7]
Max EEPROM
Burst size[6]
Max EEPROM
Burst size[5]
Max EEPROM
Burst size[4]
Max EEPROM
Burst size[3]
Max EEPROM
Burst size[2]
Max EEPROM
Burst size[1]
Max EEPROM
Burst size[0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ENABLE_CHB
ENABLE_CHA
0x01 [7]
0x01 [6]
0x01 [5]
0x01 [4]
0x01 [3]
0x01 [2]
0x01 [1]
0x01 [0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Ovrd_ENABLE
Reserved
Reserved
Reserved
0x02 [5]
0x02 [4]
0x02 [3]
0x02 [2]
0x02 [0]
0x04 [7]
0x04 [6]
0x04 [5]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Ovrd_SD_TH
Reserved
0x04 [4]
0x04 [3]
0x04 [2]
0x04 [1]
0x04 [0]
0x06 [4]
0x08 [6]
0x08 [5]
0
0
0
0
0
1
0
0
Reserved
Ovrd_RX_Detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x08 [4]
0x08 [3]
0x08 [2]
0x08 [1]
0x08 [0]
0x0B [6]
0x0B [5]
0x0B [4]
0
0
0
0
0
1
1
1
rate_delay_3
rate_delay_2
rate_delay_1
rate_delay_0
Reserved
Reserved
RXDET_A_1
RXDET_A_0
0x0B [3]
0x0B [2]
0x0B [1]
0x0B [0]
0x0E [5]
0x0E [4]
0x0E [3]
0x0E [2]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CHA_EQ_1
CHA_EQ_0
0x0F [7]
0x0F [6]
0x0F [5]
0x0F [4]
0x0F [3]
0x0F [2]
0x0F [1]
0x0F [0]
0
0
1
0
1
1
1
1
CHA_SCP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x10 [7]
0x10 [6]
0x10 [5]
0x10 [4]
0x10 [3]
0x10 [2]
0x10 [1]
0x10 [0]
1
1
1
0
1
1
0
1
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Table 6. EEPROM Register Map - Single Device With SAS Values (continued)
EEPROM Address Byte
Description
A
SMBus Register
Value
40
Description
B
SMBus Register
Value
02
Description
C
SMBus Register
Value
FE
Description
D
SMBus Register
Value
D4
Description
E
SMBus Register
Value
00
Description
F
SMBus Register
Value
2F
Description
10
SMBus Register
Value
AD
Description
11
SMBus Register
Value
40
Description
12
SMBus Register
Value
02
Description
13
SMBus Register
Value
FA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
CHA_VOD_DB_2
CHA_VOD_DB_1
CHA_VOD_DB_0
Reserved
CHA_THa_1
CHA_THa_0
CHA_THd_1
CHA_THd_0
0x11 [2]
0x11 [1]
0x11 [0]
0x12 [7]
0x12 [3]
0x12 [2]
0x12 [1]
0x12 [0]
0
1
0
0
0
0
0
0
Reserved
Reserved
RXDET_B_1
RXDET_B_0
Reserved
Reserved
Reserved
Reserved
0x15 [5]
0x15 [4]
0x15 [3]
0x15 [2]
0x16 [7]
0x16 [6]
0x16 [5]
0x16 [4]
0
0
0
0
0
0
1
0
Reserved
Reserved
CHB_EQ_1
CHB_EQ_0
CHB_SCP
Reserved
Reserved
Reserved
0x16 [3]
0x16 [2]
0x16 [1]
0x16 [0]
0x17 [7]
0x17 [6]
0x17 [5]
0x17 [4]
1
1
1
1
1
1
1
0
Reserved
Reserved
Reserved
Reserved
CHB_VOD_DB_2
CHB_VOD_DB_1
CHB_VOD_DB_0
Reserved
0x17 [3]
0x17 [2]
0x17 [1]
0x17 [0]
0x18 [2]
0x18 [1]
0x18 [0]
0x19 [7]
1
1
0
1
0
1
0
0
CHB_THa_1
CHB_THa_0
CHB_THd_1
CHB_THd_0
Reserved
Reserved
Reserved
Reserved
0x19 [3]
0x19 [2]
0x19 [1]
0x19 [0]
0x1C [5]
0x1C [4]
0x1C [3]
0x1C [2]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1D [7]
0x1D [6]
0x1D [5]
0x1D [4]
0x1D [3]
0x1D [2]
0x1D [1]
0x1D [0]
0
0
1
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1E [7]
0x1E [6]
0x1E [5]
0x1E [4]
0x1E [3]
0x1E [2]
0x1E [1]
0x1E [0]
1
0
1
0
1
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1F [2]
0x1F [1]
0x1F [0]
0x20 [7]
0x20 [3]
0x20 [2]
0x20 [1]
0x20 [0]
0
1
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x23 [5]
0x23 [4]
0x23 [3]
0x23 [2]
0x24 [7]
0x24 [6]
0x24 [5]
0x24 [4]
0
0
0
0
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CHA_VOD_2
0x24 [3]
0x24 [2]
0x24 [1]
0x24 [0]
0x25 [7]
0x25 [6]
0x25 [5]
0x25 [4]
1
1
1
1
1
0
1
0
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Table 6. EEPROM Register Map - Single Device With SAS Values (continued)
EEPROM Address Byte
Description
14
SMBus Register
Value
D4
Description
15
SMBus Register
Value
00
Description
16
SMBus Register
Value
00
Description
17
SMBus Register
Value
5F
Description
18
SMBus Register
Value
5A
Description
19
SMBus Register
Value
80
Description
1A
SMBus Register
Value
05
Description
1B
SMBus Register
Value
F5
Description
1C
SMBus Register
Value
A8
Description
1D
SMBus Register
Value
20
00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
CHA_VOD_1
CHA_VOD_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x25 [3]
0x25 [2]
0x25 [1]
0x25 [0]
0x26 [2]
0x26 [1]
0x26 [0]
0x27 [7]
1
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
ovrd_fast_idle
hi_idle_th CHA
hi_idle_th CHB
fast_idle CHA
0x27 [3]
0x27 [2]
0x27 [1]
0x27 [0]
0x28 [6]
0x28 [5]
0x28 [4]
0x28 [3]
0
0
0
0
0
0
0
0
fast_idle CHB
low_gain CHA
low_gain CHB
Reserved
Reserved
Reserved
Reserved
Reserved
0x28 [2]
0x28 [1]
0x28 [0]
0x2B [5]
0x2B [4]
0x2B [3]
0x2B [2]
0x2C [7]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2C [6]
0x2C [5]
0x2C [4]
0x2C [3]
0x2C [2]
0x2C [1]
0x2C [0]
0x2D [7]
0
1
0
1
1
1
1
1
Reserved
Reserved
CHB_VOD_2
CHB_VOD_1
CHB_VOD_0
Reserved
Reserved
Reserved
0x2D [6]
0x2D [5]
0x2D [4]
0x2D [3]
0x2D [2]
0x2D [1]
0x2D [0]
0x2E [2]
0
1
0
1
1
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2E [1]
0x2E [0]
0x2F [7]
0x2F [3]
0x2F [2]
0x2F [1]
0x2F [0]
0x32 [5]
1
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x32 [4]
0x32 [3]
0x32 [2]
0x33 [7]
0x33 [6]
0x33 [5]
0x33 [4]
0x33 [3]
0
0
0
0
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x33 [2]
0x33 [1]
0x33 [0]
0x34 [7]
0x34 [6]
0x34 [5]
0x34 [4]
0x34 [3]
1
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x34 [2]
0x34 [1]
0x34 [0]
0x35 [2]
0x35 [1]
0x35 [0]
0x36 [7]
0x36 [3]
1
0
1
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x36 [2]
0x36 [1]
0x36 [0]
0x39 [5]
0x39 [4]
0x39 [3]
0x39 [2]
0x3A [7]
0
0
0
0
0
0
0
0
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Table 6. EEPROM Register Map - Single Device With SAS Values (continued)
EEPROM Address Byte
Description
1E
SMBus Register
Value
5F
Description
1F
SMBus Register
Value
5A
Description
20
SMBus Register
Value
80
Description
21
SMBus Register
Value
05
Description
22
SMBus Register
Value
F5
Description
23
SMBus Register
Value
A8
Description
24
SMBus Register
Value
00
Description
25
SMBus Register
Value
00
Description
26
SMBus Register
Value
54
Description
27
SMBus Register
Value
54
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x3A [6]
0x3A [5]
0x3A [4]
0x3A [3]
0x3A [2]
0x3A [1]
0x3A [0]
0x3B [7]
0
1
0
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x3B [6]
0x3B [5]
0x3B [4]
0x3B [3]
0x3B [2]
0x3B [1]
0x3B [0]
0x3C [2]
0
1
0
1
1
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x3C [1]
0x3C [0]
0x3D [7]
0x3D [3]
0x3D [2]
0x3D [1]
0x3D [0]
0x40 [5]
1
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x40 [4]
0x40 [3]
0x40 [2]
0x41 [7]
0x41 [6]
0x41 [5]
0x41 [4]
0x41 [3]
0
0
0
0
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x41 [2]
0x41 [1]
0x41 [0]
0x42 [7]
0x42 [6]
0x42 [5]
0x42 [4]
0x42 [3]
1
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x42 [2]
0x42 [1]
0x42 [0]
0x43 [2]
0x43 [1]
0x43 [0]
0x44 [7]
0x44 [3]
1
0
1
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x44 [2]
0x44 [1]
0x44 [0]
0x47 [3]
0x47 [2]
0x47 [2]
0x47 [0]
0x48 [7]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x48 [6]
0x4C [7]
0x4C [6]
0x4C [5]
0x4C [4]
0x4C [3]
0x4C [0]
0x59 [0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5A [7]
0x5A [6]
0x5A [5]
0x5A [4]
0x5A [3]
0x5A [2]
0x5A [1]
0x5A [0]
0
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5B [7]
0x5B [6]
0x5B [5]
0x5B [4]
0x5B [3]
0x5B [2]
0x5B [1]
0x5B [0]
0
1
0
1
0
1
0
0
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Table 7. Example of EEPROM For Four Devices Using Two Address Maps
EEPROM ADDRESS
22
EEPROM DATA
COMMENTS
DECIMAL
HEX
0
00
0x43
1
01
0x00
2
02
0x08
EEPROM Burst Size
3
03
0x00
CRC not used
4
04
0x0B
Device 0 Address Location
5
05
0x00
CRC not used
6
06
0x0B
Device 1 Address Location
7
07
0x00
CRC not used
8
08
0x30
Device 2 Address Location
9
09
0x00
CRC not used
10
0A
0x30
Device 3 Address Location
11
0B
0x00
Begin Device 0, 1 - Address Offset 3
12
0C
0x00
13
0D
0x04
14
0E
0x07
15
0F
0x00
16
10
0x03
17
11
0xED
18
12
0x00
19
13
0x00
20
14
0xFE
EQ CHB = 03
21
15
0xD0
VOD_DB CHB = 0 (0dB)
22
16
0x00
23
17
0x2F
24
18
0xAD
25
19
0x40
26
1A
0x02
27
1B
0xFB
VOD CHA = 1.4 V
28
1C
0xD4
VOD CHA = 1.4 V
29
1D
0x00
Signal Detect Status Threshold Control
30
1E
0x00
Signal Detect status Threshold Control
31
1F
0x5F
32
20
0x7A
33
21
0x80
34
22
0x05
35
23
0xF5
36
24
0xA8
37
25
0x00
38
26
0x5F
39
27
0x5A
40
28
0x80
41
29
0x05
42
2A
0xF5
43
2B
0xA8
44
2C
0x00
45
2D
0x00
CRC_EN = 0, Address Map = 1, > 256 bytes = 0, Device Count[3:0] = 3
EQ CHA = 03
VOD_DB CHA = 0 (0dB)
VOD CHB = 1.4 V
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Table 7. Example of EEPROM For Four Devices Using Two Address Maps (continued)
EEPROM ADDRESS
EEPROM DATA
COMMENTS
DECIMAL
HEX
46
2E
0x54
47
2F
0x54
End Device 0, 1 - Address Offset 39
48
30
0x00
Begin Device 2, 3 - Address Offset 3
49
31
0x00
50
32
0x04
51
33
0x07
52
34
0x00
53
35
0x01
54
36
0xED
55
37
0x00
56
38
0x00
57
39
0xFE
EQ CHB = 03
58
3A
0xD0
VOD_DB CHB1 = 0 (0dB)
EQ CHA = 01
VOD_DB CHA = 0 (0dB)
59
3B
0x00
60
3C
0x2F
61
3D
0xAD
62
3E
0x40
63
3F
0x02
64
40
0xFB
VOD CHA = 1.4 V
65
41
0xD4
VOD CHA = 1.4 V
66
42
0x00
Signal Detect status Threshold Control
67
43
0x00
Signal Detect status Threshold Control
68
44
0x5F
69
45
0x7A
70
46
0x80
71
47
0x05
72
48
0xF5
73
49
0xA8
74
4A
0x00
75
4B
0x5F
76
4C
0x5A
77
4D
0x80
78
4E
0x05
79
4F
0xF5
80
50
0xA8
81
51
0x00
82
52
0x00
83
53
0x54
84
54
0x54
VOD CHB = 1.4 V
End Device 2, 3 - Address Offset 39
Note: CRC_EN = 0, Address Map = 1, > 256 byte = 0, Device Count[3:0] = 3. Multiple devices can point to the
same address map. Maximum EEPROM size is 8 kbits (1024 x 8-bits). EEPROM must support 1 MHz operation.
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8.6 Register Maps
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. Tie ENSMB = 1
kΩ to VDD (2.5 V mode) or VIN (3.3 V mode) to enable SMBus slave mode and allow access to the configuration
registers.
The DS125BR111 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address
inputs. The AD[3:0] Pins have internal pull-down. Based on the SMBus 2.0 specification, the DS125BR111 has a
7-bit slave address. The LSB is set to 0'b (for a WRITE). When AD[3:0] pins are left floating or pulled low,
AD[3:0] = 0000'b, the device default address byte is 0xB0.The device supports up to 16 address byte, which can
be set with the AD[3:0] inputs. Below are the 16 addresses. Use the address listed in the Slave Address Byte
column to address.
Table 8. Device Slave Address Bytes
AD[3:0] SETTINGS
FULL SLAVE ADDRESS BYTE (HEX)
7-BIT SLAVE ADDRESS (HEX)
0000
B0
58
0001
B2
59
0010
B4
5A
0011
B6
5B
0100
B8
5C
0101
BA
5D
0110
BC
5E
0111
BE
5F
1000
C0
60
1001
C2
61
1010
C4
62
1011
C6
63
1100
C8
64
1101
CA
65
1110
CC
66
1111
CE
67
The SDA, SCL Pins are 3.3 V tolerant, but are not 5 V tolerant. External pull-up resistor is required on the SDA
line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may
also require an external pull-up resistor and it depends on the Host that drives the bus.
8.6.1 Transfer Of Data Via The SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus transfers to the IDLE state.
8.6.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read
Only), default value and function information.
8.6.3 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
24
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3.
4.
5.
6.
7.
The
The
The
The
The
SNLS430C – OCTOBER 2012 – REVISED AUGUST 2014
Host drives the 8-bit Register Address.
Device drives an ACK bit (“0”).
Host drive the 8-bit data byte.
Device drives an ACK bit (“0”).
Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
8.6.4 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1” indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
8.6.5 SMBus Register Information
Table 9. SMBus Register Map
ADDRESS
0x00
0x01
0x02
REGISTER
NAME
Device ID
Control 1
Control 2
BITS
FIELD
TYPE
DEFAULT
EEPROM
REG BIT
0x00
DESCRIPTION
7
Reserved
R/W
6:3
I2C Address [3:0]
R
[6:3] SMBus strap observation
2
EEPROM reading
done
R
1 = EEPROM Done Loading
0 = EEPROM Loading
1:0
Reserved
RWSC
Set bits to 0
7:2
Reserved
R/W
1:0
ENABLE A/B
7
Override PWDN
6
PWDN Pin value
5:4
Reserved
Yes
Set bits to 0
3
PWDN Inputs
Yes
Set bit to 0
2
PWDN Oscillator
Yes
Set bit to 0
1
Reserved
0
Override ENABLE
0x00
Set bit to 0
Yes
Set bits to 0
[1]: Disable Channel B (1); Normal
Operation (0)
[0]: Disable Channel A (1); Normal
Operation (0)
Note: Must set ENABLE override in Reg
0x02[0]
R/W
0x00
[1]: Override PWDN (1); PWDN pin
control (0)
Override value for PWDN pin
[1]: PWDN - Low Power (1); Normal
Operation (0)
Note: Must set PWDN override in Reg
0x02[7]
Set bit to 0
Yes
1 = Enables Reg 0x01[1:0]
0 = Normal Operation
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Table 9. SMBus Register Map (continued)
ADDRESS
REGISTER
NAME
BITS
FIELD
TYPE
DEFAULT
EEPROM
REG BIT
0x04
Reserved
7:0
Reserved
R/W
0x00
0x05
Reserved
7:0
Reserved
R/W
0x00
Reserved
0x06
SMBus
Control
7:5
Reserved
R/W
0x10
Set bits to 0
4
Reserved
3
Register Mode
Enable
1 = Enable SMBus Slave Mode
Register Control
0 = Disable Register Control
Note: With register control "Enabled"
register updates take immediate
effect on high speed data path. When
"Disabled", SMBus registers are still
R/W, but changes will not be sent to
the high speed controls until this
register is "Enabled".
2:0
Reserved
Set bits to 0
7
Reserved
R/W
6
Reset Regs
RWSC
Self clearing reset for registers.
Writing a [1] will return register settings
to default values.
5
Reset SMBus
Master
RWSC
Self clearing reset to SMBus master
state machine
4:0
Reserved
R/W
Set bits to 0001'b
7
Reserved
R/W
6
Override SD_TH
Threshold
Yes
1 = Override by Channel - see Reg 0x12
and 0x19
0 = SD_TH pin control
5:4
Reserved
Yes
Set bits to 0
3
Override RXDET
Yes
1 = Override by Channel - see Reg
0x0E and 0x15
0 = RXDET pin control
2:0
Reserved
Yes
Set bits to 0
Signal Detect 7:2
Status
1
Reserved
R
Internal Idle B
R
0x07
0x08
0x0A
Digital Reset
and Control
Pin Override
0
Internal Idle A
Yes
DESCRIPTION
Yes
0x01
Set bits to 0
Set bit to 1
Set bit to 0
0x00
Set bit to 0
0x00
1 = LOS (No Signal Present)
0 = Signal present
Note: RES Pin = Float for these bits to
function.
0x0B
Reserved
7:0
Reserved
R/W
0x70
0x0C
Reserved
7:0
Reserved
R/W
0x00
0x0E
CH A
RXDET
Control
7:5
Reserved
R/W
0x00
4
Reserved
Yes
Set bit to 0
3:2
RXDET
Yes
CHA RXDET register control
00'b = Input is high-z impedance
01'b = Auto RX-Detect, outputs test
every 12 ms for 600 ms (50 times) then
stops; termination is high-z until
detection; once detected input
termination is 50 Ω
10'b = Auto RX-Detect, outputs test
every 12 ms until detection occurs;
termination is high-z until detection;
once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: override RXDET pin in 0x08[3].
Note: Can only be used with the
register write sequence described in
.PCIe Applications
1:0
Reserved
26
Yes
Set bits to 0
Set bits to 0
Set bits to 0
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Table 9. SMBus Register Map (continued)
ADDRESS
REGISTER
NAME
BITS
FIELD
TYPE
DEFAULT
EEPROM
REG BIT
DESCRIPTION
0x0F
CH A
EQ Control
7:0
BOOST [7:0]
R/W
0x2F
Yes
EQ Control - total of 4 levels
See Table 4
0x10
CH A
Control
7
Select Short Circuit
Protection
R/W
0xED
Yes
1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
6
Reserved
Yes
Set bit to 0
5:3
Reserved
Yes
Set bits to 0
2:0
Reserved
Yes
Set bits to 101'b
7
Reserved
6:5
Reserved
4:3
Reserved
2:0
VOD_DB Control
[2:0]
0x11
0x12
0x13
CH A
VOD_DB
Control
CH A
7
SD Threshold
6:4
Reserved
R
R/W
Reserved
R/W
CH B
Set bits to 0
0x00
Yes
OUTA VOD_DB Control (010'b Default).
Based on system interoperability
testing it is recommended to set
these bits to 000'b for SAS, PCIe, and
other non-limiting applications.
000'b = 0 dB (Recommended)
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively
lowers the output VOD gain by a factor
of the corresponding amount of dB
reduction.
Yes
Set bit to 0
Reserved
Set bits to 0
3:2
Signal Detect Status
Tassert
Yes
Assert Thresholds (1010 pattern 12
Gbps)
Use only if register 0x08 [6] = 1
00'b = 50 mV (Default)
01'b = 40 mV
10'b = 75 mV
11'b = 58 mV
Note: Override the SD_TH pin using
0x08[6].
Note: This threshold adjustment is for
SD status indication only.
1:0
Signal Detect Status
Tde-assert
Yes
De-assert Thresholds (1010 pattern 12
Gbps)
Use only if register 0x08 [6] = 1
00'b = 37 mV (Default)
01'b = 22 mV
10'b = 55 mV
11'b = 45 mV
Note: Override the SD_TH pin using
0x08[6].
Note: This threshold adjustment is for
SD status indication only.
7:2
Reserved
R/W
1:0
0x14
0x82
0x00
Set bits to 0
0x00
Set bits to 0
R
7:3
Reserved
2
Signal Detect Reset
R/W
1 = Override Signal Detect, hold "Off"
1
Signal Detect Preset
1 = Override Signal Detect, hold "On"
0
Reserved
Set bit to 0
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Table 9. SMBus Register Map (continued)
ADDRESS
0x15
REGISTER
NAME
CH B
RXDET
Control
BITS
FIELD
TYPE
R/W
DEFAULT
EEPROM
REG BIT
0x00
DESCRIPTION
7:5
Reserved
4
Reserved
Yes
Set bits to 0
Set bit to 0
3:2
RXDET
Yes
CHB RXDET register control
00'b = Input is high-z impedance
01'b = Auto RX-Detect, outputs test
every 12 ms for 600 ms (50 times) then
stops; termination is high-z until
detection; once detected input
termination is 50 Ω
10'b = Auto RX-Detect, outputs test
every 12 ms until detection occurs;
termination is high-z until detection;
once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: override RXDET pin in 0x08[3].
Note: Can only be used with the
register write sequence described in
PCIe Applications .
1:0
Reserved
Set bits to 0
0x16
CH B
EQ Control
7:0
BOOST [7:0]
R/W
0x2F
Yes
EQ Control - total of 4 levels
See Table 4
0x17
CH B
RATE
Control
7
Select Short Circuit
Protection
R/W
0xED
Yes
1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
6
Reserved
Set bit to 0
5:3
Reserved
Set bits to 0
2:0
Reserved
Set bits to 101'b
7
Reserved
6:5
Reserved
4:3
Reserved
2:0
VOD_DB Control
[2:0]
0x18
28
CH B
VOD_DB
Control
R
0x82
R/W
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Set bits to 0
Yes
OUTB VOD_DB Control (010'b Default).
Based on system interoperability
testing it is recommended to set
these bits to 000'b for SAS, PCIe, and
other non-limiting applications.
000'b = 0 dB (Recommended)
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively
lowers the output VOD gain by a factor
of the corresponding amount of dB
reduction.
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Table 9. SMBus Register Map (continued)
ADDRESS
0x19
REGISTER
NAME
BITS
CH B
7
SD Threshold
6:4
0x1C
FIELD
TYPE
Reserved
R/W
DEFAULT
EEPROM
REG BIT
0x00
DESCRIPTION
Yes
Set bits to 0
Reserved
3:2
Signal Detect Status
Tassert
Yes
Assert Thresholds (1010 pattern 12
Gbps)
Use only if register 0x08 [6] = 1
00'b = 50 mV (Default)
01'b = 40 mV
10'b = 75 mV
11'b = 58 mV
Note: Override the SD_TH pin using
0x08[6].
Note: This threshold adjustment is for
SD status indication only.
1:0
Signal Detect Status
Tde-assert
Yes
De-assert Thresholds (1010 pattern 12
Gbps)
Use only if register 0x08 [6] = 1
00'b = 37 mV (Default)
01'b = 22 mV
10'b = 55 mV
11'b = 45 mV
Note: Override the SD_TH pin using
0x08[6].
Note: This threshold adjustment is for
SD status indication only.
7:6
Reserved
R/W
0x00
5:2
Set bits to 0
Yes
1:0
0x1D
7:0
Reserved
R/W
0x2F
Yes
0x1E
7:0
Reserved
R/W
0xAD
Yes
0x1F
7:3
Reserved
R/W
0x02
Reserved
R/W
0x00
Reserved
R/W
0x00
2:0
0x20
7
Yes
Yes
6:4
3:0
0x23
7:6
Yes
5:2
Yes
1:0
0x24
0x25
0x26
CH A VOD
7:0
Reserved
R/W
0x2F
Yes
7:5
Reserved
R/W
0xAD
Yes
4:2
VOD CHA Control
VOD Control CHA: VOD / VID Ratio
000'b = 0.65
001'b = 0.70
010'b = 0.78
011'b = 0.83
100'b = 0.88
101'b = 0.91 (Default)
110'b = 1.00 (Recommended for
SAS/SATA/PCIe)
111'b = 1.05 (Recommended for
SAS/SATA/PCIe)
1:0
Reserved
Set bits to 01'b
7:6
Reserved
4:3
R
Set bits to 101'b
0x02
R/W
2:0
Yes
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Table 9. SMBus Register Map (continued)
ADDRESS
REGISTER
NAME
0x27
BITS
7
FIELD
TYPE
Reserved
R/W
DEFAULT
EEPROM
REG BIT
0x00
DESCRIPTION
Yes
6:4
3:0
0x28
Signal Detect 7
Control
6
0x2B
Yes
Reserved
R/W
0x00
Set bit to 0
Override Fast IDLE
Yes
Override Fast IDLE
1 = Use value in 0x28[3:2]
0 = Based on MODE pin
5:4
High IDLE
Yes
Enable higher SD Threshold range
[1]: CH A
[0]: CH B
3:2
Fast IDLE
Yes
Enable Fast SD response
[1]: CH A
[0]: CH B
1:0
Reduced SD Gain
Yes
Enable reduced SD Gain
[1]: CH A
[0]: CH B
7:6
Reserved
R/W
0x00
5:2
Yes
1:0
0x2C
0x2D
0x2E
CH B VOD
7:0
Reserved
R/W
0x2F
Yes
7:5
Reserved
R/W
0xAD
Yes
4:2
VOD CHB Control
VOD Control CHB: VOD / VID Ratio
000'b = 0.65
001'b = 0.70
010'b = 0.78
011'b = 0.83
100'b = 0.88
101'b = 0.91 (Default)
110'b = 1.00 (Recommended for
SAS/SATA/PCIe)
111'b = 1.05 (Recommended for
SAS/SATA/PCIe)
1:0
Reserved
Set bits to 01'b
7:5
Reserved
4:3
R
0x02
R/W
2:0
0x2F
7
Set bits to 101'b
Yes
Reserved
R/W
0x00
Yes
6:4
3:0
0x32
7:6
Yes
Reserved
R/W
0x00
5:2
Yes
1:0
0x33
7:0
Reserved
R/W
0x2F
Yes
0x34
7:0
Reserved
R/W
0xAD
Yes
0x35
7:5
Reserved
R
0x02
4:3
R/W
2:0
0x36
7
Yes
Reserved
R/W
0x00
Yes
6:4
3:0
30
Yes
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Table 9. SMBus Register Map (continued)
ADDRESS
REGISTER
NAME
0x39
BITS
7:6
FIELD
Reserved
TYPE
R/W
DEFAULT
EEPROM
REG BIT
DESCRIPTION
0x00
5:2
Yes
1:0
0x3A
7:0
Reserved
R/W
0x2F
Yes
0x3B
7:0
Reserved
R/W
0xAD
Yes
0x3C
7:5
Reserved
R
0x02
4:3
R/W
2:0
0x3D
7
Yes
Reserved
R/W
0x00
Reserved
R/W
0x00
Yes
6:4
3:0
0x40
7:6
Yes
5:2
Yes
1:0
0x41
7:0
Reserved
R/W
0x2F
Yes
0x42
7:0
Reserved
R/W
0xAD
Yes
0x43
7:5
Reserved
R
0x02
4:3
R/W
2:0
0x44
7
Yes
Reserved
R/W
0x00
Yes
Reserved
R/W
0x00
Reserved
R/W
0x05
Yes
Reserved
R/W
0x00
Yes
7:5
Version
R
0x97
4:0
Device ID
7:1
Reserved
R/W
0x00
6:4
3:0
0x47
7:4
Yes
3:0
0x48
7:6
Yes
5:0
0x4C
7:3
2:1
0
0x51
Device
Information
0x59
Yes
100'b
1 0111'b
0
Yes
0x5A
7:0
Reserved
R/W
0x54
Yes
0x5B
7:0
Reserved
R/W
0x54
Yes
Legend:
RWSC:
Read / Write / Self Clearing on Read
R/W:
Read / Write
R:
Read Only
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9 Application and Implementation
9.1 Application Information
9.1.1 Signal Integrity
In SAS and PCIe applications, specifications require Rx-Tx link training to establish and optimize signal
conditioning settings for data rates up to 12 Gbps. In link training, the Rx partner requests a series of FIR
coefficients from the TX partner at speed. This polling sequence is designed to pre-condition the signal path with
an optimized link between the endpoints. Link training occurs at the following data-rates:
Table 10. Link Training Data-Rates
PROTOCOL
MAXIMUM DATA-RATE (Gbps)
ALTERNATIVE DATA RATES (Gbps)
SAS
12.0
6.0, 3.0
PCIe
8.0
5.0, 2.5
The DS125BR111 works to extend the reach possible by using active linear equalization to the channel, boosting
attenuated signals so that they can be more easily recovered at the Rx. The repeater outputs are specially
designed to be transparent to TX FIR signaling in order to pass information critical for optimal link training to the
Rx. Suggested settings for the A-channels and B-channels in a SAS or PCIe environment are given in the table
below. Further adjustments to EQ and VOD settings may optimize signal margin on the link for different system
applications:
Table 11. Pin Mode Device Settings
CHANNEL SETTINGS
PIN MODE
EQx
Level 4
VOD_SEL
Level 7 (1)
VODx_DB
0 dB (0)
Table 12. SMBus Mode Device Settings
CHANNEL SETTINGS
SMBus REGISTER VALUE
EQ
0x03
VOD
110'b or 111'b
VODx_DB
000'b
9.1.2 RX-Detect in SAS/SATA Applications
Unlike PCIe systems, SAS/SATA systems use a low speed Out-Of-Band or OOB communications sequence to
detect and communicate between SAS Controllers/Expanders and target drives. This communication eliminates
the need to detect for endpoints like PCIe. For SAS systems, it is recommended to tie the RXDET pin high. This
will ensure any OOB sequences sent from the Controller/Expander will reach the target drive without any
additional latency due to the termination detection sequence defined by PCIe.
9.1.3 PCIe Applications
9.1.3.1 RXDET When Using SMBus Modes
PCIe systems use an input termination polling and detection sequence to begin the PCIe bus configuration
process. When using PIN MODE configuration the RXDET pin should be left Floating to allow for this process to
begin upon power-up of the DS125BR111 device. If SMBus Slave MODE configuration is required, the SMBus
register write sequence in Table 13 should be initiated upon power-up of the DS125BR111.
• Pin Settings for DS125BR111 in a PCIe Application (SMBus Slave Mode)
– ENSMB = H
– RXDET = Float
– PWDN = System control (Hold HIGH until Register Write process is completed)
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Table 13. PCIe RX-Detect Programming Sequence
STEP
SMBus
REGISTER
ADDRESS
REGISTER DATA (Hex)
1
0x08
0x08
2
0x0E
0x04 or 0x08
COMMENTS
Give RXDET control to SMBus Registers
Channel A:
0x04: Auto RX-Detect, outputs test every 12 ms for 600 ms then
stops; termination is Hi-Z until RX detection; once detected input
termination is 50 Ω
0x08: Auto RX-Detect, outputs test every 12 ms until detection
occurs; termination is Hi-Z until RX detection; once detected input
termination is 50 Ω
3
0x15
0x04 or 0x08
Channel B:
0x04: Auto RX-Detect, outputs test every 12 ms for 600 ms then
stops; termination is Hi-Z until RX detection; once detected input
termination is 50 Ω
0x08: Auto RX-Detect, outputs test every 12 ms until detection
occurs; termination is Hi-Z until RX detection; once detected input
termination is 50 Ω
4
•
0x06
0x18
Enable SMBus register control.
Register updates in Steps 1-3 are applied to high speed channels.
Pin Settings for DS125BR111 in a PCIe Application (SMBus Master Mode - EEPROM Configuration)
– ENSMB = Float
– RXDET = Float
– PWDN = System control (Hold PWDN HIGH until DONE = 0, EEPROM Write process is completed)
The highlighted bits for RXDET in the Table 6 show the equivalent RXDET control locations to the SMBus
Register write sequence shown in Table 13.
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9.2 Typical Application
SAS-3 specifications have fully specified Rx-Tx training as a means to establish and optimize signal conditioning
settings at the 12.0 Gbps data-rate. The DS125BR111 works to extend the reach possible by adding active linear
equalization to the channel, boosting attenuated signals so that they can be more easily recovered at the SAS-3
Rx. The outputs are specially designed to be transparent to TX FIR signaling passing this information critical for
optimal link training to the SAS-3 Rx. The typical device settings used in most SAS-3 environments are EQ =
Level 4, VOD_DB = 0 and VOD_SEL = 1 in Pin mode or EQ = 0x03, VOD = 111'b, and VOD_DB = 000'b in
SMBus mode.
The maximum channel attenuation for a single DS125BR111 in a SAS-3 application utilizing link training is -34
dB @ 6 GHz. Other system variables such as crosstalk and channel topology can have an impact on the link
extension possible using the DS125BR111.
DS125BR111
INA+
INA-
OUTA+
OUTA-
SAS Expander
INB+
INB-
SAS/SATA
HDD/SSD Receptacle
OUTB+
OUTBVDD
AD0/EQA0
Address
straps (pull-up
or pull-down)
1 N
AD1/EQA1
ENSMB
AD2/EQB1
SMBus
Slave
Mode(1)
3.3V
AD3/EQB0
4.7 N
4.7 N
RES
SD_TH
VDD
SDA/VODA_DB(2)
SCL/VODB_DB(2)
To system
SMBus
READEN/VOD_SEL
VIN
2.5 V
Mode(4)
VDD_SEL
DONE/RXDET
PWDN(3)
2.5V
10F
(1x)
(1)
(2)
(3)
(4)
(5)
1F
(1x)
0.1F
(2x)
Normal
operation
VDD
(DAP) GND(5)
Schematic requires different connections for SMBus Master Mode and Pin Mode
SMBus signals need to be pulled up elsewhere in the system
PWDN pin can alternatively be driven by a control device (i.e. FPGA)
Schematic requires different connections for 3.3 V mode
A minimum of 4 vias are recommended for proper thermal and electrical performance
Figure 9. DS125BR111 Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
As with any high speed design, there are many factors which influence the overall performance, this section lists
some critical areas for consideration and study.
• Limit the maximum attenuation to -34 dB @ 6 GHz for the entire channel.
• Utilize 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length
• Use Reference plane vias to ensure a low inductance path for the return current.
9.2.2 Detailed Design Procedure
The DS125BR111 is designed to be placed almost anywhere within the channel, maximum channel extension
requires the DS125BR111 be placed with attenuation of at least 10 dB on its inputs. The device settings used in
a SAS-3 environment are EQ = Level 4, VOD_SEL = 1, and VOD_DB = 0 in Pin mode or EQ = 0x03, VOD =
110'b or 111'b, and VOD_DB = 000'b in SMBus mode. This setting has proven to give the best overall SAS-3
extension for all configurations tested.
9.2.3 Application Curves
DS125BR111 settings: EQ = 0x01, VOD =
110'b, VOD_DB = 000'b
Figure 10. TLine = 5 Inch 5–Mil FR4 Trace, 12 Gbps
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10 Power Supply Recommendations
Two approaches are recommended to ensure that the DS125BR111 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) Pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be
connected to each VDD Pin such that the capacitor is placed as close as possible to the DS125BR111. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These
capacitors can be either tantalum or an ultra-low ESR ceramic.
The DS125BR111 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V
mode operation, the VIN Pin = 3.3 V is used to supply power to the device. The internal regulator will provide the
2.5 V to the VDD Pins of the device and a 0.1 µF cap is needed at each of the 2 VDD Pins for power supply decoupling (total capacitance should equal 0.2 µF). The VDD_SEL Pin must be tied to GND to enable the internal
regulator. In 2.5 V mode operation, the VIN Pin should be left open and 2.5 V supply must be applied to the 2
VDD Pins to power the device. The VDD_SEL Pin must be left open (no connect) to disable the internal regulator.
3.3 V mode
2.5 V mode
VDD_SEL
Enable
VDD_SEL
open
VIN
open
Disable
3.3 V
1 µF
VIN
10 µF
Internal
voltage
regulator
2.5 V
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
Place 0.1 µF capacitors close to VDD Pins
0.1 µF
1 µF
2.5 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
10 µF
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
Place 0.1 µF capacitors close to VDD Pins
Total capacitance should be 7 0.2 µF
Figure 11. 3.3 V or 2.5 V Supply Connection Diagram
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11 Layout
11.1 Layout Guidelines
The DS125BR111 pinout promotes makes for easy high speed routing and layout. To optimize DS125BR111
performance refer to the following guidelines;
1. Differential pairs going into or out of the DS125BR111 should have adequate pair - pair spacing to minimize
crosstalk. Keep a 5x spacing ratio as shown on the Blue pairs in the layout example.
2. Place local VIN and VDD capacitors as close as possible to the device supply pins to ensure a low inductance
layout. Often the best location is directly under the DS125BR111 pins.
3. Use return current via connections to link reference planes locally. This ensures a low inductance return
current path when the differential signal changes layers.
4. Open up the supply planes around differential vias to better match the trace impedance.
5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance.
6. Use 0201 body size coupling capacitors whenever possible, 0402 body size capacitors can also be used if
they are placed closer to the Rx on the channel.
11.2 Layout Example
In most cases DS125BR111 layouts will fit neatly into a single or 1-lane application. The example layout shows
how to "flip" one of the DS125BR111 channels to produce a 2-channel unidirectional layout.
5
2
1
6
2
25
5
4
3
2
1
2
2
1
1
5
5
5
1
2
23
8
7
2
24
7
9
1
1
GND
BOTTOM OF PKG
22
10
21
11
20
12
19
VDD
7
5
5
5
13 14 15 16 17 18
7
7
VIN
Figure 12. DS125BR111 Example Unidirectional Layout
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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31-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS125BR111RTWR
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
2B111A0
DS125BR111RTWT
ACTIVE
WQFN
RTW
24
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
2B111A0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Aug-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS125BR111RTWR
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
DS125BR111RTWT
WQFN
RTW
24
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS125BR111RTWR
WQFN
RTW
24
1000
213.0
191.0
55.0
DS125BR111RTWT
WQFN
RTW
24
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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