DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch Check for Samples: DS10CP154A FEATURES DESCRIPTION • The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch optimized for high-speed signal routing and switching over FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. The switch configuration can be accomplished via external pins or the System Management Bus (SMBus) interface. In addition, the SMBus circuitry enables the loss of signal (LOS) monitors that can inform a system of the presence of an open inputs condition (e.g. disconnected cable). 1 • • • • • • DC - 1.5 Gbps Low Jitter, Low Skew, Low Power Operation Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture Wide Input Common Mode Range Enables DC Coupled Interface to CML or LVPECL Drivers LOS Circuitry Detects Open Inputs Fault Condition On-chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space 8 kV ESD on LVDS I/O Pins Protects Adjoining Components Small 6 mm x 6 mm WQFN-40 Space Saving Package APPLICATIONS • • • High-speed Channel Select Applications Clock and Data Buffering and Muxing SD / HD SDI Routers Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. Typical Application INPUT CARD SD / HD Adaptive Equalizer SD / HD Adaptive Equalizer OUTPUT CARD SD / HD Reclocker + Cable Driver BACKPLANES DS10CP154 4x4 LVDS Crosspoint Switch DS10CP154 4x4 LVDS Crosspoint Switch SD / HD Reclocker + Cable Driver SD / HD Adaptive Equalizer SD / HD Reclocker + Cable Driver SD / HD Adaptive Equalizer SD / HD Reclocker + Cable Driver DS10CP154 4x4 LVDS Crosspoint Switch CROSSPOINT CARD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com Block Diagram S00 ± S31 8 IN0+ OUT0+ IN0- OUT0+ IN1+ OUT1+ IN1- OUT1- 4X4 IN2+ OUT2+ IN2- OUT2- IN3+ OUT3+ IN3- OUT3- System Management Bus PWDN ADDRn SCL EN_smb SDA 4 NC NC PWDN S00/SCL S01/SDA S10/ADDR0 S11/ADDR1 S20/ADDR2 S21/ADDR3 NC 40 39 38 37 36 35 34 33 32 31 Connection Diagram IN0+ 1 30 VDD IN0- 2 29 OUT0+ VDD 3 28 OUT0- IN1+ 4 27 OUT1+ DAP 26 OUT1- (GND) 25 VDD IN1- 5 IN2+ 6 16 17 18 19 20 EN_smb NC NC NC OUT3- 15 21 VDD 10 GND IN3- 14 OUT3+ S31 22 13 9 12 OUT2- IN3+ NC OUT2+ 23 S30 24 8 11 7 NC IN2VDD Figure 1. WQFN Package See Package Number RTA0040A 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name IN0+, IN0- , IN1+, IN1-, IN2+, IN2-, IN3+, IN3OUT0+, OUT0-, OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3- Pin Number I/O, Type Pin Description 1, 2, 4, 5, 6, 7, 9, 10 I, LVDS Inverting and non-inverting high speed LVDS input pins. 29, 28, 27, 26, 24, 23, 22, 21 O, LVDS Inverting and non-inverting high speed LVDS output pins. EN_smb 17 I, LVCMOS System Management Bus (SMBus) mode enable pin. The pin has an internal 20k pull down. When the pin is set to a [1], the device is in the SMBus mode. All SMBus registers are reset when the pin is toggled. S00/SCL, S01/SDA 37, 36 I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT0. In the SMBus mode, when the EN_smb = [1], these pins are the SMBus clock input and data I/O pins respectively. S10/ADDR0, S11/ADDR1 35, 34 I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT1. In the SMBus mode, when the EN_smb = [1], these pins are the User-Set SMBus Slave Address inputs. S20/ADDR2, S21/ADDR3 33, 32 I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT2. In the SMBus mode, when the EN_smb = [1], these pins are the User-Set SMBus Slave Address inputs. 13, 14 I, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT3. In the SMBus mode, when the EN_smb = [1], these pins are non-functional and should be tied to either logic [0] or [1]. 38 I, LVCMOS For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0], the device is in the power down mode. The SMBus circuitry can still be accessed provided the EN_smb pin is set to a [1]. In the SMBus mode, the device is powered up by either setting the PWDN pin to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The device will be powered down by setting the PWDN pin to [0] AND by writing a [0] to the Control Register D[7] bit ( SoftPWDN). S30, S31 PWDN NC 11, 12, 18, 19, 20, 31, 39, 40 No connect pins. May be left floating. VDD 3, 8, 15,25, 30 Power Power supply pins. GND 16, DAP Power Ground pin and pad (DAP - die attach pad). Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 3 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage LVCMOS Input Voltage −0.3V to (VCC + 0.3V) LVCMOS Output Voltage −0.3V to (VCC + 0.3V) −0.3V to +4V LVDS Input Voltage Differential Input Voltage |VID| 1.0V −0.3V to (VCC + 0.3V) LVDS Output Voltage LVDS Differential Output Voltage 0V to 1.0V LVDS Output Short Circuit Current Duration 5 ms Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) Maximum Package Power Dissipation at 25°C RTA0040A Package Package Thermal Resistance θJA +26.9°C/W θJC +3.8°C/W ESD Susceptibility +260°C 4.65W Derate RTA0040A Package 37.2 mW/°C above +25°C HBM (3) ≥8 kV MM (4) ≥250V CDM (5) (1) (2) (3) (4) (5) ≥1250V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Min Typ Max Units 3.0 3.3 3.6 V 1.0 V +85 °C 3.6 V 0 −40 Operating Free Air Temperature (TA) +25 SMBus (SDA, SCL) Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ Max Units VDD V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current VIN = 3.6V VCC = 3.6V IIL Low Level Input Current VIN = GND, VCC = 3.6V VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V VOL Low Level Output Voltage IOL= 4 mA (1) (2) (3) 4 2.0 GND EN_smb pin SDA pin 40 0.8 V 0 ±10 μA 175 250 μA 0 ±10 μA −0.9 −1.5 V 0.4 V The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ Max Units 1 V 0 +100 mV LVDS INPUT DC SPECIFICATIONS VID Input Differential Voltage VTH Differential Input High Threshold 0 VTL Differential Input Low Threshold VCMR Common Mode Voltage Range VID = 100 mV IIN Input Current VIN = 3.6V or 0V VCC = 3.6V or 0V CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF RIN Input Termination Resistor Between IN+ and IN- 100 Ω VCM = +0.05V or VCC-0.05V −100 0 0.05 ±1 mV VCC 0.05 V ±10 μA LVDS OUTPUT DC SPECIFICATIONS VOD Differential Output Voltage ΔVOD Change in Magnitude of VOD for Complimentary Output States 250 VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complimentary Output States RL = 100Ω IOS Output Short Circuit Current (4) OUT to GND COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω RL = 100Ω 350 450 mV 35 mV 1.375 V 35 mV -25 -55 mA 7 55 mA -35 1.05 1.2 -35 OUT to VCC SUPPLY CURRENT ICC1 Supply Current PWDN = 0 40 50 mA ICC2 Supply Current PWDN = 1; Broadcast Mode (1:4) 103 125 mA ICC3 Supply Current PWDN = 1; Quad Buffer Mode (4:4) 115 140 mA Typ Max Units 500 675 ps 460 675 ps (4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. AC Electrical Characteristics (1) (2) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions LVDS OUTPUT AC SPECIFICATIONS Min (3) tPLHD Differential Propagation Delay Low to High tPHLD Differential Propagation Delay High to Low tSKD1 Pulse Skew |tPLHD − tPHLD| (4) 40 100 ps tSKD2 Channel to Channel Skew (5) 40 125 ps tSKD3 Part to Part Skew tLHT Rise Time tHLT Fall Time (1) (2) (3) (4) (5) (6) RL = 100Ω (6) RL = 100Ω 50 225 ps 145 350 ps 145 350 ps The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Specification is ensured by characterization and is not tested in production. tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to all outputs). tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 5 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics(1)(2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ Max Units tON Power Up Time Time from PWDN = LH to OUTn active 7 20 μs tOFF Power Down Time Time from PWDN = HL to OUTn inactive 6 25 ns tSEL Select Time Time from Sn = LH or HL to new signal at OUTn 8 12 ns VID = 350 mV VCM = 1.2V Clock (RZ) 135 MHz 1 2.0 ps 311 MHz 0.5 1.2 ps 503 MHz 0.5 1.0 ps 750 MHz 0.5 1.0 ps 270 Mbps 7 30 ps 622 Mbps 12 26 ps 1.06 Gbps 9 24 ps 1.5 Gbps 12 28 ps 270 mbps 0.008 0.036 UIP-P 622 Mbps 0.007 0.043 UIP-P 1.06Gbps 0.008 0.064 UIP-P 1.5 Gbps 0.007 0.072 UIP-P 100 kHz JITTER PERFORMANCE (3) tRJ1 tRJ2 Random Jitter (RMS Value) (7) tRJ3 tRJ4 tDJ1 tDJ2 VID = 350 mV VCM = 1.2V K28.5 (NRZ) Deterministic Jitter (Peak to Peak Value) (8) tDJ3 tDJ4 tTJ1 tTJ2 VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) Total Jitter (Peak to Peak Value) (9) tTJ3 tTJ4 SMBus AC SPECIFICATIONS fSMB SMBus Operating Frequency 10 tBUF Bus free time between Stop and Start Conditions 4.7 μs tHD:SDA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. 4.0 μs tSU:SDA Repeated Start Condition setup time. 4.7 μs tSU:SDO Stop Condition setup time 4.0 μs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 tTIMEOUT Detect clock low timeout 25 tLOW Clock low period 4.7 tHIGH Clock high period 4.0 tPOR Time in which a device must be operational after power-on reset (7) (8) (9) 6 ns 35 ms μs 50 μs 500 ms Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 DC Test Circuits ¼ DS10CP154 Power Supply VOH OUT+ IN+ R D RL Power Supply OUT- IN- VOL AC Test Circuits and Timing Diagrams ¼ DS10CP154 OUT+ IN+ R Signal Generator D IN- RL OUT- FUNCTIONAL DESCRIPTION The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154A operates in two modes: Pin Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1). When in the Pin Mode, the switch is fully configurable with external pins. This is possible with two input select pins per output (e.g. S00 and S01 pins for OUT0). In the Pin Mode, feedback from the LOS (Loss Of Signal) monitor circuitry is not available (there is not an LOS output pin). When in the SMBus Mode, the full switch configuration and SoftPWDN can be programmed via the SMBus interface. In addition, by using the SMBus interface, a user can obtain the feedback from the built-in LOS circuitry which detects an open inputs fault condition. In the SMBus Mode, the S00 and S01 pins become SMBus clock (SCL) input and data (SDA) input pins respectively; the S10, S11, S21 and S21 pins become the User-Set SMBus Slave Address input pins (ADDR0, 1, 2 and 3) while the S30 and S31 pins become non-functional (tieing these two pins to either H or L is recommended if the device will function only in the SMBus mode). In the SMBus Mode, the PWDN pin remains functional. How this pin functions in each mode is detailed in the following sections. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 7 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com DS10CP154A OPERATION IN THE PIN MODE Power Up In the Pin Mode, when the power is applied to the device power suppy pins, the DS10CP154A enters the Power Up mode when the PWDN pin is set to logic H. When in the Power Down mode (PWDN pin is set to logic L), all circuitry is shut down except the minimum required circuitry for the LOS and SMBus Slave operation. Switch Configuration In the Pin Mode, the DS10CP154A operates as a fully pin-configurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins. Switch Configuration Truth Tables Table 1. Input Select Pins Configuration for the Output OUT0 S01 S00 INPUT SELECTED 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 Table 2. Input Select Pins Configuration for the Output OUT1 S11 S10 INPUT SELECTED 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 Table 3. Input Select Pins Configuration for the Output OUT2 S21 S20 INPUT SELECTED 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 Table 4. Input Select Pins Configuration for the Output OUT3 8 S31 S30 INPUT SELECTED 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 DS10CP154A OPERATION IN THE SMBUS MODE The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high (1). Under these conditions, the SCL pin is a clock input while the SDA pin is a serial data input pin. Device Address Based on the SMBus 2.0 specification, the DS10CP154A has a 7-bit slave address. The three most significant bits of the slave address are hard wired inside the DS10CP154A and are “101”. The four least significant bits of the address are assigned to pins ADDR3-ADDR0 and are set by connecting these pins to GND for a low (0) or to VCC for a high (1). The complete slave address is shown in the following table: Table 5. DS10CP154A Slave Address 1 0 1 ADDR3 ADDR2 ADDR1 MSB ADDR0 LSB This slave address configuration allows up to sixteen DS10CP154A devices on a single SMBus bus. Transfer of Data via the SMBus During normal operation the data on SDA must be stable during the time when SCK is high. There are three unique states for the SMBus: START: A HIGH to LOW transition on SDA while SCK is high indicates a message START condition. STOP: A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition. IDLE: If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they are high for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus Transactions A transaction begins with the host placing the DS10CP154A SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify NACK, after this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an ACKnowledge that the byte has been received. Writing to a Register To write a register, the following protocol is used (see SMBus 2.0 specification): 1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2) The Device (Slave) drives an ACK bit (“0”). 3) The Host drives the 8-bit Register Address. 4) The Device drives an ACK bit (“0”). 5) The Host drives the 8-bit data byte. 6) The Device drives an ACK bit “0”. 7) The Host drives a STOP condition. The WRITE transaction is completed, the bus goes Idle and communication with other SMBus devices may now occur. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 9 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com Reading From a Register To read a register, the following protocol is used (see SMBus 2.0 specification): 1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2) The Device (Slave) drives an ACK bit (“0”). 3) The Host drives the 8-bit Register Address. 4) The Device drives an ACK bit (“0”). 5) The Host drives a START condition. 6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 7) The Device drives an ACK bit “0”. 8) The Device drives the 8-bit data value (register contents). 9) The Host drives a NACK bit “1” indicating end of READ transfer. 10) The Host drives a STOP condition. The READ transaction is completed, the bus goes Idle and communication with other SMBus devices may now occur. REGISTER DESCRIPTIONS There are three data registers in the DS10CP154A accessible via the SMBus interface. Table 6. DS10CP154A SMBus Data Registers Address (hex) Name Access Description Switch Configuration R/W Switch Configuration Register 3 Control R/W Powerdown, LOS Enable and Pin Control Register 4 LOS RO Loss Of Signal (LOS) Reporting Register ADDRn 0 4 SCL SDA LOS Register SMBus Interface EN_smb Switch Configuration Register Control Register Switch Configuration Register The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register mapping and associated truth table. Bit 10 Default Bit Name Access Description D[1:0] 00 Input Select 0 R/W Selects which input is routed to the OUT0. D[3:2] 00 Input Select 1 R/W Selects which input is routed to the OUT1. D[5:4] 00 Input Select 2 R/W Selects which input is routed to the OUT2. D[7:6] 00 Input Select 3 R/W Selects which input is routed to the OUT3. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 Table 7. Switch Configuration Register Truth Table D1 D0 Input Routed to the OUT0 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state). Control Register The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control via the SMBus. The following table shows the register mapping. Bit Access Description 1111 PWDNn R/W Writing a [0] to the bit D[n] will power down the output OUTn when either the PWDN pin OR the Control Register bit D[7] (SoftPWDN) is set to a high [1]. D[4] x n/a R/W Undefined. D[5] x n/a R/W Undefined. D[6] 0 EN_LOS R/W Writing a [1] to the bit D[6] will enable the LOS circuitry and receivers on all four inputs. The SmartPWDN circuitry will not disable any of the inputs nor any supporting LOS circuitry depending on the switch configuration. D[7] 0 SoftPWDN R/W Writing a [0] to the bit D[7] will place the device into the power down mode. This pin is ORed together with the PWDN pin. D[3:0] Default Bit Name Table 8. DS10CP154A Power Modes Truth Table PWDN SoftPWDN PWDNn DS25CP104 Power Mode 0 0 x Power Down Mode. In this mode, all circuitry is shut down except the minimum required circuitry for the LOS and SMBus Slave operation. The SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs in this mode by setting the EN_LOS bit to a [1]. 0 1 1 1 0 1 x x x Power Up Mode. In this mode, the SmartPWDN circuitry will automatically power down any unused I/O and logic blocks and other supporting circuitry depending on the switch configuration. An output will be enabled only when the SmartPWDN circuitry indicates that that particular output is needed for the particular switch configuration and the respective PWDNn bit has logic high [1]. An input will be enabled when the SmartPWDN circuitry indicates that that particular input is needed for the particular switch configuration or the EN_LOS bit is set to a [1]. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 11 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com LOS Register The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping. Bit Default Bit Name Access Description D[0] 0 LOS0 RO Reading a [0] from the bit D[0] indicates an open inputs fault condition on the IN0. A [1] indicates presence of a valid signal. D[1] 0 LOS1 RO Reading a [0] from the bit D[1] indicates an open inputs fault condition on the IN1. A [1] indicates presence of a valid signal. D[2] 0 LOS2 RO Reading a [0] from the bit D[2] indicates an open inputs fault condition on the IN2. A [1] indicates presence of a valid signal. D[3] 0 LOS3 RO Reading a [0] from the bit D[3] indicates an open inputs fault condition on the IN3. A [1] indicates presence of a valid signal. 0000 Reserved RO Reserved for future use. Returns undefined value when read. D[7:4] INPUT INTERFACING The DS10CP154A accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS10CP154A can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10CP154A inputs are internally terminated with a 100Ω resistor. LVDS Driver DS10CP154 Receiver 100: Differential T-Line OUT+ IN+ 100: IN- OUT- Figure 2. Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input CML3.3V or CML2.5V Driver VCC 50: DS10CP154 Receiver 50: OUT+ 100: Differential T-Line IN+ 100: OUT- IN- Figure 3. Typical CML Driver DC-Coupled Interface to DS10CP154A Input 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input OUTPUT INTERFACING The DS10CP154A outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. DS10CP154 Driver OUT+ Differential Receiver 100: Differential T-Line IN+ CML or LVPECL or LVDS 100: 100: IN- OUT- Figure 5. Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A 13 DS10CP154A SNLS306C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS10CP154A PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS10CP154ATSQ/NOPB ACTIVE WQFN RTA 40 250 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 1CP154AS DS10CP154ATSQX/NOPB ACTIVE WQFN RTA 40 2500 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 1CP154AS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS10CP154ATSQ/NOPB DS10CP154ATSQX/NOP B Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS10CP154ATSQ/NOPB WQFN RTA DS10CP154ATSQX/NOPB WQFN RTA 40 250 213.0 191.0 55.0 40 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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