LINER LTC1436AIGN-PLL High efficiency low noise synchronous step-down switching regulator Datasheet

LTC1436A
LTC1436A-PLL/LTC1437A
High Efficiency Low Noise
Synchronous Step-Down
Switching Regulators
DESCRIPTION
U
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Maintains Constant Frequency at Low Output Currents
Dual N-Channel MOSFET Synchronous Drive
Programmable Fixed Frequency (PLL Lockable)
Wide VIN Range: 3.5V to 36V Operation
Low Minimum On-Time (≤ 300ns) for High
Frequency, Low Duty Cycle Applications
Very Low Dropout Operation: 99% Duty Cycle
Low Dropout, 0.5A Linear Regulator for CPU I/O
or Low Noise Audio Supplies
Built-In Power-On Reset Timer
Programmable Soft Start
Low-Battery Detector
Remote Output Voltage Sense
Foldback Current Limiting (Optional)
Pin Selectable Output Voltage
Logic Controlled Micropower Shutdown: IQ < 25µA
Output Voltages from 1.19V to 9V
Available in 24-Lead Narrow SSOP and 28-Lead
SSOP Packages
U
APPLICATIONS
■
■
■
■
Notebook and Palmtop Computers, PDAs
Cellular Telephones and Wireless Modems
Portable Instruments
Battery-Operated Devices
DC Power Distribution Systems
VIN
4.5V TO 22V
COSC
VIN
TGL
RUN/SS
CSS
0.1µF
M3
IRLML2803
TGS
SW
ITH
RC
10k
DB
CMDSH-3
LTC1436A
CC
510pF
An additional comparator is available for use as a lowbattery detector. A power-on reset timer (POR) is included
which generates a signal delayed by 65536/fCLK (300ms
typically) after the output is within 5% of the regulated
output voltage. Internal resistive dividers provide pin
selectable output voltages with remote sense capability.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Adaptive Power is a trademark of Linear Technology Corporation.
TYPICAL APPLICATION
COSC
43pF
An auxiliary 0.5A linear regulator using an external PNP
pass device provides a low noise, low dropout voltage
source. A secondary winding feedback control pin (SFB)
guarantees regulation regardless of the load on the main
output by forcing continuous operation.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V to 30V (36V maximum).
U
■
The LTC®1436A/LTC1437A are synchronous step-down
switching regulator controllers that drive external
N-channel power MOSFETs in a phase lockable, fixed
frequency architecture. The Adaptive PowerTM output stage
selectively drives two N-channel MOSFETs at frequencies
up to 400kHz while reducing switching losses to maintain
high efficiencies at low output currents.
INTVCC
SGND
BOOST
100pF
VPROG
BG
VOSENSE
+
4.7µF
+
M1
Si4412DY
L1
4.7µH
CB
0.1µF
M2
Si4412DY
RSENSE
0.02Ω
D1
MBRS140T3
PGND
SENSE +
SENSE –
CIN
22µF
35V
×2
VOUT
1.6V
5A
R1
35.7k
R2
102k
+
COUT
100µF
6.3V
×2
1000pF
1436 F01
Figure 1. High Efficiency Step-Down Converter
1
LTC1436A
LTC1436-PLL-A/LTC1437A
U
W W
W
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN).........................36V to – 0.3V
Topside Driver Supply Voltage (Boost) ......42V to – 0.3V
Switch Voltage (SW)............................. VIN + 5V to – 5V
EXTVCC Voltage .........................................10V to – 0.3V
POR, LBO Voltages ....................................12V to – 0.3V
AUXFB Voltage ..........................................20V to – 0.3V
AUXDR Voltage ..........................................28V to – 0.3V
SENSE +, SENSE –,
VOSENSE Voltages.................. INTVCC + 0.3V to – 0.3V
VPROG Voltage..................................... INTVCC to – 0.3V
PLL LPF, ITH Voltages ...............................2.7V to – 0.3V
AUXON, PLLIN, SFB,
RUN/SS, LBI Voltages ..........................10V to – 0.3V
Peak Driver Output Current < 10µs (TGL, BG) .......... 2A
Peak Driver Output Current < 10µs (TGS) ......... 250mA
INTVCC Output Current ......................................... 50mA
Operating Temperature Range
LTC143XAC ............................................. 0°C to 70°C
LTC143XAI ........................................ – 40°C to 85°C
Junction Temperature (Note 1) ............................. 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
W
U
U
PACKAGE/ORDER INFORMATION
COSC 1
RUN/SS 2
LBO 3
LBI 4
TOP VIEW
TOP VIEW
TOP VIEW
24 POR
23 BOOST
22 TGL
21 SW
PLL LPF 1
24 PLLIN
COSC 2
PLL LPF 1
RUN/SS 3
22 BOOST
ITH 4
27 POR
RUN/SS 3
21 TGL
SFB 5
28 PLLIN
COSC 2
23 POR
20 SW
26 BOOST
LBO 4
25 TGL
LBI 5
24 SW
ITH 6
23 TGS
SFB 7
22 VIN
ITH 5
20 TGS
SFB 6
19 VIN
SGND 6
SGND 7
18 INTVCC
VPROG 7
VPROG 8
17 BG
VOSENSE 8
17 INTVCC
VOSENSE 9
16 PGND
SENSE – 9
16 BG
SENSE – 10
15 EXTVCC
SENSE + 10
15 PGND
SENSE + 11
14 AUXDR
AUXON 11
14 EXTVCC
SENSE – 12
17 EXTVCC
AUXON 12
13 AUXFB
AUXFB 12
13 AUXDR
SENSE + 13
16 AUXDR
18 VIN
GN PACKAGE
24-LEAD PLASTIC SSOP
(150 MIL SSOP)
GN PACKAGE
24-LEAD PLASTIC SSOP
(150 MIL SSOP)
TJMAX = 125°C, θJA = 110°C/W
19 TGS
SGND 8
21 INTVCC
VPROG 9
20 DRVCC
VOSENSE 10
19 BG
NC 11
18 PGND
AUXON 14
15 AUXFB
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
TJMAX = 125°C, θJA = 95°C/W
ORDER PART NUMBER
ORDER PART NUMBER
ORDER PART NUMBER
LTC1436ACGN
LTC1436AIGN
LTC1436ACGN-PLL
LTC1436AIGN-PLL
LTC1437ACG
LTC1437AIG
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TA = 25°C, VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
10
50
nA
1.19
3.30
5.00
1.202
3.380
5.100
V
V
V
Main Control Loop
IIN VOSENSE
Feedback Current
VPROG Pin Open (Note 2)
VOUT
Regulated Output Voltage
1.19V (Adjustable) Selected
3.3V Selected
5V Selected
(Note 2)
VPROG Pin Open
VPROG = 0V
VPROG = INTVCC
2
●
●
●
1.178
3.220
4.900
LTC1436A
LTC1436A-PLL/LTC1437A
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 15V, VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VLINEREG
Reference Voltage Line Regulation
VIN = 3.6V to 20V (Note 2), VPROG Pin Open
TYP
MAX
UNITS
0.002
0.01
%/V
VLOADREG
Output Voltage Load Regulation
ITH Sinking 5µA (Note 2)
ITH Sourcing 5µA (Note 2)
●
●
0.5
– 0.5
0.8
– 0.8
%
%
VSFB
Secondary Feedback Threshold
VSFB Ramping Negative
●
1.16
1.19
1.22
V
ISFB
Secondary Feedback Current
VSFB = 1.5V
VOVL
Output Overvoltage Lockout
VPROG Pin Open
–1
–2
µA
1.24
1.28
1.32
V
IPROG
VPROG Input Current
0.5V > VPROG
INTVCC – 0.5V < VPROG < INTVCC
–3
3
–6
6
µA
µA
EXTVCC = 5V (Note 3)
3.6V < VIN < 30V, VAUXON = 0V
VRUN/SS = 0V, 3.6V < VIN < 15V
280
16
25
µA
µA
0.8
1.3
2
V
VRUN/SS = 0V
1.5
3
4.5
µA
∆VSENSE(MAX) Maximum Current Sense Threshold
VOSENSE = 0V, 5V, VPROG Pin Open
130
150
180
mV
t ON(MIN)
Minimum On-Time
Tested with Square Wave, SENSE – = 1.6V,
∆VSENSE = 20mV (Note 6)
250
300
ns
TGL t r
TGL t f
TGL Transition Time
Rise Time
Fall Time
CLOAD = 3000pF
CLOAD = 3000pF
50
50
150
150
ns
ns
TGS t r
TGS t f
TGS Transition Time
Rise Time
Fall Time
CLOAD = 500pF
CLOAD = 500pF
90
50
200
150
ns
ns
BG t r
BG t f
BG Transition Time
Rise Time
Fall Time
CLOAD = 3000pF
CLOAD = 3000pF
50
40
150
150
ns
ns
5.0
5.2
V
IQ
Input DC Supply Current
Normal Mode
Shutdown
VRUN/SS
RUN Pin Threshold
IRUN/SS
Soft Start Current Source
MIN
●
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 30V, VEXTVCC = 4V
VLDO INT
INTVCC Load Regulation
IINTVCC = 15mA, VEXTVCC = 4V
– 0.2
–1
%
VLDO EXT
EXTVCC Voltage Drop
IINTVCC = 15mA, VEXTVCC = 5V
130
230
mV
VEXTVCC
EXTVCC Switchover Voltage
IINTVCC = 15mA, VEXTVCC Ramping Positive
●
●
4.8
4.5
4.7
V
112
125
200
240
kHz
50
kΩ
Oscillator and Phase-Locked Loop
fOSC
Oscillator Frequency
RPLLIN
PLL IN Input Resistance
IPLLLPF
Phase Detector Output Current
Sinking Capability
Sourcing Capability
VCO High
COSC = 100pF, LTC1436 (Note 4),
LTC1436A-PLL/LTC1437A, VPLLLPF = 0V
LTC1436A-PLL/LTC1437A, VPLLLPF = 2.4V
fPLLIN < fOSC
fPLLIN > fOSC
10
10
138
kHz
15
15
20
20
µA
µA
0.6
1
V
0.2
1
µA
– 7.5
–4
%
Power-On Reset
VSATPOR
POR Saturation Voltage
IPOR = 1.6mA, VOSENSE = 1V, VPROG Pin Open
ILPOR
POR Leakage
VPOR = 12V, VOSENSE = 1.2V, VPROG Pin Open
VTHPOR
POR Trip Voltage
VPROG Pin Open, VOSENSE Ramping Negative
t DPOR
POR Delay
VPROG Pin Open
– 11
65536
Cycles
3
LTC1436A
LTC1436-PLL-A/LTC1437A
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TA = 25°C, VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
1
V
0.01
1
µA
1.19
1.22
V
1
50
nA
Low-Battery Comparator
VSATLBO
LBO Saturation Voltage
ILBO = 1.6mA, VLBI = 1.1V
ILLBO
LBO Leakage
VLBO = 12V, VLBI = 1.4V
●
VTHLBI
LBI Trip Voltage
High to Low Transition on LBO
●
IINLBI
LBI Input Current
VLBI = 1.19V
●
VHYSLBO
LBO Hysteresis
1.16
20
mV
Auxiliary Regulator/Comparator
IAUXDR
AUXDR Current
Max Current Sinking Capability
Control Current
Leakage When Off
VEXTVCC = 0V
VAUXDR = 4V, VAUXFB = 1.0V, VAUXON = 5V
VAUXDR = 5V, VAUXFB = 1.5V, VAUXON = 5V
VAUXDR = 24V, VAUXFB = 1.5V, VAUXON = 0V
IIN AUXFB
AUXFB Input Current
VAUXFB = 1.19V, VAUXON = 5V
IIN AUXON
AUXON Input Current
VAUXON = 5V
VTH AUXON
AUXON Trip Voltage
VAUXDR = 4V, VAUXFB = 1.0V
VSAT AUXDR
AUXDR Saturation Voltage
IAUXDR = 1.6mA, VAUXFB = 1.0V, VAUXON = 5V
VAUXFB
AUXFB Voltage
VAUXON = 5V, 11V < VAUXDR < 24V (Note 5)
VAUXON = 5V, 3V < VAUXDR < 7V (Note 5)
VTH AUXDR
AUXFB Divider Disconnect Voltage
VAUXON = 5V (Note 5), Ramping Negative
The ● denotes specifications which apply over the full operating
temperature range.
LTC1436ACGN/LTC1436ACGN-PLL/LTC1437ACG: 0°C ≤ TA ≤ 70°C
LTC1436AIGN/LTC1436AIGN-PLL/LTC1437AIG: – 40°C ≤ TA ≤ 85°C
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC1436ACGN/LTC1436ACGN-PLL/LTC1436AIGN/
LTC1436AIGN-PLL: TJ = TA + (PD)(110 °C/W)
LTC1437ACG/LTC1437AIG: TJ = TA + (PD)(95 °C/W)
Note 2: The LTC1436A/LTC1437A are tested in a feedback loop which
servos VOSENSE to the balance point for the error amplifier
(VITH = 1.19V).
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information
section.
4
10
5
1
mA
µA
µA
0.01
1
µA
0.01
1
µA
1.19
1.4
V
0.4
0.8
V
11.5
1.14
12
1.19
12.5
1.24
V
V
7.5
8.5
9.5
V
1.0
●
●
15
1
0.01
Note 4: Oscillator frequency is tested by measuring the COSC charge and
discharge currents and applying the formula:
(
)(
)
8.4(108)
1 + 1 –1
fOSC (kHz) = C
OSC (pF) + 11 ICHG IDIS
Note 5: The Auxiliary Regulator is tested in a feedback loop which servos
VAUXFB to the balance point for the error amplifier. For applications with
VAUXDR > 9.5V, VAUXFB uses an internal resistive divider. See
Applications Information.
Note 6: The minimum on-time test condition corresponds to an inductor
peak-to-peak ripple current ≥ 40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
LTC1436A
LTC1436A-PLL/LTC1437A
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Input Voltage
VOUT = 3.3V
Efficiency vs Input Voltage
VOUT = 5V
100
100
VOUT = 3.3V
VOUT = 5V
95
90
ILOAD = 1A
85
ILOAD = 100mA
80
90
EFFICIENCY (%)
EFFICIENCY (%)
90
ILOAD = 100mA
85
80
75
75
70
70
VIN = 10V
VOUT = 5V
RSENSE = 0.033Ω
95
95
ILOAD = 1A
EFFICIENCY (%)
Efficiency vs Load Current
100
CONTINUOUS
MODE
85
80
Burst ModeTM
OPERATION
75
70
65
Adaptive Power
MODE
60
55
0
10
15
20
INPUT VOLTAGE (V)
5
25
30
0
5
10
15
20
INPUT VOLTAGE (V)
25
1436 G01
Load Regulation
VITH Pin Voltage vs Output Current
3.0
RSENSE = 0.033Ω
∆VOUT (%)
0.4
0.3
0.2
0.1
– 0.25
2.5
– 0.50
2.0
VITH (V)
RSENSE = 0.033Ω
VOUT DROP OF 5%
– 0.75
1.0
1.5
2.0
LOAD CURRENT (A)
2.5
–1.25
0.5
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
3.0
0
EXTVCC Switch Drop
vs INTVCC Load Current
VOUT = 5V
EXTVCC = VOUT
60
VOUT = 3.3V
EXTVCC = OPEN
40
0.5
20
VEXTVCC = 0V
180
70°C
0
25°C
– 0.3
0
5
10
15
20
INPUT VOLTAGE (V)
140
25°C
120
100
– 55°C
80
60
40
20
SHUTDOWN
0
70°C
160
0.3
∆INTVCC (%)
80
200
0.5
SHUTDOWN CURRENT (µA)
2.0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (%)
1436 G06
INTVCC Regulation
vs INTVCC Load Current
100
1.0
2.5
1436 G05
Input Supply Current
vs Input Voltage
2.5
CONTINUOUS/Adaptive
Power MODE
0
0
3.0
1436 G04
1.5
Burst Mode
OPERATION
1.0
EXTVCC – INTVCC (mV)
0.5
1.5
–1.00
–1.50
0
0
10
1
0.01
0.1
LOAD CURRENT (A)
1435 G03
0
0.5
VIN – VOUT (V)
30
1436 G02
VIN – VOUT Dropout Voltage
vs Load Current
SUPPLY CURRENT (mA)
50
0.001
25
0
30
1436 G07
– 0.5
0
0
10
15
5
INTVCC LOAD CURRENT (mA)
20
1436 G08
0
2
4 6 8 10 12 14 16 18 20
INTVCC LOAD CURRENT (mA)
1436 G09
Burst Mode is a trademark of Linear Technology Corporation.
5
LTC1436A
LTC1436-PLL-A/LTC1437A
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Oscillator Frequency
vs Temperature
RUN/SS Pin Current
vs Temperature
10
4
5
3
SFB Pin Current vs Temperature
0
fO
–5
SFB CURRENT (µA)
RUN/SS CURRENT (µA)
FREQUENCY (%)
– 0.25
2
–1.50
– 0.75
–1.00
1
–1.25
–10
– 40 –15
60
35
85
10
TEMPERATURE (°C)
110
135
0
– 40 –15
85
10
35
60
TEMPERATURE (°C)
110
135
–1.50
– 40 –15
60
35
85
10
TEMPERATURE (°C)
110
1436 G11
1436 G10
Maximum Current Sense
Threshold Voltage vs Temperature
135
1436 G12
Transient Response
Transient Response
CURRENT SENSE THRESHOLD (mV)
154
152
VOUT
50mV/DIV
VOUT
50mV/DIV
150
148
ILOAD = 50mA to 1A
146
– 40 –15
85
10
35
60
TEMPERATURE (°C)
110
ILOAD = 1A to 3A
1436 G14
1436 G15
135
1436 G13
Auxiliary Regulator Load
Regulation
Soft Start: Load Current vs Time
Burst Mode Operation
VOUT
20mV/DIV
RUN/SS
5V/DIV
INDUCTOR
CURRENT
1A/DIV
VITH
200mV/DIV
ILOAD = 50mA
1436 G16
1436 G17
AUXILIARY OUTPUT VOLTAGE (V)
12.2
EXTERNAL PNP: 2N2907A
12.1
12.0
11.9
11.8
11.7
0
40
120
160
80
AUXILIARY LOAD CURRENT (mA)
200
1436 G18
6
LTC1436A
LTC1436A-PLL/LTC1437A
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Auxiliary Regulator
Sink Current Available
Auxiliary Regulator PSRR
70
20
10mA LOAD
15
50
PSRR (dB)
AUX DR CURRENT (mA)
60
10
100mA LOAD
40
30
5
20
0
0
2
4
10 12
6
8
AUX DR VOLTAGE (V)
14
16
1436 G19
10
10
100
FREQUENCY (kHz)
1000
1436 G20
U
U
U
PIN FUNCTIONS
VIN: Main Supply Pin. Must be closely decoupled to the
IC’s signal ground pin.
INTVCC: Output of the Internal 5V Regulator and EXTVCC
Switch. The driver and control circuits are powered from
this voltage. Must be closely decoupled to power ground
with a minimum of 2.2µF tantalum or electrolytic capacitor.
DRVCC: Bottom MOSFET Driver Supply Voltage.
EXTVCC: Input to the Internal Switch Connected to INTVCC.
This switch closes and supplies VCC power whenever
EXTVCC is higher than 4.7V. See EXTVCC connection in
Applications Information section. Do not exceed 10V on
this pin. Connect to VOUT if VOUT ≥ 5V.
BOOST: Supply to Topside Floating Driver. The bootstrap
capacitor is returned to this pin. Voltage swing at this pin
is from INTVCC to VIN + INTVCC.
SW: Switch Node Connection to Inductor. Voltage swing
at this pin is from a Schottky diode (external) voltage drop
below ground to VIN.
SGND: Small Signal Ground. Must be routed separately
from other grounds to the (–) terminal of COUT.
PGND: Driver Power Ground. Connects to source of
bottom N-channel MOSFET and the (–) terminal of CIN.
SENSE –: The (–) Input to the Current Comparator.
SENSE +: The (+) Input to the Current Comparator. Builtin offsets between SENSE – and SENSE + pins in conjunction
with RSENSE set the current trip thresholds.
VOSENSE: Receives the remotely sensed feedback voltage
either from the output or from an external resistive divider
across the output . The VPROG pin determines which point
VOSENSE must connect to.
VPROG: This voltage selects the output voltage. For VPROG
< VINTVCC /3 the output is set to 3.3V with VOSENSE
connected to the output. With VPROG > VINTVCC /1.5 the
output is set to 5V with VOSENSE connected to the output.
Leaving VPROG open (DC) allows the output voltage to be
set by an external resistive divider connected to VOSENSE.
COSC: External capacitor COSC from this pin to ground sets
the operating frequency.
ITH: Error Amplifier Compensation Point. The current
comparator threshold increases with this control voltage.
Nominal voltage range for this pin is 0V to 2.5V.
RUN/SS: Combination of Soft Start and Run Control
Inputs. A capacitor to ground at this pin sets the ramp time
to full current output. The time is approximately 0.5s/µF.
7
LTC1436A
LTC1436-PLL-A/LTC1437A
U
U
U
PIN FUNCTIONS
Forcing this pin below 1.3V causes the device to be shut
down. In shutdown all functions are disabled.
LBI: The (+) Input of the Low Battery Voltage Comparator.
The (–) input is connected to a 1.19V reference.
TGL: High Current Gate Drive for Main Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW.
PLLIN: External Synchronizing Input to Phase Detector.
This pin is internally terminated to SGND with 50kΩ. Tie
this pin to SGND in applications which do not use the
phase-locked loop.
TGS: High Current Gate Drive for a Small Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW. Leaving TGS open invokes Burst
Mode operation at low load currents.
PLL LPF: Output of Phase Detector and Control Input of
Oscillator. Normally a series RC lowpass filter network is
connected from this pin to ground. Tie this pin to SGND in
applications which do not use the phase-locked loop. Can
be driven by 0V to 2.4V logic signal for a frequency shifting
option.
BG: High Current Gate Drive for Bottom N-Channel
MOSFET. Voltage swing at this pin is from ground to
INTVCC (DRVCC).
SFB: Secondary Winding Feedback Input. Normally
connected to a feedback resistive divider from the
secondary winding. This pin should be tied to: ground to
force continuous operation; INTVCC in applications that
don’t use a secondary winding; and a resistive divider from
the output in applications using a secondary winding.
POR: Open Drain Output of an N-Channel Pull-Down. This
pin sinks current when the output voltage is 7.5% out of
regulation and releases 65536 oscillator cycles after the
output voltage rises to – 5% of its regulated value. The
POR output is asserted when Run/SS is low independent
of VOUT.
LBO: Open Drain Output of an N-Channel Pull-Down. This
pin will sink current when the LBI pin goes below 1.19V.
8
AUXFB: Feedback Input to the Auxiliary Regulator/
Comparator. When used as a linear regulator, this input
can either be connected to an external resistive divider or
directly to the collector of the external PNP pass device for
12V operation. When used as a comparator, this is the
noninverting input of a comparator whose inverting input
is tied to the internal 1.19V reference. See Auxiliary
Regulator/Comparator in Applications Information section.
AUXON: Pulling this pin high turns on the auxiliary regulator/
comparator. The threshold is 1.19V.
AUXDR: Open Drain Output of the Auxiliary Regulator/
Comparator. The base of an external PNP device is
connected to this pin for use as a linear regulator. An
external pull-up resistor is required for use as a comparator.
A voltage > 9.5V on AUXDR causes the internal 12V
resistive divider to be connected to AUXFB.
LBO**
SGND
VOSENSE
VPROG
10k
COUT2
90.8k
+
AUX
–
LBI**
–
+
119k
61k
320k
1.19V
gm = 1m
EA
RUN/
SOFT
START
CSS
CC
RC
1.10V
PHASE
DETECTOR
50k
PLLIN*
OV
SHUTDOWN
+
–
–
RUN/SS
VFB
1.28V
+
PWR-ON
RESET
POR
1.19V
3µA
9V
1.19V
6V
–
+
AUXDR
* LTC1436A-PLL/LTC1437A ONLY
** LTC1436A/LTC1437A ONLY
†
FOLDBACK CURRENT LIMITING
OPTION
INTVCC
+
AUXFB
AUXON
Ω
12V OUT
DFB†
ITH
30k
–
+
180k
I1
OSC
2.4V
+
–
PLL LPF*
CLP
RLP
8k
4k
Q
SENSE +
R
S
+
–
SFB
0.6V
–
+
I2
SENSE –
4.8V
INTVCC
+
–
–
+
DROPOUT
DETECTOR
SHUTDOWN
1.19V
1µA
COSC
COSC
+
SW
TGS
TGL
BOOST
CIN
PGND
BG
DRVCC
INTVCC
CONNECTION FOR
LTC1436A/LTC1436A-PLL
EXTVCC
5V
LDO
REF
VIN
SWITCH
LOGIC
1.19V
REF
VIN
VIN
+
M1
RSENSE
M2
CINTVCC
D1
M3
CB
DB
INTVCC
1436 FD
+
VOUT
+
VSEC
COUT
CSEC
LTC1436A
LTC1436A-PLL/LTC1437A
W
FUNCTIONAL DIAGRA
9
U
U
LTC1436A
LTC1436-PLL-A/LTC1437A
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC1436A/LTC1437A use a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the
oscillator sets the RS latch and turned off when the main
current comparator I1 resets the RS latch. The peak
inductor current at which I1 resets the RS latch is controlled by the voltage on ITH pin, which is the output of error
amplifier EA. VPRGM and VOSENSE pins, described in the Pin
Functions, allow EA to receive an output feedback voltage
VFB from either internal or external resistive dividers. When
the load current increases, it causes a slight decrease in
VFB relative to the 1.19V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. While the top MOSFET is off,
the bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during
each off cycle. However, when VIN decreases to a voltage
close to VOUT, the loop may enter dropout and attempt to
turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the top
MOSFET remains on, and periodically forces a brief off
period to allow CB to recharge.
The main control loop is shut down by pulling RUN/SS pin
low. Releasing RUN/SS allows an internal 3µA current
source to charge soft start capacitor CSS. When CSS
reaches 1.3V, the main control loop is enabled with the ITH
voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume.
Comparator OV guards against transient overshoots
> 7.5% by turning off the top MOSFET and keeping it off
until the fault is removed.
Low Current Operation
Adaptive Power mode allows the LTC1436A/LTC1437A to
automatically change between two output stages sized for
different load currents. TGL and BG pins drive large
synchronous N-channel MOSFETs for operation at high
currents, while the TGS pin drives a much smaller
10
N-channel MOSFET used in conjunction with a Schottky
diode for operation at low currents. This allows the loop to
continue to operate at normal frequency as the load
current decreases without incurring the large MOSFET
gate charge losses. If the TGS pin is left open, the loop
defaults to Burst Mode operation in which the large
MOSFETs operate intermittently based on load demand.
Adaptive Power mode provides constant frequency operation down to approximately 1% of rated load current. This
results in an order of magnitude reduction of load current
before Burst Mode operation commences. Without the
small MOSFET (i.e.: no Adaptive Power mode), the transition to Burst Mode operation is approximately 10% of
rated load current.
The transition to low current operation begins when comparator I2 detects current reversal and turns off the
bottom MOSFET. If the voltage across RSENSE does not
exceed the hysteresis of I2 (approximately 20mV) for one
full cycle, then on following cycles the top drive is routed to
the small MOSFET at TGS pin and BG pin is disabled. This
continues until an inductor current peak exceeds 20mV/
RSENSE or the ITH voltage exceeds 0.6V, either of which
causes drive to be returned to TGL pin on the next cycle.
Two conditions can force continuous synchronous operation, even when the load current would otherwise dictate
low current operation. One is when the common mode
voltage of the SENSE + and SENSE – pins is below 1.4V and
the other is when the SFB pin is below 1.19V. The latter
condition is used to assist in secondary winding regulation
as described in the Applications Information section.
Frequency Synchronization
A Phase-locked loop (PLL) is available on the
LTC1436A-PLL and LTC1437A to allow the oscillator to be
synchronized to an external source connected to the
PLLIN pin. The output of the phase detector at the PLL LPF
pin is also the control input of the oscillator, which
operates over a 0V to 2.4V range corresponding to – 30%
to 30% in frequency. When locked, the PLL aligns the turnon of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open or at a constant DC
voltage, PLL LPF goes low, forcing the oscillator to minimum frequency.
LTC1436A
LTC1436A-PLL/LTC1437A
U
OPERATIO
(Refer to Functional Diagram)
Power-On Reset
The POR pin is an open drain output which pulls low when
the main regulator output voltage is out of regulation.
When the output voltage rises to within 7.5% of regulation, a timer is started which releases POR after 216
(65536) oscillator cycles. In shutdown, the POR output is
pulled low.
Auxiliary Linear Regulator
The auxiliary linear regulator in the LTC1436A/LTC1437A
controls an external PNP transistor for operation up to
500mA. An internal AUXFB resistive divider set for 12V
operation is invoked when AUXDR pin is above 9.5V to
allow 12V VPP supplies to be easily implemented. When
AUXDR is below 8.5V an external feedback divider may be
used to set other output voltages. Taking the AUXON pin
low shuts down the auxiliary regulator providing a convenient logic controlled power supply.
The AUX block can be used as a comparator having its
inverting input tied to the internal 1.19V reference. The
AUXDR pin is used as the output and requires an external
pull-up to a supply less than 8.5V in order to inhibit the
invoking of the internal resistive divider.
INTVCC /DRVCC /EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the other LTC1436A/LTC1437A circuitry is derived from
the INTVCC pin. The bottom MOSFET driver supply DRVCC
pin is internally connected to INTVCC in the LTC1436A and
externally connected to INTVCC in the LTC1437A. When
the EXTVCC pin is left open, an internal 5V low dropout
regulator supplies INTVCC power. If EXTVCC is taken above
4.8V, the 5V regulator is turned off and an internal switch
is turned on to connect EXTVCC to INTVCC. This allows the
INTVCC power to be derived from a high efficiency external
source such as the output of the regulator itself or a
secondary winding, as described in the Applications Information section.
U
W
U
U
APPLICATIONS INFORMATION
The basic LTC1436A application circuit is shown in Figure
1, High Efficiency Step-Down Converter. External component selection is driven by the load requirement, and
begins with the selection of RSENSE. Once RSENSE is
known, COSC and L can be chosen. Next, the power
MOSFETs and D1 are selected. Finally, CIN and COUT are
selected. The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).
RSENSE Selection For Output Current
RSENSE is chosen based on the required output current.
The LTC1436A/LTC1437A current comparator has a maximum threshold of 150mV/RSENSE and an input common
mode range of SGND to INTVCC. The current comparator
threshold sets the peak of the inductor current, yielding a
maximum average output current IMAX equal to the peak
value less half the peak-to-peak ripple current ∆IL.
Allowing a margin for variations in the LTC1436A/
LTC1437A and external component values yields:
RSENSE =
100mV
IMAX
The LTC1436A/LTC1437A work well with RSENSE values
≥ 0.005Ω.
COSC Selection for Operating Frequency
The LTC1436A/LTC1437A use a constant frequency
architecture with the frequency determined by an external
oscillator capacitor COSC. Each time the topside MOSFET
turns on, the voltage on COSC is reset to ground. During the
on-time, COSC is charged by a fixed current plus an
additional current which is proportional to the output
voltage of the phase detector VPLLLPF (LTC1436A-PLL/
LTC1437A). When the voltage on the capacitor reaches
1.19V, COSC is reset to ground. The process then repeats.
The value of COSC is calculated from the desired operating
frequency. Assuming the phase-locked loop has no external oscillator input (VPLLLPF = 0V):
11
LTC1436A
LTC1436-PLL-A/LTC1437A
U
U
W
U
APPLICATIONS INFORMATION

1.37(104 )

COSC pF =
 Frequency kHz

( )
( )

 – 11


∆IL =
A graph for selecting COSC vs frequency is given in Figure
2. As the operating frequency is increased the gate
charge losses will be higher, reducing efficiency (see
Efficiency Considerations). The maximum recommended
switching frequency is 400kHz. When using Figure 2 for
synchronizable applications, choose COSC corresponding to a frequency approximately 30% below your center
frequency. (See Phase-Locked Loop and Frequency Synchronization.)
300
VPLLLPF = 0V
COSC VALUE (pF)
250
200
 V 
1
VOUT 1 − OUT
VIN 

f L
( )( )
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4 (IMAX). Remember, the
maximum ∆IL occurs at the maximum input voltage.
The inductor value also has an effect on low current
operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Lower inductor values (higher ∆IL) will
cause this to occur at higher load currents, which can
cause a dip in efficiency in the upper range of low current
operation. In Burst Mode operation (TGS pin open),
lower inductance values will cause the burst frequency to
decrease.
The Figure 3 graph gives a range of recommended inductor values vs operating frequency and VOUT.
150
100
60
VOUT = 5V
VOUT = 3.3V
VOUT ≤ 2.5V
50
0
0
100
200
300
400
OPERATING FREQUENCY (kHz)
500
1436 F02
Figure 2. Timing Capacitor Value
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT:
12
INDUCTOR VALUE (µH)
50
40
30
20
10
0
0
250
100
150
200
50
OPERATING FREQUENCY (kHz)
300
1436 F03
Figure 3. Recommended Inductor Values
For low duty cycle, high frequency applications where the
required minimum on-time,
tON(MIN) =
VOUT
(VIN(MAX))(f)
is less than 350ns, there may be further restrictions on the
inductance to ensure proper operation. See Minimum OnTime Considerations section for more details.
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy, or Kool Mµ® cores. Actual core loss is
independent of core size for a fixed inductor value, but it
is very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are prefered at
high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
which do not increase the height significantly.
frequency operation down to lower currents before cycle
skipping occurs.
The RDS(ON) recommended for the small MOSFET is
around 0.5Ω. Be careful not to use a MOSFET with an
RDS(ON) that is too low; remember, we want to conserve
gate charge. (A higher RDS(ON) MOSFET has a smaller gate
capacitance and thus requires less current to charge its
gate). For cost sensitive applications the small MOSFET
can be removed. The circuit will then begin Burst Mode
operation as the load current is dropped.
The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic level
threshold MOSFETs must be used in most LTC1436A/
LTC1437A applications. The only exception is applications
in which EXTVCC is powered from an external supply
greater than 8V (must be less than 10V), in which standard
threshold MOSFETs [VGS(TH) < 4V] may be used. Pay close
attention to the BVDSS specification for the MOSFETs as
well; many of the logic level MOSFETs are limited to 30V
or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RSD(ON), reverse transfer capacitance CRSS,
input voltage and maximum output current. When the
LTC1436A/LTC1437A are operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
VOUT
VIN
Power MOSFET and D1 Selection
Main Switch Duty Cycle =
Three external power MOSFETs must be selected for use
with the LTC1436A/LTC1437A: a pair of N-channel MOSFETs for the top (main) switch and an N-channel MOSFET
for the bottom (synchronous) switch.
Synchronous Switch Duty Cycle =
To take advantage of the Adaptive Power output stage, two
topside MOSFETs must be selected. A large (low RSD(ON))
MOSFET and a small (higher RDS(ON)) MOSFET are
required. The large MOSFET is used as the main switch
and works in conjunction with the synchronous switch.
The smaller MOSFET is only enabled under low load
current conditions. This increases midcurrent efficiencies
while continuing to operate at constant frequency. Also, by
using the small MOSFET the circuit can maintain constant
(V
IN − VOUT
)
VIN
The MOSFET power dissipations at maximum output
current are given by:
( )( )
2
V
PMAIN = OUT IMAX 1 + δ R DS(ON)
VIN
( ) (IMAX )(CRSS)(f)
2
V −V
PSYNC = IN OUT (IMAX ) (1 + δ )R DS (ON)
VIN
+ k VIN
1.85
Kool Mµ is a registered trademark of Magnetics, Inc.
13
LTC1436A
LTC1436-PLL-A/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside
N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For
VIN < 20V the high current efficiency generally improves
with larger MOSFETs, while for VIN > 20V the transition
losses rapidly increase to the point that the use of a higher
RDS(ON) device with lower CRSS actual provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the
duty cycle in this switch is nearly 100%. Refer to the
Foldback Current Limiting section for further applications
information.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the MOSFET
characteristics. The constant k = 2.5 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 serves two
purposes. During continuous synchronous operation, D1
conducts during the dead-time between the conduction of
the two large power MOSFETs. This prevents the body
diode of the bottom MOSFET from turning on and storing
charge during the dead-time, which could cost as much as
1% in efficiency. During low current operation, D1 operates in conjunction with the small top MOSFET to provide
an efficient low current output stage. A 1A Schottky is
generally a good compromise for both regions of operation due to the relatively small average current.
CIN and COUT Selection
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle VOUT/
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
CIN Required IRMS ≈ IMAX
14
[ (
VOUT VIN − VOUT
VIN
)]
1/ 2
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR requirement is satisified, the capacitance is adequate for filtering.
The output ripple (∆VOUT) is approximated by:

1 
∆VOUT ≈ ∆IL ESR +
4fCOUT 

where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.4IOUT(MAX) the output
ripple will be less than 100mV at maximum VIN, assuming:
COUT Required ESR < 2RSENSE
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR (size)
product of any aluminum electrolytic at a somewhat
higher price. Once the ESR requirement for COUT has been
met, the RMS current rating generally far exceeds the
IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. In the case of tantalum, it is
critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Other capacitor types
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
include Sanyo OS-CON, Nichicon PL series and Sprague
593D and 595D series. Consult the manufacturer for other
specific recommendations.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC1436A/LTC1437A. The INTVCC pin can
supply up to 15mA and must be bypassed to ground with
a minimum of 2.2µF tantalum or low ESR electrolytic.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers.
High input voltage applications, in which large MOSFETs
are being driven at high frequencies, may cause the
maximum junction temperature rating for the LTC1436A/
LTC1437A to be exceeded. The IC supply current is
dominated by the gate charge supply current when not
using an output derived EXTVCC source. The gate charge
is dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note
1 of the Electrical Characteristics. For example, the
LTC1437A is limited to less than 19mA from a 30V supply:
(
)( )(
)
TJ = 70°C + 19mA 30V 95°C / W = 124°C
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in continuous mode at maximum VIN.
EXTVCC Connection
The LTC1436A/LTC1437A contain an internal P-channel
MOSFET switch connected between the EXTVCC and
INTVCC pins. The switch closes and supplies the INTVCC
power whenever the EXTVCC pin is above 4.8V, and
remains closed until EXTVCC drops below 4.5V. This
allows the MOSFET driver and control power to be derived
from the output during normal operation (4.8V < VOUT <
9V) and from the internal regulator when the output is out
of regulation (start-up, short circuit). Do not apply greater
than 10V to the EXTVCC pin and ensure that EXTVCC < VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of Duty Cycle/Efficiency. For 5V regulators this
supply means connecting the EXTVCC pin directly to VOUT.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5V regulator resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage which has been boosted to
greater than 4.8V. This can be done with either the
inductive boost winding as shown in Figure 4a or the
capacitive charge pump shown in Figure 4b. The charge
pump has the advantage of simple magnetics.
4. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 10V range (EXTVCC <
VIN), it may be used to power EXTVCC, providing it is
compatible with the MOSFET gate drive requirements.
When driving standard threshold MOSFETs, the external supply must always be present during operation to
prevent MOSFET failure due to insufficient gate drive.
OPTIONAL EXTVCC
CONNECTION
5V ≤ VSEC ≤ 9V
+
VIN
CIN
1N4148
LTC1436A VIN
LTC1437A
TGL
EXTVCC
R6
TGS
N-CH
SGND
1µF
+
VOUT
COUT
SFB
R5
+
T1
1:N
RSENSE
N-CH
SW
BG
VSEC
N-CH
PGND
1436 F04a
Figure 4a. Secondary Output Loop and EXTVCC Connection
15
LTC1436A
LTC1436-PLL-A/LTC1437A
U
U
W
U
APPLICATIONS INFORMATION
+
+
VIN
CIN
1µF
BAT85
LTC1436A VIN
LTC1437A
TGL
EXTVCC
TGS
N-CH
0.22µF
N-CH
BAT85
GND: VOUT = 3.3V
INTVCC: VOUT = 5V
VOUT
+
COUT
SGND
1436 F05a
RSENSE
+
SW
BG
V
LTC1436A OSENSE
LTC1437A
VN2222LL
L1
VPROG
BAT85
COUT
Figure 5a. LTC1436A/LTC1437A Fixed Output Applications
N-CH
PGND
1.19V ≤ VOUT ≤ 9V
1436 F04b
VPROG
Figure 4b. Capacitive Charge Pump for EXT VCC
Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the Boost
pin supplies the gate drive voltage for the topside
MOSFET(s). Capacitor CB in the functional diagram is
charged through diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFET(s) is to be turned
on, the driver places the CB voltage across the gate source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage SW
rises to VIN and the Boost pin rises to VIN + INTVCC. The
value of the boost capacitor CB needs to be 100 times
greater than the total input capacitance of the topside
MOSFET(s). In most applications 0.1µF is adequate. The
reverse breakdown on DB must be greater than VIN(MAX).
Output Voltage Programming
The output voltage is pin selectable for all members of the
LTC1436A/LTC1437A family. The output voltage is
selected by the VPROG pin as follows:
VPROG = 0V
VPROG = INTVCC
VPROG = Open (DC)
VOUT = 3.3V
VOUT = 5V
VOUT = Adjustable
The LTC1436A/LTC1437A family also has remote output
voltage sense capability. The top of an internal resistive
divider is connected to VOSENSE. For fixed 3.3V and 5V
output voltage applications the VOSENSE pin is connected
to the output voltage as shown in Figure 5a. When using
an external resistive divider, the VPROG pin is left open (DC)
and the VOSENSE pin is connected to the feedback resistors
as shown in Figure 5b.
16
LTC1436A
LTC1437A
OPEN (DC)
R2
VOSENSE
100pF
R1
SGND
( )
VOUT = 1.19V 1 +
R2
R1
1436 F05b
Figure 5b. LTC1436A/LTC1437A Adjustable Applications
Power-On Reset Function (POR)
The power-on reset function monitors the output voltage
and turns on an open drain device when it is out of
regulation. An external pull-up resistor is required on the
POR pin.
When power is first applied or when coming out of
shutdown, the POR output is pulled to ground. When the
output voltage rises above a level which is 5% below the
final regulated output value, an internal counter starts.
After counting 216 (65536) clock cycles, the POR pulldown device turns off.
The POR output will go low whenever the output voltage
drops below 7.5% of its regulated value for longer than
approximately 30µs, signaling an out-of-regulation condition. In shutdown, the POR output is pulled low even if the
regulator’s output is held up by an external source.
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft start function and a means to shut down the
LTC1436A/LTC1437A. Soft start reduces surge currents
from VIN by gradually increasing the internal current limit.
Power supply sequencing can also be accomplished
using this pin.
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
An internal 3µA current source charges up an external
capacitor CSS. When the voltage on RUN/SS reaches 1.3V
the LTC1436A/LTC1437A begin operating. As the voltage
on RUN/SS continues to ramp from 1.3V to 2.4V, the
internal current limit is also ramped at a proportional linear
rate. The current limit begins at approximately 50mV/
RSENSE (at VRUN/SS = 1.3V) and ends at 150mV/RSENSE
(VRUN/SS > 2.7V). The output current thus ramps up
slowly, charging the output capacitor. If RUN/SS has been
pulled all the way to ground there is a delay before starting
of approximately 500ms/µF, followed by an additional
500ms/µF to reach full current.
tDELAY = 5(105)CSS seconds
Pulling the RUN/SS pin below 1.3V puts the LTC1436A/
LTC1437A into a low quiescent current shutdown (IQ <
25µA). This pin can be driven directly from logic as shown
in Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows CSS to ramp up slowly for the soft start function;
this diode and CSS can be deleted if soft start is not needed.
The RUN/SS pin has an internal 6V Zener clamp (see
Functional Diagram).
3.3V OR 5V
RUN/SS
Foldback current limiting is implemented by adding a
diode DFB between the output and ITH pins as shown in the
Function Diagram. In a hard short (VOUT = 0V), the current
will be reduced to approximately 25% of the maximum
output current. This technique may be used for all applications with regulated output voltages of 1.8V or greater.
Phase-Locked Loop and Frequency Synchronization
The LTC1436A-PLL/LTC1437A each have an internal voltage-controlled oscillator and phase detector comprising a
phase-locked loop. This allows the top MOSFET turn-on to
be locked to the rising edge of an external source. The
frequency range of the voltage-controlled oscillator is
±30% around the center frequency fO.
The value of COSC is calculated from the desired operating
frequency fO. Assuming the phase-locked loop is locked
(VPLLLPF = 1.19V):

2.1(104 )
COSC pF = 
 Frequency kHz

( )
( )

 – 11


Stating the frequency as a function of VPLLLPF and COSC:
RUN/SS
D1
( )
Frequency kHz =
CSS
CSS
8.4(108 )
1436 F06
Figure 6. Run/SS Pin Interfacing
Foldback Current Limiting
As described in Power MOSFET and D1 Selection, the
worst-case dissipation for either MOSFET occurs with a
short-circuited output, when the synchronous MOSFET
conducts the current limit value almost continuously. In
most applications this will not cause excessive heating,
even for extended fault intervals. However, when heat
sinking is at a premium or higher RDS(ON) MOSFETs are
being used, foldback current limiting should be added to
reduce the current in proportion to the severity of the fault.




1

COSC pF + 11 
+ 2000
V

 17µA + 18µA PLLLPF 



 2.4V 
[ ( ) ]
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range ∆fH is equal to the capture range: ∆fH = ∆fC =
±0.3fO.
17
LTC1436A
LTC1436-PLL-A/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the PLL LPF pin and operating frequency is
shown in Figure 7. A simplified block diagram is shown in
Figure 8.
If the external frequency (fPLLIN) is greater than the oscillator frequency (f), current is sourced continuously, pulling up the PLL LPF pin. When the external frequency is less
than fOSC, current is sunk continuously, pulling down the
PLL LPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLL LPF pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
CLP holds the voltage.
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically, RLP = 10k and CLP is 0.01µF to
0.1µF. Be sure to connect the low side of the filter to SGND.
The PLL LPF pin can be driven with external logic to obtain
a 1:1.9 frequency shift. The circuit shown in Figure 9 will
provide a frequency shift from fO to 1.9fO as the voltage
and VPLLLPF increases from 0V to 2.4V. Do not exceed 2.4V
on VPLLLPF.
1.3fO
FREQUENCY (kHz)
3.3V OR 5V
PLL LPF
fO
2.4V MAX
18k
0.7fO
1436 F09
Figure 9. Directly Driving PLL LPF Pin
0
0.5
1.0
1.5
VPLLLPF (V)
2.5
2.0
Low-Battery Comparator
1436 F07
Figure 7. Operating Frequency vs VPLLLPF
EXTERNAL
FREQUENCY
RLP
2.4V
PLL LPF
PLLIN
50k
DIGITAL
PHASE/
FREQUENCY
DETECTOR
COSC
CLP
PHASE
DETECTOR
COSC
OSC
The LTC1436A/LTC1437A have an on-chip low-battery
comparator which can be used to sense a low-battery
condition when implemented as shown in Figure 10. The
resistive divider R3, R4 sets the comparator trip point as
follows:
 R4 
VLBTRIP = 1.19V 1 + 
 R3 
VIN
R4
LBI
R3
SGND
LTC1436A
LTC1437A
LBO
–
+
1.19V REFERENCE
1436 F08
Figure 8. Phase-Locked Loop Block Diagram
18
Figure 10. Low Battery Comparator
1436 F10
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
The divided down voltage at the negative (–) input to the
comparator is compared to an internal 1.19V reference. A
20mV hysteresis is built in to assure rapid switching. The
output is an open drain MOSFET and requires a pull-up
resistor. This comparator is not active in shutdown. The
low side of the resistive divider should connect to SGND.
SFB Pin Operation
When the SFB pin drops below its ground-referenced
1.19V threshold, continuous mode operation is forced. In
continuous mode, the large N-channel main and synchronous switches are used regardless of the load on the main
output.
In addition to providing a logic input to force continuous
synchronous operation, the SFB pin provides a means to
regulate a flyback winding output. Continuous synchronous operation allows power to be drawn from the auxiliary windings without regard to the primary output load.
The SFB pin provides a way to force continuous synchronous operation as needed by the flyback winding.
The secondary output voltage is set by the turns ratio of
the transformer in conjunction with a pair of external
resistors returned to the SFB pin as shown in Figure 4a.
The secondary regulated voltage VSEC in Figure 4a is
given by:
 R6 
VSEC ≈ N + 1 VOUT > 1.19V  1 + 
 R5 
( )
where N is the turns ratio of the transformer and VOUT is
the main output voltage sensed by VOSENSE.
Auxiliary Regulator/Comparator
The auxiliary regulator/comparator can be used as a
comparator or low dropout regulator (by adding an external PNP pass device).
When the voltage present at the AUXON pin is greater than
1.19V the regulator/comparator is on. Special circuitry
consumes a small (20µ A) bias current while still remaining stable when operating as a low dropout regulator. No
excess current is drawn when the input stage is overdriven
when used as a comparator.
The AUXDR pin is internally connected to an open drain
MOSFET which can sink up to 10mA. The voltage on
AUXDR determines whether or not an internal 12V resistive divider is connected to AUXFB as described below. A
pull-up resistor is required on AUXDR and the voltage
must not exceed 28V.
With the addition of an external PNP pass device, a linear
regulator capable of supplying up to 0.5A is created. As
shown in Figure 12a, the base of the external PNP connects to the AUXDR pin together with a pull-up resistor.
The output voltage VOAUX at the collector of the external
PNP is sensed by the AUXFB pin.
The input voltage to the auxiliary regulator can be taken
from a secondary winding on the primary inductor as
shown in Figure 11a. In this application, the SFB pin
regulates the input voltage to the PNP regulator (see SFB
Pin Operation) and should be set to approximately 1V to
2V above the required output voltage of the auxiliary
regulator. A Zener diode clamp may be required to keep
VSEC under the 28V AUXDR pin specification when the
primary is heavily loaded and the secondary is not.
The AUXFB pin is the feedback point of the regulator. An
internal resistive divider is available to provide a 12V
output by simply connecting AUXFB directly to the collector of the external PNP. The internal resistive divider is
selected when the voltage at AUXFB goes above 9.5V with
1V built-in hysteresis. For other output voltages, an external resistive divider is fed back to AUXFB as shown in
Figure 11b. The output voltage VOAUX is set as follows:
VOAUX = 1.19V(1+R8/R7) < 8V
VOAUX = 12V
AUXDR < 8.5V
AUXDR > 12V
The circuit can also be used as a noninverting voltage
comparator as shown in Figure 11c. When AUXFB drops
below 1.19V, the AUXDR pin will be pulled low. A minimum current of 5µA is required to pull the AUXDR pin to
5V when used as a comparator output, in order to counteract a 1.5µA internal current source.
19
LTC1436A
LTC1436-PLL-A/LTC1437A
U
U
W
U
APPLICATIONS INFORMATION
SECONDARY WINDING
1:N
VSEC
R6
+
LTC1436A
LTC1437A AUXDR
The minimum on-time for the LTC1436A/LTC1437A in a
properly configured application is less than 300ns but
increases at low ripple current amplitudes (see Figure 12).
If an application is expected to operate close to the
minimum on-time limit, an inductor value must be chosen
that is low enough to provide sufficient ripple amplitude to
meet the minimum on-time requirement. To determine the
proper value, use the following procedure:
VOAUX
12V
AUXFB
SFB
R5
+
ON/OFF
AUXON
10µF
( )
VSEC = 1.19V 1 +
R6
> 13V
R5
1436 F11a
1. Calculate on-time at maximum supply, tON(MIN) =
(1/f)(VOUT/VIN(MAX)).
Figure 11a. 12V Output Auxiliary Regulator Using
Internal Feedback Resistors
SECONDARY WINDING
1:N
( )
VOAUX = 1.19V 1 +
VSEC
+
R6
LTC1436A
LTC1437A
VOAUX
AUXDR
R8
AUXFB
SFB
R5
R8
R7
AUXON
+
10µF
R7
ON/OFF
( )
VSEC = 1.19V 1 +
R6
R5
1436 F11b
Figure 11b. 5V Output Auxiliary Regulator Using
External Feedback Resistors
2. Use Figure 12 to obtain the peak-to-peak inductor ripple
current as a percentage of IMAX necessary to achieve
the calculated tON(MIN).
3. Ripple amplitude ∆IL(MIN) = (% from Figure 12) (IMAX)
where IMAX = 0.1/RSENSE.
 VIN(MAX ) – VOUT 
4. LMAX = tON(MIN) 

∆IL(MIN)


Choose an inductor less than or equal to the calculated
LMAX to ensure proper operation.
400
ON/OFF
INPUT
AUXON
AUXFB
LTC1436A
LTC1437A
AUXDR
–
OUTPUT
+
1.19V REFERENCE
1436 F11c
MINIMUM ON-TIME (ns)
VPULL-UP < 8.5V
350
RECOMMENDED
REGION FOR MIN
ON-TIME AND
MAX EFFICIENCY
300
250
Figure 11c. Auxiliary Comparator Configuration
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC1436A/LTC1437A are capable of turning
the top MOSFET on and off again. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit. If the duty cycle
falls below what can be accommodated by the minimum
on-time, the LTC1436A/LTC1437A will begin to skip cycles.
The output voltage will continue to be regulated, but the
ripple current and ripple voltage will increase. Therefore
this limit should be avoided.
20
200
0
50
60
70
10
20
30
40
INDUCTOR RIPPLE CURRENT (% OF IMAX)
1435A F12
Figure 12. Minimum On-Time vs Inductor Ripple Current
Because of the sensitivity of the LTC1436A/LTC1437A
current comparator when operating close to the minimum
on-time limit, it is important to prevent stray magnetic flux
generated by the inductor from inducing noise on the
current sense resistor, which may occur when axial type
cores are used. By orienting the sense resistor on the
radial axis of the inductor (see Figure 13), this noise will be
minimized.
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
INDUCTOR
L
1435A F08
Figure 13. Allowable Inductor/RSENSE Layout Orientations
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1436A/LTC1437A circuits: LTC1436A/
LTC1437A VIN current, INTVCC current, I2R losses and
topside MOSFET transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table which excludes MOSFET
driver and control currents. VIN current results in a
small (< 1%) loss which increases with VIN.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG =
f(QT + QB), where QT and QB are the gate charges of the
topside and bottom side MOSFETs. It is for this reason
that the Adaptive Power output stage switches to a low
QT MOSFET during low current operation.
By powering EXTVCC from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by a factor of Duty Cycle/
Efficiency. For example, in a 20V to 5V application,
10mA of INTVCC current results in approximately 3mA
of VIN current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the topside main
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the resistances of L and RSENSE to obtain I2R
losses. For example, if each RDS(ON) = 0.05Ω,
RL = 0.15Ω and RSENSE = 0.05Ω, then the total resistance is 0.25Ω. This results in losses ranging from 3%
to 10% as the output current increases from 0.5A to 2A.
I2R losses cause the efficiency to drop at high output
currents.
4. Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from:
Transition Loss = 2.5(VIN)1.85(IMAX)(CRSS)(f)
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead-time and
inductor core losses, generally account for less than 2%
total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT immediately shifts
by an amount equal to (∆ILOAD)(ESR), where ESR is the
effective series resistance of COUT. ∆ILOAD also begins to
charge or discharge COUT which generates a feedback
error signal. The regulator loop then acts to return VOUT to
its steady-state value. During this recovery time VOUT can
be monitored for overshoot or ringing, which would
indicate a stability problem. The ITH external components
shown in the Figure 1 circuit will provide adequate compensation for most applications.
21
LTC1436A
LTC1436-PLL-A/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients,
including load dump, reverse battery, and double battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 14 is the most straightforward approach to protect a DC/DC converter from the
ravages of an automotive battery line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
12V
VIN
LTC1436A
LTC1437A
1436 F14
Figure 14. Automotive Application Protection
22
Design Example
As a design example, assume VIN = 12V (nominal), VIN =
22V (max), VOUT = 1.6V, IMAX = 3A and f = 250kHz, RSENSE
and COSC can immediately be calculated:
100mV
= 0.033Ω
3A
 1.37(104 )
COSC = 
 – 11 = 43pF
 250 


RSENSE =
Refering to Figure 3, a 4.7µH inductor falls within the
recommended range. To check the actual value of the
ripple current the following equation is used:
∆IL =
VOUT  VOUT 
1 − V 
f L 
IN 
( )( )
The highest value of the ripple current occurs at the
maximum input voltage:
∆IL =
 1.6V 
1 − 22V  = 1.3A

250kHz 4 .7µH 
1.6V
(
)
The lowest duty cycle also occurs at maximum input
voltage. The on-time during this condition should be
checked to make sure it doesn’t violate the LTC1436A/
LTC1437A’s minimum on-time and cause cycle skipping
to occur. The required on-time at VIN(MAX) is:
tON(MIN) =
50A IPK RATING
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
should not conduct during double battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1436A/LTC1437A have a maximum input voltage of 36V, most applications will be
limited to 30V by the MOSFET BVDSS.
VOUT
(VIN(MAX) )(f)
=
1.6V
= 291ns
(22V)(250kHz)
The ∆IL was previously calculated to be 1.3A, which is
43% of IMAX. From Figure 12, the LTC1436A/LTC1437A’s
minimum on-time at 43% ripple is about 235ns. Therefore, the minimum on-time is sufficient and no cycle
skipping will occur.
LTC1436A
LTC1436A-PLL/LTC1437A
U
W
U
U
APPLICATIONS INFORMATION
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input
voltage with T (estimated) = 50°C:
PMAIN =
[
]
1.6V 2
(3) 1+ (0.005)(50°C − 25°C ) (0.042Ω)
22V
+ 2.5(22V )
1.85
(3A)(100pF )(250kHz) = 88mW
The most stringent requirement for the synchronous
N-channel MOSFET occurs when VOUT = 0 (i.e. short
circuit). In this case the worst-case dissipation rises to:
2
( )
PSYNC = ISC(AVG) 1 + δ RDS(ON)


With the 0.033Ω sense resistor ISC(AVG) = 4A will result,
increasing the Si4412DY dissipation to 950mW at a die
temperature of 105°C.
CIN is chosen for an RMS current rating of at least 1.5A at
temperature. COUT is chosen with an ESR of 0.03Ω for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
VORIPPLE = RESR ( ∆IL ) = 0.03Ω (1.3 A ) = 39 mVP- P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1436A/LTC1437A. These items are also illustrated
graphically in the layout diagram of Figure 15. Check the
following in your layout:
1. Are the signal and power grounds segregated? The
LTC1436A/LTC1437A signal ground pin must return to
the (–) plate of COUT. The power ground connects to the
source of the bottom N-channel MOSFET, anode of the
Schottky diode, and (–) plate of CIN, which should have
as short lead lengths as possible.
2. Does the LTC1436A/LTC1437A VOSENSE pin connect to
the (+) plate of COUT? In adjustable applications, the
resistive divider R1/R2 must be connected between the
(+) plate of COUT and signal ground. The 100pF capacitor should be as close as possible to the LTC1436A/
LTC1437A.
3. Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as
possible to the LTC1436A/LTC1437A.
4. Does the (+) plate of CIN connect to the drain of the
topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s).
5. Is the INTVCC decoupling capacitor connected closely
between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents.
6. Keep the switching node SW away from sensitive smallsignal nodes. Ideally, the switch node should be placed
at the furthest point from the LTC1436A/LTC1437A.
7. Route the PLLIN line away from Boost and SW pins to
avoid unwanted pickup (Boost and SW pins have high
dV/dTs).
8. SGND should be used exclusively for grounding external components on PLL LPF, COSC, ITH, LBI, SFB,
VOSENSE and AUXFB pins.
9. If operating close to the minimum on-time limit, is the
sense resistor oriented on the radial axis of the inductor? See Figure 13.
23
LTC1436A
LTC1436-PLL-A/LTC1437A
U
U
W
U
APPLICATIONS INFORMATION
CLP
RLP
1
COSC
2
CSS
3
4
5
CC
RC
6
CC2
7
8
OPEN
100pF
9
10
11
PLLIN
PLL LPF
POR
COSC
RUN/SS
BOOST
LBO
TGL
LBI
SW
ITH
TGS
SFB
LTC1437A
VIN
SGND
INTVCC
VPROG
DRVCC
VOSENSE
NC
BG
PGND
12
SENSE –
EXTVCC
13
SENSE +
AUXDR
AUX 14
AUXON
ON/OFF
AUXFB
1000pF
28
+
EXT CLOCK
27
26
25
M1
+
24
CIN
23
M3
VIN
D1
22
DB
21
20
–
+
4.7µF
19
M2
CB
0.1µF
18
17
16
L1
15
5V EXT VCC
CONNECTION
–
R1
OUTPUT DIVIDER
REQUIRED WITH
VPRGM OPEN
+
VOUT
COUT
R2
RSENSE
+
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 15. LTC1437A Layout Diagram
24
1437 F15
LTC1436A
LTC1436A-PLL/LTC1437A
U
TYPICAL APPLICATIONS
Intel Mobile CPU VID Core Power Converter with 1.8V I/O Supply
10k
0.1µF
1
COSC
43pF
2
CSS
0.1µF
3
CC2
1000pF
4
CC
220pF
7
RC
10k
6
24
PLL LPF
PLLIN
VIN
COSC
TGL
ITH
TGS
4.7Ω
18
VPROG
SW
SGND
INTVCC
VOSENSE
M1
Si4410DY
21
19
M3
IRLML2803
L1
3.3µH
BOOST
BG
1000pF
10
SENSE+
AUX 11 AUXON
ON/OFF
12
AUXFB
PGND
AUXDR
RSENSE
0.015Ω
3
17
VCC
SENSE
VCORE
1.3V TO 2V
7A
6
*DB 0.22µF
22
SENSE –
CIN
22µF
35V
X2
+
20
LTC1436A-PLL
9
VIN
4.5V TO 22V
0.1µF
RUN/SS
100pF
8
EXTERNAL
FREQUENCY
SYNCHRONIZATION
D1
MBRS140T3
+
16
4.7µF
5
M2
Si4410DY
COUT
820µF
4V
×2
+
LTC1706-19
FB
15
VID
13
0 1 2 3
GND
7 8 1 2
4
SGND
(PIN 6)
FROM µP
47k
VIN2
3.3V
47µF
4V**
MMBT2907L
10.5k
*CMDSH-3
**INPUT CAPACITOR MAY NOT BE NECESSARY IF
3.3V SUPPLY HAS SUFFICIENT CAPACITANCE
51pF
20k
VI/O
1.8V
150mA
47µF
4V
1436 TA09
LTC1436A 3.3V/4A Fixed Output with 5V Auxiliary Output
VIN
4.5V TO 28V
COSC
68pF
1
2
CC2
51pF
CSS
0.1µF
CC
510pF
RC
10k
3
4
5
6
7
8
9
POR
COSC
RUN/SS
BOOST
LBO
TGL
LBI
SW
ITH
TGS
SFB
VIN
LTC1436A
SGND
VPROG
INTVCC
BG
VOSENSE
PGND
10
SENSE –
EXTVCC
11
SENSE +
AUXDR
AUX 12
AUXON
ON/OFF
AUXFB
1000pF
+
24
23
22
CIN
22µF
35V
× 2 MBRS1100T3
M1
S4412DY
21
+
M3
IRLML2803
20
CSEC
3.3µF
35V
24V
VOUT
3.3V
4A
19
CMDSH-3
T1
10µH
1:1
0.1µF
18
17
+
4.7µF
M2
Si4412DY
16
RSENSE
0.025Ω
+
MBRS140T3
15
COUT
100µF
10V
×2
SGND
(PIN 7)
47k
14
13
R8
180k
51pF
2N2905A
R6
430k
+
VOUT2
5V
100mA
R7
56k
3.3µF
R5
100k
1436 TA02
25
LTC1436A
LTC1436-PLL-A/LTC1437A
U
TYPICAL APPLICATIONS
LTC1436A-PLL 2.5V/5V Adjustable Output with
Foldback Current limiting and 5V Auxiliary Output
CLP
RLP 0.01µF
10k
1
COSC
68pF
CSS
0.1µF
RC, 10k
CC
5
6
ITH
TGL
SFB
SW
24
23
EXT
CLOCK
8
9
10
AUX 11
ON/OFF
12
M1
Si4410DY
21
20
+
M3
IRLML2803
19
CMDSH-3
ITH
(PIN 4)
T1
10µH
1:1.6
0.1µF
+
4.7µF
M2
Si4410DY
RSENSE
0.02Ω
R1
100k
1%
24V
VOUT
2.5V
5A
+
R2
35.7k
1%
100pF
MBRS140T3
CSEC
3.3µF
35V
COUT
100µF
10V
×2
47k
SGND
(PIN 6)
R8
180k
1N4148
CIN
22µF
35V
× 2 MBRS1100T3
+
22
TGS
LTC1436A-PLL
18
VPROG
VIN
17
VOSENSE
INTVCC
16
SENSE –
BG
15
SENSE +
PGND
14
AUXON
EXTVCC
13
AUXDR
AUXFB
OPEN
1000pF
BOOST
SGND
7
100pF
POR
RUN/SS
4
51pF
PLLIN
COSC
3
510pF
CC2
PLL LPF
2
VIN
4.5V TO 24V
51pF
R6
430k
3.3µF
R5
100k
+
R7
56k
VOUT2
5V
0.2A
ZETEX
FZT749
100Ω
100Ω
1436 TA03
LTC1436A-PLL 5V/3A Fixed Output with 12V/200mA Auxiliary Output
and Uncommitted Comparator
VIN
4.5V TO 28V
CLP
RLP 0.01µF
10k
1
COSC
CSS
RC, 10k
CC2
0.1µF
68pF
CC
510pF
51pF
2
3
4
5
6
7
8
9
1000pF
10
COMP 11
ON/OFF
12
PLL LPF
PLLIN
COSC
POR
RUN/SS
BOOST
ITH
TGL
SFB
SW
SGND
TGS
24 EXT
CLOCK
23
CIN
22µF/35V
×2
22
M1
Si4412DY
21
M4, IRLL014
20
1:2.2
M3
IRLML2803
19
LTC1436A-PLL
18
VPROG
VIN
17
VOSENSE
INTVCC
16
SENSE –
BG
15
SENSE +
PGND
14
AUXON
EXTVCC
13
AUXDR
AUXFB
COMPARATOR
+
CMDSH-3
0.1µF
T1
10µH
+
4.7µF
RSENSE
0.025Ω
+
47k
+
COUT1
100µF
10V
×2
0.01µF
100k
1%k
11.3k
1%k
SGND
(PIN 6)
1436 TA04
T1: DALE LPE6562-A092
26
CSEC
3.3µF
35V
VOUT1
3.3V
4A
CMDSH-3
M2
Si4412DY
MBRS140T3
VOUT2
12V
0.5A
LTC1436A
LTC1436A-PLL/LTC1437A
U
TYPICAL APPLICATIONS
LTC1436A-PLL Low Noise High Efficiency 5V/1A Regulaor
CLP
RLP 0.01µF
10k
1
COSC
CSS
0.1µF
RC, 10k
39pF
CC
51pF
3
4
510pF
CC2
2
5
6
7
100pF
8
PLLIN
PLL LPF
POR
COSC
BOOST
RUN/SS
TGL
ITH
SFB
SW
SGND
TGS
LTC1436A-PLL
VPROG
VIN
VOSENSE
INVCC
SENSE –
BG
SENSE +
VOUT 11
AUXON
ON/OFF
12
AUXFB
PGND
9
1000pF
10
EXTVCC
AUXDR
24
23
VIN
5.5V TO 28V
EXT CLOCK
250kHz
+
22
CIN
22µF
35V
M1
IRF7201
21
20
L1
50µH
M3
IRLML2803
19
18
V1
6.3V
RSENSE
0.1Ω
0.1µF
CMDSH-3
R1
240k
1%
17
16
+
4.7µF
M2
IRF7201
15
R2
56k
1%
MBRS140T3
100pF
14
13
R8
180k
1%
R7
56k
1%
51pF
SFB = 0V: CONTINUOUS MODE
SFB = 5V: BURST ENABLED
+
COUT
100µF
10V
SGND
(PIN 6)
47k
VOUT
5V
1A
+
ZETEX
FMMT549
22µF
HEAT SINK
1436 TA07
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.0075 – 0.0098
(0.191 – 0.249)
0.053 – 0.069
(1.351 – 1.748)
0.337 – 0.344*
(8.560 – 8.737)
24 23 22 21 20 19 18 17 16 15 14 13
0.004 – 0.009
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.229 – 0.244
(5.817 – 6.198)
0.025
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.150 – 0.157**
(3.810 – 3.988)
1
2 3
4
5 6
7
8
9 10 11 12
GN24 (SSOP) 0595
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0° – 8°
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.0256
(0.65)
BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.301 – 0.311
(7.65 – 7.90)
0.010 – 0.015
(0.25 – 0.38)
0.002 – 0.008
(0.05 – 0.21)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
G28 SSOP 0694
27
LTC1436A
LTC1436-PLL-A/LTC1437A
U
TYPICAL APPLICATION
LTC1437A 5V/3A Fixed Output with 12V Auxiliary Output
CLP
RLP 0.01µF
10k
1
COSC
39pF
CSS
CC2
51pF
0.1µF
2
3
4
5
CC
510pF
RC
10k
6
7
8
INT VCC
9
10
11
PLL LPF
PLLIN
COSC
POR
RUN/SS
BOOST
LBO
TGL
LBI
SW
ITH
TGS
SFB
VIN
LTC1437A
SGND
INVCC
VPROG
DRVCC
VOSENSE
NC
BG
PGND
12
SENSE –
EXTVCC
13
SENSE +
AUXDR
AUX 14
AUXON
ON/OFF
AUXFB
1000pF
28
27
VIN
5.5V TO 28V
EXT
CLOCK
CIN
22µF
35V
× 2 MBRS1100T3
+
26
M1
IRF7403
25
24
+
23
CSEC
3.3µF
35V
M3
IRLML2803
22
CMDSH-3
21
20
T1
22µH
1:2.2
0.1µF
+
RSENSE
0.03Ω
M2
IRF7403
18
VOUT
5V
3A
COUT
100µF
10V
×2
+
4.7µF
19
24V
MBRS140T3
SGND
(PIN 8)
17
47k
16
15
VOUT2
12V
0.2A
MMBT2907
R6
1M
3.3µF
R5
100k
+
T1: DALE LPE6562-A092
1436 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
LTC1142HV/LTC1142
Dual High Efficiency Synchronous Step-Down Switching Regulators
Dual Synchronous, VIN ≤ 20V
LTC1148HV/LTC1148
High Efficiency Step-Down Switching Regulator Controllers
Synchronous, VIN ≤ 20V
LTC1159
High Efficiency Synchronous Step-Down Switching Regulator
Synchronous, VIN ≤ 40V, For Logic Threshold FETs
LT 1375/LT1376
1.5A, 500kHz Step-Down Switching Regulators
High Frequency, Small Inductor, High Efficiency
Switchers, 1.5A Switch
LTC1430
High Power Step-Down Switching Regulator Controller
High Efficiency 5V to 3.3V Conversion at Up to 15A
LTC1435A
High Efficency, Low Noise Synchronous Step-Down
Switching Regulator
16-Pin Narrow SO and SSOP
LTC1438/LTC1439
Dual High Efficiency, Low Noise, Synchronous Step-Down
Switching Regulators
Full-Featured Dual Controllers
®
COMMENTS
LT1510
Constant-Voltage/ Constant-Current Battery Charger
1.3A, Li-Ion, NiCd, NiMH, Pb-Acid Charger
LTC1538-AUX
Dual High Efficiency, Low Noise, Synchronous Step-Down
Switching Regulator
5V Standby in Shutdown
LTC1539
Dual High Efficiency, Low Noise, Synchronous Step-Down
Switching Regulator
5V Standby in Shutdown
LTC1706-19
VID Voltage Programmer
Intel Mobile Pentium®II Compliant
Pentium is a registered trademark of Intel Corp.
28
Linear Technology Corporation
14367afa LT/TP 0898 REV A 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1996