Cypress CY7C453-20JI 512x9 2kx9 and 4kx9 cascadable clocked fifos with programmable Datasheet

54
CY7C451
CY7C453
CY7C454
512x9, 2Kx9, and 4Kx9 Cascadable
Clocked FIFOs with Programmable
Features
and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit memory array, the
CY7C453 has a 2048-word by 9-bit memory array, and the
CY7C454 has a 4096-word by 9-bit memory array. Devices
can be cascaded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking
of parity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 9 (CY7C451)
• 2,048 x 9 (CY7C453)
• 4,096 x 9 (CY7C454)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — ICC=70 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Available in PLCC packages
Both FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the FIFO on
the rising edge of the CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle. The output port
is controlled in a similar manner by a free-running read clock (CKR)
and a read enable pin (ENR). The read (CKR) and write (CKW)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are achievable in the standalone configuration, and up to 83.3 MHz is achievable when FIFOs
are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI) and
cascade output (XO). The XO signal is connected to the XI of the next
device, and the XO of the last device should be connected to the XI
of the first device. In standalone mode, the input (XI) pin is simply tied
to VSS.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.
Functional Description
The CY7C451, CY7C453, and CY7C454 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
D0 – 8
Logic Block Diagram
Pin Configurations
INPUT
REGISTER
CKW
PLCC/LCC
Top View
ENW
D0 D1 D2 D3 D4 D5 D6
FLAG/PARITY
PROGRAM
REGISTER
PARITY
WRITE
CONTROL
FLAG
LOGIC
RAM
ARRAY
512x 9
2048x 9
4096x9
WRITE
POINTER
MR
FL/RT
XI
HF
E/F
PAFE/XO
READ
POINTER
4 3 2 1 32 31 30
29
28
27
26
25
24
23
22
21
20
XI
ENW
CKW
VCC
VSS
HF
E/F
PAFE/XO
Q0
5
6
7
7C451
8
7C453
9
7C454
10
11
12
13
14 15 16 17 1819
Q1 Q2 Q3 Q4 Q5 Q6 Q7
RESET
LOGIC
EXPANSION
LOGIC
TRI–STATE
OUTPUT REGISTER
D7
D8
FL/RT
MR
VSS
CKR
ENR
OE
Q8 /PG/PE
C451-2
READ
CONTROL
OE
RETRANSMIT
LOGIC
Q0–7,Q8/PG/PE
Cypress Semiconductor Corporation
Document #: 38-06033 Rev. *A
•
CKR
ENR C451-1
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 27, 2002
CY7C451
CY7C453
CY7C454
Functional Description (continued)
The CY7C451, CY7C453, and CY7C454 provide three status pins
to the user. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than or Equal to Half Full, Greater than
Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full
flag (PAFE) and XO functions share the same pin. The Almost Empty/Full flag is valid in the standalone and width expansion configurations. In the depth expansion, this pin provides the
expansion out (XO) information that is used to signal the
next FIFO when it will be activated.
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the CKR. The flags denoting
Half Full, Almost Full, and Full states are updated exclusively
by CKW. The synchronous flag architecture guarantees that
the flags maintain their status for some minimum time.
The CY7C451, CY7C453, and the CY7C454 use center power
and ground for reduced noise. Both configurations are fabricated using an advanced RAM 2.8 technology. Input ESD
protection is greater than 2001V, and latch-up is prevented
by the use of reliable layout techniques and guard rings.
The flags are synchronous, i.e., they change state relative to
either the read clock (CKR) or the write clock (CKW). When
Selection Guide
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Maximum Frequency (MHz)
83.3
71.4
50
33.3
Maximum Cascadable Frequency
83.3
71.4
50
33.3
Maximum Access Time (ns)
9
10
15
20
Minimum Cycle Time (ns)
12
14
20
30
Minimum Clock HIGH Time (ns)
5
6.5
9
12
Minimum Clock LOW Time (ns)
5
6.5
9
12
Minimum Data or Enable Set-Up (ns)
4
5
6
7
Minimum Data or Enable Hold (ns)
0
0
0
0
Maximum Flag Delay (ns)
9
10
15
20
Commercial
140
140
120
100
Military/Industrial
150
150
130
110
Maximum Current (mA)
Selection Guide (continued)
Density
OE, Depth Cascadable
Package
CY7C451
CY7C453
CY7C454
512 x 9
2,048 x 9
4,096 x 9
Yes
Yes
Yes
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ....................................−65°C to +150 °C
Latch-Up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.................................................−55°C to +125 °C
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
Commercial
0° C to +70 °C
5V ± 10%
−40°C to +85° C
5V ± 10%
DC Input Voltage .................................................−3.0V to +7.0V
Industrial
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
Document #: 38-06033 Rev. *A
Page 2 of 24
CY7C451
CY7C453
CY7C454
Pin Definitions
Signal
Name
I/O
Description
D0 – 8
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 – 8) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW then data is written into the FIFO’s
programming register. D8 is ignored if the device is configured for parity generation.
Q0 – 7
O
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 – 7)
out of the FIFO’s memory. If MR is active at the rising edge of CKR then data is read from the
programming register.
Q8/PG/PE
O
Function varies according to mode:
Parity disabled - same function as Q0 – 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
ENW
I
Enable Write: enables the CKW input (for both non-program and program modes)
ENR
I
Enable Read: enables the CKR input (for both non-program and program modes)
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
O
Half Full Flag - synchronized to CKW.
E/F
O
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
PAFE/XO
O
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
XI
I
Not Cascaded - XI is tied to VSS
Cascaded - Expansion Input, connected to XO of previous device
FL/RT
I
First Load/ Retransmit Pin:
Cascaded - the first device in the daisy chain will have FL tied to VSS; all other devices will have FL
tied to VCC (Figure 2)
Not Cascaded - tied to VCC;
Retransmit function is also available in stand alone mode by strobing RT
MR
I
Master Reset: resets device to empty condition.
Non-Programming Mode: program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D0 – 8 is written into the programmable register on the rising
edge of CKW. Program register contents appear on Q 0 – 8 after the rising edge of CKR.
OE
I
Output Enable for Q0 – 7 and Q8/PG/PE pins
Document #: 38-06033 Rev. *A
Page 3 of 24
CY7C451
CY7C453
CY7C454
Electrical Characteristics Over the Operating Range
7C451-12
7C453-12
7C454-12
Parameter
Description
Test Conditions
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH
Voltage
VCC = Min., IOH = −2.0 mA
VOL
Output LOW
Voltage
VCC = Min., IOL = 8.0 mA
VIH[2]
Input HIGH Voltage
2.2
VCC
2.2
VCC
2.2
VCC
VIL[2]
Input LOW Voltage
−0.5
0.8
−0.5
0.8
−0.5
0.8
IIX
Input Leakage
Current
VCC = Max.
−10
+10
−10
+10
−10
+10
−10
IOS[3]
Output Short
Circuit Current
VCC = Max., VOUT = GND
−90
IOZL
IOZH
Output OFF, High Z
Current
OE > VIH, VSS < VO < VCC
−10
ICC1[4]
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
140
140
Mil/Ind
150
150
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
70
Mil/Ind
Standby Current
VCC = Max.,
IOUT = 0 mA
Com’l
Mil/Ind
ICC2
[5]
ISB[6]
2.4
2.4
0.4
2.4
2.4
0.4
−90
−90
V
2.2
VCC
V
−0.5
0.8
V
+10
µA
−90
120
100
mA
130
110
mA
70
70
70
mA
80
80
80
80
mA
30
30
30
30
mA
30
30
30
30
mA
+10
−10
mA
µA
+10
−10
0.4
+10
+10
−10
0.4
V
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25° C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
12
pF
Notes:
2. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or VSS .
3. Test no more than one output at a time for not more than one second.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs
switch at f MAX/2. Outputs are unloaded.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX ).
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06033 Rev. *A
Page 4 of 24
CY7C451
CY7C453
CY7C454
AC Test Loads and Waveforms[8, 9, 10, 11, 12]
R1500Ω
ALL INPUT PULSES
5V
OUTPUT
3.0V
CL
R2
333Ω
INCLUDING
JIG AND
SCOPE
Equivalent to:
GND
< 3 ns
90%
10%
90%
10%
< 3 ns
C451-4
C451-5
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
Switching Characteristics Over the Operating Range[13]
7C451-12
7C453-12
7C454-12
Parameter
Description
Min.
Max.
7C451-14
7C453-14
7C454-14
Min.
Max.
7C451-20
7C453-20
7C454-20
Min.
Max.
7C451-30
7C453-30
7C454-30
Min.
Max.
Unit
tCKW
Write Clock Cycle
12
14
20
30
ns
tCKR
Read Clock Cycle
12
14
20
30
ns
tCKH
Clock HIGH
5
6.5
9
12
ns
tCKL
Clock LOW
5
tA[14]
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
0
ns
tSD
Data Set-Up
4
5
6
7
ns
tHD
Data Hold
0
0
0
0
ns
tSEN
Enable Set-Up
4
5
6
7
ns
tHEN
Enable Hold
0
0
0
0
ns
tOE
OE LOW to Output Data Valid
tOLZ[7,15]
OE LOW to Output Data in Low Z
tOHZ
[7,15]
6.5
9
9
0
9
10
10
0
12
15
15
0
ns
20
20
0
ns
ns
ns
OE HIGH to Output Data in High Z
9
10
15
20
ns
tPG
Read HIGH to Parity Generation
9
10
15
20
ns
tPE
Read HIGH to Parity Error Flag
9
10
15
20
ns
tFD
Flag Delay
9
10
15
20
ns
tSKEW1
[16]
Opposite Clock After Clock
0
0
0
0
ns
Notes:
8. CL = 30 pF for all AC parameters except for tOHZ .
9. CL = 5 pF for tOHZ .
10. All AC measurements are referenced to 1.5V except tOE , tOLZ, and tOHZ.
11. tOE and t OLZ are measured at ± 100 mV from the steady state.
12. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH .
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms
and capacitance as in notes 8 and 9, unless otherwise specified.
14. Access time includes all data outputs switching simultaneously.
15. At any given temperature and voltage condition, tOLZ is greater than t OHZ for any given device.
16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than t SKEW1 after the clock, the decision of whether or not to include the opposite clock in the current
clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost
Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the
clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
Document #: 38-06033 Rev. *A
Page 5 of 24
CY7C451
CY7C453
CY7C454
Switching Characteristics Over the Operating Range[13] (continued)
7C451-12
7C453-12
7C454-12
Parameter
Description
Min.
Max.
7C451-14
7C453-14
7C454-14
Min.
Max.
7C451-20
7C453-20
7C454-20
Min.
Max.
7C451-30
7C453-30
7C454-30
Min.
Max.
Unit
tSKEW2[17]
Opposite Clock Before Clock
12
14
20
30
ns
tPMR
Master Reset Pulse Width (MR LOW)
12
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled
Write/Read)
12
14
20
30
ns
tMRF
MR HIGH to Flags Valid
12
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
12
14
20
30
ns
tSMRP
Program Mode—MR LOW Set-Up
12
14
20
30
ns
tHMRP
Program Mode—MR LOW Hold
9
10
15
25
ns
tFTP
Program Mode—Write HIGH to Read HIGH
12
14
20
30
ns
tAP
Program Mode—Data Access Time
tOHP
Program Mode—Data Hold Time from MR
HIGH
0
0
0
0
tPRT
Retransmit Pulse Width
12
14
20
30
tRTR
Retransmit Recovery Time
12
14
20
30
12
14
20
30
ns
ns
17. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than t SKEW2 before the clock, the decision of whether or not to include the opposite clock in the
current clock cycle is arbitrary. See Note 16 for definition of clock and opposite clock.
Document #: 38-06033 Rev. *A
Page 6 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms
Write Clock Timing Diagram
tCKW
tCKH
CKW
tCKL
ENABLED WRITE
tSD
D0 – 8
DISABLED WRITE
tHD
VALID DATA IN
tSEN
tHEN
ENW
tSEN
tFH
tHEN
E/F, PAFE,HF
tFH
tFD
Read Clock Timing Diagram
tCKR
tCKH
CKR
DISABLED READ
tA
PREVIOUS WORD
tSEN
C451-6
tCKL
ENABLED READ
tOH
Q0 – 8
tFD
NEW WORD
tHEN
ENR
tSEN
tFH
tHEN
E/F,PAFE
tFH
tFD
tFD
C451-7
[18,19,20,21]
Master Reset (Default with Free-Running Clocks) Timing Diagram
tPMR
MR
tSCMR
tMRR
CKW
FIRST
WRITE
ENW
tSCMR
tMRR
CKR
ENR
tOHMR
Q0 – 8
tAMR
ALL DATA
OUTPUTS LOW
VALID DATA
tMRF
E/F,PAFE
tMRF
HF
Notes:
18. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW.
19. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW.
20. All data outputs (Q0 – 8 ) go LOW as a result of the rising edge of MR after t AMR.
21. In this example, Q0 – 8 will remain valid until t OHMR if either the first read shown did not occur or if the read occurred soon enough such that the valid
data was caused by it.
Document #: 38-06033 Rev. *A
Page 7 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram
[20,21]
tSMRP
tHMRP
MR
tSCMR
CKW
ENW
tCKH
tMRR
LAST
VALID
WRITE
PGM
WRITE
tHD
LAST
WORD
PGM
WORD
tSCMR
CKR
ENR
WORD 1
tSMRP
WORD 2
tHMRP
LAST
VALID
READ
PGM
READ
tCKH
LOW
tOHMR
Q0– 8
SECOND
WRITE
tFTP
LOW
tSD
D0– 8
FIRST
WRITE
tAP
VALID DATA
tOHP
tAMR
ALL DATA
OUTPUTS LOW
PGM WORD
C451-9
[20,21]
Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram
tSMRP
tHMRP
tCKW
MR
tSCMR
CKW
tCKH
LAST
VALID
WRITE
tCKL
tMRR
PGM
WRITE
tSEN
FIRST
WRITE
SECOND
WRITE
tHEN
ENW
tFTP
D0– 8
LAST
WORD
PGM
WORD
WORD 1
WORD 2
tCKR
tSCMR
CKR
tSMRP
tMRR
tHMRP
PGM
READ
LAST
VALID
READ
tCKH
tSEN
tCKL
tHEN
ENR
tOHMR
Q0– 8
VALID DATA
tAP
tOHP
PGM WORD
tAMR
ALL DATA
OUTPUTS LOW
C451-10
Document #: 38-06033 Rev. *A
Page 8 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
[22,25,26]
Read to Empty Timing Diagram
COUNT
3
1
2
1
0
1 (NO CHANGE)
0
LATENTCYCLE
CKR
R2
ENABLED
READ
R1
ENABLED
READ
R3
ENABLED
READ
R4
FLAG
UPDATE
READ
R5
ENABLED
READ
tFD
tFD
ENR
tSKEW1
tSKEW2
W1
ENABLED
WRITE
CKW
LOW
ENW
tFD
E/F
PAFE
LOW
C451-12
Read to Empty Timing Diagram with Free-Running Clocks
COUNT
1
CKR
0
[22,23,24,25]
LATENTCYCLE
1
R1
ENABLED
READ
R2
IGNORED
READ
R3
IGNORED
READ
tSKEW2
R4
FLAG
UPDATE
READ
0
R5
ENABLED
READ
R6
IGNORED
READ
ENR
tSKEW1
W1
CKW
tSKEW2
W2
W3
ENABLED
WRITE
W4
W5
W6
ENW
HIGH
HF
tFD
tFD
tFD
E/F
PAFE
LOW
C451-11
Notes:
22. “Count” is the number of words in the FIFO.
23. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than t SKEW2 before R4, R4 includes
W3 in the flag update.
25. CKR is clock; CKW is opposite clock.
26. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than t SKEW1 after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs greater than tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty
state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count
or the FIFO’s data outputs.
Document #: 38-06033 Rev. *A
Page 9 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks
COUNT
17
16
17
R1
ENABLED
READ
CKR
[22,25,27]
18
R2
17
R3
16
R4
ENABLED
READ
15
R6
ENABLED
READ
R5
ENABLED
READ
ENR
tSKEW1
CKW
tSKEW2
W2
ENABLED
WRITE
W1
W3
ENABLED
WRITE
W4
W5
W1
W6
ENW
HIGH
HF
HIGH
E/F
tFD
tFD
tFD
PAFE
C451-14
[22,25,27,28,29]
Read to Almost Empty Timing Diagram with Read Flag Cycle and Update Free-Running Clocks
18 (no change)
COUNT
17
CKR
17
16
R1
ENABLED
READ
FLAG UPDATE CYCLE
18
R2
R3
R4
FLAG
UPDATE
READ
17
15
16
R5
ENABLED
READ
R6
ENABLED
READ
R7
ENABLED
READ
W5
W6
W7
ENR
tSKEW1
CKW
tSKEW2
W2
ENABLED
WRITE
W1
W3
ENABLED
WRITE
W4
ENW
HF
E/F
HIGH
HIGH
tFD
tFD
tFD
PAFE
C451-13
Notes:
27. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full.
28. R4 only updates the flag status. It does not affect the count because ENR is HIGH.
29. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 =>18; two enabled writes: W2, W3) before a read
(R4) can update flags to the Less Than Half Full state.
Document #: 38-06033 Rev. *A
Page 10 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks
COUNT
1024
[256]
CKW
1024
[256]
1025
[257]
W1
ENABLED
WRITE
[22,30,31,32]
1024
[256]
1023
[255]
W2
W3
W4
ENABLED
WRITE
1025
[257]
1026
[258]
W5
ENABLED
WRITE
W6
ENABLED
WRITE
ENW
tSKEW1
CKR
tSKEW2
R2
ENABLED
READ
R1
R3
ENABLED
READ
R4
R5
R6
ENR
tFD
tFD
tFD
HF
HIGH
E/F
HIGH
PAFE
C451-15
Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks
[22,30,31,32,33,34]
1023 (no change)
[255]
COUNT 1024
[256]
CKW
1025
[257]
1024
[256]
W1
ENABLED
WRITE
W2
FLAG UPDATE CYCLE
1023
[255]
W3
1024
[256]
1025
[257]
1026
[258]
W4
FLAG
UPDATE
WRITE
W5
ENABLED
WRITE
W6
ENABLED
WRITE
W7
ENABLED
WRITE
R4
R5
R6
R7
ENW
tSKEW1
CKR
tSKEW2
R2
ENABLED
READ
R1
R3
ENABLED
READ
ENR
tFD
tFD
tFD
HF
E/F
PAFE
HIGH
HIGH
C451-16
Notes:
30. CKW is clock and CKR is opposite clock.
31. Count = 2,049 indicates Half Full for the CY7C454, count=1,025 indicates Half Full for the CY7C453, and count = 257 indicates Half Full for the CY7C451.
Values for CY7C451 count are shown in brackets.
32. When the FIFO contains 2048[1024,256] words, the rising edge of the next enabled write causes the HF to be true (LOW).
33. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH.
34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (1,025 =>1,023; two enabled reads: R2 and R3) before
a write (W4) can update flags to less than Half Full.
Document #: 38-06033 Rev. *A
Page 11 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Write to Almost Full Timing Diagram
COUNT
2030
[494]
2032
[496]
2031
[495]
CKW
[22,27,30,35,36]
W1
ENABLED
WRITE
2030
[494]
2031
[495]
W2
ENABLED
WRITE
2031
[495]
2032
[496]
2033
[497]
2030
[494]
2031
[495]
2032
[496]
W3
ENABLED
WRITE
W4
ENABLED
WRITE
W5
ENABLED
WRITE
FLAG UPDATE
ENW
tSKEW1
tSKEW2
R1
ENABLED
READ
CKR
R2
ENABLED
READ
ENR
tFD
tFD
tFD
tFD
PAFE
LOW
HF
E/F
HIGH
C451-18
Write to Almost Full Timing Diagram with Free-Running Clocks
COUNT
2031
[495]
CKW
2032
[496]
W1
ENABLED
WRITE
2031
[495]
W2
[22,27,30]
2031
[495]
2030
[494]
W3
W4
ENABLED
WRITE
2032
[496]
2033
[497]
W5
ENABLED
WRITE
W6
ENABLED
WRITE
ENW
tSKEW1
R2
ENABLED
READ
R1
CKR
tSKEW2
R3
ENABLED
READ
R4
R6
R5
ENR
HF
LOW
E/F
HIGH
tFD
tFD
tFD
PAFE
C451-17
Notes:
35. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than t SKEW1 after W2, W2 does not recognize R1 when
updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be
enabled to update flags.
36. The dashed lines show W3 as a flag update write rather than an enabled write because ENW is deasserted.
Document #: 38-06033 Rev. *A
Page 12 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks
[22,27,30]
2030 (no change)
[494]
COUNT 2031
[495]
CKW
2032
[496]
2031
[495]
W1
ENABLED
WRITE
FLAG UPDATE CYCLE
2030
[494]
W2
W3
W4
FLAG
UPDATE
WRITE
2031
[495]
2032
[496]
2033
[497]
W5
ENABLED
WRITE
W6
ENABLED
WRITE
W7
ENABLED
WRITE
R5
R6
R7
ENW
tSKEW1
CKR
tSKEW2
R1
R2
ENABLED
READ
R4
R3
ENABLED
READ
ENR
LOW
HF
HIGH
E/F
tFD
tFD
tFD
PAFE
C451-19
Write to Full Flag Timing Diagram with Free-Running Clocks
COUNT
2047
[511]
CKW
2048
[512]
[22,23,30,37]
LATENT CYCLE
2047
[511]
W1
ENABLED
WRITE
W2
IGNORED
WRITE
W3
IGNORED
WRITE
tSKEW2
W4
FLAG
UPDATE
WRITE
2048
[512]
W5
ENABLED
WRITE
W6
IGNORED
WRITE
ENW
tSKEW1
CKR
tSKEW2
R2
R1
R3
ENABLED
READ
R4
R6
R5
ENR
HF
LOW
tFD
tFD
tFD
E/F
LOW
PAFE
C451-20
Notes:
37. W2 is ignored because the FIFO is full (count = 4096[2048,512]). It is important to note that W3 is also ignored because R3, the first enabled read after full,
occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than t SKEW2 before W4, W4
includes R3 in the flag update.
Document #: 38-06033 Rev. *A
Page 13 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Even Parity Generation Timing Diagram
CKR
[38,39]
ENABLED READ
DISABLED READ
tPG
Q8/PG/PE
Q0– 7
PREVIOUS WORD:
EVEN NUMBER OF 1s
NEW WORD
ODD NUMBER OF 1s
ENR
C451-21
[38,40]
Even Parity Generation Timing Diagram
CKR
ENABLED READ
DISABLED READ
tPG
Q8/PG/PE
Q0– 7
PREVIOUS WORD:
ODD NUMBER OF 1s
NEW WORD
EVEN NUMBER OF 1s
ENR
C451-22
Notes:
38. In this example, the FIFO is assumed to be programmed to generate even parity.
39. If Q0 – 7 “new word” also has an even number of 1s, then PG stays LOW.
40. If Q0 – 7 “new word” also has an odd number of 1s, then PG stays HIGH.
Document #: 38-06033 Rev. *A
Page 14 of 24
CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Even Parity Checking [41]
CKW
WRITE M+1
WRITE M
WRITE M+2
ENW
WORD M:
EVEN NUMBER
OF “1”s
D0– 8
WORD M+ 1:
ODD NUMBER
OF “1”s
WORD M+ 2:
EVEN NUMBER
OF “1”s
CKR
READ M
READ M+1
READ M+2
ENR
tPE
tPE
F1
Q8/PG/
PE
8 LSBs OF
WORD M-1
Q0– 7
8 LSBs OF
WORD M
8 LSBs OF
WORD M+1
8 LSBs OF
WORD M+2
C451-23
Output Enable Timing
[42,43]
CKR
ENR
READ M+1
LOW
OE
tOHZ
Q0– 8
tOE
VALID DATA
WORD M
VALID DATA
WORD M+1
tOLZ
C451-24
Retransmit Timing[44, 45]
FL/RT
tPRT
tRTR
ENR/ENW
E/F,HF,PAFE
C451–25
Notes:
41. In this example, the FIFO is assumed to be programmed to check for even parity.
42. This example assumes that the time from the CKR rising edge to valid word M+1 > tA.
43. If ENR was HIGH around the rising edge of CKR (i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1.
44. Clocks are free running in this case.
45. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
Document #: 38-06033 Rev. *A
Page 15 of 24
CY7C451
CY7C453
CY7C454
Architecture
The CY7C451, CY7C453, and CY7C454 consist of an array
of 512/2048/4096 words of 9 bits each (implemented by an
array of dual-port RAM cells), a read pointer, a write pointer,
control signals (CKR, CKW, ENR, ENW, MR, OE, FL/RT, XI,
XO), and flags (HF, E/F, PAFE).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty condition signified by E/F and PAFE being LOW and HF being
HIGH. All data outputs (Q0 − 8) go low at the rising edge of
MR. In order for the FIFO to reset to its default state, a
falling edge must occur on MR and the user must not read
or write while MR is LOW (unless ENR and ENW are HIGH
or unless the device is being programmed). Upon completion of the Master Reset cycle, all data outputs will go LOW
tAMR after MR is deasserted. All flags are guaranteed to be
valid tMRF after MR is taken HIGH.
FIFO Operation
When the ENW signal is active (LOW), data present on the
D0 − 8 pins is written into the FIFO on each rising edge of
the CKW signal. Similarly, when the ENR signal is active,
data in the FIFO memory will be presented on the Q0 − 8
outputs. New data will be presented on each rising edge of
CKR while ENR is active. ENR must be set up t SEN before
CKR for it to be a valid read function. ENW must occur tSEN
before CKW for it to be a valid write function.
An output enable (OE) pin is provided to tri-state the Q0 − 8
outputs when OE is not asserted. When OE is enabled,
data in the output register will be available to Q0 − 8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0 − 8 outputs
even after additional reads occur.
Programming
The CY7C451, CY7C453, and CY7C454 are programmed
during a master reset cycle. If MR and ENW are LOW, a
rising edge on CKW will write D0 − 8 inputs into the programming register. MR must be set up a minimum of tSMRP before the program write rising edge and held tHMRP after the
program write falling edge. The user has the ability to also
perform a program read during the master reset cycle. This
will occur at the rising edge of CKR when MR and ENR are
asserted. The program read must be performed a minimum
of tFTP after a program write, and the program word will be
available tAP after the read occurs. If a program write does
not occur, a program read may occur a minimum of tSMRP
after MR is asserted. This will read the default program
value.
When free-running clocks are tied to CKW and CKR, programming can still occur during a master reset cycle with the adherence to a few additional timing parameters. The enable pins
must be set-up tSEN before the rising edge of CKW or CKR.
Hold times of tHEN must also be met for ENW and ENR.
Data present on D0 − 5 during a program write will determine
the distance from Empty (Full) that the Almost Empty (Almost Full) flags will become active. See Table 1 for a
description of the six possible FIFO states. P in 1 refers to
the decimal equivalent of the binary number represented
by D0 − 5. Programming options for the CY7C451 and
CY7C453 are listed in Table 5. Programming resolution is
16 words for either device.
The programmable PAFE function is only valid when the
CY7C451/453/454 are not cascaded. If the user elects not
to program the FIFO’s flags, the default (P=1) is as follows:
Almost Empty condition (Almost Full condition) is activated
when the CY7C451/453/454 contain 16 or less words
(empty locations).
Parity is programmed with the D6 − 8 bits. See Table 6 for a
summary of the various parity programming options. Data
present on D6 − 8 during a program write will determine
whether the FIFO will generate or check even/odd parity for
the data present on D0−8 thereafter. If the user elects not
to program the FIFO, the parity function is disabled. Flag
operation and parity are described in greater detail in subsequent sections.
Flag Operation
The CY7C451/453/454 provide three status pins when not
cascaded. The three pins, E/F, PAFE, and HF, allow decoding of six FIFO states (Table 1). PAFE is not available when
FIFOs are cascaded for depth expansion. All flags are synchronous, meaning that the change of states is relative to
one of the clocks (CKR or CKW, as appropriate. See Figure
1). The synchronous architecture guarantees some minimum valid time for the flags. The Empty and Almost Empty
flag states are exclusively updated by each rising edge of
the read clock (CKR). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while
ENR=LOW) causes the flag pins to output a state that represents Empty. The Half Full, Almost Full, and Full flag
states are updated exclusively by the write clock (CKW).
For example, if the CY7C453 FIFO contains 2047 words
(2048 words indicate Full for the CY7C453), the next write
(rising edge of CKW while ENW=LOW) causes the flag pins
to output a state that is decoded as Full.
]
Table 1. Flag Truth Table[46].
E/F
0
PAFE
0
HF
1
State
Empty
1
1
0
1
1
1
Almost Empty
Less than or
Equal to Half Full
Document #: 38-06033 Rev. *A
CY7C451 512 x 9
Number of Words
in FIFO
0
1⇒(16•P)
(16•P)+1⇒256
CY7C453 2K x 9
Number of Words
in FIFO
0
CY7C454 4K x 9
Number of Words
in FIFO
0
1 ⇒(16•P)
(16•P)+1⇒1024
1 ⇒(16•P)
(16•P)+1⇒2048
Page 16 of 24
CY7C451
CY7C453
CY7C454
Table 1. Flag Truth Table[46].
E/F
PAFE
HF
State
1
1
0
1
0
0
Greater than Half
Full
Almost Full
0
0
0
Full
CY7C451 512 x 9
Number of Words
in FIFO
CY7C453 2K x 9
Number of Words
in FIFO
CY7C454 4K x 9
Number of Words
in FIFO
2049 ⇒ 4095−(16•P)
257⇒511−(16•P)
1025⇒2047−(16•P)
512− (16•P) ⇒ 511
2048−(16•P) ⇒ 2047 4096−(16•P) ⇒4095
512
2048
4096
Notes:
46. P is the decimal value of the binary number represented by D0 - 5. When programming the CY7C451/453/454, P can have values from 0 to 15 for the
CY7C451 and values from 0 to 63 for the CY7C453 and CY7C454. See Table 5 for D0 - 5 representation. P = 0 signifies Almost Empty state = Empty
state.
dates the flag. If a write occurs at least tSKEW2 before a
read, the write is guaranteed to be included when CKR
updates flag. If a write occurs within tSKEW1/tSKEW2 after or
before CKR, then the decision of whether or not to include
the write when the flag is updated by CKR is arbitrary.
D Q
E
CKR
E/F
F
D Q
CKW
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the
boundary flags (Empty, Full). Both operations are described
below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
D Q
PAE
CKR
PAFE
PAF
CKW
HF
D Q
D Q
HF
CKW
INTERNAL LOGIC
PIN
Figure 1. Flag Logic Diagram.
Flag Operation (continued)
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half
Full, Almost Full, Full) are exclusively updated by CKW, careful
attention must be given to the flag operation. The user must
be aware that if a boundary (Empty, Almost Empty, Half Full,
Almost Full, or Full) is crossed due to an operation from a clock
that the flag is not synchronized to (i.e., CKW does not affect
Empty or Almost Empty), a flag update cycle is necessary to
represent the FIFO’s new state. The signal to which a flag is
not synchronized will be referred to as the opposite clock
(CKW is opposite clock for Empty and Almost Empty flags;
CKR is the opposite clock for Half Full, Almost Full, and Full
flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the FIFO.
When updating flags, the CY7C451/453/454 must make a decision as to whether or not the opposite clock was recognized
when a clock updates the flag. For example (when updating
the Empty flag), if a write occurs at least tSKEW1 after a read,
the write is guaranteed not to be included when CKR up-
Document #: 38-06033 Rev. *A
The Empty flag is synchronized to the CKR signal (i.e., the
Empty flag can only be updated by a clock pulse on the CKR
pin). An empty FIFO that is written to will be described with an
Empty flag state until a rising edge is presented to the CKR
pin. When making the transition from Empty to Almost Empty
(or Empty to Less than or Equal to Half Full), a clock cycle on
the CKR is necessary to update the flags to the current state.
In such a state (flags showing Empty even though data has
been written to the FIFO), two read cycles are required to read
data out of FIFO. The first read serves only to update the flags
to the Almost Empty or Less than or Equal to Half Full state,
while the second read outputs the data. This first read cycle is
known as the latent or flag update cycle because it does not
affect the data in the FIFO or the count (number of words in
FIFO). It simply deasserts the Empty flag. The flag is updated
regardless of the ENR state. Therefore, the update occurs
even when ENR is unasserted (HIGH), so that a valid read
is not necessary to update the flags to correctly describe
the FIFO. In this example, the write must occur at least
tSKEW2 before the flag update cycle in order for the FIFO to
guarantee that the write will be included in the count when
CKR updates the flags. When a free-running clock is connected to CKR, the flag is updated each cycle. Table 2
shows an example of a sequence of operations that update
the Empty flag.
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (i.e., the Full
flag can only be updated by a clock pulse on the CKW pin). A
full FIFO that is read will be described with a Full flag until a
rising edge is presented to the CKW pin. When making the
transition from Full to Almost Full (or Full to Greater Than Half
Full), a clock cycle on the CKW is necessary to update the
flags to the current state. In such a state (flags showing Full
even through data has been read from the FIFO), two write
cycles are required to write data into the FIFO. The first write
serves only to update the flags to the Almost Full or Greater
Page 17 of 24
CY7C451
CY7C453
CY7C454
Than Half Full state, while the second write inputs the data.
This first write cycle is known as the latent or flag update cycle
because it does not affect the data in the FIFO or the count
(number of words in the FIFO). It simply deasserts the Full flag.
The flag is updated regardless of the ENW state. Therefore,
the update occurs even when ENW is deasserted (HIGH),
so that a valid write is not necessary to update the flags to
correctly describe the FIFO. In this example, the read must
occur at least tSKEW2 before the flag update cycle in order
for the FIFO to guarantee that the read will be included in
the count when CKW updates the flags. When a free-running clock is connected to CKW, the flag updates each cycle. Full flag operation is similar to the Empty flag operation
described in Table 2.
Non-Boundary Flags (Almost Empty, Half Full, Almost Full)
The CY7C451/453/454 feature programmable Almost Empty
and Almost Full flags. Each flag can be programmed a specific
distance from the corresponding boundary flags (Empty or
Full). The flags can be programmed to be activated at the
Empty or Full boundary, or at a distance of up to 1008
words/locations for the CY7C453 and CY7C454 (240
words/locations for the CY7C451) from the Empty/Full boundary. The programming resolution is 16 words/locations. When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAFE flag will be asserted
signifying that the FIFO is Almost Empty. When the FIFO is
within that same number of empty locations from being Full,
the PAFE will also be asserted signifying that the FIFO is
Almost Full. The HF flag is decoded to distinguish the
states.
The default distance (CY7C451/453/454 not programmed)
from where PAFE becomes active to the boundary (Empty,
Full) is 16 words/locations. The Almost Full and Almost
Empty flags can be programmed so that they are only active at Full and Empty boundaries. However, the operation
will remain consistent with the non-boundary flag operation
that is discussed below.
Almost Empty is only updated by CKR while Half Full and Almost Full are updated by CKW. Non-boundary flags employ
flag update cycles similar to the boundary flag latent cycles in
order to update the FIFO status. For example, if the FIFO just
reaches the Greater than Half Full state, and then two words
are read from the FIFO, a write clock (CKW) will be required
to update the flags to the Less than Half Full state. However,
unlike the boundary flag latent cycle, the state of the enable
pin (ENW in this case) affects the operation. Therefore,
set-up and hold times for the enable pins must be met (tSEN
and tHEN). If the enable pin is active during the flag update
cycle, the count and data are updated in addition to PAFE
and HF. If the enable pin is not asserted during the flag
update cycle, only the flags are updated. Table 3 and Table
4 show an example of a sequence of operations that update
the Almost Empty and Almost Full flags.
Programmable Parity
The CY7C451/453/454 also features even or odd parity checking and generation. D6 − 8 are used during a program write
to describe the parity option desired. Table 6 gives a summary of programmable parity options. If the user elects not
to program the device, then parity is disabled. Parity information is provided on one multi-mode output pin
(Q8/PG/PE). The three possible modes are described in
the following paragraphs. Regardless of the mode selected, the OE pin retains three-state control of all 9 Q 0 − 8 bits.
Table 2. Empty Flag (Boundary Flag) Operation Example.
Status Before Operation
Current
Number
State of
of Words
FIFO
E/F AFE HF
in FIFO
Empty
0
0
1
0
Empty
0
0
1
1
Empty
0
0
1
2
AE
1
0
1
2
AE
1
0
1
1
Empty
0
0
1
0
Empty
1
0
1
1
AE
1
0
1
1
Operation
Write
(ENW = 0)
Write
(ENW = 0)
Read
(ENR = X)
Read
(ENR = 0)
Read
(ENR = 0)
Write
(ENR = 0)
Read
(ENR = X)
Read
(ENR = 0)
Status After Operation
Next
Number
State
of words
of FIFO
E/F AFE HF in FIFO
Empty
0
0
1
1
Write
Empty
0
0
1
2
Write
AE
1
0
1
2
Flag Update
AE
1
0
1
1
Read
Empty
0
0
1
0
Empty
0
0
1
1
Read (transition from
Almost Empty to Empty)
Write
AE
1
0
1
1
Flag Update
Empty
0
0
1
0
Read (transition from
Almost Empty to Empty)
Parity Disabled (Q8 mode)
When parity is disabled (or user does not program parity option) the CY7C451/453/454 stores all 9 bits present on D0 − 8
inputs internally and will output all 9 bits on Q0 − 8 Parity
Generate (PG mode).
Document #: 38-06033 Rev. *A
Comments
This mode is used to generate either even or odd parity (as
programmed) from D0 − 7. D8 input is ignored. The parity bit
is stored internally as D8 and during a subsequent read will
be available on the PG pin along with the data word from
which the parity was generated (Q 0 − 7). For example, if
Page 18 of 24
CY7C451
CY7C453
CY7C454
parity generate is set to ODD and the D 0 − 7 inputs have an
EVEN number of 1s, PG will be HIGH.
Parity Check (PE mode)
If the CY7C451/453/454 is programmed for parity checking,
the FIFO will compare the parity of D0 − 8 with the program
register. If the expected parity is present, D8 will be set
HIGH internally. When this word is later read, PE will be
HIGH. If a parity error occurs, D8 will be set LOW internally.
When this word is later read, PE will be LOW. For example,
if parity check is set to odd and D0 − 8 have an even number
of 1s, a parity error occurs. When that word is later read,
PE will be asserted (LOW).
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. WCLK and RCLK may be free running but must be disabled
during and tRTR after the retransmit pulse. With every valid read cycle
after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Modes
During width expansion all flags (programmable and nonprogrammable) are available. The CY7C451/453/454 can be expanded in width to provide word width greater than nine in
increments of nine. During width expansion mode all control
line inputs are common. When the FIFO is being read near the
Empty (Full) boundary, it is important to note that both sets of
flags should be checked to see if they have been updated to
the Not Empty (Not Full) condition to insure that the next read
(write) will perform the same operation on all devices.
Checking all sets of flags is critical so that data is not read from
the FIFOs “staggered” by one clock cycle. This situation could
Document #: 38-06033 Rev. *A
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than tSKEW2 after the
first write to two width-expanded devices, A and B, device
A may go Almost Empty (read recognized as flag update)
while device B stays Empty (read ignored). This occurs because a read can be either recognized or ignored if it occurs within tSKEW2 of a write. The next read cycle outputs
the first half of the first word on device A while device B
updates its flags to Almost Empty. Subsequent reads will
continue to output “staggered” data assuming more data
has been written to the FIFOs.
Depth Expansion Mode
The CY7C451/453/454 can operate up to 83.3 MHz when cascaded. Depth expansion is accomplished by connecting expansion out (XO) of the first device to expansion in (XI) of
the next device, with XO of the last device connected to XI
of the first device. The first device has its first load pin (FL)
tied to VSS while all other devices must have this pin tied
to VCC. The first device will be the first to be write and read
enabled after a master reset.
Proper operation also requires that all cascaded devices have
common CKW, CKR, ENW, ENR, D0 − 8, Q0 − 8, and MR pins.
When cascaded, one device at a time will be read enabled
so as to avoid bus contention. By asserting XO when appropriate, the currently enabled FIFO alerts the next FIFO
that it should be enabled. The next rising edge on CKR puts
Q0 − 8 outputs of the first device into a high-impedance
state. This occurs regardless of the state of ENR or the next
FIFO’s Empty flag. Therefore, if the next FIFO is empty or
undergoing a latent cycle, the Q0 − 8 bus will be in a high-impedance state until the next device receives its first read,
which brings its data to the Q0 − 8 bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single
device. Because the controls of the FIFOs are in parallel when
cascaded, they all get programmed the same. During program
mode, only parity is programmed since Almost Full and Almost
Empty flags are not available when CY7C451/453/454 are
cascaded. Only the “first device” (FIFO with FL=LOW) will
output its program register contents on Q0 − 8 during a program read. Q0 − 8 of all other devices will remain in a
high-impedance state to avoid bus contention.
Page 19 of 24
CY7C451
CY7C453
CY7C454
CKW
ENW
CKR
ENR
XI
D0 – 8
Q0 – 8
CKW
CKR
CY7C451/3/4
ENW
ENR
MR
DATA IN
OE
D0– 8
MR
HF
E/F
FL/RT
PAFE/XO
DATA OUT
Q0– 8
VSS
OE
XI
D0 – 8
Q0 – 8
CKW
CKR
ENW
ENR
CY7C451/3/4
HF
MR
OE
E/F
FL/RT
PAFE/XO
FULL
EMPTY
VCC
Figure 2. Depth Expansion with CY7C451/3/4.
Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[47] .
Status Before Operation
Status After Operation
E/F
AFE
HF
Number of
Words
in FIFO
E/F
PAFE
HF
Number
of words
in FIFO
AE
1
0
1
32
Write
(ENW = 0)
AE
1
0
1
33
Write
AE
1
0
1
33
Write
(ENW = 0)
AE
1
0
1
34
Write
AE
1
0
1
34
Read
(ENR = 0)
<HF
1
1
1
33
Flag Update and Read
<HF
1
1
1
33
Read
(ENR = 1)
<HF
1
1
1
33
Ignored Read
(ENR = 1)
<HF
1
1
1
33
Read
(ENR = 0)
AE
1
0
1
32
Read (Transition from
<HF to AE)
Current
State of
FIFO
Operation
Next
State
of FIFO
Comments
Notes:
47. Applies to both CY7C451, CY7C453, and CY7C454 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains
32 or fewer words.
Document #: 38-06033 Rev. *A
Page 20 of 24
CY7C451
CY7C453
CY7C454
.]
Table 4. Almost Full Flag Operation Example[48] .
E/F
PAFE
HF
Number of
Words in
FIFO
CY7C451
Read
(ENR=0)
Current
AF
1
0
0
496
2032
4080
Next
AF
1
0
0
495
2031
4079
Read
(ENR=0)
Current
AF
1
0
0
495
2031
4079
Next
AF
1
0
0
494
2030
4078
Write
(ENW=1)
Current
AF
1
0
0
494
2030
4078
Next
AF
1
1
0
494
2030
4078
Write
(ENW=0)
Current
>HF
1
1
0
494
2030
4078
Next
>HF
1
1
0
495
2031
4079
Write
(ENW =0)
Current
>HF
1
1
0
495
2031
4079
Next
>HF
1
0
0
496
2032
4080
State
of FIFO
Operation
Number of
Words in
FIFO
CY7C453
Number
of Words
in FIFO
CY7C454
Comments
Read
Read
Flag Update
Write
Write (Transition
from >HF to AF)
Table 5. Programmable Almost Full/Almost Empty Options - CY7C451/CY7C453/CY7C454[49] .
PAFE Active when CY7C451/453/454 is:
P[50]
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Completely Full and Empty.
0
0
0
0
0
0
1
16 or less locations from Empty/Full (default)
1
0
0
0
0
1
0
32 or less locations from Empty/Full
2
0
0
0
0
1
1
48 or less locations from Empty/Full
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
1
1
1
0
224 or less locations from Empty/Full
14
0
0
1
1
1
1
240 or less locations from Empty/Full
15
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
0
992 or less locations from Empty/Full
62
1
1
1
1
1
1
1008 or less locations from Empty/Full
63
.
.
.
.
.
.
.
.
.
.
.
.
Table 6. Programmable Parity Options.
D8
D7
D6
Condition
0
X
X
Parity disabled.
1
0
0
Generate even parity on PG output pin.
1
0
1
Generate odd parity on PG output pin.
1
1
0
Check for even parity. Indicate error on PE output pin.
1
1
1
Check for odd parity. Indicate error on PE output pin.
Notes:
48. Programmed so that Almost Full becomes active when the FIFO contains 16 or less empty locations.
49. D4 and D5 are don’t care for CY7C451.
50. Referenced in Table 1.
Document #: 38-06033 Rev. *A
Page 21 of 24
CY7C451
CY7C453
CY7C454
Ordering Information
512x9 Clocked FIFO
Speed
(ns)
12
14
20
30
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C451-12JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C451-12JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-14JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C451-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-20JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C451-20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C451-30JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
2Kx9 Clocked FIFO
Speed
(ns)
12
14
20
30
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C453-12JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453-12JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-14JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-20JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453-20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453-30JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
4Kx9 Clocked FIFO
Speed
(ns)
12
14
20
30
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C454-12JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C454-12JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C454-14JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C454-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C454-20JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C454-20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C454-30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C454-30JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
Document #: 38-06033 Rev. *A
Page 22 of 24
CY7C451
CY7C453
CY7C454
Package Diagram
32-Lead Plastic Leaded Chip Carrier J65
Document #: 38-06033 Rev. *A
Page 23 of 24
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C451
CY7C453
CY7C454
Document Title: CY7C451, CY7C453, CY7C454 512 x 9, 2K x 9, and 4K x 9, Cascadable Clocked FIFOs with Programmable Flags
Document Number: 38-06033
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110174
09/29/01
SZV
Change from Spec number: 38-00125 to 38-06033
*A
122284
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
Document #: 38-06033 Rev. *A
Page 24 of 24