LINER LTC4244IGN-1 Rugged, compactpci bus hot swap controller Datasheet

LTC4244/LTC4244-1
Rugged, CompactPCI Bus
Hot Swap Controllers
U
FEATURES
■
■
■
■
■
■
■
■
DESCRIPTIO
Controls –12V, 3.3V, 5V and 12V Supplies
±14.4V Absolute Maximum Rating for 12VIN
and –12VIN Input Pins
Insensitive to Supply Voltage Transients
Adjustable Foldback Current Limit with Circuit Breaker
LOCAL_PCI_RST# Logic On-Chip
PRECHARGE Output Biases I/O Pins During Card
Insertion and Extraction
LTC4244-1 Designed for Applications without –12V
Available in 20-Lead Narrow SSOP Package
U
APPLICATIO S
■
Hot Board Insertion into CompactPCI Bus
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
The LTC®4244/LTC4244-1 are Hot SwapTM controllers that
allow a board to be safely inserted into and removed from
a CompactPCITM bus slot. External N-channel transistors
control the 5V and 3.3V supplies while on-chip switches
control the ±12V supplies. The 3.3V and 5V supplies can
be ramped up at an adjustable rate. Electronic circuit
breakers protect all four supplies against overcurrent
faults. After the power-up cycle is complete, the TIMER pin
capacitor serves as auxiliary VCC allowing the LTC4244/
LTC4244-1 to function without interruption in the presence of voltage spikes on the 12VIN supply. The PWRGD
output indicates when all four supplies are within tolerance. The OFF/ON pin is used to cycle board power or reset
the circuit breaker. The PRECHARGE output can be used
to bias the bus I/O pins during card insertion and extraction. PCI_RST# is combined on-chip with HEALTHY# in
order to generate LOCAL_PCI_RST#.
U
TYPICAL APPLICATIO
C8
0.01µF PER
POWER PIN
5V
C9
0.01µF PER
POWER PIN
R1
0.005Ω
3.3VIN
R21
1.8Ω
Z1
CLOAD(5VOUT)
Q1
IRF7457
CLOAD(3.3VOUT)
Z3
Z2
R4
10Ω
R3
10Ω
Z4
C7
0.01µF
3.3VIN 3.3VSENSE GATE 3.3VOUT 5VIN
12VIN
12V
5VSENSE
C1
R5 0.33µF
1k
5VOUT
12VOUT
VEEIN
–12V
CLOAD(12VOUT)
OFF/ON
LTC4244
HEALTHY#
PWRGD
PCI_RST#
RESETIN
TIMER
DRIVE RESETOUT
GND PRECHARGE
R15
1Ω
C4
0.01µF
R16
1Ω
C5
0.01µF
C3 4.7nF
GROUND
I/O PIN 1
I/O PIN 128
R13
10Ω
I/O DATA LINE 1
•
•
•
I/O DATA LINE 128
Z1, Z2: SMAJ12A
•
•
•
+
FAULT
R17
10k
R10 18Ω
VEEOUT
–12V
100mA
VEEOUT
R18 10k
LONG V(I/O)
VOUT
12V
500mA
+
R19 1k
BD_SEL#
R20
1.2k
VOUT
3.3V
7A
+
LONG 3.3V
C6
0.01µF
VOUT
5V
5A
+
R22
2.7Ω
LONG 5V
3.3V
R2
Q2
0.007Ω IRF7457
5VIN
R11
10k
R12
10k
R9 24Ω
Z3, Z4: SMAJ5.0A
C2
0.082µF
R6
10k
LOCAL_PCI_RST#
VOUT
3.3V
R8 1k
Q3
R7 12Ω
1V MMBT2222A
±10%
R14
10Ω
CLOAD(VEEOUT)
•
•
•
VIN
3.3V
RESET#
I/O #1
I/O #128
PCI
BRIDGE
CHIP
4244 F01
Figure 1. Typical Compact PCI Application
42441f
1
LTC4244/LTC4244-1
W W
W
AXI U
U
ABSOLUTE
RATI GS
U
U
W
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2, 3)
Supply Voltages
12VIN ................................................................ 14.4V
VEEIN .............................................................. –14.4V
Input Voltages (OFF/ON, RESETIN) ........– 0.3V to 13.5V
Output Voltages (FAULT, PWRGD, RESETOUT)
...........................................................– 0.3V to 13.5V
Analog Voltages and Currents
5VOUT, DRIVE, 5VIN, 3.3VSENSE, 3.3VIN, 3.3VOUT, 5VSENSE
...........................................................– 0.3V to 13.5V
PRECHARGE, GATE ....................................... ±20mA
VEEOUT ................................................ –14.4V to 0.3V
TIMER, 12VOUT ........................................... – 0.3V to 14.4V
Operation Temperature Range
LTC4244C/LTC4244C-1 ........................... 0°C to 70°C
LTC4244I/LTC4244I-1 ........................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
12VIN
1
20 12VOUT
VEEIN
2
19 VEEOUT
5VOUT
3
18 3.3VOUT
TIMER
4
17 3.3VIN
OFF/ON
5
16 3.3VSENSE
FAULT
6
15 GATE
PWRGD
7
14 5VSENSE
GND
8
13 5VIN
RESETIN
9
12 PRECHARGE
RESETOUT 10
LTC4244CGN
LTC4244CGN-1
LTC4244IGN
LTC4244IGN-1
11 DRIVE
GN PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 140°C, θJA = 135°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VEEIN = –12V, V3.3VIN = 3.3V, V5VIN = 5V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
IDD
V12VIN Supply Current
OFF/ON = 0V
●
VLKO
Undervoltage Lockout
12VIN, Ramping Down
5VIN, Ramping Down
3.3VIN, Ramping Down
VEEIN, Ramping Up (LTC4244 Only)
TIMER, Ramping Down, V12VIN = 6V
●
●
●
●
●
VFB
Foldback Current Limit Voltage
VFB = (V5VIN – V5VSENSE), V5VOUT = 0V, TIMER = 0V
VFB = (V5VIN – V5VSENSE), V5VOUT = 3V, TIMER = 0V
VFB = (V3.3VIN – V3.3VSENSE), V3.3VOUT = 0V, TIMER = 0V
VFB = (V3.3VIN – V3.3VSENSE), V3.3VOUT = 2V, TIMER = 0V
VCB
Circuit Breaker Trip Voltage
VCB = (V5VIN – V5VSENSE), TIMER = FLOAT
VCB = (V3.3VIN – V3.3VSENSE), TIMER = FLOAT
tOC
IGATE(UP)
UNITS
4
10
8
4
2.25
–8.25
8.25
9
4.25
2.5
–9.25
9.25
10
4.5
2.75
–10.25
10.25
●
●
●
●
11
46
11
46
16
51
16
51
21
56
21
56
mV
mV
mV
mV
●
●
45
45
52
52
57
57
mV
mV
Overcurrent Fault Response Time (V5VIN – V5VSENSE) = 100mV, TIMER = FLOAT
(V3.3VIN – V3.3VSENSE) = 100mV, TIMER = FLOAT
●
●
17
17
25
25
35
35
µs
µs
GATE Pin Output Current
OFF/ON = 0V, VGATE = 2V, TIMER = 0V
●
–20
–67
–100
µA
IGATE(DN)
VGATE = 5V, OFF/ON = 4V
●
20
60
100
µA
IGATE(FAULT)
OFF/ON = 0V, VGATE = 2V, TIMER = FLOAT, FAULT = 0V
●
4
8
16
mA
V
mA
V
V
V
V
V
∆VGATE
External Gate Voltage
∆VGATE = (V12VIN – VGATE), IGATE = –1µA
●
0.6
1
∆V12V
Internal Switch Voltage Drop
∆V12V = (V12VIN – V12VOUT), I = 500mA
●
225
600
mV
∆VVEE = (VEEOUT – VEEIN), IEE = 100mA
●
110
250
mV
∆VVEE
42441f
2
LTC4244/LTC4244-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VEEIN = –12V, V3.3VIN = 3.3V, V5VIN = 5V, unless
otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
ICL
Current Foldback
12VIN = 12V, 12VOUT = 0V, TIMER = 0V
12VIN = 12V, 12VOUT = 10V, TIMER = 0V
VEEIN = –12V, VEEOUT = 0V, TIMER = 0V
VEEIN = –12V, VEEOUT = –10V, TIMER = 0V
TTS
Thermal Shutdown Temperature
Junction Temperature, Ramping Up
VTH
Power Good Threshold Voltage
VIL
UNITS
●
●
●
●
–100
–550
50
350
–360
–850
225
610
–1000
–1500
350
870
12VOUT, Ramping Down
5VOUT, Ramping Down
3.3VOUT, Ramping Down
VEEOUT, Ramping Up, LTC4244 Only
●
●
●
●
10.8
4.50
2.80
–10.8
Logic Input Low Voltage
OFF/ON, RESETIN, FAULT
●
VIH
Logic Input High Voltage
OFF/ON, RESETIN, FAULT
●
IIN
OFF/ON, RESETIN Input Current
OFF/ON, RESETIN = 0V
OFF/ON, RESETIN = 12V
●
●
±10
±10
µA
µA
RESETOUT, FAULT Leakage
Current
RESETOUT, FAULT = 5V, OFF/ON = 0V, RESETIN = 3.3V
●
±10
µA
PWRGD Output Current
PWRGD = 5V, OFF/ON = 4V
●
±10
µA
5VSENSE Input Current
5VSENSE = 5V, 5VOUT = 0V
●
57
100
µA
3.3VSENSE Input Current
3.3VSENSE = 3.3V, 3.3VOUT = 0V
●
56
100
µA
5VIN Input Current
5VIN = 5V, TIMER = 0V
●
0.8
1.5
mA
3.3VIN Input Current
3.3VIN = 3.3V, TIMER = FLOAT
3.3VIN = 3.3V, TIMER = 0V
●
●
510
400
700
550
µA
µA
5VOUT Input Current
5VOUT = 5V, OFF/ON = 0V, TIMER = 0V
●
107
200
µA
3.3VOUT Input Current
3.3VOUT = 3.3V, OFF/ON = 0V, TIMER = 0V
●
170
300
µA
mA
mA
mA
mA
°C
150
11.1
4.61
2.90
–11.1
11.4
4.75
3.00
–11.4
V
V
V
V
0.8
V
2
V
PRECHARGE Input Current
VPRECHARGE = 1V
●
0.1
10
µA
ITIMER
TIMER Pin Current
OFF/ON = 0V, VTIMER = 0V
OFF/ON = 5V, VTIMER = 5V
●
●
16
25
21
45
26
70
µA
mA
VTIMER
TIMER Threshold Voltage
TIMER_HI, (V12VIN – VTIMER), FAULT = 0V, Ramping Up
TIMER_LO, VTIMER, Ramping Down
●
●
1.3
0.5
1.6
0.8
1.9
1.1
V
V
∆VTIMER
External Timer Voltage
∆VTIMER = (V12VIN – VTIMER), ITIMER = –1µA
●
1
V
RDIS
12VOUT Discharge Resistance
5VOUT Discharge Resistance
3.3VOUT Discharge Resistance
VEEOUT Discharge Resistance
OFF/ON = 4V
OFF/ON = 4V
OFF/ON = 4V
OFF/ON = 4V
●
●
●
●
1000
500
500
1000
Ω
Ω
Ω
Ω
VOL
Output Low Voltage
PWRGD, RESETOUT, FAULT, I = 1mA
●
0.4
V
VPXG
PRECHARGE Reference Voltage
VDRIVE = 2V
●
1.05
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
440
200
200
390
0.95
1
Note 3: The 12VIN and VEEIN pins will withstand transient surges up to
±15V, respectively, upon hot insertion.
42441f
3
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V and 5V Current Foldback
Profile
12VOUT Current vs 12VOUT
Voltage
60
VEEOUT Current vs VEEOUT Voltage
1.0
–0.6
0.9
50
5V
30
20
CURRENT (A)
0.7
40
CURRENT (A)
VOLTAGE (mV)
–0.5
0.8
3.3V
0.6
0.5
0.4
–0.3
–0.2
0.3
0.2
10
–0.4
–0.1
0.1
0
0
0
2
3
VOLTAGE (V)
1
4
5
0
0
2
4
6
8
VOLTAGE (V)
10
4244 G01
12
0
–4
–6
–8
VOLTAGE (V)
–10
4244 G02
12V Foldback Current Limit vs
Temperature
12V Internal Switch Voltage Drop
vs Temperature
0.6
0.30
VEEOUT = 10V
12VOUT = 10V
–12
4244 G03
VEE Foldback Current Limit vs
Temperature
0.9
0.8
–2
0.5
0.25
0.4
0.20
I12VOUT = 550mA
12VOUT = 0V
0.5
0.4
0.3
VOLTAGE (V)
0.6
CURRENT (A)
CURRENT (A)
0.7
0.3
VEEOUT = 0V
0.2
0.15
0.10
0.2
0.1
0.05
0.1
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
0
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G04
VOLTAGE (mV)
VOLTAGE (V)
0.10
0.04
3.3VOUT = 2V
50
50
40
40
VOLTAGE (mV)
0.12
30
20
5VOUT = 0V
10
0.02
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G07
0
–50
100
60
5VOUT = 3V
0.06
75
3.3VIN Foldback Current Limit
Voltage vs Temperature
60
0.08
0
25
50
TEMPERATURE (°C)
4244 G06
5VIN Foldback Current Limit
Voltage vs Temperature
IVEEIN = 100mA
0
–50
–25
4244 G05
VEE Internal Switch Voltage Drop
vs Temperature
0.14
0
–50
100
30
20
3.3VOUT = 0V
10
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G08
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G09
42441f
4
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3VIN and 5VIN Circuit Breaker
Trip Voltage vs Temperature
5VIN
51.6
51.2
TIME (µs)
VOLTAGE (mV)
51.4
51.0
3.3VIN
50.8
50.6
25.0
3.94
24.5
3.93
24.0
3.92
CURRENT (mA)
52.0
51.8
12VIN Supply Current vs
Temperature
3.3VIN and 5VIN Circuit Breaker
Trip Filter Time vs Temperature
23.5
23.0
3.91
3.90
22.5
3.89
22.0
3.88
50.4
50.2
50.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
21.5
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G10
3.87
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G11
12VIN Undervoltage Lockout vs
Temperature
100
4244 G12
5VIN Undervoltage Lockout vs
Temperature
VEEIN Undervoltage Lockout vs
Temperature
9.30
–9.22
4.34
9.25
–9.24
4.32
RAMPING-UP
RAMPING-UP
9.15
9.10
RAMPING-DOWN
–9.28
–9.30
9.05
–9.32
9.00
–9.34
8.95
–50
–25
0
25
50
TEMPERATURE (°C)
75
4.30
VOLTAGE (V)
–9.26
RAMPING-UP
VOLTAGE (V)
VOLTAGE (V)
9.20
4.26
4.24
–25
0
25
50
TEMPERATURE (°C)
75
4244 G13
RAMPING-DOWN
4.22
RAMPING-DOWN
–9.36
–50
100
4.28
4.20
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G14
3.3VIN Undervoltage Lockout vs
Temperature
4244 G15
12VOUT Powergood Threshold
Voltage vs Temperature
2.54
100
VEEIN Powergood Threshold
Voltage vs Temperature
11.090
–11.050
11.085
–11.055
RAMPING-UP
2.53
2.50
2.49
2.48
11.070
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G16
11.055
–50
–11.060
–11.065
–11.070
–11.075
11.060
2.46
2.45
–50
11.075
11.065
RAMPING-DOWN
2.47
VOLTAGE (V)
11.080
2.51
VOLTAGE (V)
VOLTAGE (V)
2.52
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G17
–11.080
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G18
42441f
5
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
5VOUT Powergood Threshold
Voltage vs Temperature
3.3VOUT Powergood Threshold
Voltage vs Temperature
2.902
80
4.602
2.901
60
2.900
40
VOLTAGE (V)
4.600
4.599
4.598
4.597
4.596
CURRENT (µA)
OFF/ON = 0V
4.601
VOLTAGE (V)
Gate Pin Current vs Temperature
4.603
2.899
2.898
2.897
0
–20
2.896
–40
2.895
–60
OFF/ON = 4V
4.595
4.594
–50
–25
0
25
50
TEMPERATURE (°C)
75
2.894
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G19
–80
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
4244 G20
Gate Pin Fault Current vs
Temperature
16
20
4244 G21
Timer Pin Off Current vs
Temperature
Timer Pin On Current vs
Temperature
20.30
FAULT = 0V
100
60
14
50
20.25
10
8
6
CURRENT (mA)
CURRENT (µA)
CURRENT (mA)
12
20.20
20.15
40
30
20
4
20.10
10
2
–25
0
25
50
TEMPERATURE (°C)
75
100
20.05
–50
–25
0
25
50
TEMPERATURE (°C)
75
4244 G22
75
12VIN – VTIMER
100
VOL vs Temperature
700
250
600
12VOUT
1.62
200
RESETOUT
500
RESISTANCE (Ω)
1.60
VOLTAGE (V)
0
25
50
TEMPERATURE (°C)
4244 G24
Discharge Resistance vs
Temperature
1.64
1.58
1.56
1.54
1.52
VEEOUT
400
3.3VOUT
300
5VOUT
200
150
PWRGD
100
FAULT
1.50
50
100
1.48
1.46
–50
–25
4244 G23
Timer Threshold Voltage vs
Temperature
1.66
0
–50
100
RESISTANCE (Ω)
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G25
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G26
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4244 G27
42441f
6
LTC4244/LTC4244-1
U
U
U
PI FU CTIO S
12VIN (Pin 1): 12V Supply Input. A 0.5Ω switch is connected between 12VIN and 12VOUT with a foldback current
limit. An undervoltage lockout circuit prevents the switches
from turning on while the 12VIN pin voltage is less than 9V.
12VIN also provides power to the LTC4244’s internal VCC
node.
VEEIN (Pin 2): –12V Supply Input. A 1Ω switch is connected between VEEIN and VEEOUT with a foldback current
limit. An undervoltage lockout circuit prevents the switches
from turning on while the VEEIN pin voltage is greater than
–9.25V. The VEEIN undervoltage lockout function is disabled for the LTC4244-1.
5VOUT (Pin 3): 5V Output Sense. The PWRGD pin will not
pull low until the 5VOUT pin voltage exceeds 4.61V. A 200Ω
active pull-down discharges 5VOUT to ground when the
power switches are turned off.
TIMER (Pin 4): Current Fault Inhibit Timing Input and
Auxiliary VCC. Connect a capacitor from TIMER to GND.
When the LTC4244 is turned on, a 21µA pull-up current
source is connected to TIMER. Current limit faults will be
ignored until the voltage at the TIMER pin rises to within
1.6V of 12VIN. After the TIMER pin has completed ramping up, the TIMER capacitor serves as an auxiliary charge
reservoir for VCC in the event the 12VIN pin voltage
momentarily drops below the undervoltage lockout threshold voltage. When the LTC4244 is turned off (OFF/ON >
2V), the TIMER pin is pulled down to GND. After the TIMER
pin voltage drops to within 0.8V of GND, the TIMER latch
is reset and the part is ready for another power cycle.
OFF/ON (Pin 5): Digital Input. Connect the CPCI BD_SEL#
signal to the OFF/ON pin. When the OFF/ON pin is pulled
low, the GATE pin is pulled high by a 67µA current source
and the internal 12V and –12V switches are turned on.
When the OFF/ON pin is pulled high, the GATE pin will be
pulled to ground by a 60µA current source and the 12V and
–12V switches turn off.
FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Current limit faults
are ignored until the voltage at the TIMER pin is within 1.6V
of 12VIN. Once the TIMER cycle is complete, FAULT will
pull low and the LTC4244 latches off in the event of an
overcurrent fault. The part will remain in the latched off
state until the OFF/ON pin is cycled high then low. Forcing
the FAULT pin low with an external pull-down will cause
the part to latch into the off state after a 25µs deglitching
time.
PWRGD (Pin 7): Open-Drain Digital Power Good Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V12VOUT ≥ 11.1V, V3.3VOUT ≥
2.9V, V5VOUT ≥ 4.61V, and VEEOUT ≤ –11.1V. When any of
the supplies falls below its power good threshold voltage,
PWRGD will go high after a 14µs deglitching time.
GND (Pin 8): Device Ground.
RESETIN (Pin 9): Digital Input. Connect the CPCI PCI_RST#
signal to the RESETIN pin. Pulling the RESETIN pin low will
cause RESETOUT to pull low. RESETOUT will also pull low
when PWRGD is high.
42441f
7
LTC4244/LTC4244-1
U
U
U
PI FU CTIO S
RESETOUT (Pin 10): Open-Drain Digital Output. Connect
the CPCI_LOCAL_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of the RESETIN and
PWRGD.
DRIVE (Pin 11): Precharge Base Drive Output. Provides
base drive for an external NPN emitter-follower that in turn
biases the PRECHARGE node.
PRECHARGE (Pin 12): Precharge Monitor Input. An internal error amplifier servos the DRIVE pin voltage to keep the
PRECHARGE node at 1V. See Applications Information for
generating voltages other than 1V. If not used, tie the
PRECHARGE pin to ground.
GATE (Pin 15): High Side Gate Drive for the External 3.3V
and 5V N-Channel Pass Transistors. An external series RC
network is required for current limit loop compensation
and setting the minimum ramp-up time. During power-up,
the slope of the voltage rise at the GATE is set by the 67µA
current source connected through a Schottky diode to
12VIN and the external capacitor connected to GND (C1 in
Figure 1) or by the 3.3V or 5V current limit and the bulk
capacitance in the 3.3VOUT or 5VOUT supply lines. During
power down, the slew rate of the GATE voltage is set by the
60µA current source connected to GND and the external
GATE capacitor (C1 in Figure 1).
5VIN (Pin 13): 5V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 5VIN pin is less than 4.25V.
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 5V or 3.3V supplies go
into current limit. In the event of an overcurrent fault, the
GATE pin is immediately pulled to GND.
5VSENSE (Pin 14): 5V Current Limit Sense. With a sense
resistor placed in the supply path between 5VIN and
5VSENSE, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature makes the current limit decrease as the
voltage at the 5VOUT pin approaches GND. When the
TIMER pin is high, the circuit breaker function is enabled.
If the voltage across the sense resistor exceeds 52mV, the
circuit breaker is tripped after a 25µs time delay. In the
event of a short-circuit or large overcurrent transient
condition, the GATE pin voltage will be adjusted to maintain a constant 150mV across the sense resistor and a
constant current through the switch.
3.3VSENSE (Pin 16): 3.3V Current Limit Sense. With a
sense resistor placed in the supply path between 3.3VIN
and 3.3VSENSE, the GATE pin voltage will be adjusted to
maintain a constant 51mV across the sense resistor and a
constant current through the switch while the TIMER pin
is low. A foldback feature makes the current limit decrease
as the voltage at the 3.3VOUT pin approaches GND. When
the TIMER pin is high, the circuit breaker function is
enabled. If the voltage across the sense resistor exceeds
52mV, the circuit breaker is tripped after a 25µs time delay.
In the event of a short-circuit or large overcurrent transient
condition, the GATE pin voltage will be adjusted to maintain a constant 150mV across the sense resistor and a
constant current through the switch.
If no 3.3V input supply is available, short the 3.3VSENSE pin
to the 5VIN pin.
42441f
8
LTC4244/LTC4244-1
U
U
U
PI FU CTIO S
3.3VIN (Pin 17): 3.3V Supply Sense Input. An undervoltage lockout circuit prevents the switches from turning on
when the voltage at the 3.3VIN pin is less than 2.5V. If no
3.3V input supply is available, short the 3.3VIN pin to the
5VIN pin.
3.3VOUT (Pin 18): Analog Input Used to Monitor the 3.3V
Output Supply Voltage. The PWRGD pin cannot pull low
until the 3.3VOUT pin voltage exceeds 2.9V. If no 3.3V input
supply is available, tie the 3.3VOUT pin to the 5VOUT pin. A
200Ω active pull-down discharges 3.3VOUT to ground
when the power switches are turned off.
VEEOUT (Pin 19): -12V Supply Output. A 1Ω switch is
connected between VEEIN and VEEOUT. VEEOUT must be less
than –11.1V before the PWRGD pin pulls low. The VEEOUT
power good comparator is disabled for the LTC4244-1. A
390Ω active pull-up discharges VEEOUT to ground when
the power switches are turned off.
12VOUT (Pin 20): 12V Supply Output. A 0.5Ω switch is
connected between 12VIN and 12VOUT. 12VOUT must
exceed 11.1V before the PWRGD pin can pull low. A 440Ω
active pull-down discharges 12VOUT to ground when the
power switches are turned off.
42441f
9
LTC4244/LTC4244-1
W
BLOCK DIAGRA
17
16
15
14
13
3.3VIN
GND
8
3.3VSENSE
GATE
5VSENSE
VCC
5VIN
5VOUT
3.3VOUT
67µA
50mV
–+
+–
–
60µA
+
VEEIN
–+
–
50mV
+
CP_OFF
TIMER_LO ≥ 50mV
TIMER_HI ≥ 150mV
UVL
MONITOR
–+
+
–
+–
–
5V
CURRENT
FAULT
+–
3.3V
CURRENT FAULT
+
TIMER_LO ≥ 50mV
TIMER_HI ≥ 150mV
FAULT
8µs
RISING
EDGE
DELAY
6
12VIN
REF
VCC
21µA
TIMER_HI
VCC
4
VCC UVL
RESET
5
7
10
THERMAL
FAULT
TIMER
46µs
FALLING
EDGE
DELAY
CP_OFF
25µs
RISING
EDGE
DELAY
5V CURRENT FAULT
3.3V CURRENT FAULT
VEE CURRENT FAULT
12V CURRENT FAULT
S
Q
R
Q
TIMER_HI
S
Q
R
Q
TIMER_LO
OFF/ON
PWRGD
VCC
14µs
FALLING
EDGE
DELAY
RESETOUT
THERMAL
SHUTDOWN
5VIN
THERMAL
FAULT
4R
DRIVE
–
11
R
9
RESETIN
+
VCC
PRECHARGE
CP_OFF
THERMAL FAULT
1
12V SWITCH
CONTROL
REFERENCE
12V CURRENT FAULT
REF
12VOUT
12VIN
5VOUT
CP_OFF
3.3VOUT
CHARGE
PUMP
POWER GOOD
MONITOR
REF
2
VEE SWITCH
CONTROL
20
3
18
CP_OFF
VEEOUT
VEEIN
CP_OFF
THERMAL FAULT
VCC
12
19
4244 BD
VEE CURRENT FAULT
42441f
10
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When a circuit board is inserted into a live CompactPCI
(CPCI) bus, the supply bypass capacitors can draw huge
inrush currents from the CPCI power bus as they charge
up. These transient currents can create glitches on the
power bus, causing other boards in the system to reset.
The LTC4244 is designed to turn a board’s back-end
supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live
CPCI connector without glitching the system power supplies. It also protects the system supplies from shorts,
precharges the bus I/O connector pins during hot insertion
and extraction, and monitors the supply voltages.
The LTC4244 is specifically designed for CPCI applications where the Hot Swap controller resides on the plugin board.
LTC4244 Feature Summary
• Allows safe insertion and removal from a CPCI backplane.
• Controls all four CPCI supplies: -12V, 12V, 3.3V and 5V.
• Current limit during power up: the supplies are allowed
to power up in current limit. This allows the LTC4244 to
power up boards with widely varying capacitive loads
without tripping the circuit breaker. The maximum
allowable power-up time is adjustable using the TIMER
pin capacitor.
• Internal 12V and –12V power switches.
• PWRGD output: monitors the voltage status of the four
back-end supply voltages.
• PCI_RST# combined on chip with HEALTHY# to create
LOCAL_PCI_RST# output. Simply connect the
PCI_RST# signal to the RESETIN pin and the
LOCAL_PCI_RST# signal to the open-drain RESETOUT
pin.
• Precharge output: on-chip reference and error amplifier
provide 1V for biasing bus I/O connector pins during
CPCI card insertion and extraction.
• TIMER/AUX. VCC: After power-up, the TIMER pin capacitor serves as auxiliary VCC, thus enabling the
LTC4244 to ride out large voltage spikes on the 12VIN
supply without interruption.
• Adjustable foldback current limit for the 5V and 3.3V
supplies: an adjustable analog current limit with a value
that depends on the output voltage. If the output is
shorted to ground the current limit drops to keep power
dissipation and supply glitches to a minimum.
• Undervoltage lockout: All four input voltages are protected by undervoltage lockouts.
• 12V and –12V circuit breakers: if either supply remains
in analog foldback current limit for more than 25µs, the
circuit breakers will trip, the supplies are turned off and
the FAULT pin is pulled low.
The LTC4244 is pin-for-pin compatible with the LTC1644.
There are, however, some important differences between
the two parts:
• Adjustable 5V and 3.3V circuit breakers: if either supply
exceeds its current limit for more than 25µs, the circuit
breaker will trip, the supplies will be turned off and the
FAULT pin is asserted low. In the event of a short circuit
on either supply, an analog current limit will prevent the
supply current from exceeding three times the circuit
breaker threshold current.
• Space saving 20-pin SSOP package.
LTC4244 vs LTC1644
• TIMER: The LTC4244’s TIMER pin threshold voltage is
1.6V below V12VIN vs 1V for the LTC1644. After powerup, the LTC4244’s TIMER pin also doubles as auxiliary
VCC.
• VEEIN UVL: The LTC4244 has a –9.5V UVL threshold
protecting the VEEIN supply. The LTC1644 has no VEEIN
UVL feature.
42441f
11
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
• 5VIN UVL Threshold Voltage: The LTC4244’s 5VIN UVL
threshold voltage is 4.25V vs. 2.5V for the LTC1644.
• VEEOUT PWRGD Threshold Voltage: The LTC4244 VEEOUT
power good threshold voltage is –11.1V vs –10.5V for
the LTC1644.
• Absolute Maximum Ratings: The LTC4244’s absolute
maximum ratings for the 12VIN and VEEIN pins are
±14.4V, respectively, vs ±13.2V for the LTC1644.
• 5V/3.3V Circuit Breakers: If a short-circuit occurs after
power-up, the LTC4244 actively limits the voltage
dropped across the external 5V and 3.3V sense resistors to 150mV for 25µs before tripping the circuit
breaker. In the event either the 5V or 3.3V sense resistor
voltage exceeds 150mV, the LTC1644 trips the circuit
breaker without delay.
• 5V/3.3V Circuit Breaker Threshold Voltage: The LTC4244
threshold voltage is 52mV ±5mV vs 55mV ±15mV for
the LTC1644.
• External Gate Voltage: After power-up, the voltage drop
from the 12VIN pin to the GATE pin is 0.6V for the
LTC4244 vs 50mV for the LTC1644.
Hot Plug Power-Up Sequence
The LTC4244 is specifically designed for hot plugging
CPCI boards. The typical application circuit is shown in
Figure 1.
CPCI Connector Pin Sequence
The staggered lengths of the CPCI male connector pins
ensure that all power supplies are physically connected to
the LTC4244 before back-end power is allowed to ramp up
(BD_SEL# asserted low). The long pins, which include 5V,
3.3.V, V(I/O) and GND, mate first. The short BD_SEL# pin
mates last. At least one long 5V power pin must be
connected to the LTC4244 in order for the PRECHARGE
voltage to be available during the insertion sequence.
The following is a typical hot insertion sequence:
1. ESD clips make contact.
2. Long power and ground pins make contact and Early
Power is established. The 1V precharge voltage becomes valid at this stage of insertion. Power is also
applied to the pull-up resistors connected to the FAULT,
PWRGD and OFF/ON pins. All power switches are held
off at this stage of insertion.
3. Medium length pins make contact. Both FAULT and
PWRGD continue to be pulled up high at this stage in the
hot plug sequence, and the power switches are still held
off. The 12V and –12V connector pins also make
contact at this stage. Zener clamps Z1 and Z2 plus shunt
RC snubbers R16-C5 and R15-C4 help protect the VEEIN
and 12VIN pins, respectively, from large voltage transients during hot insertion.
The signal pins also connect at this point. These include
the HEALTHY# signal (which is connected to the PWRGD
pin), the PCI_RST# signal (which is connected to the
RESETIN pin) and the I/O connector pins (which are
biased at 1V by the LTC4244’s precharge circuit).
4. Short pins make contact. The BD_SEL# signal is connected to the OFF/ON pin. If the BD_SEL# signal is
grounded on the backplane, the plug-in card power-up
cycle begins immediately. System backplanes that do
not ground the BD_SEL# signal will instead have circuitry that detects when BD_SEL# makes contact with
the plug-in board. The system logic can then control the
power up process by pulling BD_SEL# low.
Power-Up Sequence
The back-end 3.3VOUT and 5VOUT power planes are isolated from the 3.3VIN and 5VIN power planes by external
N-channel pass transistors Q1 and Q2, respectively. Internal pass transistors isolate the back-end 12VOUT and
VEEOUT power planes from the 12VIN and VEEIN power
planes.
42441f
12
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Sense resistors R1 and R2 provide current fault detection
and R5 and C1 provide current control loop compensation
as well as ramp rate control for the GATE pin voltage.
Resistors R3 and R4 prevent high frequency oscillations
in MOSFET’s Q1 and Q2.
A power-up sequence begins when the OFF/ON pin is
pulled low (Figure 2). This enables the pass transistors to
turn on and an internal 21µA current source is connected
to TIMER. Once the pass transistors begin to conduct
current, the supplies will start to power up. Current limit
faults are ignored while the TIMER pin voltage is ramping
up and is less than (12VIN – 1.6V). When all four supply
voltages are within tolerance, HEALTHY# will pull low and
LOCAL_PCI_RST# is free to follow PCI_RST#.
Power-Down Sequence
When the BD_SEL# signal is pulled high, a power-down
sequence begins (Figure 3).
Internal switches are connected to each of the output
voltage supply pins to discharge the bypass capacitors to
ground. The TIMER pin is immediately pulled low. The
GATE pin is pulled down by a 60µA current source to
prevent the load currents on the 3.3V and 5V supplies from
going to zero instantaneously and glitching the power
supply voltages. When any of the output voltages dips
below its threshold, the HEALTHY# signal pulls high and
LOCAL_PCI_RST# will be asserted low.
TIMER
10V/DIV
TIMER
10V/DIV
GATE
10V/DIV
GATE
10V/DIV
12VOUT
10V/DIV
5VOUT
10V/DIV
3.3VOUT
10V/DIV
VEEOUT
10V/DIV
12VOUT
10V/DIV
5VOUT
10V/DIV
3.3VOUT
10V/DIV
VEEOUT
10V/DIV
BD_SEL#
10V/DIV
BD_SEL#
10V/DIV
HEALTHY#
10V/DIV
HEALTHY#
10V/DIV
LCL_PCI_RST#
10V/DIV
LCL_PCI_RST#
10V/DIV
10ms/DIV
Figure 2. Normal Power-Up Sequence
4244 F02
20ms/DIV
4244 F03
Figure 3. Normal Power-Down Sequence
42441f
13
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Once the power-down sequence is complete, the CPCI
card may be removed from the slot. During extraction, the
precharge circuit continues to bias the bus I/O connector
pins at 1V until the long 5V and 3.3V connector pin
connections are broken.
The maximum power-up time for this condition can be
approximated by:
GATE Pin Capacitor Selection
where VTH,MOSFET(MAX) is the maximum threshold voltage
of the external 5V or 3.3V MOSFET.
Both the load capacitance and the LTC4244’s GATE pin
capacitor (C1 in Figure 1) affect the ramp rate of the 5VOUT
and 3.3VOUT voltages. The precise relationship can be
expressed as:
ILIMIT(5V) – ILOAD(5V)
dVOUT IGATE
=
or =
or
dt
C1
CLOAD(5VOUT)
=
(1)
ILIMIT(3.3V) – ILOAD(3.3V)
CLOAD(3.3VOUT)
whichever is slowest. The power-up time for any of the
LTC4244’s outputs where the inrush current is constrained
by that supply’s foldback current limit can be approximated as:
ton(nVOUT) <
2 • CLOAD • n VOUT
ILIMIT(nVOUT) – ILOAD(nVOUT)
(2)
Where n VOUT = 5VOUT, 3.3VOUT, 12VOUT or VEEOUT. For
example, if CLOAD=2000µF, ILIMIT(5VOUT) = 6A and
ILOAD(5VOUT) = 5A, the 5VOUT turn-on time will be less than
20ms.
If the value of C1 is large enough that it alone determines
the output voltage ramp rate, then the magnitude of the
inrush current initially charging the load capacitance is:
IINRUSH =
CLOAD
• IGATE
C1
(3)
tON <
(VOUT + VTH,MOSFET(MAX)) • C1(MAX)
IGATE(MIN)
(4)
In general, the edge rate (dI/dt) at which the back-end 5V
and 3.3V supply currents are turned on can be limited by
increasing the size of C1. Applications that are sensitive to
the edge rate should characterize how varying the size of
C1 reduces dI/dt for the external MOSFET selected for a
particular design.
In the event of a short-circuit or overcurrent condition, the
LTC4244’s GATE pin can be pulled down within 2µs since
a 1kΩ (R5 in Figure 1) decouples C1 from the gates of the
external MOSFET’s (Q1 and Q2 in Figure 1).
TIMER Pin Capacitor Selection
During a power-up sequence, a 21µA current source is
connected to the TIMER pin and current limit faults are
ignored until the voltage ramps to within 1.6V of 12VIN.
This feature allows the part to power up large capacitive
loads using its foldback current limit. The TIMER inhibit
period can be expressed as:
t TIMER =
CTIMER • (12VIN – VTIMER )
ITIMER
(5)
The timer period should be set longer than the duration of
any inrush current that exceeds the LTC4244’s foldback
current limit but yet be short enough not to exceed the
maximum, safe operating area of the external 5V and 3.3V
pass transistors in the event of a short circuit (see Design
Example). As a design aid, the TIMER period as a function
of the timing capacitor using standard values from 0.1µF
to 0.82µF is shown in Table 1.
42441f
14
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Table 1. tTIMER vs CTIMER
Short-Circuit Protection
CTIMER (±10%)
tTIMER(MIN)
tTIMER(MAX)
0.1µF
35ms
74ms
0.22µF
77ms
162ms
0.33µF
115ms
243ms
0.47µF
164ms
346ms
0.68µF
238ms
500ms
0.82µF
287ms
603ms
During a normal power-up sequence, if the TIMER pin is
done ramping and any supply is still in current limit all of
the pass transistors will be immediately turned off and
FAULT will be pulled low as shown in Figure 4.
In order to prevent excessive power dissipation in the pass
transistors and prevent voltage spikes on the supplies
during short-circuit conditions, the current limit on each
supply is designed to be a function of the output voltage.
As the output voltage drops, the current limit decreases.
Unlike a traditional circuit breaker function where large
currents can flow before the breaker trips, the current
foldback feature guarantees that the supply current will be
kept at a safe level.
The TIMER pin is immediately pulled low when the BD_SEL#
pin signal goes high.
Thermal Shutdown
The internal switches for the 12V and –12V supplies are
protected by a thermal shutdown circuit. When the junction temperature of the die reaches 150°C, all switches will
be latched off and the FAULT pin will be pulled low.
If either the 12V or –12V supply exceeds current limit
after power-up, the shorted supply’s current will drop
TIMER
10V/DIV
GATE
10V/DIV
3.3VOUT
10V/DIV
5VOUT
10V/DIV
12VOUT
10V/DIV
VEEOUT
10V/DIV
BD_SEL#
10V/DIV
HEALTHY#
10V/DIV
LCL_PCI_RST#
10V/DIV
FAULT
10V/DIV
20ms/DIV
4244 F04
Figure 4. Power-Up Into a Short on a 3.3V Output
42441f
15
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
immediately to its ILIMIT value. If that supply remains in
current limit for more than 25µs, all of the supplies will be
latched off. The 25µs prevents quick current spikes—for
example, from a fan turning on—from causing false trips
of the circuit breaker.
After power-up, the 5V and 3.3V supplies are protected
from short circuits by dual-level circuit breakers. In the
event that either supply’s current exceeds the nominal
current limit, an internal timer is started. If the supply is
still overcurrent after 25µs, the circuit breaker trips and all
the supplies are turned off (Figure 5). An analog current
limit loop prevents the supply current from exceeding 3×
the nominal current limit in the event of a short circuit
(Figure 6). The LTC4244 will stay in the latched off state
until the OFF/ON pin is cycled high then low or the 12VIN
power supply is cycled low then high.
resistor. As shown in Figure 1, a sense resistor is connected between 5VIN and 5VSENSE for the 5V supply. For
the 3.3V supply, a sense resistor is connected between
3.3VIN and 3.3VSENSE. The typical current limit and the
foldback current levels are given by Equations 6 and 7:
ILIMIT(nVOUT) =
51mV
RSENSE(nVOUT)
IFOLDBACK(nVOUT) =
(6)
16 mV
RSENSE(nVOUT)
(7)
where n VOUT = 5VOUT or 3.3VOUT.
The current limit for the internal 12V switch is set at
850mA folding back to 360mA and the –12V switch at
610mA folding back to 225mA.
The current limit and the foldback current level for the 5V
and 3.3V outputs are both a function of the external sense
GATE
20V/DIV
GATE
20V/DIV
5VOUT
10V/DIV
3.3VOUT
5V/DIV
FAULT
5V/DIV
FAULT
5V/DIV
TIMER
20V/DIV
TIMER
20V/DIV
5VIN – 5VSENSE
100mV/DIV
3VIN – 3VSENSE
500mV/DIV
10µs/DIV
Figure 5. Overcurrent Fault on 5V Output
4244 F05
10µs/DIV
4244 F06
Figure 6. Short-Circuit Fault on 3.3V Output
42441f
16
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Calculating RSENSE
Determining the most appropriate value for the sense
resistor first requires knowing the maximum current needed
by the load under worst-case conditions. Two other parameters affect the value of the sense resistor. First is the
tolerance of the LTC4244’s circuit breaker threshold voltage. The LTC4244’s nominal circuit breaker threshold
voltage is VCB(NOM) = 52mV; however it exhibits ±5mV
tolerance over process and temperature. Second is the
tolerance (RTOL) of the sense resistor. Sense resistors are
available in RTOL’s of ±1%, ±2% and ±5% and exhibit
temperature coefficients of resistance (TCR’s) between
±75ppm/°C and ±100ppm/°C. How the sense resistor
changes as a function of temperature depends on the
I2 • R power being dissipated by it. The power rating of the
sense resistor should accommodate steady-state fault
current levels so that the component is not damaged
before the circuit breaker trips.
Table 2 lists ITRIP(MIN) and ITRIP(MAX) versus some suggested values of RSENSE. Table 7 lists manufacturers and
part numbers for these resistor values.
Table 2. ITRIP vs RSENSE
RSENSE (1% RTOL)
ITRIP(MIN)
ITRIP(MAX)
0.005Ω
9.31A
11.5A
0.007Ω
6.6A
8.2A
0.011Ω
4.2A
5.2A
Output Voltage Monitor
The status of all four output voltages is monitored by the
power good function. In addition, the PCI_RST# signal is
logically combined on-chip with the HEALTHY# signal to
create LOCAL_PCI_RST# (see Table 3). As a result,
LOCAL_PCI_RST# will be pulled low whenever HEALTHY#
is pulled high independent of the state of the PCI_RST#
signal.
If any of the output voltages drop below the power good
threshold for more than 14µs, the PWRGD pin will be
pulled high and the LOCAL_PCI_RST# signal will be
asserted low.
Table 3. LOCAL_PCI_RST# Truth Table
PCI_RST#
HEALTHY#
LOCAL_PCI_RST#
LO
LO
LO
LO
HI
LO
HI
LO
HI
HI
HI
LO
Precharge
The PRECHARGE input and DRIVE output pins are intended for use in generating the 1V precharge voltage that
is used to bias the bus I/O connector pins during board
insertion and extraction. The LTC4244 is also capable of
generating precharge voltages other than 1V. Figure 7
shows a circuit that can be used in applications requiring
a precharge voltage of less than 1V. The circuit in Figure␣ 8
can be used for applications that need precharge voltages
greater than 1V.
Precharge resistors are used to connect the 1V bias voltage to the I/O lines with minimal disturbance. Figure 1
shows the precharge application circuit for 5V signaling.
The precharge resistor requirements are more stringent
for 3.3V and Universal Hot Swap boards. If the total leakage current on the I/O line is less 2µA, then a 50k resistor
can be connected directly from the 1V bias voltage to the
I/O line. However, many ICs connected to the I/O lines can
have leakage currents up to 10µA. For these applications,
a 10k resistor is used but must be disconnected when the
board is seated as determined by the state of the BD_SEL#
signal. Figure 9 shows a precharge circuit that uses a bus
switch to connect the individual 10k precharge resistors to
the LTC4244’s 1V PRECHARGE pin. The electrical connection is made (bus switches closed) when the voltage on the
BD_SEL# pin of the plug-in card is pulled-up to 5VIN,
which occurs just after the long pins have made contact.
The bus switches are electrically disconnected when the
short, BD_SEL# connector pin makes contact and the
42441f
17
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
LTC4244*
LTC4244*
GND
PRECHARGE
8
12
4.7nF 18Ω
5%
R10A
DRIVE
GND
11
8
VPRECHARGE =
12Ω
5%
R10A
11
4.7nF 18Ω
5%
1k
5%
12Ω
5%
3.3VIN
Q3
PRECHARGE OUT MMBT2222A
VPRECHARGE = R10A + R10B • 1V
R10A
R10A
• 1V
R10A + R10B
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4244 F07
C9
0.01µF PER
POWER PIN
5VIN
PCB EDGE
BACKPLANE
CONNECTOR
R22
2.7Ω
13 5V
IN
R20
1.2k
5%
LONG 5V
R19
1k 5%
BD_SEL#
C7
0.01µF
4244 F08
Figure 8. Precharge Voltage >1V Application Circuit
Figure 7. Precharge Voltage <1V Application Circuit
BACKPLANE
CONNECTOR
DRIVE
R10B
3.3VIN
Q3
MMBT2222A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
5V
12
1k
5%
R10B
PRECHARGE OUT
PRECHARGE
Z4
LTC4244*
5 OFF/ON
GND
PRECHARGE
8
DRIVE
12
11
R9
24Ω
R10
18Ω 5%
C3 4.7nF
GROUND
R23
51.1k 5%
100Ω
0.1µF
Q2
MMBT3906
R24
75k
5%
OE
R13
10Ω
5%
I/O PIN 1
Q3
R7
MMBT2222A 12Ω 5%
PRECHARGE OUT
1V ±10%
IOUT = ±55mA
UP TO 128 I/O LINES
I/O PIN 128
Z4: SMAJ5.0A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
3VIN
I/O
• • •
R14
10Ω
5%
IN
VDD
BUS SWITCH
OUT
OUT
R11
R12
10k
10k
5%
5%
• • •
• • •
DATA BUS
R8
1k 5%
I/O
PCI
BRIDGE
CHIP
4244 F09
Figure 9. Precharge Bus Switch Application Circuit for 3.3V and Universal Hot Swap Boards
42441f
18
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
BD_SEL# voltage drops below 4.4V thus causing the bus
switch OE to be pulled high by Q2.
The CompactPCI specification assumes that there is a
diode to 3.3V on the circuit that is driving the BD_SEL# pin.
The 1.2k resistor pull-up to 5VIN on the plug-in card will be
clamped by the diode to 3.3V. If the BD_SEL# pin is being
driven high, the actual voltage on the pin will be approximately 3.9V. This is still above the high TTL threshold of
the LTC4244 OFF/ON pin, but low enough for Q2 to disable
the bus switches and thus disconnect the 10k precharge
resistors from the I/O lines. Since the power to the bus
switch is derived from a front-end power plane, a 100Ω
resistor should be placed in series with the power supply
of the bus switch.
When the plug-in card is removed from the connector, the
BD_SEL# connection is broken first, and the BD_SEL#
voltage pulls up to 5VIN. This causes Q2 to turn off, which
re-enables the bus switch, and the precharge resistors are
again connected to the LTC4244 PRECHARGE pin for the
remainder of the extraction process.
Other CompactPCI Applications
The LTC4244-1 is designed for CompactPCI designs
where the –12V supply is not being used on the plug-in
board. The VEEOUT power good comparator, VEEIN UVL,
and VEE circuit breaker functions are disabled. The VEEIN
pin should be connected to GND and the VEEOUT pin left
floating if a –12V output is not needed.
If no 3.3V supply input is required, Figure 10 illustrates
how the LTC4244 should be configured: 3.3VSENSE and
3.3VIN are connected to 5VIN and 3.3VOUT is connected to
5VOUT.
For applications where the BD_SEL# connector pin is
typically connected to ground on the backplane, the circuit
in Figure 11 allows the LTC4244 to be reset simply by
pressing a pushbutton switch on the CPCI plug in board.
This arrangement eliminates the requirement to extract
and reinsert the CPCI board in order to reset the LTC4244’s
circuit breaker.
V(I/O)
TIMER/Auxiliary VCC
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
Once the TIMER pin voltage has ramped to within 1.6V of
12VIN, the auxiliary VCC function is enabled. In the event
the 12VIN supply voltage collapses, the LTC4244 will
continue to draw power from the charge stored on the
TIMER pin capacitor until the internal VCC node drops
below its undervoltage lockout threshold or the 12VIN
supply voltage recovers, whichever happens first.
BACKPLANE
CONNECTOR
PCB EDGE
BACKPLANE
CONNECTOR
BD_SEL#
1.2k
1k 5
OFF/ON
LTC4244*
GROUND
8
GND
4244 F11
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. BD_SEL# Pushbutton Toggle Switch
R2
0.007Ω
5VIN
5V
PUSHBUTTON
SWITICH
100Ω
0.25W
Q2
IRF7457
5VOUT
LONG 5V
R4
10Ω
Z4
17
16
13
3.3VIN 3.3VSENSE 5VIN
GROUND
8
14
5VSENSE
15
GATE
R5
1k
18
C1
0.33µF
3
3.3VOUT 5VOUT
LTC4244*
GND
4244 F10
Z4: SMAJ5.0A
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. No 3.3V Supply Application Circuit
42441f
19
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Power MOSFET Selection Criteria
The LTC4244 uses external MOSFETs to limit the 5V and
3.3V supply currents. The following criteria should be
used when selecting these MOSFET’s:
1. The on resistance should be low enough to prevent an
excessive voltage drop across the sense resistor and
the series MOSFET at rated load current given the
amount of gate to source voltage provided by the
LTC4244.
2. The drain-to-source breakdown voltage should be high
enough for the device to survive overvoltage transients
that may occur during fault conditions (the 5V and 3.3V
transient voltage limiters shown in Figure 1 will limit the
maximum drain-source voltage seen by these MOSFET’s
during fault conditions).
3. The MOSFET package must be able to handle the
maximum, steady state power dissipation for the ON
state without exceeding the device’s rated maximum
junction temperature. The MOSFET’s steady-state, dissipated power can be expressed as:
PON = IMAX2 • RDS(ON)
(8)
The increase in steady-state junction-to-ambient temperature is given by:
TJ – TA = PON • RθJA
(9)
4. The MOSFET package must be able to dissipate the heat
resulting from the power pulse during the transition
from off to on. A worst-case approximation for the
magnitude of the power pulse is:
POFF-ON <
n VOUT • (IINRUSH + ILOAD )
2
(10)
where n VOUT = 5VOUT or 3.3VOUT, IINRUSH is the transient current initially charging the load capacitance and
ILOAD is the steady-state load current. The duration, tON,
of the power pulse can be expressed as:
tON =
CLOAD • VOUT
IINRUSH
5. The MOSFET package must be able to sustain the
maximum pulse power that occurs in the event the
LTC4244 attempts to power-up either the 5V or 3.3V
back-end supply into a short circuit (see Design Example for a sample calculation).
Table 8 lists some power MOSFET’s that can be used with
the LTC4244.
Input Overvoltage Transient Protection
Hot plugging a board into a backplane generates inrush
currents from the backplane power supplies due to the
charging of the plug-in board capacitance. To reduce this
transient current to a safe level, the CPCI Hot Swap
specification restricts the amount of unswitched capacitance used on the input side of the plug-in board. Each
medium or long power pin connected to the CPCI female
connector on the plug-in board is required to have a 10nF
ceramic bypass capacitor to ground. Bulk capacitors are
only allowed on the switched output side of the LTC4244
(5VOUT, 3.3VOUT, 12VOUT, VEEOUT). Some bulk capacitance is allowed on the 5VIN and 3.3VIN Early Power
planes, but only because a current limiting resistor is
assumed to decouple the connector pin from the bulk
capacitance. Circuits normally placed on the unswitched
side Early Power plane (PCI Bridge, for example) need to
to be decoupled by a current limiting resistor.
Disallowing bulk capacitors on the input power pins mitigates the inrush current during Hot Swap. However, it also
tends to create a resonant circuit formed by the inductance
of the backplane power supply trace in series with the
inductance of the connector pin and the parasitic capacitance of the plug-in board (mainly due to the large power
FET). Upon board insertion, the ringing of this circuit can
exhibit a peak overshoot of 2.5 times the steady-state
voltage (>30V for 12VIN).
There are two methods for abating the effects of these high
voltage transients: using voltage limiters to clip the transient to a safe level and snubber networks. Snubber
networks are series RC networks whose time constants
(11)
42441f
20
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
are experimentally determined based on the board’s parasitic resonance circuits. As a starting point, the capacitors
in these networks are chosen to be 10× to 100× the power
MOSFET’s COSS under bias. The series resistor is a value
determined experimentally that ranges from 1Ω to 50Ω,
depending on the parasitic resonance circuit. Note that in
all LTC4244 circuit schematics, both transient voltage
limiters and snubber networks have been added to the
12VIN and VEEIN supply rails and should always be used.
Snubber networks are not necessary on the 3.3VIN or the
5VIN supply lines since their absolute maximum voltage
ratings are 13.5V. Transient voltage limiters, however, are
recommended as these devices provide large-scale transient protection for the LTC4244 in the event of abrupt
changes in supply current. All protection networks should
be mounted very close to the LTC4244’s supply pins using
short lead lengths to minimize trace resistance and inductance. This is shown schematically in Figures 12 and 13
and a recommended layout of the transient protection
devices around the LTC4244 is shown in Figure 14.
R2
0.007Ω
5VIN
5V
R1
0.005Ω
3VIN
3.3V
Q2
IRF7457
Q1
IRF7457
3VOUT
3.3V
R3
10Ω
17
3.3VIN
5VOUT
5V
15
16
3.3VSENSE GATE
R4
10Ω
18
13
14
3.3VOUT 5VIN
Z3
R5
1k
C1
0.047µF
3
5VOUT
5VSENSE
Z4
LTC4244*
GND
Z3, Z4: SMAJ5.0A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
8
4244 F12
Figure 12. Place Transient Protection Devices Close to LTC4244’s 5VIN and 3.3VIN Pins
C5
0.1µF
11
12
14
15
16
17
18
19
Z4
VIAS TO
GND PLANE
Z1
LTC4244*
C5
R14
Figure 13. Place Transient Protection Devices
Close to LTC4244’s 12VIN and VEEIN Pins
10
9
C4
R13
8
4244 F16
Z1, Z2: SMAJ12CA
*ADDITIONAL DETAILS OMITTED FOR CLARITY
7
8
Z3
Z2
6
GND
5VIN
5
LTC4244*
R14
10Ω
4
VEEIN
3
C4
0.1µF
2
12VIN
2
Z1
20
1
R13
10Ω
3.3VIN
13
–12VIN
1
12VIN
4244 F14
Z1
12VIN
VEEIN
GND
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
Figure 14. Recommended Layout for Transient Protection
Components
42441f
21
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
PCB Layout Considerations
Swap applications where load currents can be 10A, narrow PCB tracks exhibit more resistance than wider tracks
and operate at more elevated temperatures. Since the
sheet resistance of 1 ounce copper foil is approximately
0.45mΩ/o, track resistance and voltage drops add up
quickly in high current applications. Thus, to keep PCB
track resistance, voltage drop and temperature to a minimum, the suggested trace width in these applications for
1 ounce copper foil is 0.03” for each ampere of DC current.
For proper operation of the LTC4244’s circuit breaker,
4-wire Kelvin sense connections between the sense resistor and the LTC4244’s 5VIN and 5VSENSE pins and 3.3VIN
and 3.3VSENSE pins are strongly recommended. The PCB
layout should be balanced and symmetrical to minimize
wiring errors. In addition, the PCB layout for the sense
resistors and the power MOSFETs should include good
thermal management techniques for optimal device power
dissipation. A recommended PCB layout for the sense
resistor, the power MOSFET and the GATE drive components around the LTC4244 is illustrated in Figure 15. In Hot
CURRENT FLOW
TO LOAD
3.3VIN
3.3V
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
CURRENT FLOW
TO LOAD
SENSE
RESISTOR
SO-8
W
D
G
D
S
D
S
D
S
VIA/PATH
TO GND
R3
TRACK WIDTH W:
0.03" PER AMPERE
ON 1 OZ Cu FOIL
3.3VOUT
3.3V
W
GATE
R5
12
11
9
13
8
10
14
7
15
16
17
18
19
20
C1
6
5
4
3
2
1
LTC4244*
CTIMER
GND
CURRENT FLOW
TO SOURCE
VIA TO
GND PLANE
GND
W
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
4244 F15
Figure 15. Recommended Layout for Power MOSFET, Sense Resistor and GATE Components for the 3.3V Rail
42441f
22
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
the PC board. For 1 ounce copper foil plating, a general rule
is 1 ampere of DC current per via making sure the via is
properly dimensioned so that solder completely fills the
void. For other plating thicknesses, check with your PCB
fabrication facility.
Design Example
As a design example, consider a CPCI Hot Swap application with the following power supply requirements:
Table 4. Design Example Power Supply Requirements
VOLTAGE
SUPPLY
MAXIMUM DC
SUPPLY CURRENT
LOAD
CAPACITANCE
12V
450mA
100µF
5V
5A
2200µF
3.3V
7A
2200µF
–12V
100mA
100µF
The first step is to select the appropriate values of RSENSE
for the 5V and 3.3V supplies. Calculating the value of
RSENSE is based on ILOAD(MAX) and the lower limit for the
circuit breaker threshold voltage (47mV for both the 5V
and 3.3V circuit breakers). If a 1% tolerance is assumed
for the sense resistors, then 5mΩ and 7mΩ resistor
values yield the following minimum and maximum ITRIP
values:
perature curve, the device’s on-resistance can be expected
to increase by about 20% over its room temperature value.
Recalculation of the steady-state values of RON and junction temperature yields approximately 12.6mΩ and 81°C,
respectively. The I • R drop across the 3.3V sense resistor
and series MOSFET at maximum load current under these
conditions will be less than 124mV.
The next step is to select appropriate values for C1 and
CTIMER. Assuming that the total current for the 5V supply
is constrained to less than 6A during power-up (6 × 5V
medium length connector pins at 1A per pin), then the
inrush current shouldn’t exceed:
IINRUSH < 6A – ILOAD(5VOUT) = 6A – 5A = 1A
This yields:
C1 >
⇒ C1 >
IGATE(MAX) • 2200µF
IINRUSH(MAX)
ITRIP(MIN)
ITRIP(MAX)
5mΩ
9.3A
11.5A
7mΩ
6.6A
8.2A
So sense resistor values of 7mΩ and 5mΩ should suffice
for the 5V and 3.3V supplies, respectively.
The second step is to select MOSFETs for the 5V and 3.3V
supplies. The IRF7457’s on resistance is less than 10.5mΩ
for VGS > 4.5V and a junction temperature of 25°C. Since
the maximum load current requirement for the 3.3V supply is 7A, the steady-state power the device may be
required to dissipate is 514mW. The IRF7457 has a
junction-to-ambient thermal resistance of 50°C/Watt. If a
maximum ambient temperature of 50°C is assumed, this
yields a junction temperature of 75.7°C. According to the
IRF7457’s Normalized On-Resistance vs Junction Tem-
(13)
100µA • 2200µF
= 220nF
1A
Hence a C1 value of 330nF ±10% should suffice. The value
of CTIMER for this design example will be constrained by
the duration of the 12V supply inrush current, which
according to Equation 2 is:
Table 5. ITRIP vs RSENSE
RSENSE (1% RTOL)
(12)
tON(12VOUT) <
⇒ tON(12VOUT) <
2 • CLOAD • 12V
ILIMIT(MIN) – ILOAD(MAX)
2 • 100µF • 12V
= 24ms
550mA – 450mA
(14)
In order to guarantee that the LTC4244’s TIMER fault
inhibit period is greater than 24ms, the value of CTIMER
should be:
CTIMER >
⇒ CTIMER >
24ms • ITIMER(MAX)
12V – VTIMER(MAX)
(15)
24ms • 26µA
= 61.8nF
12V – 1.9 V
So a value of 82nF (±10%) should suffice.
42441f
23
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
The next step is to verify that the thermal ratings of the
external 5V and 3.3V MOSFETs aren’t being exceeded
during power-up cycles into the designed loads or into a
short circuit.
The amount of heating in the 5V and 3.3V MOSFETs during
a normal power cycle depends on the LTC4244’s GATE pin
current (refer to Gate Current vs Temperature plot in the
Typical Performance Characteristics section). The magnitude of the off-on power pulse that results in maximum
heating of the MOSFETs is given by Equation 10 as:
POFF-ON =
(
n VOUT • IINRUSH(MIN) + ILOAD(n VOUT)
2
) (16)
where
IINRUSH(MIN) =
The duration and magnitude of the power pulse that
results during a short-circuit condition on either the 5V or
3.3V outputs are a function of the TIMER capacitor and the
LTC4244’s foldback current limit. Figure 16 shows the
worst-case power dissipated in the 5V and 3.3V external
FETs vs V5VOUT and V3.3VOUT, respectively. In the case of
the 3.3V external MOSFET, the maximum dissipated power
is 24 Watts (V3.3VOUT = 0.9V). For the 5V external MOSFET,
the maximum dissipated power is 22 Watts (V5VOUT =
1.75V). The maximum duration of the short-circuit powerpulse is given by Equation 19 as:
tPULSE < CTIMER(MAX) •
⇒ tPULSE <
CLOAD
• IGATE(MIN)
C1(MAX)
(17)
12V – VTIMER(MIN)
ITIMER(MIN)
(19)
(82nF + 8.2nF) • (12V – 1.3V)
16µA
⇒ tPULSE < 60.3ms
The duration of the power-pulse is given by Equation 11
as:
25
CLOAD • n VOUT
IINRUSH(MIN)
5V RSENSE = 0.007Ω
3.3V RSENSE = 0.005Ω
(18)
Solving these equations for the 5V and 3.3V supplies
yields:
Table 6
POFF-ON
tINRUSH(MAX)
5V MOSFET
12.8W
90ms
3.3V MOSFET
11.8W
60ms
DISSIPATED POWER (W)
tINRUSH <
20
5V MOSFET
15
10
3.3V MOSFET
5
0
Under these conditions, the IRF7457 datasheet’s Thermal
Response vs Pulse Duration curve indicates that the
junction-to-ambient temperature will increase by 60°C for
the 5V MOSFET and 46°C for the 3.3V MOSFET.
0
1
3
4
2
OUTPUT VOLTAGE (V)
5
4244 F16
Figure 16. Worst-Case 5V and 3.3V MOSFET
Dissipated Power vs Output Voltage
42441f
24
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
The IRF7457’s Thermal Response vs Pulse Duration curve
indicates that the worst-case increase in junction-toambient temperature during a power-cycle for the 3.3V
MOSFET is less than 96°C while the worst-case increase
in junction-to-ambient temperature for the 5V MOSFET is
less than 88°C.
Power MOSFET and Sense Resistor Selection
Tables 7 and 8 list current sense resistors and power
MOSFET transistors, respectively, that can be used with
the LTC4244’s circuit breakers. Table 9 lists supplier web
site addresses for discrete components mentioned
throughout the LTC4244 data sheet.
Transient Voltage Suppressors SMAJ12A and SMAJ5.0A
are supplied by:
Diodes, Incorporated
Westlake Village, CA 91362 USA
Phone: 01 (805) 446-4800
Web Site: http://www.vishay.com or
http://www.diodes.com
Transistors MMBT2222A and MMBT3906 are supplied
by:
ON Semiconductor
Phoenix, AZ 85008 USA
Phone: 01 (602) 244-6600
Web Site: http://www.onsemi.com
Obtaining Information on Specific Parts
For more information or to request a copy of the
CompactPCI specification, contact the PCI Industrial Computer Manufacturers Group at:
PCI Industrial Computer Manufacturers Group
Wakefield, MA 01880 USA
Phone: 01 (718) 224-1239
Web Site: http://www.picmg.com
42441f
25
LTC4244/LTC4244-1
U
W
U U
APPLICATIO S I FOR ATIO
Table 7. Sense Resistor Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
DESCRIPTION
MANUFACTURER
1A
LR120601R055F
WSL1206R055
0.055Ω, 0.5W, 1% Resistor
IRC-TT
Vishay Dale
2A
LR120601R028F
WSL1206R028
0.028Ω, 0.5W, 1% Resistor
IRC-TT
Vishay Dale
5A
LR120601R011F
WSL2010R011
0.011Ω, 0.5W, 1% Resistor
IRC-TT
Vishay Dale
7.6A
WSL2512R007
0.007Ω, 1W, 1% Resistor
Vishay Dale
10A
WSL2512R005
0.005Ω, 1W, 1% Resistor
Vishay Dale
Table 8. N-Channel Power MOSFET Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
DESCRIPTION
MANUFACTURER
0A to 2A
MMDF3N02HD
Dual N-Channel SO-8, RDS(ON) = 0.1Ω
ON Semiconductor
2A to 5A
MMSF5N02HD
Single N-Channel SO-8, RDS(ON) = 0.025Ω
ON Semiconductor
5A to 10A
MTB50N06V
Single N-Channel DD-Pak, RDS(ON) = 0.028Ω
ON Semiconductor
5A to 10A
IRF7457
Single N-Channel SO-8, RDS(ON) = 0.007Ω
International Rectifier
5A to 10A
Si7880DP
Single N-Channel PowerPAKTM, RDS(ON) = 0.003 Ω
Vishay Siliconix
PowerPAK is a trademark of Vishay Siliconix
Table 9. Manufacturers’ Web Site
MANUFACTURER
WEB SITE
International Rectifier
www.irf.com
ON Semiconductor
www.onsemi.com
IRC-TT
www.irctt.com
Vishay Dale
www.vishay.com
Vishay Siliconix
www.vishay.com
Diodes, Inc.
www.diodes.com
42441f
26
LTC4244/LTC4244-1
U
PACKAGE DESCRIPTIO
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.045 ±.005
20 19 18 17 16 15 14 13 12
.254 MIN
.150 – .165
.0165 ± .0015
11
.229 – .244
(5.817 – 6.198)
.058
(1.473)
REF
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN20 (SSOP) 0204
42441f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4244/LTC4244-1
U
TYPICAL APPLICATIO
C9
0.01µF PER
POWER PIN
C8
0.01µF PER
POWER PIN
5V
R1
0.005Ω
3.3VIN
CLOAD(5VOUT)
Q1
IRF7457
CLOAD(3.3VOUT)
Z3
LONG 3.3V
Z2
R4
10Ω
R3
10Ω
Z4
C7
0.01µF
3.3VIN 3.3VSENSE GATE 3.3VOUT 5VIN
12VIN
12V
5VSENSE
C1
R5 0.33µF
1k
5VOUT
12VOUT
VEEIN
CLOAD(12VOUT)
OFF/ON
BD_SEL#
VEEOUT
R18 10k
LTC4244-1
FAULT
LONG V(I/O)
R17
10k
HEALTHY#
PWRGD
PCI_RST#
RESETIN
TIMER
DRIVE RESETOUT
GND PRECHARGE
R15
1Ω
C4
0.01µF
C3 4.7nF
R9 24Ω
GROUND
I/O PIN 128
R13
10Ω
I/O DATA LINE 1
•
•
•
•
•
•
I/O DATA LINE 128
Z1, Z2: SMAJ12A
VOUT
12V
500mA
+
R19 1k
I/O PIN 1
VOUT
3.3V
7A
+
R21
1.8Ω
R20
1.2k
VOUT
5V
5A
+
R22
2.7Ω
LONG 5V
3.3V
R2
Q2
0.007Ω IRF7457
5VIN
R10 18Ω
R11
10k
R12
10k
1V
±10%
C2
0.082µF
LOCAL_PCI_RST#
VOUT
3.3V
R8 1k
Q3
R7 12Ω
MMBT2222A
VIN
3.3V
RESET#
I/O #1
•
•
•
R14
10Ω
R6
10k
I/O #128
PCI
BRIDGE
CHIP
Z3, Z4: SMAJ5.0A
4244 F17
Figure 17. Typical LTC4244-1 Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Hot Swap Controller
Dual Supplies from 3V to 12V, Additional –12V
LTC1422
Hot Swap Controller
Single Supply Hot Swap in SO-8 from 3V to 12V
LT1640AL/LT1640AH
Negative Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
LT1641-1/LT1641-2
Positive Voltage Hot Swap Controllers in SO-8
Supplies from 9V to 80V, Latch Off/Autoretry
LTC1642
Fault Protected Hot Swap Controller
3V to 15V, Overvoltage Protection Up to 33V
LTC1643AL/LTC1643AL-1 PCI Bus Hot Swap Controllers
LTC1643AH
3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1644
Compact PCI Bus Hot Swap Controller
3.3V, 5V, ±12V, Local Reset Logic and Precharge
LTC1645
2-Channel Hot Swap Controller
Operates from 1.2V to 12V, Power Sequencing
LTC1646
Dual CompactPCI Hot Swap Controller
3.3V, 5V Supplies Only
LTC1647
Dual Hot Swap Controller
Dual ON Pins for Supplies from 3V to 15V
LTC4211
Hot Swap Controller with Multifunction Current Control
Single Supply, 2.5V to 16.5V, MSOP
LTC4240
CompactPCI Hot Swap Controller
I2C Interface Allows Control and Readback of Device Functions
LT4250
–48V Hot Swap Controller in SO-8
–20V to –80V, Active Current Limiting
LTC4251
–48V Hot Swap Controller in SOT-23
Floating Supply, Active Current Limiting and Fast Circuit Breaker
42441f
28 Linear Technology Corporation
LT/TP 0204 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2003