Intersil ISL97694AIRTZ Single or multiple cell li-ion battery powered 4-channel and 6-channel led driver Datasheet

Single or Multiple Cell Li-ion Battery Powered
4-Channel and 6-Channel LED Drivers
ISL97692, ISL97693, ISL97694A
The ISL97692, ISL97693, ISL97694A are Intersil’s highly
integrated 4- and 6-channel LED drivers for display
backlighting. These parts maximize battery life by featuring
only 1mA quiescent current, and by operating down to 2.4V
input voltage, with no need for higher voltage supplies.
Features
The ISL97692 has four channels and provides 8-bit PWM
dimming with adjustable dimming frequency up to 30kHz. The
ISL97693 has six channels with Direct PWM dimming control.
The ISL97694A has 6 channels and provides 8-, 10-, or 12-bit
PWM dimming with adjustable dimming frequency up to
30kHz, 7.5kHz, or 1.875kHz, respectively, controlled with I2C
or PWM input.
• 90% efficient at 6P5S, 3.7V and 20mA (ISL97693, ISL97694A)
The ISL97692 and ISL97694A feature phase shifting that may
be enabled optionally, providing an optimized phase delay
between channels. In the ISL97692 and ISL97694A, phase
shifting can multiply the effective dimming frequency by four
and six allowing above audio-band PWM dimming with 10-bit
dimming resolution.
The ISL97692, ISL97693, ISL97694A employ adaptive boost
architecture, which keeps the headroom voltage as low as
possible to maximize battery life while allowing ultra low
dimming duty cycle as low as 0.005% at 100Hz dimming
frequency in Direct PWM mode.
The ISL97692, ISL97693, ISL97694A incorporate extensive
protection functions including string open and short circuit
detections, OVP, and OTP.
The ISL97692, ISL97693 are offered in the 16 Ld 3x3mm TQFN
package, and a 16 bump 1.7x1.7mm WLCSP for the ISL97692.
The ISL97694A is offered in the 20 Ld 3x4mm TQFN package. All
parts operate in ambient temperature range of -40°C to +85°C.
L1
VIN: 2.4V~5.5V
• 4 channels, up to 40mA each (ISL97692) or 6 channels, up to
30mA each (ISL97693, ISL97694A)
• Low 0.8mA quiescent current
• PWM dimming control with internally generated clock
- 8-bit resolution with adjustable dimming frequency up to
30kHz (ISL97692, ISL97694A)
- 12-bit resolution with adjustable dimming frequency up to
1.875kHz (ISL97694A)
- Optional automatic channel phase shift (ISL97692,
ISL97694A)
- Linear dimming from 0.025%~100% up to 5kHz or
0.4%~100% up to 30kHz (ISL97692, ISL97694A)
• Direct PWM dimming with 0.005% minimum duty cycle at
100Hz
• ±2.5% output current matching
• Adjustable switching frequency from 400kHz to 1.5MHz
Applications
• Tablet, Notebook PC and Smart Phone Displays LED
Backlighting
Related Literature
• AN1733 “ISL97694AIRT-EVZ Evaluation Board User Guide”
• AN1734 “ISL97693AIRT-EVZ Evaluation Board User Guide”
• AN1735 “ISL97692 Evaluation Board User Guide” Coming
Soon.
10
D1
10µH
• 2.4V minimum input voltage, supports single cell applications
VOUT: 24.5V, 6 x 20mA
4.7µF 4.7µF
4.7µF
10
1
VIN
1µF
LX
COMP
100pF 470k
2.2nF
12k
ILED (mA)
OVP
15nF
23.7k
ISL97694A
ISET
53k
PGND
0.1
0.01
AGND
fPWM: 200Hz
SDA/PWMI
SCL
CH1
EN
CH2
0.001
fPWM: 100Hz
CH3
FPWM
CH4
0.0001
0.001
291k
FSW
CH5
CH6
143k
FIGURE 1. ISL97694A TYPICAL APPLICATION DIAGRAM
May 1, 2014
FN7839.5
1
0.01
0.1
1
INPUT DIMMING DUTY CYCLE (%)
10
FIGURE 2. ULTRA LOW PWM DIMMING LINEARITY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97692, ISL97693, ISL97694A
Table of Contents
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Dimming Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Direct PWM Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM Dimming Frequency Adjustment (ISL97692, ISL97694A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Dynamic Headroom Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soft-Start and Power ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-OFF Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operation with Input Voltage Greater than 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SMBus/I2C Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Slave Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SMBus/I2C Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boost Output Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
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Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused LED Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dimming Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Current Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
22
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCB Layout with TQFN and WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
General Power PAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fault Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Circuit Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
26
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26
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Typical Application Circuits
L1
V IN: 2 .4V ~5.5V
D1
10µH
VOUT : 24 .5V , 4 x 20 mA
4.7µF 4.7µF
4.7 µF
10
VIN
1µF
LX
COMP
100pF 470 k
OVP
15nF
2 .2nF 23 .7k
12k
ISL97692
ISET
PGND
53k
AGND
ENPS
CH1
PWMI
CH2
EN
CH3
FPWM
CH4
291 k
FSW
143 k
FIGURE 3. ISL97692 TYPICAL APPLICATION DIAGRAM - 4P7S
L1
V IN: 2 .4V ~5.5V
D1
10µH
VOUT : 24.5V, 6 x 20mA
4.7µF 4.7µF
4.7 µF
10
VIN
1µF
LX
COMP
100pF 470 k
OVP
15nF
2 .2nF
12k
23 .7k
ISL97693
ISET
53k
PGND
AGND
PWMI
EN
CH1
CH2
CH3
FSW
143 k
CH4
CH5
CH6
FIGURE 4. ISL97693 TYPICAL APPLICATION DIAGRAM - 6P7S
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Typical Application Circuits (Continued)
L1
V IN: 2 .4V ~5.5V
D1
10µH
VOUT : 24.5V, 6 x 20mA
4.7µF 4.7µF
4.7 µF
10
VIN
1µF
LX
COMP
100 pF 470k
OVP
15nF
2.2nF
12k
23.7k
ISL97694A
ISET
PGND
53k
AGND
SDA/PWMI
SCL
EN
CH1
CH2
CH3
FPWM
CH4
291 k
FSW
CH5
CH6
143 k
FIGURE 5. ISL97694A TYPICAL APPLICATION DIAGRAM- 6P7S
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ISL97692, ISL97693, ISL97694A
Block Diagrams
24V, 4x40mA
VIN: 2.4V TO 5.5V
OPTIONAL FUSE
10µH
VIN
LX
O/P SHORT
EN
REG
INTERNAL BIAS
OVP
OVP
FSW
OSC &
RAMP
COMP
PWM/
PFM
LOGIC
FET
DRIVERS
IMAX ILIMIT
PGND
COMP
GM
AMP
+
-
ISET
8-BIT
DAC
HIGHEST
VF
STRING
DETECT
DYNAMIC
HEADROOM
CONTROL
OPEN CKT, SHORT CKT
DETECTION
CH1
CH2
CH3
CH4
1
+
-
2
REF
GEN
3
REF_OVP REF_VSC
+
-
PWMI
8-BIT
DIGITIZER
FPWM
ENPS
4
DIRECT
PWM
DETECT
PHASE
SHIFT & PWM
DIMMING
CONTROLLER
ISL97692
TEMP
SENSOR
FIGURE 6. ISL97692 BLOCK DIAGRAM
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Block Diagrams (Continued)
24V, 6x30mA
VIN: 2.4V TO 5.5V
OPTIONAL FUSE
10µH
VIN
LX
O/P SHORT
EN
INTERNAL BIAS
REG
OVP
OVP
FSW
OSC &
RAMP
COMP
PWM/
PFM
LOGIC
FET
DRIVERS
IMAX ILIMIT
PGND
GM
AMP
COMP
8-BIT
DAC
HIGHEST
VF
STRING
DETECT
DYNAMIC
HEADROOM
CONTROL
+
-
+
-
OPEN CKT, SHORT CKT
DETECTION
1
2
REF
GEN
ISET
CH1
CH2
CH3
CH4
CH5
CH6
3
4
5
REF_OVP REF_VSC
+
-
PWMI
6
PWM
DIMMING
CONTROLLER
ISL97693
TEMP
SENSOR
FIGURE 7. ISL97693 BLOCK DIAGRAM
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Block Diagrams (Continued)
24V, 6x30mA
VIN: 2.4V TO 5.5V
OPTIONAL FUSE
10µH
VIN
LX
O/P SHORT
EN
REG
INTERNAL BIAS
OVP
OVP
FSW
OSC &
RAMP
COMP
PWM/
PFM
LOGIC
FET
DRIVERS
IMAX ILIMIT
PGND
GM
AMP
COMP
8-BIT
DAC
HIGHEST
VF
STRING
DETECT
DYNAMIC
HEADROOM
CONTROL
+
-
+
-
OPEN CKT, SHORT CKT
DETECTION
1
2
REF
GEN
ISET
CH1
CH2
CH3
CH4
CH5
CH6
3
4
5
REF_OVP REF_VSC
SCL
SDA/PWMI
+
-
I2C
CONTROLLER
6
PHASE
SHIFT & PWM
DIMMING
CONTROLLER
FPWM
DIRECT
PWM
DETECT
ISL97694A
TEMP
SENSOR
FIGURE 8. ISL97694A BLOCK DIAGRAM
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7
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Pin Configurations
s
ISL97692
(1.7x1.7x0.53mm, 16 BALL, 0.4mm PITCH WLCSP)
TOP VIEW
CH3
CH2
CH1
15
14
13
16 CH4
ISL97692
(16 LD TQFN)
TOP VIEW
AGND 1
FPWM
EN
LX
A
COMP
PWMI
VIN
PGND
B
AGND
ISET
FSW
OVP
C
CH4
CH3
CH2
CH1
D
4
3
2
1
12 OVP
COMP 2
ISET 3
ENPS
11 FSW
Thermal PAD
FPWM 8
VIN 7
EN 6
9 LX
PWMI 5
ENPS 4
10 PGND
ISL97694A
(20 LD TQFN)
TOP VIEW
CH4
CH3
CH2
1
6
16
CH1
12 OVP
AGND
2
15
OVP
11 FSW
COMP
3
14
FSW
13
NC
Thermal PAD
4
SCL
5
12
PGND
NC
6
11
LX
7
8
9
10
FPWM
ISET
VIN
VIN 8
9 LX
EN 7
COMP 4
PWMI 6
17
CH6
10 PGND
ISET 5
18
EN
AGND 3
8
19
SDA/PWMI
Thermal PAD
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CH5
CH1
CH5 1
CH6 2
20
13
CH2
14
CH3
15
16 CH4
ISL97693
(16 LD TQFN)
TOP VIEW
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Pin Descriptions
ISL97692
PIN
NAME
TQFN
WLCSP
ISL97693
ISL97694A
AGND
1
C4
3
2
Analog Ground for precision circuits.
CH5
-
-
1
20
Channel 5 current sink and channel monitoring. Tie pin to GND if channel
unused.
CH6
-
-
2
1
Channel 6 current sink and channel monitoring. Tie pin to GND if channel
unused.
COMP
2
B4
4
3
External compensation. Fit a series RC comprising 12k and 15nF from COMP
to GND.
ISET
3
C3
5
4
Channel current setting. The LED channel current is adjusted from 2mA to
40mA (ISL97692) or to 30mA with (ISL97693, ISL97694A) resistor RSET from
ISET pin to GND.
ENPS
4
A4
-
-
Enable Phase Shift PWM Dimming Control. High = Enable. Low = Disable.
PWMI
5
B3
6
-
PWM Input Signal for ISL97692/3 for brightness control.
SCL
(ISL97694A)
-
-
-
5
I2C serial clock input. Mode selection to PWMI input when tied to GND for
ISL97694A.
SDA/PWMI
(ISL97694A)
-
-
-
7
I2C serial data input and output. PWMI input when SCL tied to GND for
ISL97694A.
EN
6
A2
7
8
Enable Input. High = Normal operation. Low = Shutdown.
DESCRIPTION
VIN
7
B2
8
9
Input Supply Voltage.
FPWM
8
A3
-
10
Tie FPWM to VIN to select Direct PWM mode. In Direct PWM mode, the channel
outputs follow the PWMI pin’s frequency and pulse width.
Connect resistor RFPWM from FPWM to GND to select PWM dimming frequency
adjustment. In this mode, the channel outputs follow the PWMI pin’s PWM
duty, and the LED PWM dimming frequency is set by the value of resistor
RFPWM.
LX
9
A1
9
11
Input to boost switch.
PGND
10
B1
10
12
Power ground (LX, CIN, and COUT Power return).
FSW
11
C2
11
14
Switching Frequency Adjustment. The boost switching frequency is adjusted
from 400kHz to 1.5MHz with resistor RFSW from FSW pin to GND.
OVP
12
C1
12
15
Overvoltage protection input.
CH1
13
D1
13
16
Channel 1 current sink and channel monitoring. Tie pin to GND if channel
unused.
CH2
14
D2
14
17
Channel 2 current sink and channel monitoring. Tie pin to GND if channel
unused.
CH3
15
D3
15
18
Channel 3 current sink and channel monitoring. Tie pin to GND if channel
unused.
CH4
16
D4
16
19
Channel 4 current sink and channel monitoring. Tie pin to GND if channel
unused.
NC
-
-
-
6, 13
PAD
Submit Document Feedback
-
9
Not connected internally.
Connect to PGND and refer to the figure 32 in the General Power PAD Design
Considerations.
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Ordering Information
PART NUMBER
(Notes 1, 4)
PART
MARKING
ISL97692IRTZ (Note 2)
7692
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
PKG.
DWG. #
16 Ld 3x3x0.75mm TQFN
L16.3x3D
ISL97692IIZ-T (Note 3)
7692
-40 to +85
16 Bump 1.7x1.7mm, 0.4mm Pitch WLCSP
W4x4.16B
ISL97693IRTZ (Note 2)
7693
-40 to +85
16 Ld 3x3x0.75mm TQFN
L16.3x3D
ISL97694AIRTZ (Note 2)
694A
-40 to +85
20 Ld 3x4x0.8mm TQFN
L20.3x4A
ISL97692IRTZ-EVALZ
Evaluation board for TQFN
ISL97692IIZ-EVZ
Evaluation board for WLCSP
ISL97693IRTZ-EVALZ
Evaluation board for TQFN
ISL97694AIRT-EVZ
Evaluation board for TQFN
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and
SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/
JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL97692, ISL97693, ISL97694A. For more information on MSL please
see tech brief TB363.
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10
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Absolute Maximum Ratings
Thermal Information
(Note 5)
VIN, ISET, COMP, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
PWMI, FPWM, FSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
EN, ENPS, SCL, SDA/PWMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
CH1 to CH6, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Maximum Average Current Into LX Pin for TQFN . . . . . . . . . . . . . . . . . .2.6A
Maximum Average Current Into LX Pin for CSP . . . . . . . . . . . . . . . . . . . . 1A
ESD Ratings
Human Body Model (Tested per JESD22-A114F)
(ISL97692, ISL97693) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Human Body Model (Tested per JESD22-A114F) (ISL97694A) . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (JESD22-C101E) . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Ld TQFN (Notes 6, 7) . . . . . . . . . . . . . . .
51
4.6
20 Ld TQFN (Notes 6, 7) . . . . . . . . . . . . . . .
45
3.0
16 Bump WLCSP (Note 6) . . . . . . . . . . . . . .
82
N/A
Thermal Characterization (Typical) (Note 8)
PSIJT (°C/W)
16 Ld TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.11
20 Ld TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.1
Thermal Characterization (Typical)
PSIJB (°C/W)
16 Bump WLCSP (Note 9) . . . . . . . . . . . . . . . . . . . . . . . .
22
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V to 5.5V
Output Voltage (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Up to 26V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Voltage Ratings are all with respect to the AGND pin.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings.
9. PSIJB is the PSI junction-to-board thermal characterization parameter.
Electrical Specifications
range, -40°C to +85°C.
PARAMETER
VIN = EN = 3.3V, TA = +25°C unless otherwise noted. Boldface limits apply over the operating temperature
DESCRIPTION
CONDITION
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
GENERAL
VIN
IVIN_Standby
IVIN
Backlight Supply Voltage, (Notes 11, 12)
TA = +25°C
Standby current
EN = Low, LDO disabled
VIN Active Current, ILED = 40mA (ISL97692) All channels 100% duty
30mA (ISL97693/(ISL97694A)
All channels 0% duty
VOUT
Output Voltage
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
2.4
2
EN Input Low Voltage
ENHi
EN Input High Voltage
V
µA
2.5
mA
0.8
mA
VIN  2.7V, ILED = 40mA (ISL97692) 30mA
(ISL97693/4A)
Undervoltage Lockout Hysteresis
ENLow
5.5
1
2.15
26
V
2.35
V
150
mV
0.5
1.5
V
V
BOOST SWITCHING REGULATOR
SS
SWILimit
rDS(ON)
Soft-start
100% LED Duty Cycle
Boost FET Current Limit for QFN
Boost FET Current Limit for CSP
2.7V< VIN < 5.5V, fSW = 600kHz, L = 10µH,
TA ≤ +55°C
Internal Boost Switch ON-Resistance
TA = +25°C
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11
7
ms
2.45
2.8
3.2
A
1.2A
1.6A
A
212
m
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Electrical Specifications
range, -40°C to +85°C. (Continued)
PARAMETER
Eff_peak
DMAX
DMIN
fSW
VIN = EN = 3.3V, TA = +25°C unless otherwise noted. Boldface limits apply over the operating temperature
DESCRIPTION
Peak Efficiency
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
Boost Switching Frequency
CONDITION
MIN
(Note 10)
MAX
(Note 10)
UNIT
VIN = 5.5V, VOUT = 21V, TA = +25°C,
RFSW = 144kΩICH1-CH6 = 20mA,
L = 10µH with DCR 150mΩ
90
%
VIN = 2.7V, VOUT = 21V, TA = +25°C,
RFSW = 144kΩICH1-CH6 = 20mA,
L = 10µH with DCR 150mΩ
76
%
FSW = 400kHz
93.5
%
FSW = 1.5MHz
93
%
FSW = 400kHz
11
%
FSW = 1.5MHz
15
%
RFSW = 216kΩ
360
RFSW = 72.1kΩ
RFSW = 57.7kΩ
ILX_leakage
TYP
400
440
1.2
1.35
1.5
kHz
MHz
1.65
MHz
10
µA
LX Leakage Current
LX = 26V
Channel-to-Channel DC Current Matching
ILED = 20mA
-2.5
+2.5
%
Current Accuracy
ILED = 20mA
-3
+3
%
REFERENCE
IMATCH
IACC
FAULT DETECTION
VSC
Channel Short Circuit Threshold
Vtemp
Over-Temperature Threshold
VOVPlo
Overvoltage Limit on OVP Pin
OVPfault
6.75
8
9.25
150
1.180
OVP Short Detection Fault Level
1.22
V
°C
1.245
V
75
mV
300
mV
CURRENT SOURCES
Vheadroom
Dominant Channel Current Source
Headroom at CH Pin
ILED = 20mA
TA = +25°C
ILED(max)
Maximum LED Current per Channel
2.7V < VIN < 5.5V, VOUT = 21V
(ISL97692 QFN)
40
mA
2.7V < VIN < 5.5V, VOUT = 21V
(ISL97692 WLCSP, ISL97693, and
ISL97694A)
30
mA
PWM GENERATOR
VIL
Guaranteed Range for PWM Input Low
Voltage
VIH
Guaranteed Range for PWM Input High
Voltage
0.5
1.5
8-bit Dimming Resolution
FPWMI
PWMI Input and Output Frequency Range
V
V
100
30,000
Hz
10-bit Dimming Resolution
100
7.5
kHz
12-bit Dimming Resolution
100
1.87
kHz
DPWMACC
Direct PWM Dimming Output Resolution
(ISL97692, ISL97693 and ISL97694A)
80
ns
tDPWM_ON_MIN
Direct PWM Dimming Minimum On-Time
(ISL97692, ISL97693 and ISL97694A)
350
ns
PWMACC
PWM Dimming with Adjustable Dimming
Frequency Output Resolution
FPWM
(ISL97692, ISL97694A)
8
bit
ISL97694A, En10Bit = 1
10
bit
ISL97694A, En12Bit = 1
12
bit
Generated PWM Dimming Frequency Range (ISL97692, ISL97694A)
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12
100
30,000
Hz
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Electrical Specifications
range, -40°C to +85°C. (Continued)
PARAMETER
VIN = EN = 3.3V, TA = +25°C unless otherwise noted. Boldface limits apply over the operating temperature
DESCRIPTION
CONDITION
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
0.5
V
VDD
V
0.17
V
10
µA
SMBus/I2C INTERFACE (ISL97694A only)
VIL
Guaranteed Range for Data, Clock Input Low
Voltage
VIH
Guaranteed Range for Data, Clock Input High
Voltage
VOL
SMBus/I2C Output Data Line Logic Low
Voltage
IPULLUP = 4mA
Input Leakage On SDA/SCL
Measured at 4.8V
ILEAK
1.5
-10
SMBus/I2C TIMING SPECIFICATIONS (ISL97694A only)
tEN-SMBus/I2C
Minimum Time between VIN>UVLO and
SMBus/I2C Enabled
FSCL
SCL Clock Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
2
ms
400
kHz
1.3
µs
0.6
µs
tHD:STA
Hold Time After (Repeated) START Condition
tSU:STA
Repeated Start Condition Setup Time
0.6
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tHD:DAT
Data Hold Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tHIGH
Low Period of SCL Clock
1.3
µs
tLOW
High Period of SCL Clock
0.6
µs
After this Period, the First Clock is Generated
tF
Clock/data Fall Time
300
ns
tR
Clock/data Rise Time
300
ns
NOTES:
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. At maximum VIN of 5.5V, minimum VOUT is 6V. Minimum VOUT can be lower at lower VIN.
12. Limits established by characterization and are not production tested.
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13
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Typical Performance Curves
95
92
6P5S LEDs
85
6P6S LEDs
EFFICIENCY (%)
EFFICIENCY (%)
88
86
84
6P7S LEDs
82
70
65
78
55
3.7
4.2
4.7
50
5.2
6P7S LEDs
75
60
3.2
6P6S LEDs
80
80
76
2.7
6P5S LEDs
90
90
0
20
40
60
80
100
PWM DIMMING (%)
INPUT VOLTAGE (V)
FIGURE 9. EFFICIENCY vs VIN (ICH: 20mA, fDIM: 200Hz, FOR
LEDs: 6P5S, 6P6S, 6P7S)
FIGURE 10. EFFICIENCY vs PWM DIMMING (VIN: 3.7V, ICH: 20mA,
fDIM: 200Hz, FOR LEDs: 6P5S, 6P6S, 6P7S)
2.5
MATCHING ACCURACY (%)
LED CURRENT (mA)
20
15
10
5
0
0
20
40
60
80
100
1.5
IC#3
0.5
-0.5
IC#2
-1.5
-2.5
IC#1
0
FIGURE 11. PWM DIMMING LINEARITY (VIN: 3.7V, VOUT: 21V FOR
6P7S, fDIM: 200Hz)
IL
VOUT
VOUT
VLX
VLX
VCH
VCH
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14
2
3
4
5
6
7
FIGURE 12. CHANNEL MATCHING ACCURACY (VIN: 3.7V, VOUT: 21V
FOR 6P7S, ICH: 20mA)
IL
FIGURE 13. START-UP (100% DIRECT PWM DIMMING, VIN: 3.7V,
ICH: 20mA, LEDs: 6P7S, fDIM: 200Hz)
1
CHANNEL NUMBER
INPUT DIMMING DUTY CYCLE (%)
FIGURE 14. START-UP (100% DECODED PWM DIMMING, VIN: 3.7V,
ICH: 20mA, LEDs: 6P7S, fDIM: 200Hz)
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Typical Performance Curves (Continued)
IL
IL
VOUT
VOUT
VLX
VLX
VCH
VCH
FIGURE 15. START-UP (50% DIRECT PWM DIMMING, VIN: 3.7V,
ICH: 20mA, LEDs: 6P7S, fDIM: 200Hz)
FIGURE 16. START-UP (50% DECODED PWM DIMMING, VIN: 3.7V,
ICH: 20mA, LEDs: 6P7S, fDIM: 200Hz)
S:Start
R/W A
A
A P:Stop
SCL
PWM INPUT
SDA
Slave address:01011010 Command code (8bit) Brightness(100%): 11111111
ICH
I_CH
FIGURE 17. MINIMUM DIMMING DUTY CYCLE
(0.003% DIRECT PWM DIMMING MODE, fDIM: 100Hz)
FIGURE 18. I2C CONTROL TIMING AND CHANNEL CURRENT
(100% DIMMING, ISL97694A)
IL
I_L
IL
VLX
V_LX
V LX
V_CH1
VCH1
V CH 1
VCH2
V_CH2
V CH 2
FIGURE 19. DECODED PWM DIMMING WITH PHASE SHIFT
(VIN: 3.7V, ICH: 20mA, DIM: 17%, fDIM: 250Hz,
LEDs: 6P6S)
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15
FIGURE 20. DIRECT PWM DIMMING WITHOUT PHASE SHIFT
(VIN: 3.7V, ICH: 20mA, DIM: 17%, fDIM: 250Hz,
LEDs: 6P6S)
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Theory of Operation
For example, for a 200Hz input PWM frequency, the minimum
duty cycle is:
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97692,
ISL97693, ISL97694A employs current mode control boost
architecture that has a fast current sense loop and a slow voltage
feedback loop. This architecture achieves the fast transient
response, which is essential for portable product backlight
applications where the backlight must not flicker when the
power source is changed from a drained battery to an AC/DC
adapter.
The number of LEDs that can be driven by ISL97692, ISL97693,
ISL97694A depends on the type of LED chosen in the
application. The maximum output is 26V at 40mA from 2.7V
input.
Enable
Take the EN input high to enable the ISL97692, ISL97693,
ISL97694A for normal operation and low to enter low-power
shutdown, which immediately turns off LED channels and the
boost regulator.
Dimming Controls
The ISL97692, ISL97693, ISL97694A allows the LED current to be
programmed in the range 2mA to 40mA (ISL97692) or 2mA to
30mA (ISL97693, ISL97694A) by RSET per Equation 1:
1066
I LEDmax = --------------R SET
(EQ. 1)
Min Duty Cycle = 350ns  200Hz = 0.007%
(EQ. 4)
The resolution is calculated by Equation 5 according to the input
PWM frequency, and the fixed 80ns resolution of ISL97692,
ISL97693, ISL97694A.
1
PWM Resolution = ------------------------------------------------------------------------------80ns  Input PWM Frequency
(EQ. 5)
Thus the effective resolution at 200Hz is 15.9 bits:
1
PWM Resolution = -------------------------------------- = 62500 = 15.9bits
80ns  200Hz
(EQ. 6)
Phase Shift Control
The ISL97692, ISL97694A are capable of delaying the phase of
each current source. Conventional LED drivers exhibit the worst
load transients to the boost circuit by turning on all channels
simultaneously, as shown in Figures 21 and 23. In contrast, the
ISL97692, ISL97694A phase shift each channel by turning them
on once during each PWM dimming period, as shown in
Figures 22 and 24. At each dimming duty cycle (except at 100%)
the sum of the phase shifted total current will be less than a
conventional LED drivers’ total current.
For the ISL97692, ISL97694A, the channels are separated by
360°/N, where N is number of channels enabled. For example, if
three channels are enabled, they will be separated by 120°.
If the channels are combined for higher current application, the
phase shift function must be disabled by connecting the ENPS
pin to ground.
Where:
- 1066 is a constant determined by design
- RSET is the resistor from ISET pin to GND (Ω
- ILEDmax is the peak current set by resistor RSET (A)
For example, if the required LED current (ILEDmax) is 40mA, then
the RSET value needed is:
ILED1-20mA
R SET = 1066  0.04 = 26.65k
ILED4-20mA
(EQ. 2)
ILED2-20mA
ILED3-20mA
Choose the nearest standard resistor: 26.65k0.1%
ILED_Total_80mA
Direct PWM Dimming
The ISL97693 always operates in Direct PWM dimming mode.
The ISL97692 and ISL97694A can be selected to operate in
Direct PWM dimming mode by connecting the FPWM pin to VIN
and the SCL pin of ISL97694A must be tied to GND.
5
10
TIME (ms)
15
FIGURE 21. CONVENTIONAL 4-CH LED DRIVER WITH 10% PWM
DIMMING CHANNEL CURRENT (UPPER) AND TOTAL
CURRENT (LOWER)
With Direct PWM, the channel outputs follow the input PWM
signal frequency and pulse width, as provided to the PWMI pin.
When PWMI is high, all channels sink the current set by the RSET
resistor. When PWMI is low, all channels are high-Z.
The maximum allowed input PWM frequency at PWMI is 30kHz.
The minimum duty is calculated by Equation 3 according to the
input PWM frequency, and is set by the minimum channel
on-time of 350ns.
Min Duty Cycle = 350ns  Input PWM Frequency
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(EQ. 3)
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
PWMI
ILED1-20mA
60%
40%
tPWMIN
tFPWM (tPWMOUT)
tOFF
tON
40%
60%
ILED2-20mA
ILED1
ILED3-20mA
ILED2
ILED4-20mA
ILED3
ILED_Total_20mA
ILED4
5
10
TIME (ms)
FIGURE 22. ISL97692 PHASE SHIFT 4-CHANNELS LED DRIVER WITH
10% PWM DIMMING CHANNEL CURRENT (UPPER) AND
TOTAL CURRENT (LOWER)
ILED1
FIGURE 25. ISL97692 4 -CHANNELS PHASE SHIFT TIMING
ILLUSTRATION
PWM Dimming Frequency Adjustment
(ISL97692, ISL97694A)
ILED4-20mA
The ISL97692 and ISL97694A can use an internal oscillator to
generate the PWM dimming frequency. In this mode, the duty of
the signal at PWMI pin is measured with 8-, 10- or 12-bit
resolution, and applied to the internally generated PWM
dimming frequency. The dimming frequency is set by an external
resistor RFPWM at the FPWM pin for ISL97692 and ISL97694A,
per Equation 7:
ILED3-20mA
ILED2-20mA
ILED1-20mA
ILED_Total_80mA
R0
R FPWM = ----------------F PWM
5
10
TIME (ms)
FIGURE 23. CONVENTIONAL LED DRIVER PWM DIMMING CHANNEL
AND TOTAL CURRENT AT 50% DUTY CYCLE
ILED4-20mA
ILED3-20mA
Where:
- R0 is determined by design
- R0 = 58.1 X 106 for 8-bit
- R0 = 14.5 X 106 for 10-bit
- R0 = 36.2 X 105 for 12-bit
- FPWM is the required PWM dimming frequency (Hz)
- RFPWM is the resistor from FPWM pin to GND (
For example, to set the PWM dimming frequency to 480Hz at
8-bit resolution:
6
58.1 10
R FPWM = ------------------------ = 121k
480
ILED2-20mA
ILED1-20mA
(EQ. 8)
The maximum allowed input and output PWM dimming
frequency varies according to the PWM resolution, per Table 1.
This is configurable for the ISL97694A by the En12Bit and
En10Bit bits in register 0x01.
ILED_Total_40mA
10
TIME (ms)
5
FIGURE 24. ISL97692 PHASE SHIFT LED DRIVER PWM DIMMING
CHANNEL AT 50% DUTY CYCLE
TABLE 1. MAX PWM DIMMING FREQUENCY SET BY RFPWM
PART
ISL97692
ISL97694A
Submit Document Feedback
(EQ. 7)
17
MAX FREQUENCY
(kHz)
PWM RESOLUTION
(BIT MODE)
30
8
30
8
7.5
10
1.875
12
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Current Matching and Current Accuracy
Each channel of the LED current is regulated by a current sink
circuit.
The LED peak current is set by the external RSET resistor
according to Equation 1. The current sink MOSFETs in each LED
driver channel output are designed to run at ~300mV to optimize
power loss versus accuracy requirements. The sources of errors
of the channel-to-channel current matching come from internal
amplifier offsets, internal layout and reference accuracy. These
parameters are optimized for current matching and absolute
current accuracy. Absolute accuracy is also determined by the
external resistor RSET, and so a 0.1% tolerance resistor is
recommended.
Dynamic Headroom Control
The ISL97692, ISL97693, ISL97694A features a proprietary
Dynamic Headroom Control circuit that detects the highest
forward voltage string or effectively the lowest voltage on any of
the channel pins. When this lowest channel voltage is lower than
the short circuit threshold, VSC, such voltage will be used as the
feedback signal for the boost regulator. The boost makes the
output to the correct level, such that the lowest channel pin is at
the target headroom voltage. Since all LED stacks are connected
to the same output voltage, the other channel pins will have a
higher voltage, but the regulated current source circuit on each
channel will ensure that each channel has the same current. The
output voltage will regulate cycle-by-cycle and it is always
referenced to the highest forward voltage string in the
architecture.
Soft-Start and Power ON
Once the ISL97692, ISL97693, ISL97694A are powered up and
the EN pin is taken high, the boost regulator will begin to switch
and the current in the inductor will ramp-up. The current in the
boost power switch is monitored and the switching is terminated
in any cycle where the current exceeds the current limit. The
ISL97692, ISL97693, ISL97694A includes a soft-start feature
where this current limit starts at a low value (350mA). This is
stepped up to the final 2.8A current limit in seven further steps of
350mA. These steps will happen over typically 7ms, and will be
extended at low LED PWM frequencies if the LED duty cycle is
low. This allows the output capacitor to be charged to the
required value at a low current limit and prevents high input
current for systems that have only a low to medium output
current requirement.
UVLO
VIN
(RISING)
VO
SOFT-START
(7ms)
FEEDBACK
REGULATION
ESTABLISHED
EN
PWMI
ICHn
Power-OFF Sequence
VIN
VO
VUVLO - 150mV
BOOST CONVERTER
TURNED OFF
tOFF AFTER REACHING
{VUVLO - 150mV}
EN
DEPENDS ON APPLICATION
PWMI
ICHn
Operation with Input Voltage Greater than
5.5V
The ISL97692, ISL97693, ISL97694A boost regulator can
operate from an input voltage higher than 5.5V, and up to 23V, as
long as an additional supply voltage between 2.4V and 5.5V is
available for the VIN pin. Please refer to Figure 26 for a typical
application schematic adopting this solution.
Note that there will be also an initial in-rush current to COUT when
VIN is applied. This is determined by the ramp rate of VIN and the
values of COUT and L
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
L1
V BATT : 2.4 V~21 .8V
D1
10 µH
V OUT: 24 .5V , 6 x 20 mA
4.7µF 4.7µF
4.7µF
2.4V~5.5 V
VIN
LX
COMP
100 pF 470 k
OVP
15 nF
2.2nF
12k
23 .7k
ISL97694A
ISET
53 k
PGND
AGND
SDA/PWMI
SCL
EN
CH1
CH2
CH3
FPWM
CH4
291k
FSW
CH5
CH6
143k
FIGURE 26. LED DRIVER OPERATION WITH INPUT VOLTAGE UP TO 26V
SMBus/I2C Communications
Slave Device Address
The ISL97694A is controlled by SMBus/I2C for PWM dimming, and
The slave address contains 7 MSB plus one LSB as R/W bit, but
these 8 bits are usually called Slave Address bytes. As shown in
Figure 27, the high nibble of the Slave Address byte is 0x5 or
b’0101’ to denote the “backlight controller class”. Bit 0 is always the
R/W bit, as specified by the SMBus/I2C protocol. If the device is in
the write mode where bit 0 is 0, the slave address byte is 0x5A or
b’01011010’. If the device is in the read mode where bit 0 is 1, the
slave address byte is 0x5B or b’01011011’.
powers up in the shutdown state. The ISL97694A is enabled when
both the EN pin is high and the BL_CTL bit in register 0x01 is
programmed to 1.
Write Byte
The Write Byte protocol is only three bytes long. The first byte starts
with the slave address followed by the “command code,” which
translates to the “register index” being written. The third byte
contains the data byte that must be written into the register selected
by the “command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
MSB
0
1
0
1
1
0
1
R/W
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EB
DEVICE ADDRESS
/W
R IT
DEVICE IDENTIFIER
RE
AD
As shown in Figure 30, the four byte long Read Byte protocol starts
out with the slave address followed by the “command code”, which
translates to the “register index.” Subsequently, the bus direction
turns around with the rebroadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains the data
being returned by the backlight controller. That byte value in the
data byte reflects the value of the register being queried at the
“command code” index. Note the bus directions, which are
highlighted by the shaded label that is used on cycles during which
the slaved backlight controller “owns” or “drives” the Data line. All
other cycles are driven by the “host master.”
IT
Read Byte
FIGURE 27. SLAVE ADDRESS BYTE DEFINITION
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
SMBus/I2C Register Definitions
When the ISL97694A is configured to 10-bit or 12-bit operation,
write the PWM Brightness Control Register LSB (address 0x02) first.
The subsequent write of PWM Brightness Control Register MSB
(address 0x00) updates the contents of both registers to the PWM
engine.
The backlight controller registers are Byte wide and accessible
via the SMBus/I2C Read/Write Byte protocols. Their bit
assignments are provided in Figures 29 and 30 with reserved bits
containing a default value of “0”.
SMBCLK
tF
tR
tLOW
VIH
VIL
tHIGH
tHD:DAT
tHD:STA
tSU:STA
tSU:DAT
tSU:STO
SMBDAT
VIH
VIL
P
tBUF
S
P
S
NOTES:
SMBus/I2C DESCRIPTION
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
R/W = READ ENABLE AT HIGH; WRITE ENABLE AT LOW
FIGURE 28. SMBUS/I2C INTERFACE for ISL97694A
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
W
A
COMMAND CODE
A
DATA BYTE
A
P
MASTER TO SLAVE
SLAVE TO MASTER
FIGURE 29. WRITE BYTE PROTOCOL for ISL97694A
1
7
1
1
8
1
1
8
1
1
8
1
1
S
SLAVE ADDRESS
W
A
COMMAND CODE
A
S
SLAVE ADDRESS
R
A
DATA BYTE
A
P
MASTER TO SLAVE
SLAVE TO MASTER
FIGURE 30. READ BYTE PROTOCOL for ISL97694A
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May 1, 2014
ISL97692, ISL97693, ISL97694A
TABLE 2. I2C REGISTER ALL LOCATIONS FOR ISL97694A
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
VALUE
SMBUS/I2C
PROTOCOL
0x00
PWM Brightness Control
Register MSB
BRT11
BRT10
BRT9
BRT8
BRT7
BRT6
BRT5
BRT4
0xFF
Read and Write
0x01
Device Control Register
-
-
-
-
PS_EN
BL_CTL
0x00
Read and Write
0x02
PWM Brightness Control
Register LSB
BRT3
BRT2
BRT1
BRT0
-
-
0xF0
Read and Write
En12Bit En10Bit
-
-
TABLE 3. I2C REGISTER FUNCTIONS FOR ISL97694A
ADDRESS
REGISTER
DATA BIT DESCRIPTIONS
0x00
PWM Brightness Control
Register MSB
BRT[11..4] = DPWM duty cycle brightness control
In 8 bit PWM data mode, PWM data is BRT[11..4]
In 10 bit PWM data mode, PWM data is BRT[11..2]
In 12 bit PWM data mode, PWM data is BRT[11..0]
0x01
Device Control Register
PS_EN = Phase shift On/Off (1: Phase shift enabled, 0: Phase shift disabled)
BL_CTL = Backlight On/Off (1: driver enabled if EN pin is high, 0 = driver shutdown)
{En12Bit, En10Bit} = {0,0} to select 8 bit PWM data mode
{En12Bit, En10Bit} = {0,1} to select 10 bit PWM data mode
{En12Bit, En10Bit} = {1,0} to select 12 bit PWM data mode
0x02
PWM Brightness Control
Register LSB
BRT[3.0] = DPWM duty cycle brightness control (10 and 12 bit PWM data modes only). Note: this data
is saved, but the PWM engine is only updated with BRT[11..0] or BRT[11..2] when the PWM Brightness
Control Register MSB 0x00 is written
Component Selection
The design of the boost converter is simplified by an internal
compensation scheme allowing easy design without complicated
calculations. Please select your component values using the
following recommendations.
Input Capacitor
It is recommended that a 4.7µF to 10µF X5R/X7R or equivalent
ceramic input capacitor is used.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the boost output voltage, VOUT,
and keeps the voltage at a safe level. The OVP threshold is set as
Equation 9:
R1 + R2
V OVP  min  = 1.22V  ---------------------R2
(EQ. 9)
Where:
- 1.22V is the intended bandgap voltage by design
- VOVP is the maximum boost output voltage, VOUT (V)
- R1 is the resistor from OVP pin to the boost output (
- R2 is the resistor from OVP pin to GND (
The total R1 plus R2 series resistance should be high to minimize
power loss through the resistor network.
For example, choosing R1 = 470k and R2 = 23.7k per the
Typical Application Circuits on page 3 and Block Diagrams on
page 5. Set VOVP(typ) to 25.41V (Equation 10).
470 + 23.7
V OVP  typ  = 1.22V  ---------------------------- = 25.41V
23.7
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(EQ. 10)
The OVP threshold, R1, and R2 tolerances should also be taken
into account (Equations 11 and 12).
R1min + R2max
V OVP  min  = 1.18V  ---------------------------------------------R2max
(EQ. 11)
R1max + R2min
V OVP  max  = 1.24V  ---------------------------------------------R2min
(EQ. 12)
Calculating VOVP using the OVP threshold range (1.18V to 1.24V)
and 0.1% resistor tolerances gives an actual VOVP range of 24.53V
to 25.88V for the 25.4V previous example (Equations 13 and 14).
 470  0.999  +  23.7  1.001 
V OVP  min  = 1.18V  -------------------------------------------------------------------------------- = 24.53V
 23.7  1.001 
(EQ. 13)
 470  1.001  +  23.7  0.999 
 max  = 1.24V  -------------------------------------------------------------------------------- = 25.88V
 23.7  0.999 
(EQ. 14)
V
OVP
It is recommended that parallel capacitors are placed across the
OVP resistors such that R1/R2 = C2/C1. Using a C1 value of at
least 30pF is recommended. These capacitors reduce the AC
impedance of the OVP node, which reduces noise susceptibility
when using high value resistors.
Boost Output Voltage Range
The working range of the boost output voltage, VOUT is from 40%
to 100% of the maximum output voltage, VOVP, set by resistors
R1 and R2, as described in the previous section.
The target applications should be considered carefully to ensure that
VOVP is not set unnecessarily high. For example, using R = 470k
and R2 = 23.7k per the “Typical Application Circuits” on page 3
sets VOVP to between 24.53V to 25.88V when tolerances are
considered.
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
The minimum voltage, VOVP(min) = 24.53V, sets the maximum
number of LEDs per channel because this is the worst case
minimum voltage that the boost converter is guaranteed to
supply.
Output Capacitor
The maximum voltage, VOVP(max) = 25.88V, sets the minimum
number of LEDs per channel because it sets the lowest voltage
that the boost converter is guaranteed to reach:
40% x 25.88V = 10.35V.
Schottky Diode
Using LEDs with a VF tolerance of 3V to 4V, this VOVP example is
suitable for strings of 4 to 6 LEDs. If fewer than 4 LEDs per
channel are specified, VOVP must be reduced.
Compensation
Switching Frequency
The boost switching frequency is adjusted by resistor RFSW
(Equation 15):
10
 8.65 10 
f SW = -------------------------------R FSW
(EQ. 15)
Where:
- 8.65x1010 is determined by design
- fSW is the desirable boost switching frequency (Hz)
- RFSW is resistor from FSW pin to GND (
It is recommended that a two of 4.7µF X5R/X7R or equivalent
ceramic output capacitor is used.
The Schottky diode should be rated for at least the same forward
current as the inductor, and for a reverse voltage equal to at least
the maximum output voltage, OVP.
The ISL97692, ISL97693, ISL97694A are boost regulator uses a
current mode control architecture with a standardized external
compensation network connected to the COMP pin. The
component values shown in the “Typical Application Circuits” on
page 3, are ideal for most typical applications. The network
comprises a series RC of 12kΩ and 15nF from COMP to GND.
Applications
Unused LED Channels
Connect unused LED channels to GND.
Dimming Mode Setting
Inductor
TABLE 5. DIMMING MODE SETTING OF ISL97694A
Choose the inductance according to Table 4:
TABLE 4. INDUCTOR SELECTION
BOOST FREQUENCY
INDUCTANCE
(µH)
400kHz to 700kHz
10 to 15
700kHz to 1MHz
6.8 to 10
1MHz to 1.5MHz
4.7 to 8.2
1.5MHz
3.3 to 4.7
(EQ. 16)
Where:
- IL is the minimum inductor saturation current rating (A)
- VOUT is the maximum output voltage set by OVP (V)
- ILED is the sum of the channel currents (A)
- VIN is the minimum input voltage (V)
If the calculation produces a current rating higher than the 3.08A
maximum boost switch current limit, then a 3A inductor current
rating is adequate.
For example, for a system using 4 LED channels with 30mA per
channel and a maximum output voltage (OVP) of 24.53V with an
input supply of 2.7V minimum as shown by Equation 17:
1.35  24.53   4  0.03 
I L = ----------------------------------------------------------------- = 1.47A
2.7
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SCL
SDA /PWMI
Direct PWM
GND
PWM
VIN
Phase shift
PWM
GND
PWM
Connect a resistor FPWM pin to
GND
I2C Control
SCL
SDA
Connect a resistor FPWM pin to
GND
FPWM
High Current Applications
The inductor saturation current rating should be as provided by
Equation 16:
1.35  V OUT  I LED
I L = ----------------------------------------------------V IN
DIMMING
MODE
(EQ. 17)
Each channel of the ISL97692 supports 40mA continuous sink
current. Each channel of the ISL97693, ISL97694A supports 30mA
continuous sink current. For applications that need higher current,
multiple channels can be ganged together (Tables 6 and 7).
TABLE 6. GANGED ISL97692 CHANNELS FOR HIGHER CURRENT
TOTAL
CHANNELS
CHANNEL
CURRENT
CHANNEL CONNECTIONS
4
40mA per channel
CH1, CH2, CH3, CH4
2
80mA per channel
{CH1 & CH2}, {CH3 & CH4}
1
160mA
{CH1 & CH2 & CH3 & CH4}
TABLE 7. GANGED ISL97693, ISL97694A CHANNELS FOR HIGHER
CURRENT
TOTAL
CHANNELS
CHANNEL
CURRENT
CHANNEL CONNECTIONS
6
30mA per channel
CH1, CH2, CH3, CH4, CH5, CH6
3
60mA per channel
{CH1, CH2}, {CH3, CH4}, {CH5, CH6}
2
90mA per channel
{CH1, CH2, CH3},
{CH4, CH5, CH6}
1
180mA
{CH1, CH2, CH3, CH4, CH5, CH6}
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Figure 31 shows CH1 and CH2 ganged for a high current
application.
output capacitors and away from the higher dv/dt traces. The
OVP connection then needs to be as short as possible to the pin.
The AGND connection of the lower OVP components is critical for
good regulation.
8. The COMP network and the rest of the analog components (on
ISET, FPWM, FSW, etc.) should be reference to AGND.
9. The heat of the chip is mainly dissipated through the exposed
thermal pad so maximizing the copper area around is a good
idea. A solid ground is always helpful for the thermal and EMI
performance.
CH1
10. The inductor and input and output capacitors should be mounted
as tight as possible, to reduce the audible noise and inductive
ringing.
CH2
FIGURE 31.
PCB Layout Considerations
PCB Layout with TQFN and WLCSP Package
Figures 33 and 34 shows the example of the PCB layout of
ISL97694A and ISL97692 WLCSP. This type of layout is
particularly important for this type of product, resulting in
high-current flow in the main loop’s traces. Careful attention
should be focused in the following layout details:
1. The typical application diagram (Figures 3, 4 and 5 on
pages 3, and 4) the separation of PGND and AGND is
essential, keeping the AGND referenced only local to the chip.
This minimizes switching noise injection to the feedback
sensing and analog areas, as well as eliminating DC errors
form high-current flow in resistive PC board traces.
2. Boost input capacitors, output capacitors, inductor and Schottky
diode should be placed together in a nice tight layout. Keeping
the grounds of the input, and output connected with low
impedance and wide metal is very important to keep these
nodes closely coupled.
3. If possible, try to maintain central ground node on the board and
use the input capacitors to avoid excessive input ripple for high
output current supplies. The filtering capacitors should be placed
close by the VIN pin.
4. Careful consideration should be taken with any traces carrying
high di/dt pulsating signals. Traces carrying high di/dt pulsating
signals should be kept as short and as tight as possible. The
current loop generates a magnetic field which can couple to
another conductor inducing unwanted voltage. Components
should be placed such that current flows through them in a
straight line as much as possible. This will help reduce size of
loops and reduce the EMI from the PCB.
11. For WLCSP, the solder pad on the PCB should not be larger than
the solder mask opening for the ball pad on the package. The
optimal solder joint strength, it is recommended a 1:1 ratio for
the two pads. Generally, vias should not be used to route highcurrent paths.
12. The amount of copper that should be poured (thickness)
depends upon the power requirement of the system. Insufficient
copper will increase resistance of the PCB, which will increase
heat dissipation.
13. While designing the layout of switched controllers, do not use the
auto routing function of the PCB layout software. The auto
routing connects the nets with same electrical name and does
not account for ideal trace lengths and positioning.
General Power PAD Design Considerations
Figures 32 show an example of how to use vias to reduce the heat
from the IC. For optimal thermal performance, use vias to distribute
heat away from the IC and to a system power plane. Fill the thermal
pad area with vias that are spaced 3x their radius (typically), centerto-center, from each other. The via diameters should be kept small,
but they should be large enough to allow solder wicking during
reflow. To optimize heat transfer efficiency, do not connect vias
using “thermal relief” patterns. The vias should be directly
connected to the plane with plated through-holes. Connect all vias to
the correct voltage potential (power plane) indicated in the
datasheet. For the ISL97692, ISL97693, ISL97694A, the thermal
pad can be connected to ground (GND).
5. If trace lengths are long, the resistance of the trace increases
and can cause some reduction in IC efficiency, and can also
cause system instability. Traces carrying power should be made
wide and short.
6. In discontinuous conduction mode, the direction of the current is
interrupted every few cycles. This may result in large di/dt
(transient load current). When injected in the ground plane the
current may cause voltage drops, which can interfere with
sensitive circuitry. The analog ground and power ground of the IC
should be connected very close to the IC to mitigate this issue
ISL97692, ISL97693 TQFN
ISL97694A TQFN
FIGURE 32. VIA PATTERN
7. For optimum load regulation and true VOUT sensing, the OVP
resistors should be connected independently to the top of the
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FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
PCB Layout
ISL97694A
INDUCTOR
CH1‐6
PVIN
DIODE
OVP RESISTORS
COUT
CIN
COUT
TOP LAYER(PGND)
PGND
PGND
BOTTOM LAYER(AGND)
PVOUT
TOP VIEW
BOTTOM VIEW
FIGURE 33. EXAMPLE OF PCB LAYOUT of ISL97694A
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ISL97692, ISL97693, ISL97694A
PCB Layout (Continued)
PVOUT
D1
PGND_OUT
RU RL
COUT1
COUT2
L1
PGND_OUT
ISL97692
PVIN
CIN1
CIN2
PGND_IN
PGND_IN and PGND_OUT
connected via bottom layer
AGND of analog setting components
very close to AGND pin
FIGURE 34. EXAMPLE OF PCB LAYOUT of ISL97692 WLCSP
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ISL97692, ISL97693, ISL97694A
Fault Protection and Monitoring
Overvoltage Protection (OVP)
The ISL97692, ISL97693, ISL97694A features extensive
protection functions to handle failure conditions automatically.
Refer to Figure 35 and Table 8 for details of the fault protections.
The integrated OVP circuit monitors the boost output voltage, VOUT,
and keeps the voltage at a safe level. The OVP threshold is set as
Equation 18:
The LED failure mode is either open or short circuit. An open
circuit failure of an LED only results in the loss of one channel of
LEDs without affecting other channels. Similarly, a short circuit
condition on a channel that results in that channel being turned
off does not affect other channels.
OVP = 1.22V   R UPPER + R LOWER   R LOWER
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97692, ISL97693, ISL97694A use feedback
from the LEDs to determine when it is in a stable operating
region and prevents apparent faults during these transient
events from allowing any of the LED stacks to fault out.
See Table 8 for more details.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels, which are above the short
circuit protection threshold, nominally 8V (the action taken is
described in Table 8).
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as
either an infinite resistance or a gradually increasing finite
resistance. The ISL97692, ISL97693, ISL97694A monitors the
current in each channel such that any string, which reaches the
intended output current is considered “good”. Should the current
subsequently fall below the target, the channel will be considered
an “open circuit”. Furthermore, should the boost output of the
ISL97692, ISL97693, ISL97694A reaches the VOVP limit, all
channels which are not “good” will immediately be considered as
“open circuit”.
(EQ. 18)
Where:
- 1.22V is the intended bandgap voltage by design
- VOVP is the maximum boost output voltage, VOUT (V)
- RUPPER is resistor from OVP pin to the boost output (
- RLOWER is resistor from OVP pin to GND (
Undervoltage Lockout
If the input voltage falls below the VUVLO level of ~2V, the
ISL97692, ISL97693, ISL97694A will stop switching and be reset.
Operation will restart only if the VIN is back in the normal
operating range.
Over-Temperature Protection (OTP)
The ISL97692, ISL97693, ISL97694A have an over-temperature
protection threshold set to +150°C. If this threshold is reached,
the boost stops switching and the ISL97692, ISL97693,
ISL97694A output current sinks are switched off. The ISL97692,
ISL97693, ISL97694A can be restarted by toggling VIN to below the
VUVLO level of ~2V, then back up to the normal input voltage
level, or by power recycling VIN.
Detection of an “open circuit” channel will result in a time-out
before disabling of the affected channel.
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ISL97692, ISL97693, ISL97694A
LX
VOUT
VIN
LX
FAULT
O/P
SHORT
DRIVER
OVP
IMAX
ILIMIT
FET
DRIVER
LOGIC
VSC
CH1
FAULT FLAG
CHx
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
FAULT
DETECT
LOGIC
DC1
PWM/OC1/SC1
DC2
Q1
Qx
PWM/OCx/SCx
PWM
GENERATOR
FIGURE 35. ISL97692, ISL97693, ISL97694A SIMPLIFIED FAULT PROTECTIONS
TABLE 8. ISL97692, ISL97693, ISL97694A PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
VOUT
REGULATED BY
OTHER CHANNELS ACTION
1
CH1 Short Circuit
Upper
Over-Temperature
Protection limit (OTP)
not triggered and
CH1 < 8V
CH1 ON and burns power.
2
CH1 Short Circuit
OTP triggered
Boost converter and channels are shut down until VIN is cycled
-
3
CH1 Short Circuit
OTP not triggered,
CH1 > 8V
CH1 disabled after 6 PWM cycle
time-out
Normal Operation
Highest LED string VF
of other channels
4
CH1 Open Circuit with OTP not triggered,
infinite resistance
CH1 < 8V
VOUT will ramp to OVP. CH1 will
time-out after 6 PWM cycles and
switch off. VOUT will then reduce to
normal level
Normal Operation
Highest LED string VF
of other channels
5
Output LED stack
voltage too high
Any channel that is below the target current will time-out after 6 PWM Highest LED string VF
cycles while VOUT is regulated at VOVP, and VOUT will then return to the of channels above
target current
normal regulation voltage required for other channels
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VOUT = VOVP
27
Normal Operation
Highest LED string VF
of other channels
FN7839.5
May 1, 2014
ISL97692, ISL97693, ISL97694A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
May 1, 2014
FN7839.5
Electrical Spec table under“Boost FET Current Limit for CSP” on page 11: Changed the Min from 1.20 to 1.2A
and Typ from 1.6 to 1.6A, removed the Max 2.0 value.
November 27, 2013
Electrical spec table on page 12 under FPWMI: Added 8- bit, 10-bit and 12-bit dimming resolution.
Electrical spec table on page 12 under PWMACC frequency output resolution: Added ISL97694A with frequency
range 10-bit and 12-bit.
Updated Equation 7 on page 17: From 58.1x106 to R0 and added R0 for 10-bit and 12-bit of ISL97694A.
November 6, 2013
- Updated Equation 6 on page 16: From 350ns to 80ns and the effective resolution at 200Hz from 13.50 bits to
15.9 bits
October 28, 2013
Ordering information table on page 10: Changed part marking for Part number ISL97692IIZ-T from TBD to
7692.
Electrical Spec Table on “BOOST SWITCHING REGULATOR” on page 11: Added “Boost FET Current Limit for CSP”.
September 19, 2013
- Added ISL97692 WLCSP to pin description, pin configuration, package diagram.
- Replaced “Operating Conditions” to “Recommended Operating Conditions” on page 11.
- Added part number ISL97692IIZ-T and ISL97693IRT-EVZ to Ordering information on page 10.
- Added Maximum Average Current into LX pin for WLCSP in Absolute Maximum Ratings on page 11.
- Added Boost FET current limit for WLCSP on page 11.
- Added LED max current for WLCSP on page 12.
- Updated Equation 6 on page 16.
- Thermal Information table on page 11: Added 16 Bump WLSCP to thermal resistance and thermal
characterization sections.
- PCB layout considerations updated on page 23.
- Example of WLCSP PCB layout added in Figure 35 on page 26.
- Added POD W4x4.16B “16 Ball Wafer Level Chip Scale Package (WLCSP)” to data sheet.
November 30, 2012
FN7839.4
Changed HBM from 2kV to 2.5kV.
September 7, 2012
FN7839.3
Changed CDM from 1kV to 2kV.
June 28, 2012
FN7839.2
- Modified title on page 1
- IVIN typ lowered to 0.8mA
- tENLow typ removed
- Added “Operation with Input Voltage Greater than 5.5V” on page 18.
- Updated Figure 20
- Added Figure 26, “LED DRIVER OPERATION WITH INPUT VOLTAGE UP TO 26V,” on page 19.
-Removed “Coming Soon” from ISL97694A parts in “Ordering Information” on page 10.
May 25, 2012
FN7839.1
Corrected LX pin connection in Figures 1, 3, 4 and 5. Moved tie point in between L1 and D1.
Changed Title in Figure 12 from “Accuracy vs WPM Dimming” to “Channel Matching Accuracy”
Revised Figures 9 and 10.
April 16, 2012
FN7839.0
Initial release.
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ISL97692, ISL97693, ISL97694A
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL97692, ISL97693, ISL97694A
Package Outline Drawing
W4x4.16B
4x4 ARRAY 16 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 2, 8/13
PIN 1
(A1 CORNER)
X
1.200
0.400
1.655±0.03
Y
D
0.400
16X 0.265±0.035
C
1.200
1.655±0.03
B
0.228
A
(4X)
4
0.10
TOP VIEW
3
2
1
0.295
0.200
0.228
BOTTOM VIEW
Z
PACKAGE
OUTLINE
0.10 Z
SEATING PLANE
3
0.290
2
0.265±0.035
Ø0.10 M Z X Y
Ø0.05 M Z
4
0.400
0.240
6 NSMD
TYPICAL RECOMMENDED LAND PATTERN
0.200±0.030
0.500±0.050
SIDE VIEW
NOTES:
1. Dimensions and tolerance and tolerance per ASMEY 14.5 - 1994.
2. Dimension is measured at the maximum bump diameter
parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the
spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. All dimensions are in millimeters.
6. NSMD refers to non-solder mask defined pad design per Intersil
Techbrief www.intersil.com/data/tb/tb451.pdf
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Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
5
8
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
0.75 ±0.05
C
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
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ISL97692, ISL97693, ISL97694A
Package Outline Drawing
L20.3x4A
20 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 6/10
3.00
0.10 M C A B
0.05 M C
4 20x 0.25 +0.05
17
-0.07
A
B
A
16x 0.50
6
PIN #1
INDEX AREA
20
16
1
6
PIN 1
INDEX AREA
4.00
2.65 +/0.10
-0.15
11
6
0.10 (4X)
A
10
VIEW "A-A"
TOP VIEW
7
1.65 +0.10
-0.15
20x 0.40+/-0.10
BOTTOM VIEW
SEE
DETAIL "X"
0.10 C
SEATING PLANE
0.08 C
0.80 MAX
C
SIDE VIEW
(3.80)
(2.65)
(16x 0.50)
(20x 0.25)
(20x 0.60)
C
0 . 2 REF
(1.65)
(2.80)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220VEGD-NJI.
either a mold or mark feature.
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