MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tunability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP196B has a digitally selectable resolution of about 10 ps and a net range of up to 10.4 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (Pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0]. The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 4. The IN/IN inputs can accept LVPECL (SE or Diff), or LVDS level signals. Because the MC100EP196B is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by LEN, in cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Switching devices from all “1” states on D[0:9] with SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will increase the delay equivalent to “D0”, the minimum increment. Select input pins D[10:0] may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage at the VCF pin can be accomplished by placing a 2.2 kW resistor between VCF and VEE for a 3.3 V power supply. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. Features • • • • • • June, 2014 − Rev. 2 MARKING DIAGRAMS* MC100 EP196B AWLYYWWG LQFP−32 FA SUFFIX CASE 873A 32 1 1 1 MC100 EP196B ALYWG G 32 QFN32 MN SUFFIX CASE 488AM A WL, L Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. • NECL Mode Operating Range: Maximum Input Clock Frequency >1.2 GHz Typical Programmable Range: 0 ns to 10 ns Delay Range: 2.2 ns to 12.4 ns 10 ps Increments Linearity ±40 ps max PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V © Semiconductor Components Industries, LLC, 2014 http://onsemi.com VCC = 0 V with VEE = −3.0 V to −3.6 V • IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels • A Logic High on the EN Pin Will Force Q to Logic Low • D[10:0] Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels • VBB Output Reference Voltage • These are Pb−Free Devices 1 Publication Order Number: MC100EP196B/D 27 D1 28 D3 29 D2 30 VEE 31 D4 32 D5 D6 D7 MC100EP196B 26 25 D8 1 24 D9 2 23 D10 3 22 4 21 IN IN VBB D0 VCC Q MC100EP196B 5 20 6 19 7 18 VEF Q VCC VCC 17 8 15 FTUNE 16 EN 14 CASCADE 13 CASCADE 12 VCC 11 SETMAX 10 SETMIN VEE 9 LEN VCF VEE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP (Top View) 27 26 D1 28 D2 29 D3 30 VEE D4 31 D5 D6 D7 32 25 D8 1 24 VEE D9 2 23 D0 D10 3 22 VCC IN 4 21 Q IN 5 20 Q VBB 6 19 VCC VEF 7 18 VCC VCF 8 17 FTUNE MC100EP196B 12 13 14 15 16 VCC CASCADE CASCADE EN LEN VEE 11 SETMAX 10 SETMIN 9 Exposed Pad (EP) Figure 2. 32−Lead QFN (Top View) http://onsemi.com 2 MC100EP196B Table 1. PIN DESCRIPTION Pin Name I/O Default State Description 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[0:9] LVCMOS, LVTTL, ECL Input Low Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE. (Note 1) 3 D[10] LVCMOS, LVTTL, ECL Input Low Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW to VEE. (Note 1) 4 IN LVPECL, LVDS Low Noninverted Differential Input. Internal 75 kW to VEE. 5 IN LVPECL, LVDS High Inverted Differential Input. Internal 75 kW to VEE. 6 VBB − − ECL Reference Voltage Output 7 VEF − − Reference Voltage for ECL Mode Connection 8 VCF − − LVCMOS, ECL, OR LVTTL Input Mode Select 9, 24, 28 VEE − − Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 13, 18, 19, 22 VCC − − Positive Supply Voltage. All VCC Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 10 LEN ECL Input Low Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE. 11 SETMIN ECL Input Low Single−ended Minimum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) 12 SETMAX ECL Input Low Single−ended Maximum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) 14 CASCADE ECL Output − Inverted Differential Cascade Output for D[10]. Typically Terminated with 50 W to VTT = VCC − 2 V. 15 CASCADE ECL Output − Noninverted Differential Cascade Output. for D[10] Typically Terminated with 50 W to VTT = VCC − 2 V. 16 EN ECL Input Low 17 FTUNE Analog Input − Fine Tune Input 21 Q ECL Output − Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V. 20 Q ECL Output − Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V. Single−ended Output Enable Pin. Internal 75 kW to VEE. 1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. http://onsemi.com 3 MC100EP196B Table 2. CONTROL PIN Pin State EN LOW (Note 3) Function HIGH LEN Output Holds Logic Low State LOW (Note 3) HIGH SETMIN SETMAX D10 Input Signal is Propagated to the Output Transparent or LOAD mode for real time delay values present on D[0:10]. LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10] are not recognized and do not affect delay. LOW (Note 3) Output Delay set by D[0:10] HIGH Set Minimum Output Delay LOW (Note 3) Output Delay set by D[0:10] HIGH Set Maximum Output Delay LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH HIGH CASCADE Output LOW, CASCADE Output HIGH 3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected. Table 3. CONTROL D[0:10] INTERFACE VCF VEF Pin (Note 4) VCF No Connect VCF 1.5 V $ 100 mV ECL Mode LVCMOS Mode LVTTL Mode (Note 5) 4. Short VCF (pin 8) and VEF (pin 7). 5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value is 2.2 kW $5%), between VCF and VEE pins. Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE CONTROL DATA SELECT INPUTS PINS (D [0:10]) POWER SUPPLY LVCMOS LVTTL LVPECL LVNECL PECL Mode Operating Range YES YES YES N/A NECL Mode Operating Range N/A N/A N/A YES Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor ESD Protection (R1) Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) QFN−32 LQFP−32 Flammability Rating Oxygen Index: 28 to 34 75 kW > 2 kV > 100 V > 2 kV Pb−Free Pkg Level 1 Level 2 UL 94 V−0 @ 0.125 in Transistor Count 1237 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D. http://onsemi.com 4 5 http://onsemi.com Figure 3. Logic Diagram VEE VEF VCF VBB EN IN IN FTUNE SET MAX SET MIN LEN 512 GD* D9 1 0 D10 Latch 256 GD* D8 1 0 D7 1 CASCADE CASCADE 128 GD* 0 64 GD* D6 1 0 16 GD* 1 D4 10 BIT LATCH D5 1 0 8 GD* D3 1 0 4 GD* D2 1 0 2 GD* D1 1 0 (FIXED MINIMUM DELAY APPROX. 2.4 ns) *GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE 32 GD* 0 D0 1 GD* 1 0 1 GD* 1 0 Q Q MC100EP196B MC100EP196B Table 6. THEORETICAL DELAY VALUES D(9:0) Value SETMIN SETMAX Programmable Delay* XXXXXXXXXX H L 0 ps 0000000000 L L 0 ps 0000000001 L L 10 ps 0000000010 L L 20 ps 0000000011 L L 30 ps 0000000100 L L 40 ps 0000000101 L L 50 ps 0000000110 L L 60 ps 0000000111 L L 70 ps 0000001000 L L 80 ps 0000010000 L L 160 ps 0000100000 L L 320 ps 0001000000 L L 640 ps 0010000000 L L 1280 ps 0100000000 L L 2560 ps 1000000000 L L 5120 ps 1111111111 L L 10230 ps XXXXXXXXXX L H 10240 ps *Fixed minimum delay not included. Table 7. TYPICAL FTUNE DELAY PIN Input Range Output Range VCC−VEE (V) 0 − 60 (ps) http://onsemi.com 6 MC100EP196B 15000 14000 13000 85°C 12000 25°C 11000 10000 DELAY ( ps) −40°C 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 0 100 200 300 400 500 600 700 800 900 1000 Rating Unit Decimal Value of Select Inputs (D[9:0]) Figure 4. Measured Delay vs. Select Inputs Table 8. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 VCC Positive Mode Power Supply VEE = 0 V 6 V VEE Negative Mode Power Supply VCC = 0 V −6 V VI Positive Mode Input Voltage Negative Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) qJC Tsol Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free VI ≤ VCC VI ≥ VEE 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W 2S2P standard boards QFN−32 12 °C/W LQFP−32 12 to 17 °C/W 265 °C <2 to 3 sec @ 260°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 7 MC100EP196B Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 90 115 170 100 140 170 100 145 175 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 8) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) VIL mV LVPECL CMOS TTL 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 LVPECL CMOS TTL 1305 0 0 1675 800 800 1305 0 0 1675 800 800 1305 0 0 1675 800 800 Input LOW Voltage (Single−Ended) mV VBB ECL Output Voltage Reference VCF LVTTL Mode Input Detect Voltage VEF Reference Voltage for ECL Mode Connection VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) IIH Input HIGH Current (@ VIH) IIL Input LOW Current (@ VIL) IN, IN 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 V 1900 2020 2150 1900 2020 2150 1900 2020 2150 mV 1.2 3.3 1.2 3.3 1.2 3.3 V 0 150 0 150 0 150 mA 0 150 0 150 0 150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 8. All loading with 50 W to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 8 MC100EP196B Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current (Note 11) 90 115 170 100 140 170 100 145 175 mA VOH Output HIGH Voltage (Note 12) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 12) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) LVNECL −1225 −880 −1225 −880 −1225 −880 Input LOW Voltage (Single−Ended) LVNECL −1995 −1625 −1995 −1625 −1995 −1625 VBB ECL Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV VEF Reference Voltage for ECL Mode Connection −1400 −1280 −1250 −1400 −1280 −1250 −1400 −1280 −1250 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) VEE+ 1.2 0.0 VEE+ 1.2 0.0 VEE+ 1.2 0.0 V IIH Input HIGH Current (@ VIH) 0 150 0 150 0 150 mA IIL Input LOW Current (@ VIL) 0 150 0 150 0 150 mA VIL IN, IN mV mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 11. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) > 3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC − VEE operation at ≤ 3.8 V. 12. All loading with 50 W to VCC − 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 9 MC100EP196B Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14) −40°C Min Characteristic Symbol Typ fmax Maximum Frequency Voutpp Output Voltage Amplitude 610 820 tPLH tPHL Propagation Delay IN to Q; D(0−10) = 0, SETMIN IN to Q; D(0−10) = 1023, SETMAX EN to Q; D(0−10) = 0 D0 to CASCADE 2000 10900 1990 375 2400 12400 2500 475 tRANGE Programmable Range tPD (max) − tPD (min) 8950 9950 Dt 25°C Max Min 1.2 Typ 85°C Max Min 1.2 Typ GHz 610 820 mV 610 820 2800 13900 2990 575 2150 11500 2130 400 2500 13000 2600 500 2950 14500 3130 600 2250 12250 2380 425 2700 13750 2800 525 3050 15250 3380 625 10950 9450 10450 11450 10110 11100 12110 ps ps Step Delay (Note 15) ps 10 16 32 65 155 310 620 1200 2500 4900 11 18 33 72 166 325 650 1300 2600 5200 15 26 46 92 195 370 720 1400 2800 5500 NLIN Non−Linearity (Notes 16 and 17) 0 to 511 decimal values for D[9:0] range 512 to 1023 dec. values for D[9:0] range 1 to 1023 decimal values for D[9:0] range ±7.0 ±7.0 ±11 ±7.0 ±7.0 ±11 ±7.0 ±7.0 ±11 tSKEW Duty Cycle Skew (Note 18) |tPHL−tPLH| 25 ts Setup Time tR tjitter Unit 1.2 D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High th Max 90 25 90 25 ps 90 ps ps D to LEN D to IN (Note 19) EN to IN (Note 20) 200 500 300 −40 −550 100 200 500 300 −40 −590 100 200 500 300 −40 −650 120 LEN to D IN to EN (Note 21) 200 400 50 −320 200 400 40 −350 200 400 30 −400 EN to IN (Note 22) SET MAX to LEN SET MIN to LEN 300 400 350 −150 180 220 300 400 350 −170 200 250 300 400 350 −200 210 260 Hold Time ps Release Time ps RMS Random Clock Jitter @ 1.2 GHz IN to Q; D(0:10) = 0 or SETMIN IN to Q; D(0:10) = 1023 or SETMAX VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Time @ 50 MHz 20−80% (Q) 20−80% (CASCADE) ps 0.9 1.9 2.0 5.0 150 800 1200 85 110 115 160 140 210 1.1 2.6 2.0 5.0 150 800 1200 100 120 120 175 140 230 1.2 3.3 2.0 5.0 150 800 1200 100 120 130 190 165 250 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 16. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps. 17. For NLIN, Max temperature is 70°C. 18. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 19. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 20. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75 mV to that IN/IN transition. 21. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition. 22. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. http://onsemi.com 10 MC100EP196B IN VINPP = VIH(D) − VIL(D) IN Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 5. AC Reference Measurement Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained is dependent on the voltage applied to the FTUNE pin. To provide this further level of resolution, the FTUNE pin must be capable of adjusting the additional delay finer than the 10 ps digital resolution (See Logic Diagram). This requirement is easily achieved because a 60 ps additional delay can be obtained over the entire FTUNE voltage range (See Figure 6). This extra analog range ensures that the FTUNE pin will be capable even under worst case conditions of covering a digital resolution. Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. To determine the voltage range necessary for the FTUNE input, Figure 6 should be used. There are numerous voltage ranges which can be used to cover a given delay range; users are given the flexibility to determine which one best fits their designs. 90 80 VCC = 0 V VEE = −3.3 V 25°C 70 −40°C DELAY (ps) 60 50 40 30 20 85°C 10 0 −10 −3.3 −2.97 −2.64 −2.31 VEE −1.98 −1.65 −1.32 −0.99 −0.66 −0.33 FTUNE VOLTAGE (V) 0 VCC Figure 6. Typical EP196B Delay versus FTUNE Voltage Cascading Multiple EP196Bs To increase the programmable range of the EP196B, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196Bs without the need for any external gating. Furthermore, this capability requires only one more address line per added EP196B. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 7 illustrates the interconnect scheme for cascading two EP196Bs. As can be seen, this scheme can easily be expanded for larger EP196B chains. The D10 input of the EP196B is the CASCADE control pin. With the interconnect scheme of Figure 7 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP196B. For a 2−device configuration, A11 is not required. http://onsemi.com 11 MC100EP196B Need if Chip #3 is used ADDRESS BUS A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 VEE D3 D2 D1 D7 D6 D5 D4 VEE D3 D2 D1 D8 VEE D8 VEE D9 D0 D9 D0 VCC D10 D10 EP196B IN Q IN Q IN VCC EP196B Q INPUT OUTPUT Figure 7. Cascading Interconnect Architecture http://onsemi.com 12 NC EN CASCADE VCF CASCADE NC VCC VCC VCC VEF SETMAX VCC CHIP #1 SETMIN VBB VEE CASCADE CASCADE VCC SETMAX LEN VEE VCF SETMIN VEF VCC EN CHIP #2 VBB Q LEN IN MC100EP196B (1111111111 on the A0—A9 address bus) D10 will be asserted to signal the need to cascade the delay to the next EP196B device. When D10 is asserted, the SET MIN pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay. Table 12 shows the delay time of two EP196B chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D10 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 7. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. An expansion of the latch section of the block diagram is pictured in Figure 8. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 7 is LOW this device’s CASCADE output will also be low while the CASCADE output will be high. In this condition the SET MIN pin of chip #2 will be asserted HIGH and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SET MIN and SET MAX deasserted so that its delay will be controlled entirely by the address bus A0—A9. If the delay needed is greater than can be achieved with 1023 gate delays TO SELECT MULTIPLEXERS SET MIN BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset SET MAX Figure 8. Expansion of the Latch Section of the EP196B Block Diagram http://onsemi.com 13 MC100EP196B Table 12. Delay Value of Two EP196B Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 Total D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value 0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps 0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps 0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps 0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps 0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps 0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps 0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps 0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps 0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps 0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps 0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps 0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps 0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps 0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps 0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps 0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2 INPUT FOR CHIP #1 Total D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps 1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps 1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps 1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps 1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps 1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps 1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps 1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps 1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps 1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps 1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps 1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps 1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps 1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps 1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps 1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps http://onsemi.com 14 Delay Value Delay Value MC100EP196B Multi−Channel Deskewing be sent through each EP196B as shown in Figure 9. One signal channel can be used as reference and the other EP196Bs can be used to adjust the delay to eliminate the timing skews. Nearly any high−speed system can be fine−tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances. The most practical application for EP196B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can EP196B IN IN Q Q #1 EP196B IN IN Q Q #2 EP196B IN IN Q Q #N Control Logic Digital Data Figure 9. Multiple Channel Deskewing Diagram Measure Unknown High Speed Device Delays If the programmed delay through the second EP196B is too long, the flip−flop output will be at logic high. On the other hand, if the programmed delay through the second EP196B is too short, the flip−flop output will be at a logic low. If the programmed delay is correctly fine−tuned in the second EP196B, the flip−flop will bounce between logic high and logic low. The digital code in the second EP196B can be directly correlated into an accurate device delay. EP196Bs provide a possible solution to measure the unknown delay of a device with a high degree of precision. By combining two EP196Bs and EP31 as shown in Figure 10, the delay can be measured. The first EP196B can be set to SETMIN and its output is used to drive the unknown delay device, which in turn drives the input of a D flip−flop of EP31. The second EP196B is triggered along with the first EP196B and its output provides a clock signal for EP31. The programmed delay of the second EP196B is varied to detect the output edge from the unknown delay device. EP196B CLOCK IN IN CLOCK Q Q Unknown Delay Device #1 D Q EP31 CLK EP196B IN IN Q Q #2 Control Logic Figure 10. Multiple Channel Deskewing Diagram http://onsemi.com 15 Q MC100EP196B Zo = 50 W Q D Receiver Device Driver Device Zo = 50 W Q D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC100EP196BFAG LQFP−32 (Pb−Free) 250 Units / Tray MC100EP196BFAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel MC100EP196BMNG QFN−32 (Pb−Free) 74 Units / Rail MC100EP196BMNR4G QFN−32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 16 MC100EP196B PACKAGE DIMENSIONS 25 0.20 (0.008) AB T-U Z BASE METAL 1 −U− −T− B V B1 17 8 P F DETAIL Y V1 AE −Z− 9 S1 D J DETAIL Y 9 ÉÉ ÉÉ ÉÉ ÉÉ N AE 4X 0.20 (0.008) AC T-U Z 8X S SECTION AE−AE M_ R DETAIL AD G C E −AB− 0.10 (0.004) AC H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 17 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q_ 0.250 (0.010) −AC− GAUGE PLANE SEATING PLANE AC T-U Z 32 M 4X A1 0.20 (0.008) A −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C MC100EP196B PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A A D ÉÉ ÉÉ PIN ONE LOCATION L L B L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C A DETAIL B 0.10 C ÉÉÉ ÇÇÇ ÇÇÇ EXPOSED Cu TOP VIEW (A3) A1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION 0.08 C SEATING PLANE C SIDE VIEW NOTE 4 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 9 K D2 32X 5.30 3.35 17 8 MILLIMETERS MAX MIN 1.00 0.80 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 3.25 2.95 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 32X 0.63 L E2 1 32 3.35 5.30 25 e e/2 32X BOTTOM VIEW b 0.10 M C A B 0.05 M C NOTE 3 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 18 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EP196B/D