FMP3217BAx CMOS LPRAM Document Title 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Sep.16th, 2005 Preliminary 0.1 Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions Added Operating Temperature descriptions Nov.10th ,2005 Preliminary 0.2 Revised P/N according to the new P/N system Jun.01st ,2006 0.3 Revised ISB1 to 120uA Feb. 2nd , 2007 1 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Three state output and TTL Compatible • Package Type : 48-FBGA-6.00x8.00 mm2 FMP3217BAx-FxxX : Normal FMP3217BAx-GxxX : Pb-Free FMP3217BAx-HxxX : Pb-Free & Halogen Free • Organization : 2M x 16 • Power Supply Voltage : 2.7~3.3V • Low Power & Page Modes FMP3217BA1 : support the PASR/DPD function FMP3217BA2 : support the Direct DPD function FMP3217BA4 : support the PASR/DPD/PAGE function FMP3217BA5 : support the Direct DPD/PAGE function • Separated I/O power(VCCQ) & Core Power(VCC) • Page read/write operation by 16 words (FMP3217BA4, FMP3217BA5) • DPD mode by using MRS only • Operating Temperature Ranges: (FMP3217BA1, FMP3217BA4) Special (-10’C to +60’C) Commercial (0’C to +70’C) Extended (-25’C to +85’C) Industrial (-40’C to +85’C) • Direct DPD mode when /ZZ goes low (FMP3217BA2, FMP3217BA5) PRODUCT FAMILY Power Dissipation Operating Voltage (V) ICC1 Speed Product Family f = 1MHz Min. Typ. Max. FMP3217BAx-H60E FMP3217BAx-H70E 2.7 60ns 70ns 3.3 3.0 ISB1 (CMOS Standby Current) ICC2 f = fmax Typ. Max. Typ. Max. Typ. Max. 1.5mA 3mA 15mA 12mA 20mA 80uA 120uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) PIN DESCRIPTION 1 2 3 4 5 6 A /LB /OE A0 A1 A2 /ZZ B I/O9 /UB A3 A4 /CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCCQ I/O13 DNU A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 H A18 A8 A9 A10 A11 A20 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. VCC VSS Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 Data cont 48-FBGA : Top View(Ball Down) Column Addresses Name Function Name Function /ZZ Low Power Modes VCC Core Power /CS Chip Select Input VCCQ I/O Power /CS /OE Output Enable Input VSS Ground /OE /WE Write Enable Input /UB Upper Byte(I/O9~16) A0~A20 Address Inputs /LB Lower Byte(I/O 1~8) I/O1~I/O16 Data Inputs/Outputs DNU Do Not Use /WE Control Logic /UB /LB /ZZ 2 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM PRODUCT LIST Part Name Function FMP3217BAx-H60E FMP3217BAx-H70E 48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) FUNCTIONAL DESCRIPTION /CS /ZZ /OE /WE /LB /UB I/O1-8 I/O9-16 Mode Power H H X1) X1) X1) X1) High-Z High-Z Deselected Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselected Direct DPD2) H L X1) X1) X1) X1) High-Z High-Z Deselected Low Power Modes3) X1) H X1) X1) H H High-Z High-Z Deselected Standby High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active H H H L X1) H H H X1) L L H Dout High-Z Lower Byte Read Active L H H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L L H X1) L L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active 1. X means don’t care.(Must be low or high state) 2. In case of FMP3217BA2 & FMP3217BA5 product 3. In case of FMP3217BA1 & FMP3217BA4 product ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit VIN, VOUT -0.2 to Vcc+0.3V V Vcc -0.2 to 3.6 V PD 1.0 W TSTG -65 to 150 ’C Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS FMP3217BA Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Symbol Unit Min Max Min Max Min Max VCC 2.7 3.3 2.7 3.3 2.7 3.3 V VCCQ 2.7 3.3 2.25 2.75 1.65 1.95 V V Ground VSS 0 0 0 0 0 0 Input high voltage VIH 0.8VCCQ VCC+0.21) 0.8VCCQ VCC+0.21) 0.8VCCQ VCC+0.21) V Input low voltage VIL -0.22) 0.2VCCQ -0.22) 0.2VCCQ -0.22) 0.2VCCQ V Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.3 Feb. 2007 FMP3217BAx CAPACITANCE1) CMOS LPRAM (f=1MHz , TA=25’C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input leakage current Item Symbol ILI VIN=VSS to VCC Test Conditions -1 - 1 uA Output leakage current ILO /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 - 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V - - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH - - 20 mA Output low voltage VOL IOL=0.5mA 0.2VCCQ V Output high voltage VOH IOH=-0.5mA Standby Current(TTL) ISB /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL - - 0.3 mA Average operating current Standby Current(CMOS) Low Power Modes 0.8VCCQ V ISB1 /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC - - 120 uA ISB0 /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) - - 10 uA ISB0a /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection - - 90 uA ISB0b /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection - - 100 uA ISB0c /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection - - 120 uA Operating Range Device Range Ambient Temperature FMP3217BAx-XxxS Special -10℃ to +60℃ FMP3217BAx-XxxC Commercial 0℃ to +70℃ FMP3217BAx-XxxE Extended -25℃ to +85℃ FMP3217BAx-XxxI Industrial -40℃ to +85℃ 4 VDD VDDQ 2.7V to 3.3V 1.65V to Vcc Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) 30pf Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL 1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V) Speed Bins Parameter List Read Cycle Time Symbol 60ns 70ns Units Min Max Min Max tRC 60 20k 70 20k ns Address Access Time tAA - 60 - 70 ns Chip Select to Output tCO - 60 - 70 ns Output Enable to Valid Output tOE - 25 - 25 ns /UB, /LB Access Time tBA - 60 - 70 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns /UB, /LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Read Chip Disable to High- Z Output Write tHZ 0 5 0 5 ns /UB, /LB Disable to High- Z Output tBHZ 0 5 0 5 ns Output Disable to High- Z Output tOHZ 0 5 0 5 ns Output Hold from Address Change tOH 5 - 5 - ns Write Cycle Time tWC 60 20k 70 20k ns Chip Select to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 50 - 60 - ns /UB, /LB Valid to End of Write tBW 50 - 60 - ns Write Pulse Width tWP 50 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z Page tWHZ 0 5 0 5 ns Data to Write Time Overlap tDW 20 - 20 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns Page Mode Cycle Time tPC 20 - 25 - ns Page Mode Address Access Time tPAA - 20 - 25 ns Maximum Cycle Time tMRC - 20k - 20k ns /CS High Pulse Width tCP 10 - 10 - ns 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH Standby Mode State machines Power On /CS=VIH Wait 200us /CS=VIH, /ZZ=VIH Initial State /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL /CS=VIH, /ZZ=VIL Active Mode /CS=VIL /ZZ=VIH /CS=VIH /ZZ=VIL /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH, /ZZ=VIL Standby Mode /CS=VIL /ZZ=VIH Low Power Modes 1 (32M/16M/8M bits) Low Power Modes 2 (Data Invalid) /CS=VIH, /ZZ=VIL Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 120 (ISB1) 0 Invalid 10 (ISB0) 200 ¼ valid 90 (ISB0a) 0 ½ valid 100 (ISB0b) 0 valid 120 (ISB0c) 0 Low Power Modes 6 Revision 0.3 Feb. 2007 FMP3217BAx READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) tRC Address tAA tOH Data Out READ CYCLE (2) Previous Data Valid Data Valid (/ZZ=/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ Data Out tOHZ tBLZ tLZ High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A20 tOH tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ tBLZ Data Out High-Z tPAA tPAA Data Valid Data Valid tPAA tPAA tPAA tPAA tPAA tOHZ tLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 7 Revision 0.3 Feb. 2007 FMP3217BAx WRITE CYCLE (1) CMOS LPRAM (/WE controlled, /ZZ=VIH) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, /ZZ=/WE=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data in Data Out WRITE CYCLE (3) tDH Data Valid High-Z High-Z (/UB, /LB controlled, /ZZ=VIH) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data in Data Out tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 8 Revision 0.3 Feb. 2007 FMP3217BAx PAGE WRITE CYCLE CMOS LPRAM (Address controlled, /ZZ=VIH) tMRC tPC tWC tPC tPC tPC tPC tPC tPC A0~A3 A4~A20 /CS /UB, /LB tAS(3) /WE tDW Data in High-Z tDH Data Valid tDW tDH Data Valid tDW Data Valid tWHZ Data Out tDH tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid High-Z tOW Data Undefined 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. 9 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM LOW POWER MODES 1. Mode Register Set A20 ~ A5 0 A4 A3 A2 ZZ Array On/Off on /ZZ Half Selection Enable/Disable /ZZ Enable/Disable A1 A0 Array Refresh Area Array On/Off on /ZZ A4 Type A3 Type 0 Deep Power Down Enable 0 Partial Array Refresh Mode (Default) 1 DPD Disable (Default) 1 Reduced Memory Size Mode Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Half Selection (Top / Bottom) Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Array Refresh Area A2 Type A1 A0 Type 0 Bottom (Default) 0 0 Full Array (Default) 1 Top 0 1 RFU 1 0 ½ Array 1 1 ¼ Array 2. MRS Update tWC Address tAS(3) tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 10 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM 3. Deep Power Down Mode Entry/Exit tWC A4 tAS(3) tWR(4 ) tCW(2 ) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE tR Next Cycle tZZmin /ZZ Register Write(DPD) Deep Power down exit Deep Power down start Parameter Description Min Max Units tZZWE ZZ low to Write Enable Low 0 1 us tR(Deep Power Down Mode only) Operation Recovery Time 200 - us tZZmin Low Power Mode Time 10 - us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-07FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-0FFFFFh 1Mbx16 16Mb X 00 Full 000000h-1FFFFFh 2Mbx16 32Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb Reduced Memory Size Mode (A3=1, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-07FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-0FFFFFh 1Mbx16 16Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb 11 Revision 0.3 Feb. 2007 FMP3217BAx CMOS LPRAM PACKAGE DIMENSION Unit : millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View A1 INDEX MARK B B1 B 0.05 0.05 6 5 4 3 2 1 A B C #A1 C C C1 D C1/2 E F G H B/2 0.25/Typ. E2 D A Y 0.85/Typ. E Detail A E1 0.30 Side View C - Min Typ A - 0.75 Max - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E - 1.10 1.20 E1 - 0.85 - E2 0.20 0.25 0.30 Y - - 0.08 12 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) Revision 0.3 Feb. 2007