NSC LP3907SQ-JXQX Dual high-current step-down dc/dc and dual linear regulator with i2c compatible interface Datasheet

LP3907
Dual High-Current Step-Down DC/DC and Dual Linear
Regulator with I2C Compatible Interface
General Description
Features
The LP3907 is a multi-function, programmable Power Management Unit, optimized for low power FPGAs, microprocessors and DSPs. This device integrates two highly efficient 1A/
600mA step-down DC/DC converters with dynamic voltage
management (DVM), two 300mA linear regulators and a
400kHz I2C compatible interface to allow a host controller access to the internal control registers of the LP3907. The
LP3907 additionally features programmable power-on sequencing and a tiny 4 x 4 x 0.8mm 24–pin LLP pin package.
■ Compatible with advanced applications processors and
Key Specifications
Step-Down DC/DC Converter (Buck)
■ 1A/600mA output current
■ Programmable VOUT from:
— Buck1 : 0.8V–2.0V @ 1A
— Buck2 : 1.0V–3.5V @ 600mA
■ Up to 96% efficiency
■ 2.1MHz PWM switching frequency
■ PWM - PFM automatic mode change under low loads
■ ±3% output voltage accuracy
■ Automatic soft start
FPGAs
■ 2 LDOs for powering Internal processor functions and I/Os
■ High speed serial interface for independent control of
device functions and settings
Precision internal reference
Thermal overload protection
Current overload protection
24-lead 4 × 4 × 0.8mm LLP package
Software Programmable Regulators
External Power-on-reset function for Buck1 and Buck2
(i.e., Power Good with delay function)
■ Undervoltage lock out detector to monitor input supply
voltage
■
■
■
■
■
■
Applications
■ FPGA, DSP core power
■ Applications processors
■ Peripheral I/O power
Linear Regulators (LDO)
■ Programmable VOUT of 1.0V–3.5V
■ ±3% output voltage accuracy
■ 300mA output current
■ 30mV (typ) dropout
© 2007 National Semiconductor Corporation
300178
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LP3907 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible
Interface
August 2007
LP3907
Typical Application Circuit
30017801
FIGURE 1. Application Circuit
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2
LP3907
30017802
FIGURE 2. Application Circuit
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LP3907
Connection Diagram
30017803
FIGURE 3. 24-Lead LLP Package (Top View)
Note: The physical placement of the package marking will vary from part to part.
(*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code. See http://www.national.com/quality/
marking_conventions.html for more information on marking information.
(**) Package received will have XXXX replaced with the specific part version ordered.
Ordering Information
Voltage Option
Order Number
Voltage “JXQX”
LP3907SQ-JXQX
24-lead LLP
SQA024AE
Voltage “JXQX”
LP3907SQX-JXQX
24-lead LLP
SQA024AE
Voltage “JXQX”
LP3907SQ-JXQX**
24-lead LLP
SQA024AE
24-lead LLP
SQA024AE
07PJXQX
Voltage “JXQX” LP3907SQX-JXQX**
Package Type NSC Package
Drawing
Package
Marking
Ordering
Spec
Supplied As
07-JXQX
NOPB
1000 tape & reel
07-JXQX
NOPB
4500 tape & reel
07PJXQX
S7001874
1000 tape & reel
S7001997
4500 tape & reel
** For Forced PWM Buck Regulators.
Default Voltage Options
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Regulator
Version “JXQX” Default Voltages (V)
SW1
1.2
SW2
3.3
LDO1
2.6
LDO2
3.3
4
LP3907
Pin Descriptions
Pin
Pin Name
I/O
Type
1
VINLDO12
I
PWR
Functional Description
Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)
2
EN_T
I
D
Enable for preset power on sequence. (see page 24)
3
NPOR
O
D
nPOR Power on reset pin for both Buck1 and Buck 2. Open drain
logic output 100K pullup resistor. nPOR is pulled to ground when
the voltages on these supplies are not good. See nPOR section
for more info.
4
GND_SW1
G
G
Buck1 NMOS Power Ground
5
SW1
O
PWR
Buck1 switcher output pin
6
VIN1
I
PWR
Power in from either DC source or Battery to Buck1
7
ENSW1
I
D
Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
8
FB1
I
A
Buck1 input feedback terminal
9
GND_C
G
G
Non switching core ground pin
10
AVDD
I
PWR
11
FB2
I
A
Buck2 input feedback terminal
12
ENSW2
I
D
Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
13
VIN2
I
PWR
Power in from either DC source or Battery to Buck2
14
SW2
O
PWR
Buck2 switcher output pin
15
GND_SW2
G
G
Buck2 NMOS Power ground
16
SDA
I/O
D
I2C Data (bidirectional)
17
SCL
I
D
I2C Clock
18
GND_L
G
G
LDO ground
19
VINLDO1
I
PWR
Power in from either DC source or battery to input terminal to
LDO1
20
LDO1
O
PWR
LDO1 Output
21
ENLDO1
I
D
LDO1 enable pin, a logic HIGH enables the LDO1
22
ENLDO2
I
D
LDO2 enable pin, a logic HIGH enables the LDO2
23
LDO2
O
PWR
LDO2 Output
24
VINLDO2
I
PWR
Power in from either DC source or battery to input terminal to
LDO2
Analog Power for Buck converters
A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
5
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LP3907
Operating Ratings: Bucks
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Notes 1, 2, 7, 18)
VIN
VEN
Junction Temperature (TJ) Range
2.8V to 5.5V
0 to (VIN + 0.3V)
−40°C to +125°
C
Ambient Temperature (TA) Range (Note 6) −40°C to +85°C
VIN, SDA, SCL
−0.3V to +6V
GND to GND SLUG
±0.3V
Power Dissipation (PD_MAX)
(TA=85°C, TMAX=125°C, )(Note 5)
1.43W
Junction Temperature (TJ-MAX)
150°C
Storage Temperature Range
−65°C to +150°C
Maximum Lead Temperature (Soldering)
260°C
ESD Ratings
Human Body Model (Note 4)
Thermal Properties
(Notes 3, 5, 6)
Junction-to-Ambient Thermal
Resistance (θJA) SQA024AE
28°C/W
2kV
General Electrical Characteristics
(Notes 1, 2, 7, 13, 17)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.
Symbol
IQ
VPOR
Parameter
Conditions
VINLDO12 Shutdown Current
VIN = 3.6V
Power-On Reset Threshold
VDD Falling Edge(Note 17)
TSD
Thermal Shutdown Threshold
TSDH
Themal Shutdown Hysteresis
UVLO
Under Voltage Lock Out
Min
Typ
Max
3
Units
µA
1.9
V
160
°C
20
°C
Rising
2.9
Falling
2.7
V
I2C Compatible Interface Electrical Specifications
(Note 13)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40°C to +125°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
400
kHz
FCLK
Clock Frequency
tBF
Bus-Free Time Between Start and Stop
(Note 13)
1.3
µs
tHOLD
Hold Time Repeated Start Condition
(Note 13)
0.6
µs
tCLKLP
CLK Low Period
(Note 13)
1.3
µs
tCLKHP
CLK High Period
(Note 13)
0.6
µs
tSU
Set Up Time Repeated Start Condition
(Note 13)
0.6
µs
tDATAHLD
Data Hold time
(Note 13)
0
µs
tDATASU
Data Set Up Time
(Note 13)
100
ns
TSU
Set Up Time for Start Condition
(Note 13)
0.6
µs
TTRANS
Maximum Pulse Width of Spikes that
(Note 13)
Must be Suppressed by the Input Filter of
Both DATA & CLK Signals.
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6
50
ns
Unless otherwise noted, VIN = 3.6, CIN = 1.0µF, COUT = 0.47µF. Typical values and limits appearing in normal type apply for TJ =
25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes
2, 7, 8, 9, 10, 11, 12)
Symbol
VIN
Parameter
Operational Voltage Range
Conditions
Min
VINLDO1 and VINLDO2 PMOS
pins (Note 15)
VOUT Accuracy Output Voltage Accuracy (Default VOUT) Load current = 1 mA
Typ
Max
Units
1.74
5.5
V
−3
3
%
Line Regulation
VIN = (VOUT + 0.3V) to 5.0V,
(Note 12), Load Current = mA
0.15
%/V
Load Regulation
VIN = 3.6V,
Load Current = 1mA to IMAX
0.011
%/mA
ISC
Short Circuit Current Limit
LDO1-2, VOUT = 0V
500
VIN – VOUT
Dropout Voltage
Load Current = 50mA
(Note 10)
30
PSRR
Power Supply Ripple Rejection
F = 10kHz, Load Current = IMAX
45
dB
θn
Supply Output Noise
10Hz < F < 100KHz
80
µVrms
IQ (Notes 11,
14)
Quiescent Current “On”
IOUT = 0mA
40
µA
Quiescent Current “On”
IOUT = IMAX
60
µA
ΔVOUT
mA
200
mV
Quiescent Current “Off”
EN is de-asserted(Note 16)
0.03
µA
TON
Turn On Time
Start up from shut-down
300
µs
COUT
Output Capacitor
Capacitance for stability
0°C ≤ TJ ≤ 125°C
0.33
0.47
µF
−40°C ≤ TJ ≤ 125°C
0.68
1.0
µF
ESR
5
500
mΩ
Buck Converters SW1, SW2
Unless otherwise noted, VIN = 3.6, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in normal
type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°
C to +125°C. (Notes 2, 7, 8, 9, 11, 18)
Symbol
VOUT
Parameter
Conditions
Min
Typ
−3
Max
Units
+3
%
Output Voltage Accuracy
Default VOUT
Line Regulation
2.8< VIN < 5.5
IO =10mA
0.089
%/V
Load Regulation
100mA < IO < IMAX
0.0013
%/mA
Eff
Efficiency
Load Current = 250mA
ISHDN
Shutdown Supply Current
EN is de-asserted
fOSC
Internal Oscillator Frequency
IPEAK
Buck1 Peak Switching Current Limit
Buck2 Peak Switching Current Limit
1.0
1.7
No load PFM Mode
96
%
0.01
µA
2.1
MHz
1.5
A
IQ (Note 14)
Quiescent Current “On”
RDSON (P)
Pin-Pin Resistance PFET
RDSON (N)
Pin-Pin Resistance NFET
TON
Turn On Time
Start up from shut-down
CIN
Input Capacitor
Capacitance for stability
10
µF
CO
Output Capacitor
Capacitance for stability
10
µF
7
33
µA
200
mΩ
180
mΩ
500
µs
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LP3907
Low Drop Out Regulators, LDO1 and LDO2
LP3907
I/O Electrical Characteristics
Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C. (Note 13)
Symbol
Parameter
VIL
Input Low Level
VIH
Input High Level
Conditions
Limit
Min
Max
Units
0.4
V
V
1.2
Power On Reset Threshold/Function (POR)
Symbol
Parameter
Conditions
Min
Typ
nPOR
nPOR = Power on reset forBuck1 and
Buck2
Default
50
nPOR
threshold
Percentage of Target voltage Buck1 or
Buck2
VBUCK1 AND VBUCK2 rising
94
VBUCK1 OR VBUCK2 falling
85
Max
Units
ms
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at TJ
= 140°C (typ.)
Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MILSTD - 883 3015.7)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX). See Applications section.
Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 9: The device maintains a stable, regulated output voltage without a load.
Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal value.
Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
Note 12: VIN minimum for line regulation values is 1.8V.
Note 13: This specification is guaranteed by design.
Note 14: The IQ can be defined as the standing current of the LP3907 when the I2C bus is active and all other power blocks have been disabled via the I2C
bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system
designer when the LP3907 is powered using a battery.
Note 15: Pins 24, 19 can operate from VIN min of 1.74 to a VIN max of 5.5V. This rating is only for the series pass PMOS power FET. It allows the system design
to use a lower voltage rating if the input voltage comes from a buck output.
Note 16: The IQ exhibits a higher current draw when the EN pin is de-asserted because the I22 buffer pins draw an additional 2µA.
Note 17: VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and
is also different from the nPOR function, which signals if the regulators are in a specified range.
Note 18: Buck VIN ≥ VOUT + 1V.
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Output Voltage Change vs Temperature (LDO1)
VIN = 3.6V, VOUT = 2.6V, 100mA load
LP3907
Typical Performance Characteristics — LDO
TA = 25°C unless otherwise noted
Output Voltage Change vs Temperature (LDO2)
VIN = 3.6V, VOUT = 3.3V, 100mA load
30017835
30017836
Load Transient (LDO1)
3.6 VIN, 2.6VOUT, 0 – 150 mA load
Load Transient (LDO2)
3.6 VIN, 3.3 VOUT, 0 – 150mA load
30017837
30017838
Line Transient (LDO1)
3.6 - 4.2 VIN, 2.6 VOUT, 300mA load
Line Transient (LDO2)
3 – 4.2 VIN, 3.3VOUT, 300 mA load
30017839
30017840
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LP3907
Enable Start-up time (LDO1) )
0-3.6 VIN, 2.6 VOUT, 1mA load
Enable Start-up time (LDO2)
0 – 3.6 VIN, 3.3 VOUT, 1 mA load
30017841
30017842
LDO Maximum Load
VIN = 1.74V
30017867
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LP3907
Typical Performance Characteristics — Bucks
VIN= 2.8V to 5.5V, TA = 25°C
Shutdown Current vs. Temp
Output Voltage vs. Supply Voltage
(VOUT = 1.0 V)
30017843
30017844
Output Voltage vs. Supply Voltage
(VOUT = 1.8V)
Output Voltage vs. Supply Voltage
(VOUT = 3.5V)
30017845
30017846
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LP3907
Typical Performance Characteristics — Buck1
VIN= 2.8V to 5.5V, TA = 25°C, VOUT = 1.2V, 2.0V
Efficiency vs Output Current
(VOUT =2.0V, L= 2.2µH — Forced PWM mode)
Efficiency vs Output Current
(VOUT =1.2V, L= 2.2µH —(Forced PWM mode)
30017847
30017848
Efficiency vs Output Current
(VOUT =1.2V, L= 2.2µH — PWM mode to PFM mode)
Efficiency vs Output Current
(VOUT =2.0V, L= 2.2µH — PWM mode to PFM mode)
30017850
30017849
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LP3907
Typical Performance Characteristics — Buck2
VIN= 4.5V to 5.5V, TA = 25°C, VOUT = 1.8V, 3.3V
Efficiency vs Output Current
(VOUT =3.3V, L= 2.2µH — Forced PWM mode)
Efficiency vs Output Current
( VOUT =1.8V, L= 2.2µH —Forced PWM mode)
30017851
30017852
Typical Performance Characteristics — Buck2
VIN= 4.3V to 5.5V, TA = 25°C, VOUT = 1.8V, 3.3V
Efficiency vs Output Current
(VOUT =1.2V, L= 2.2µH — PWM mode to PFM mode)
Efficiency vs Output Current
(VOUT =2.0V, L= 2.2µH — PWM mode to PFM mode)
30017853
30017854
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LP3907
Typical Performance Characteristics — Bucks
VIN= 3.6V, TA = 25°C, VOUT = 1.2V unless otherwise noted
Mode Change by Load Transient
VOUT = 1.2V, ILOAD = 50–150mA (PFM to PWM Mode)
Load Transient Response
VOUT = 1.2V, ILOAD = 300–500mA (PWM Mode)
30017856
30017857
Line Transient Response
VIN = 3.6 – 4.2V, VOUT = 1.2V, 250mA load
Line Transient Response
VIN = 3.6 – 4.2V, VOUT = 3.3V, 250 mA load
30017859
30017858
Start up into PWM Mode
VOUT = 1.2V, 1.0A load
Start up into PWM Mode
VOUT = 3.3 V, 600mA load
30017860
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30017861
14
LP3907
Start up into PFM Mode
VOUT = 1.2V, 30mA load
Start up into PFM Mode
VOUT = 3.3V, 30mA load
30017880
30017862
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LP3907
DC/DC Converters
OVERVIEW
The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2)
and two Buck converters (SW1 and SW2). The table hereunder lists the output characteristics of the various regulators.
Supply Specification
Output
VOUT Range(V)
Resolution (mV)
IMAX
Maximum Output
Current (mA)
analog
1.0 to 3.5
100
300
analog
1.0 to 3.5
100
300
SW1
digital
0.8 to 2.0
50
1000
SW2
digital
1.0 to 3.5
100
600
Supply
Load
LDO1
LDO2
*For default values of the regulators, please consult page 3 of this datasheet.
LINEAR LOW DROPOUT REGULATORS (LDOS)
LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and
LDO2 are enabled through the ENLDO pin or through the
corresponding LDO1 or LDO2 control register. The output
voltages of both LDOs are register programmable. The default output voltages are factory programmed during Final
Test, which can be tailored to the specific needs of the system
designer.
NO-LOAD STABILITY
The LDOs will remain stable and in regulation with no external
load. This is an important consideration in some circuits, for
example, CMOS RAM keep-alive applications.
grammable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both LDO1 and
LDO2 are enabled by applying a logic 1 to the ENLDO1 and
ENLDO2 pin. Enable/disable control is also provided through
enable bit of the LDO1 and LDO2 control registers. The value
of the enable LDO bit in the register is logic 1 by default. The
output voltage can be altered while the LDO is enabled.
30017822
LDO1 AND LDO2 CONTROL REGISTERS
LDO1 and LDO2 can be configured by means of the LDO1
and LDO2 control registers. The output voltage is pro-
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FUNCTIONAL DESCRIPTION
The LP3907 incorporates two high-efficiency synchronous
switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable
system processors. Using a voltage mode architecture with
synchronous rectification, both bucks have the ability to deliver up to 1000mA and 600mA, respectively, depending on
the input voltage and output voltage (voltage head room), and
the inductor chosen (maximum current capability).
There are three modes of operation depending on the current
required - PWM, PFM, and shutdown. PWM mode handles
current loads of approximately 70mA or higher, delivering
voltage precision of +/-3% with 90% efficiency or better.
Lighter output current loads cause the device to automatically
switch into PFM for reduced current consumption (IQ = 15µA
typ.) and a longer battery life. The Standby operating mode
turns off the device, offering the lowest current consumption.
PWM or PFM mode is selected automatically or PWM mode
can be forced through the setting of the buck control register.
Both SW1 and SW2 can operate up to a 100% duty cycle
(PMOS switch always on) for low drop out control of the output
voltage. In this way the output voltage will be controlled down
to the lowest possible input voltage.
Additional features include soft-start, under-voltage lock-out,
current overload protection, and thermal overload protection.
CURRENT LIMITING
A current limit feature allows the converter to protect itself and
external components during overload conditions. PWM mode
implements current limiting using an internal comparator that
trips at 1.5A for Buck1 and at 1.0A for Buck2 (typ). If the output
is shorted to ground the device enters a timed current limit
mode where the NFET is turned on for a longer duration until
the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing
runaway.
PFM OPERATION
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current
to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock
cycles:
A. The inductor current becomes discontinuous
or
B. The peak PMOS switch current drops below the IMODE
level
CIRCUIT OPERATION DESCRIPTION
A buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectifying NFET connected between the output and ground
(BCKGND pin) and a feedback path. During the first portion
of each switching cycle, the control block turns on the internal
PFET switch. This allows current to flow from the input
through the inductor to the output filter capacitor and load. The
inductor limits the current to a ramp with a slope of
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical) above
the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds
the I PFM level set for PFM mode. The typical peak current in
PFM mode is:
by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off,
blocking current flow from the input, and then turns the NFET
synchronous rectifier on. The inductor draws current from
ground through the NFET to the output filter capacitor and
load, which ramps the inductor current down with a slope of
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see figure below),
the PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘sleep’ mode is less than 30µA, which allows the part to
achieve high efficiencies under extremely light load condi-
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load.
PWM OPERATION
During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward voltage
inversely proportional to the input voltage is introduced.
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LP3907
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the buck uses an internal NFET as a
synchronous rectifier to reduce rectifier forward voltage drop
and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
SW1, SW2: Synchronous StepDown Magnetic DC/DC Converters
LP3907
tions. When the output drops below the ‘low’ PFM threshold,
the cycle repeats to restore the output voltage to ~1.6% above
the nominal PWM output voltage.
If the load current should increase during PFM mode (see
figure below) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into
fixed-frequency PWM mode.
Power On Sequence). The SW1 and SW2 output voltages
revert to default values when the power on sequence has
been completed. The default output voltage for each buck
converter is factory programmable. (See Application Notes).
SW1, SW2 CONTROL REGISTERS
SW1, SW2 can be enabled/disabled through the corresponding control register.
The Modulation mode PWM/PFM is by default automatic and
depends on the load as described above in the functional description. The modulation mode can be overridden by setting
I2C bit to a logic 1 in the corresponding buck control register,
forcing the buck to operate in PWM mode regardless of the
load condition.
SW1, SW2 OPERATION
SW1 and SW2 have selectable output voltages ranging from
0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3907 are
I2C register controlled and are enabled by default through the
internal state machine of the LP3907 following a Power-On
event that moves the operating mode to the Active state. (see
30017814
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and
bias circuitry of the converters are turned off. The NFET
switch will be on in shutdown to discharge the output. When
the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up
and under voltage conditions when the supply is less than
2.8V.
down to the lowest possible input voltage. When the device
operates near 100% duty cycle, output voltage ripple is approximately 25mV. The minimum input voltage needed to
support the output voltage is
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
SOFT START
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-rush current during
start-up. During start-up the switch current limit is increased
in steps. Soft start is activated only if EN goes from logic low
to logic high after VIN reaches 2.8V. Soft start is implemented
by increasing switch current limit in steps of 180mA, 300mA,
and 720mA for Buck1; 161mA, 300mA and 536mA for Buck2
(typ. Switch current limit). The start-up time thereby depends
on the output capacitor and load current demanded at startup.
— RINDUCTOR
— ILOAD
— RDSON, PFET
LOW DROPOUT OPERATION
The LP3907 can operate at 100% duty cycle (no switching;
PMOS switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be controlled
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18
Load current
Drain to source resistance of
PFET switch in the triode region
Inductor resistance
POWER ON
EN_T assertion causes the LP3907 to emerge from Standby
mode to Full Operation mode at a preset timing sequence. By
default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are 500K internally pulled
down, which causes the part to stay OFF until enabled. If the
30017809
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LP3907
user wishes to have a preset timing sequence to power on the
regulators, the external regulator enables must be tied LOW.
Otherwise, simply tie the enables of each specific regulator
HIGH to turn on automatically.
EN_T is edge triggered with rising edge signaling the chip to
power on. The EN_T input is deglitched and the default is set
at 1ms. As shown in the next 2 diagrams, a rising EN_T edge
will start a power on sequence, while a falling EN_T edge will
start a shutdown sequence. If EN_T is high, toggling the external enables of the regulators will have no effect on the chip.
The regulators can also be programmed through I2C to turn
on and off. By default, I2C enables for the regulators on ON.
The regulators are on following the pattern below:
Regulators on = (I2C enable) AND (External pin enable OR
EN_T high).
FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER
SUPPLIES
The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with ENSW1
and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.
If the user desires a set power on sequence, he can program
the chip through I2C and raise EN_T from LOW to HIGH to
activate the power on sequencing.
LP3907
LP3907 Default Power-Up Sequence
30017810
Power-On Timing Specification
Symbol
Description
Min
Typ
Max
Units
t1
Programmable Delay from EN_T assertion to VCC_Buck1 On
1.5
ms
t2
Programmable Delay from EN_T assertion to VCC_Buck2 On
2
ms
t3
Programmable Delay from EN_T assertion to VCC_LDO1 On
3
ms
t4
Programmable Delay from EN_T assertion to VCC_LDO2 On
6
ms
Note: The LP3907 default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2, 3, 6, or 11ms.
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20
LP3907
LP3907 Default Power-Off Sequence
30017811
Symbol
Description
Min
Typ
Max
Units
t1
Programmable Delay from EN_T deassertion to VCC_Buck1 Off
1.5
ms
t2
Programmable Delay from EN_T deassertion to VCC_Buck2 Off
2
ms
t3
Programmable Delay from EN_T deassertion to VCC_LDO1 Off
3
ms
t4
Programmable Delay from EN_T deassertion to VCC_LDO2 Off
6
ms
Note: The LP3907 default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10ms. Default setting is the same as the on sequence.
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LP3907
is logic LOW when either of the buck outputs are below 91%
of the rising value , or when one or both outputs fall below
82% of the desired value. The time delay between output
voltage level and nPOR is enabled is (50µs, 50ms, 100ms,
200ms) 50ms by default. The system designer can choose
the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.
Flexible Power-On Reset (i.e., Power
Good with delay)
The LP3907 is equipped with an internal Power-On-Reset
(“POR”) circuit which monitors the output voltage levels on
bucks 1 and 2. The nPOR is an open drain logic output which
NPOR With Counter Delay
30017821
The above diagram shows the simplest application of the
Power On Reset, where both switcher enables are tied together. In Case 1, RDY1 causes NPOR to transition LOW and
triggers the NPOR delay counter. If the power supply for
Buck2 does not come on within that period, NPOR will stay
LOW, indicating a power fail mode. Case 2 indicates the vice
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versa scenario if Buck1 supply did not come on. In both cases
the NPOR remains LOW.
Case 3 shows a typical application of the Power On Reset,
where both switcher enables are tied together. Even if RDY1
ramps up slightly faster than RDY2 (or vice versa), the NPOR
signal will trigger a programmable delay before going HIGH,
as explained below.
22
LP3907
Faults Occurring in Counter Delay After Startup
30017881
The above timing diagram details the Power good with delay
with respect to the enable signals EN1, and EN2. The RDY1,
RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:
Comparator Level
If EN1 and RDY1 signals are High at time t1, then the RDY1
signal rising edge triggers the programmable delay counter
(50μs, 50ms, 100ms, 200ms). This delay forces NPOR LOW
between time interval t1 and t2. NPOR is then pulled high after
the programmable delay is completed. Now if EN2 and RDY2
are initiated during this interval the NPOR signal ignores this
event.
If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.
Buck Supply Level
HIGH
Greater than 94%
LOW
Less than 85%
The circuits for EN1 and RDY1 is symmetrical to EN2 and
RDY2, so each reference to EN1 and RDY1 will also work for
EN2 and RDY2 and vice versa.
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LP3907
NPOR Mask Window
30017813
If the EN1 and RDY1 are initiated in normal operation, then
NPOR is asserted and deasserted as explained above.
In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the
NPOR being asserted again, a masked window ( 5ms )
counter delay is triggered off the EN2 rising edge. NPOR is
still held HIGH for the duration of the mask, whereupon the
NPOR status afterwards will depend on the status of both
RDY1 and RDY2 lines.
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In Case 2, we see the case where EN2 is initiated after the
RDY1 triggered programmable delay, but RDY2 never goes
HIGH (Buck2 never turns on). Normal operation operation of
NPOR occurs wilth respect to EN1 and RDY1, and the NPOR
signal is held HIGH for the duration of the mask window. We
see that NPOR goes LOW after the masking window has
timed out because it is now dependent on RDY1 and RDY2,
where RDY2 is LOW.
24
LP3907
Design Implementation of the Flexible Power-On Reset
30017812
An internal Power-on reset of the IC is used with EN1, and
EN2 to produce a reset signal (LOW) to the delay timer
NPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S=R=1 never
occurs. The mask timers are triggered off EN1 and EN2 which
are gated with RDY1, and RDY2 to generate outputs to the
final AND gate to generate the NPOR.
four voltage regulators whenever this supply voltage is less
than 2.8VDC.
The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8VDC trip point
for a VIN OK – Not OK detector. This VIN OK signal is then
used to gate the enable signals to the four regulators of the
LP3907. When VINLDO12 is greater than 2.8VDC the four
enables control the four regulators, when VINLDO12 is less
than 2.8VDC the four regulators are disabled by the VIN detector being in the “Not OK” state. The circuit has built in
hysteresis to prevent chattering occurring.
Under Voltage Lock Out
The LP3907 features an “under voltage lock out circuit”. The
function of this circuit is to continuously monitor the raw input
supply voltage (VINLDO12) and automatically disables the
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LP3907
Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400kbit/s. See I2C specification from Philips for further details.
I2C Compatible Serial Interface
I2C SIGNALS
The LP3907 features an I2C compatible serial interface, using
two dedicated pins: SCL and SDA for I2C clock and data respectively. Both signals need a pull-up resistor according to
the I2C specification. The LP3907 interface is an I2C slave that
is clocked by the incoming SCL clock.
I2C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
30017816
I2C Signals: Data Validity
to HIGH while the SCL is HIGH. The 2C master always genI2C START AND STOP CONDITIONS
erates START and STOP bits. The I2C bus is considered to
START and STOP bits classify the beginning and the end of
be busy after START condition and free after STOP condition.
the I2C session. START condition is defined as the SDA signal
During data transmission, I2C master can generate repeated
transitioning from HIGH to LOW while the SCL line is HIGH.
START conditions. First START and repeated START condiSTOP condition is defined as the SDA transitioning from LOW
tions are equivalent, function-wise.
30017817
START and STOP Conditions
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30017818
I2C Chip Address
30017819
w = write (SDA = “0”)
r = read )SDA = “1”)
acl = aclmpw;edge )SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 chip address: 0x60
I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read
Cycle waveform.
30017824
I2C Read Cycle
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LP3907
bit which is a data direction bit (R/W). Please note that according to industry 2C standards for 7-bit addresses, the MSB
of an 8-bit address is removed, and communication actually
starts with the 7th most significant bit. For the eighth bit (LSB),
a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be written. The third byte contains data to write to the selected
register.
LP3907 has a chip address of 60’h, which is factory programmed.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an acknowledgement (“ACK”) after each byte has been received.
After the START condition, the 2C master sends a chip address. This address is seven bits long followed by an eighth
LP3907
LP3907 Control Registers
Register
Address
Register
Name
Read/
Write
Register Description
0x02
ICRA
R
Interrupt Status Register A
0x07
SCR1
R/W
System Control 1 Register
0x10
BKLDOEN
R/W
Buck and LDO Output Voltage Enable Register
0x11
BKLDOSR
R
Buck and LDO Output Voltage Status Register
0x20
VCCR
R/W
Voltage Change Control Register 1
0x23
B1TV1
R/W
Buck1 Target Voltage 1 Register
0x24
B1TV2
R/W
Buck1 Target Voltage 2 Register
0x25
B1RC
R/W
Buck1 Ramp Control
0x29
B2TV1
R/W
Buck2 Target Voltage 1 Register
0x2A
B2TV2
R/W
Buck2 Target Voltage 2 Register
0x2B
B2RC
R/W
Buck2 Ramp Control
0x38
BFCR
R/W
Buck Function Register
0x39
LDO1VCR
R/W
LDO1 Voltage control Registers
0x3A
LDO2VCR
R/W
LDO2 Voltage control Registers
INTERRUPT STATUS REGISTER (ISRA) 0X02
This register informs the System Engineer of the temperature status of the chip.
D7-2
D1
D0
Name
—
Temp 125°C
—
Access
—
R
—
Data
Reserved
Status bit for thermal warning
PMIC T>125°C
0 – PMIC Temp. < 125°C
1 – PMIC Temp. > 125°C
Reserved
Reset
0
0
0
CONTROL 1 REGISTER (SCR1) 0X07
This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode for
the bucks, and also to select between an internal and external clock for the bucks.
D7
D6-4
D3
D2
D1
D0
—
EN_DLY
—
FPWM2
FPWM1
ECEN
Access —
R/W
—
R/W
R/W
R/W
Data
Reserved
Selects the preset
Reserved
delay sequence
from EN_T assertion
(shown below)
Buck2 PWM /PFM
Mode select
0 – Auto Switch PFM PWM operation
1 – PWM Mode Only
Buck 1 PWM /PFM
Reserved
Mode select
0 – Auto Switch PFM PWM operation
1 – PWM Mode Only
Reset
0
010
0
0
Name
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1
28
0
LP3907
EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
Delay (ms)
EN_DLY<2:0>
Buck1
Buck2
LDO1
LDO2
1
1
1
1
001
1
1.5
2
2
010
1.5
2
3
6
011
1.5
2
1
1
100
1.5
2
3
6
101
1.5
1.5
2
2
110
3
2
1
1.5
111
2
3
6
11
000
BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10
This register controls the enables for the Bucks and LDOs.
D7
D6
D5
D4
D3
D2
D1
D0
Name
—
LDO2EN
—
LDO1EN
—
BK2EN
—
BK1EN
Access
—
R/W
—
R/W
—
R/W
—
R/W
Data
Reserved
0 – Disable
1 – Enable
Reserved
0 – Disable
1 – Enable
Reserved
0 – Disable
1 – Enable
Reserved
0 – Disable
1 – Enable
Reset
0
1
1
1
0
1
0
1
BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11
This register monitors whether the Bucks and LDOs meet the voltage output specifications.
D7
D6
D5
D4
D3
D2
D1
D0
Name
BKS_OK
LDOS_OK
LDO2_OK
LDO1_OK
—
BK2_OK
—
BK1_OK
Access
R
R
R
R
—
R
—
R
Data
0 – Buck 1-2
Not Valid
1 – Bucks
Valid
0 – LDO 1-2
0 – LDO2 Not 0 – LDO1 Not Reserve
Not Valid
Valid
Valid
d
1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid
0 – Buck2 Not Reserve
Valid
d
1 – Buck2
Valid
0 – Buck1 Not
Valid
1 – Buck1
Valid
Reset
0
0
0
0
0
0
0
0
BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20
This register selects and controls the output target voltages for the buck regulators.
D7-6
D5
D4
D3-2
D1
D0
Name
—
B2VS
B2GO
—
B1VS
B1GO
Access
—
R/W
R/W
—
R/W
R/W
Data
Reserved
Buck2 Target Voltage
Select
0 – B2VT1
1 – B2VT2
Buck2 Voltage Ramp Reserved
CTRL
0 – Hold
1 – Ramp to B2VS
selection
Buck1 Target Voltage
Select
0 – B1VT1
1 – B1VT2
Buck1 Voltage Ramp
CTRL
0 – Hold
1 – Ramp to B1VS
selection
Reset
00
0
0
0
0
00
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LP3907
BUCK1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24
This register allows the user to program the output target voltage of Buck1.
BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23
This register allows the user to program the output target voltage of Buck1.
Name
Access
Data
D7-5
D4-0
—
BK1_VOUT1
Name
—
R/W
Access
Reserved
Buck1 Output Voltage (V)
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000
D4-0
—
BK1_VOUT2
—
R/W
Reserved
Buck1 Output Voltage (V)
5’h00
Ext Ctrl
5’h00
Ext Ctrl
5’h01
0.80
5’h01
0.80
5’h02
0.85
5’h02
0.85
5’h03
0.90
5’h03
0.90
5’h04
0.95
5’h04
0.95
5’h05
1.00
5’h05
1.00
5’h06
1.05
5’h06
1.05
5’h07
1.10
5’h07
1.10
5’h08
1.15
5’h08
1.15
5’h09
1.20
5’h09
1.20
5’h0A
1.25
5’h0A
1.25
5’h0B
1.30
5’h0B
1.30
5’h0C
1.35
5’h0C
1.35
5’h0D
1.40
5’h0D
1.40
5’h0E
1.45
5’h0E
1.45
5’h0F
1.50
5’h0F
1.50
5’h10
1.55
5’h10
1.55
5’h11
1.60
5’h11
1.60
5’h12
1.65
5’h12
1.65
5’h13
1.70
5’h13
1.70
5’h14
1.75
5’h14
1.75
5’h15
1.80
5’h15
1.80
5’h16
1.85
5’h16
1.85
5’h17
1.90
5’h17
1.90
5’h18
1.95
5’h18
1.95
5’h19
2.00
5’h19
2.00
5’h1A–5’h1F
Reset
Data
D7-5
2.00
5’h1A–5’h1F
01001
Reset
30
000
01001
2.00
LP3907
BUCK1 RAMP CONTROL REGISTER (B1RC) - 0x25
This register allows the user to program the rate of change between the target voltages of Buck1.
Name
Access
Data
D7
D6-4
D3-0
----
----
B1RS
----
----
Reserved
Reserved
R/W
Data Code
Ramp Rate mV/us
4h'0
Instant
4h'1
1
4h'2
2
4h'3
3
4h'4
4
4h'5
5
4h'6
6
4h'7
7
4h'8
8
4h'9
9
4h'A
10
4h'B - 4h'F
Reset
0
010
10
1000
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LP3907
BUCK2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A
This register allows the user to program the output target voltage of Buck2.
BUCK2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29
This register allows the user to program the output target voltage of Buck2.
Name
Access
Data
D7-5
D4-0
—
BK2_VOUT1
Name
—
R/W
Access
Reserved
Buck2 Output Voltage (V)
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000
D4-0
—
BK2_VOUT2
—
R/W
Reserved
Buck2 Output Voltage (V)
5’h00
Ext Ctrl
5’h00
Ext Ctrl
5’h01
1.0
5’h01
1.0
5’h02
1.1
5’h02
1.1
5’h03
1.2
5’h03
1.2
5’h04
1.3
5’h04
1.3
5’h05
1.4
5’h05
1.4
5’h06
1.5
5’h06
1.5
5’h07
1.6
5’h07
1.6
5’h08
1.7
5’h08
1.7
5’h09
1.8
5’h09
1.8
5’h0A
1.9
5’h0A
1.9
5’h0B
2.0
5’h0B
2.0
5’h0C
2.1
5’h0C
2.1
5’h0D
2.2
5’h0D
2.2
5’h0E
2.4
5’h0E
2.4
5’h0F
2.5
5’h0F
2.5
5’h10
2.6
5’h10
2.6
5’h11
2.7
5’h11
2.7
5’h12
2.8
5’h12
2.8
5’h13
2.9
5’h13
2.9
5’h14
3.0
5’h14
3.0
5’h15
3.1
5’h15
3.1
5’h16
3.2
5’h16
3.2
5’h17
3.3
5’h17
3.3
5’h18
3.4
5’h18
3.4
5’h19
3.5
5’h19
3.5
5’h1A–5’h1F
Reset
Data
D7-5
3.5
5’h1A–5’h1F
01001
Reset
32
000
01001
3.5
LP3907
BUCK2 RAMP CONTROL REGISTER (B2RC) - 0x2B
This register allows the user to program the rate of change between the target voltages of Buck2
Name
Access
Data
D7
D6-4
D3-0
----
----
B2RS
----
----
Reserved
Reserved
R/W
Data Code
Ramp Rate mV/us
4h'0
Instant
4h'1
1
4h'2
2
4h'3
3
4h'4
4
4h'5
5
4h'6
6
4h'7
7
4h'8
8
4h'9
9
4h'A
10
4h'B - 4h'F
Reset
0
010
10
1000
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LP3907
netic Interference (EMI). The spread spectrum modulation
frequency refers to the rate at which the frequency ramps up
and down, centered at 2MHz.
BUCK FUNCTION REGISTER (BFCR) – 0x38
This register allows the Buck switcher clock frequency to be
spread across a wider range, allowing for less Electro-mag-
30017825
This register also allows dynamic scaling of the NPOR Delay
Timing. The LP3907 is equipped with an internal Power-OnReset (“POR”) circuit which monitors the output voltage levels
on the buck regulators, allowing the user to more actively
monitor the power status of the chip.
The Under Voltage Lock-Out feature continuously monitor the
raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage
D7-2
D4
is less than 2.8VDC. This prevents the user from damaging
the power source (i.e. battery), but can be disabled if the user
wishes.
Note that if the supply to VDD_M is close to 2.8V with a heavy
load current on the regulators, the chip is in danger of powering down due to UVLO. If the user wishes to keep the chip
active under those conditions, enable the “Bypass UVLO”
feature.
D3
D1
D0
Name
—
BP_UVLO
TPOR
BK_SLOMOD
BK_SSEN
Access
—
R/W
R/w
R/W
R/W
Bypass UVLO
monitoring
0 - Allow UVLO
1 - Disable UVLO
NPOR Delay Timing
00 - 50µs
01 - 50ms
10 - 100ms
11 - 200ms
Buck Spread Spectrum
Modulation
0 – 10 kHz triangular wave
1 – 2 kHz triangular wave
Spread Spectrum
Function Output
0 – Disabled
1 – Enabled
01
1
Data
Reserved
Reset
000
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0
34
0
Name
Access
Data
D7-5
D4-0
—
LDO1_OUT
Name
—
R/W
Access
Reserved
LDO1 Output voltage (V)
000
D4-0
—
LDO2_OUT
—
R/W
Reserved
LDO2 Output voltage (V)
5’h00
1.0
5’h00
1.0
5’h01
1.1
5’h01
1.1
5’h02
1.2
5’h02
1.2
5’h03
1.3
5’h03
1.3
5’h04
1.4
5’h04
1.4
5’h05
1.5
5’h05
1.5
5’h06
1.6
5’h06
1.6
5’h07
1.7
5’h07
1.7
5’h08
1.8
5’h08
1.8
5’h09
1.9
5’h09
1.9
5’h0A
2.0
5’h0A
2.0
5’h0B
2.1
5’h0B
2.1
5’h0C
2.2
5’h0C
2.2
5’h0D
2.3
5’h0D
2.3
5’h0E
2.4
5’h0E
2.4
5’h0F
2.5
5’h0F
2.5
5’h10
2.6
5’h10
2.6
5’h11
2.7
5’h11
2.7
5’h12
2.8
5’h12
2.8
5’h13
2.9
5’h13
2.9
5’h14
3.0
5’h14
3.0
5’h15
3.1
5’h15
3.1
5’h16
3.2
5’h16
3.2
5’h17
3.3
5’h17
3.3
5’h18
3.4
5’h18
3.4
5’h19
3.5
5’h19
3.5
5’h1A–5’h1F
Reset
Data
D7-5
3.5
5’h1A–5’h1F
01111
Reset
35
000
3.5
10111
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LP3907
LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A
This register allows the user to program the output target voltage of LDO 2.
LDO1 CONTROL REGISTER (LDO1VCR) – 0X39
This register allows the user to program the output target voltage of LDO 1.
LP3907
External Capacitors
The regulators on the LP3907 require external capacitors for
regulator stability. These are specifically designed for
portable applications requiring minimum board space and
smallest components. These capacitors must be correctly selected for good performance.
Application Notes
ANALOG POWER SIGNAL ROUTING
All power inputs should be tied to the main VDD source (i.e.
battery), unless the user wishes to power it from another
source. (i.e. external LDO output).
The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog
VDD inputs must have an input voltage between 2.8 and 5.5V,
as specified in the Electrical Characteristics Section in the
front of the datasheet.
The other VINs (VINLDO1, VINLDO2, VIN1, VIN2) can actually
have inputs lower than 2.8V, as long as it's higher than the
programmed output (+0.3V, to be safe).
The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.
LDO CAPACITOR SELECTION
Input Capacitor
An input capacitor is required for stability. It is recommended
that a 1.0μF capacitor be connected between the LDO input
pin and ground (this capacitance value may be increased
without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog ground.
Any good quality ceramic, tantalum, or film capacitor may be
used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be
guaranteed by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain approximately
1.0μF over the entire operating temperature range.
COMPONENT SELECTION
Inductors for SW1 and SW2
There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor current
ripple is small enough to achieve the desired output voltage
ripple. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at
25ºC, so ratings at maximum ambient temperature of the application should be requested from the manufacturer.
There are two methods to choose the inductor saturation current rating:
Output Capacitor
The LDOs on the LP3907 are designed specifically to work
with very small ceramic output capacitors. A 0.47µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the application circuit.
It is also possible to use tantalum or film capacitors at the
device output, COUT (or VOUT), but these are not as attractive
for reasons of size and cost.
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that
is within the range 5 mΩ to 500 mΩ for stability.
Method 1:
The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as follows:
IRIPPLE:
IOUTMAX:
VIN:
L:
f:
VOUT:
Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 0.47µF to 4.7µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1.0µF ceramic
capacitor is in the range of 20mΩ to 40mΩ, which easily
meets the ESR requirement for stability for the LDOs.
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct device
operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show some
decrease over time due to aging. The capacitor parameters
are also dependent on the particular case size, with smaller
sizes giving poorer performance figures in general. As an example, below is typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot.
Average to peak inductor current
Maximum load current
Maximum input voltage to the buck
Min inductor value including worse case tolerances
(30% drop can be considered for method 1)
Minimum switching frequency (1.6 MHz)
Buck Output voltage
Method 2:
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the maximum current limit of 1250mA for Buck1 and
1750mA for Buck2.
Given a peak-to-peak current ripple (IPP) the inductor needs
to be at least
Inductor
LSW1,2
www.national.com
Value Unit Description
2.2
µH
SW1,2 inductor
Notes
D.C.R. 70mΩ
36
The worse case is when VIN = 2VOUT.
30017828
Graph Showing a Typical Variation in Capacitance vs. DC
Bias
Output Capacitor Selection for SW1, SW2
A 10μF, 6.3V ceramic capacitor should be used on the output
of the sw1 and sw2 magnetic dc/dc converters. The output
capacitor needs to be mounted as close as possible to the
output of the device. A large value may be used for improved
input voltage filtering. The recommended capacitor types are
X7R or X5R. Y5V type capacitors should not be used. DC bias
characteristics of ceramic capacitors must be considered
when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC
bias curves should be requested from them and analyzed as
part of the capacitor selection process.
The output filter capacitor of the magnetic dc/dc converter
smooths out current flow from the inductor to the load, helps
maintain a steady output voltage during transient load
changes and reduces output voltage ripple. These capacitors
must be selected with sufficient capacitance and sufficiently
low ESD to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and
can be calculated as follows:
As shown in the graph, increasing the DC Bias condition can
result in the capacitance value that falls below the minimum
value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec
for the 0402 case size capacitor at higher bias voltages. It is
therefore recommended that the capacitor manufacturers'
specifications for the nominal value capacitor are consulted
for all conditions, as some capacitor sizes (e.g. 0402) may not
be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance
to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C.
Many large value ceramic capacitors, larger than 1µF are
manufactured with Z5U or Y5V temperature characteristics.
Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient
temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
0.47µF to 4.7µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have
to be larger in capacitance (which means bigger and more
costly) than a ceramic capacitor with the same ESR value. It
should also be noted that the ESR of a typical tantalum will
increase about 2:1 as the temperature goes from 25°C down
to −40°C, so some guard band must be allowed.
Voltage peak-to-peak ripple due to ESR can be expressed as
follows:
VPP–ESR = 2 × IRIPPLE × RESR
Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the peak-topeak ripple:
Input Capacitor Selection for SW1 and SW2
A ceramic input capacitor of 10µF, 6.3V is sufficient for the
magnetic dc/dc converters. Place the input capacitor as close
as possible to the input of the device. A large value may be
used for improved input voltage filtering. The recommended
capacitor types are X7R or X5R. Y5V type capacitors should
not be used. DC bias characteristics of ceramic capacitors
must be considered when selecting case sizes like 0805 and
0603. The input filter capacitor supplies current to the PFET
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the
output capacitor (RESR). The RESR is frequency dependent as
well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient
temperature.
37
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LP3907
switch of the dc/dc converter in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A
ceramic capacitor’s low ESR (Equivalent Series Resistance)
provides the best noise filtering of the input voltage spikes due
to fast current transients. A capacitor with sufficient ripple
current rating should be selected. The Input current ripple can
be calculated as:
LP3907
Min Value
Unit
CLDO1
Capacitor
0.47
µF
LDO1 output capacitor
Description
Ceramic, 6.3V, X5R
Recommended Type
CLDO2
0.47
µF
LDO2 output capacitor
Ceramic, 6.3V, X5R
CSW1
10.0
µF
SW1 output capacitor
Ceramic, 6.3V, X5R
CSW2
10.0
µF
SW2 output capacitor
Ceramic, 6.3V, X5R
Buck regulators. (Read below: Factory programmable options). The I2C-less system must rely on the correct default
output values of the LDO and Buck converters.
I2C Pullup Resistor
Both SDA and SCL terminals need to have pullup resistors
connected to VINLDO12 or to the power supply of the I2C
master. The values of the pull-up resistors (typ. ∼1.8kΩ) are
determined by the capacitance of the bus. Too large of a resistor combined with a given bus capacitance will result in a
rise time that would violate the max. rise time specification. A
too small resistor will result in a contention with the pull-down
transistor on either slave(s) or master.
Factory Programmable Options
The following options are EPROM programmed during final
test of the LP3907. The system designer that needs specific
options is advised to contact the local National Semiconductor sales office.
Operation without I2C Interface
Operation of the LP3907 without the I2C interface is possible
if the system can operate with default values for the LDO and
Factory programmable options
Current value
Enable delay for power on
code 010 (see Control 1 register section)
SW1 ramp speed
8 mV/µs
SW2 ramp speed
8 mV/µs
The I2C Chip ID address is offered as a metal mask option.
The current value equals 0x60.
Power dissipation of Buck1
PBuck1 = PIN – POUT =
VoutBuck1* IoutBuck1 * (1 -η1) / η1 [V*A]
HIGH VINHIGH-LOAD OPERATION
Additional information is provided when the IC is operated at
extremes of VIN and regulator loads. These are described in
terms of the Junction temperature and, Buck output ripple
management.
η1 = efficiency of buck 1
Power dissipation of Buck2
PBuck2 = PIN – POUT =
VoutBuck2 * IoutBuck2 * (1 - η2) / η2 [V*A]
η2 = efficiency of Buck2
Where η is the efficiency for the specific condition taken from
efficiency graphs.
JUNCTION TEMPERATURE
The maximum junction temperature TJ-MAX-OP of 125ºC of the
IC package.
The following equations demonstrate junction temperature
determination, ambient temperature TA-MAX and Total chip
power must be controlled to keep TJ below this maximum:
TJ-MAX-OP = TA-MAX + (θJA) [ °C/ Watt] * (PD-MAX) [Watts]
Total IC power dissipation PD-MAX is the sum of the individual
power dissipation of the four regulators plus a minor amount
for chip overhead. Chip overhead is Bias, TSD & LDO analog.
PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * VIN)
[Watts].
Power dissipation of LDO1
PLDO1 = (VINLDO1- VOUTLDO1) * IoutLDO1 [V*A]
Power dissipation of LDO2
PLDO2 = (VINLDO2 - VoutLDO2) * IoutLDO2 [V*A]
www.national.com
38
The LP3907 is a monolithic device with integrated power
FETs. For that reason, it is important to pay special attention
to the thermal impedance of the LLP package and to the PCB
layout rules in order to maximize power dissipation of the LLP
package.
The LLP package is designed for enhanced thermal performance and features an exposed die attach pad at the bottom
center of the package that creates a direct path to the PCB
for maximum power dissipation. Compared to the traditional
leaded packages where the die attach pad is embedded inside the molding compound, the LLP reduces one layer in the
thermal path.
The thermal advantage of the LLP package is fully realized
only when the exposed die attach pad is soldered down to a
thermal land on the PCB board with thermal vias planted un-
39
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LP3907
derneath the thermal land. Based on thermal analysis of the
LLP package, the junction-to-ambient thermal resistance
(θJA) can be improved by a factor of two when the die attach
pad of the LLP package is soldered directly onto the PCB with
thermal land and thermal vias, as opposed to an alternative
with no direct soldering to a thermal land. Typical pitch and
outer diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although
thicker copper may be used to further improve thermal performance. The LP3907 die attach pad is connected to the
substrate of the IC and therefore, the thermal land and vias
on the PCB board need to be connected to ground (GND pin).
For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame Package
(LLP).” on http://www.national.com This application note also
discusses package handling, solder stencil and the assembly
process.
Thermal Performance of the LLP
Package
LP3907
Physical Dimensions inches (millimeters) unless otherwise noted
4 X 4 X 0.8 mm 24-Pin LLP Package
NS Package SQA24A
For ordering, refer to Ordering Information table
www.national.com
40
LP3907
Notes
41
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LP3907 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible
Interface
Notes
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(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
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LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
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Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
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can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
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Copyright© 2007 National Semiconductor Corporation
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