TI1 MSP430F2417TZQW Mixed signal microcontroller Datasheet

MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Voltage Range 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 365 µA at 1 MHz, 2.2 V
– Standby Mode (VLO): 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Wake-Up From Standby Mode in Less Than
1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Three-Channel Internal DMA
12-Bit Analog-to-Digital (A/D) Converter With
Internal Reference, Sample-and-Hold, and
Autoscan Feature
Dual 12-Bit Digital-to-Analog (D/A) Converters
With Synchronization
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers
On-Chip Comparator
Four Universal Serial Communication
Interfaces (USCIs)
– USCI_A0 and USCI_A1
– Enhanced UART Supporting AutoBaudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1
– I2C™
– Synchronous SPI
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Brownout Detector
Bootstrap Loader
•
•
•
•
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Family Members:
– MSP430F2416
– 92KB + 256B Flash Memory
– 4KB RAM
– MSP430F2417
– 92KB + 256B Flash Memory
– 8KB RAM
– MSP430F2418
– 116KB + 256B Flash Memory
– 8KB RAM
– MSP430F2419
– 120KB + 256B Flash Memory
– 4KB RAM
– MSP430F2616
– 92KB + 256B Flash Memory
– 4KB RAM
– MSP430F2617
– 92KB + 256B Flash Memory
– 8KB RAM
– MSP430F2618
– 116KB + 256B Flash Memory
– 8KB RAM
– MSP430F2619
– 120KB + 256B Flash Memory
– 4KB RAM
Available in 80-Pin Quad Flat Pack (LQFP), 64Pin LQFP, and 113-Pin Ball Grid Array (BGA)
(See Table 1)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430F261x and MSP430F241x series are microcontroller configurations with two built-in 16-bit timers, a
fast 12-bit A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface
(USCI) modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x
devices, with the exception that the DAC12 and the DMA modules are not implemented.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc. The 12x12mm LQFP-64 package is also available as a non-magnetic package for medical imaging applications.
Table 1. Available Options (1)
TA
-40°C to 105°C
(1)
(2)
PACKAGED DEVICES (2)
PLASTIC 113-PIN BGA (ZQW)
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN LQFP (PM)
MSP430F2416TZQW
MSP430F2417TZQW
MSP430F2418TZQW
MSP430F2419TZQW
MSP430F2616TZQW
MSP430F2617TZQW
MSP430F2618TZQW
MSP430F2619TZQW
MSP430F2416TPN
MSP430F2417TPN
MSP430F2418TPN
MSP430F2419TPN
MSP430F2616TPN
MSP430F2617TPN
MSP430F2618TPN
MSP430F2619TPN
MSP430F2416TPM
MSP430F2417TPM
MSP430F2418TPM
MSP430F2419TPM
MSP430F2616TPM
MSP430F2617TPM
MSP430F2618TPM
MSP430F2619TPM
MSP430F2618TPMR-NM
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and
programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-FET430U64 (PM Package)
– MSP-FET430U80 (PN Package)
• Standalone Target Board
– MSP-TS430PM64
• Production Programmer
– MSP-GANG430
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MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
Device Pinout, MSP430F241x, 80-Pin PN Package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
1
2
60
59
P7.6
P7.5
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
3
4
5
6
58
57
56
55
P7.4
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
Ve REF+
VREF-/VeREF-
7
8
9
10
11
54
53
52
51
50
P7.0
DVSS2
DVCC2
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
12
13
14
15
49
48
47
46
P5.5/SMCLK
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
16
45
17
18
19
44
43
42
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P2.0/ACLK/CA2
20
41
P4.5/TB5
80-PIN
PN PACKAGE
(TOP VIEW)
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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MSP430F241x
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AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
Device Pinout, MSP430F241x, 64-Pin PM Package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
VREF-/VeREF-
1
2
3
4
5
6
7
8
9
10
11
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
12
13
14
15
16
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
Ve REF+
64-PIN
PM PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
37
36
35
34
33
P4.1/TB1
P4.0/TB0
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
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MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AV CC
DVSS1
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
Device Pinout, MSP430F261x, 80-Pin PN Package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
P6.4/A4
1
2
3
60
59
58
P7.6
P7.5
P7.4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
4
5
6
57
56
55
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
7
8
9
54
53
52
P7.0
DVSS2
DVCC2
51
50
49
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
80-PIN
PN PACKAGE
(TOP VIEW)
Ve REF+/DAC0
VREF-/VeREFP1.0/TACLK/CAOUT
10
11
12
P1.1/TA0
P1.2/TA1
P1.3/TA2
13
14
15
48
47
46
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
16
45
17
18
44
43
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P1.7/TA2
P2.0/ACLK/CA2
19
20
42
41
P4.6/TB6
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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P5.5/SMCLK
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
XT2IN
XT2OUT
TDI/TCLK
TDO/TDI
TCK
TMS
RST/NMI
P6.1/A1
P6.0/A0
AV SS
P6.2/A2
DVSS1
AV CC
Device Pinout, MSP430F261x, 64-Pin PM Package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DV CC1
1
48
P6.3/A3
2
47
P5.3/UCB1CLK/UCA1STE
P6.4/A4
3
46
P5.2/UCB1SOMI/UCB1SCL
P6.5/A5/DAC1
P6.6/A6/DAC0
4
5
45
44
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P6.7/A7/DAC1/SVSIN
6
43
P4.7/TBCLK
VREF+
7
42
P4.6/TB6
XIN
8
41
P4.5/TB5
40
39
P4.4/TB4
P4.3/TB3
XOUT
Ve REF+/DAC0
9
10
64-PIN
PM PACKAGE
(TOP VIEW)
P5.4/MCLK
VREF-/Ve REF-
11
38
P4.2/TB2
P1.0/TACLK/CAOUT
12
37
P4.1/TB1
P1.1/TA0
13
36
P4.0/TB0
P1.2/TA1
14
35
P3.7/UCA1RXD/UCA1SOMI
P1.3/TA2
P1.4/SMCLK
15
16
34
33
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
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P3.4/UCA0TXD/UCA0SIMO
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P2.7/TA0/CA7
P2.6/ADC12CLK/DMAE0/CA6
P2.5/ROSC/CA5
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.0/ACLK/CA2
P1.7/TA2
P1.5/TA0
6
P1.6/TA1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Device Pinout, 113-Pin ZQW Package
NOTE
For terminal assignments, see Table 2.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
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MSP430F241x
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Functional Block Diagram, MSP430F241x, 80-Pin PN Package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS1/2
Flash
RAM
120KB
116KB
92KB
92KB
4KB
8KB
8KB
4KB
AVCC
AVSS
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
ADC12
12-Bit
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
8
Channels
4x8 I/O
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
Timer_B7
Watchdog
WDT+
MPY,
MPYS,
MAC,
MACS
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
Functional Block Diagram, MSP430F241x, 64-Pin PM Package
XIN/ XOUT/
XT2IN XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS
Flash
RAM
120KB
116KB
92KB
92KB
4KB
8KB
8KB
4KB
AVCC
AVSS
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
ADC12
12-Bit
2x8 I/O
Interrupt
capability
8
Channels
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
8
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MSP430F241x
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Functional Block Diagram, MSP430F261x, 80-Pin PN Package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
Flash
120kB
116kB
92kB
92kB
56kB
DVSS1/2
AVCC
RAM
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
4x8 I/O
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
Functional Block Diagram, MSP430F261x, 64-Pin PM Package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
Flash
120kB
116kB
92kB
92kB
56kB
DVSS
AVCC
RAM
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
2x8 I/O
Interrupt
capability
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
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Table 2. Terminal Functions
TERMINAL
NO.
NAME
I/O
DESCRIPTION
64
PIN
80
PIN
113
PIN
AVCC
64
80
A2
Analog supply voltage, positive terminal. Supplies only the analog portion of
ADC12 and DAC12.
AVSS
62
78
B2, B3
Analog supply voltage, negative terminal. Supplies only the analog portion of
ADC12 and DAC12.
DVCC1
1
1
A1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
63
79
A3
Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2
52
F12
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2
53
E12
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/ CAOUT
12
12
G2
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK
input/Comparator_A output
P1.1/TA0
13
13
H1
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0
output/BSL transmit
P1.2/TA1
14
14
H2
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1
output
P1.3/TA2
15
15
J1
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2
output
P1.4/SMCLK
16
16
J2
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
17
K1
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
18
K2
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
19
L1
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2
20
20
M1
I/O
General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/CA3
21
21
M2
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0/CA4
22
22
M3
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A
output/BSL receive/Comparator_A input
P2.3/CA0/TA1
23
23
L3
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A
input
P2.4/CA1/TA2
24
24
L4
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A
input
P2.5/ROSC/CA5
25
25
M4
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO
nominal frequency/Comparator_A input
P2.6/ADC12CLK/
DMAE0 (1)/CA6
26
26
J4
I/O
General-purpose digital I/O pin/conversion clock - 12-bit ADC/DMA channel 0
external trigger/Comparator_A input
P2.7/TA0/CA7
27
27
L5
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A
input
P3.0/UCB0STE/
UCA0CLK
28
28
M5
I/O
General-purpose digital I/O pin/USCI_B0 slave transmit enable/USCI_A0
clock input/output
P3.1/UCB0SIMO/
UCB0SDA
29
29
L6
I/O
General-purpose digital I/O pin/USCI_B0 slave in/master out in SPI mode,
SDA I2C data in I2C mode
P3.2/UCB0SOMI/
UCB0SCL
30
30
M6
I/O
General-purpose digital I/O pin/USCI_B0 slave out/master in in SPI mode,
SCL I2C clock in I2C mode
P3.3/UCB0CLK/
UCA0STE
31
31
L7
I/O
General-purpose digital I/O/USCI_B0 clock input/output, USCI_A0 slave
transmit enable
P3.4/UCA0TXD/
UCA0SIMO
32
32
M7
I/O
General-purpose digital I/O pin/USCI_A transmit data output in UART mode,
slave data in/master out in SPI mode
P3.5/UCA0RXD/
UCA0SOMI
33
33
L8
I/O
General-purpose digital I/O pin/USCI_A0 receive data input in UART mode,
slave data out/master in in SPI mode
P3.6/UCA1TXD/
UCA1SIMO
34
34
M8
I/O
General-purpose digital I/O pin/USCI_A1 transmit data output in UART mode,
slave data in/master out in SPI mode
P3.7/UCA1RXD/
UCA1SOMI
35
35
L9
I/O
General-purpose digital I/O pin/USCI_A1 receive data input in UART mode,
slave data out/master in in SPI mode
(1)
10
MSP430F261x devices only
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MSP430F241x
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Table 2. Terminal Functions (continued)
TERMINAL
NO.
NAME
I/O
DESCRIPTION
64
PIN
80
PIN
113
PIN
P4.0/TB0
36
36
M9
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare:
Out0 output
P4.1/TB1
37
37
J9
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare:
Out1 output
P4.2/TB2
38
38
M10
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare:
Out2 output
P4.3/TB3
39
39
L10
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare:
Out3 output
P4.4/TB4
40
40
M11
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare:
Out4 output
P4.5/TB5
41
41
M12
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare:
Out5 output
P4.6/TB6
42
42
L12
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6
output
P4.7/TBCLK
43
43
K11
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/UCB1STE/
UCA1CLK
44
44
K12
I/O
General-purpose digital I/O pin/USCI_B1 slave transmit enable/USCI_A1
clock input/output
P5.1/UCB1SIMO/
UCB1SDA
45
45
J11
I/O
General-purpose digital I/O pin/USCI_B1 slave in/master out in SPI mode,
SDA I2C data in I2C mode
P5.2/UCB1SOMI/
UCB1SCL
46
46
J12
I/O
General-purpose digital I/O pin/USCI_B1 slave out/master in in SPI mode,
SCL I2C clock in I2C mode
P5.3/UCB1CLK/
UCA1STE
47
47
H11
I/O
General-purpose digital I/O/USCI_B1 clock input/output, USCI_A1 slave
transmit enable
P5.4/MCLK
48
48
H12
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
49
G11
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
50
G12
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/SVSOUT
51
51
F11
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high
impedance - Timer_B TB0 to TB6/SVS comparator output
P6.0/A0
59
75
D4
I/O
General-purpose digital I/O pin/analog input A0 - 12-bit ADC
P6.1/A1
60
76
A4
I/O
General-purpose digital I/O pin/analog input A1 - 12-bit ADC
P6.2/A2
61
77
B4
I/O
General-purpose digital I/O pin/analog input A2 - 12-bit ADC
P6.3/A3
2
2
B1
I/O
General-purpose digital I/O pin/analog input A3 - 12-bit ADC
P6.4/A4
3
3
C1
I/O
General-purpose digital I/O pin/analog input A4 - 12-bit ADC
P6.5/A5/DAC1 (2)
4
4
C2
C3
I/O
General-purpose digital I/O pin/analog input A5 - 12-bit ADC/DAC12.1 output
(2)
5
5
D1
I/O
General-purpose digital I/O pin/analog input A6 - 12-bit ADC/DAC12.0 output
6
6
D2
I/O
General-purpose digital I/O pin/analog input A7 - 12-bit ADC/DAC12.1
output/SVS input
P6.6/A6/DAC0
P6.7/A7/DAC1 (2)/SVSIN
P7.0
54
E11
I/O
General-purpose digital I/O pin
P7.1
55
D12
I/O
General-purpose digital I/O pin
P7.2
56
D11
I/O
General-purpose digital I/O pin
P7.3
57
C12
I/O
General-purpose digital I/O pin
P7.4
58
C11
I/O
General-purpose digital I/O pin
P7.5
59
B12
I/O
General-purpose digital I/O pin
P7.6
60
A12
I/O
General-purpose digital I/O pin
P7.7
61
A11
I/O
General-purpose digital I/O pin
P8.0
62
B10
I/O
General-purpose digital I/O pin
P8.1
63
A10
I/O
General-purpose digital I/O pin
(2)
MSP430F261x devices only
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Table 2. Terminal Functions (continued)
TERMINAL
NO.
NAME
64
PIN
I/O
DESCRIPTION
80
PIN
113
PIN
P8.2
64
D9
I/O
General-purpose digital I/O pin
P8.3
65
A9
I/O
General-purpose digital I/O pin
P8.4
66
B9
I/O
General-purpose digital I/O pin
P8.5
67
B8
I/O
General-purpose digital I/O pin
P8.6/XT2OUT
68
A8
O
General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
P8.7/XT2IN
69
A7
I
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only
standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
XT2IN
53
I
Input port for crystal oscillator XT2
RST/NMI
58
74
B5
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in
flash devices).
TCK
57
73
A5
I
Test clock (JTAG). TCK is the clock input port for device programming test
and bootstrap loader start.
TDI/TCLK
55
71
A6
I
Test data input or test clock input. The device protection fuse is connected to
TDI/TCLK.
TDO/TDI
54
70
B7
I/O
TMS
56
72
B6
I
Test mode select. TMS is used as an input port for device programming and
test.
VeREF+/DAC0 (3)
10
10
F2
I
Input for an external reference voltage/DAC12.0 output
VREF+
7
7
E2
O
Output of positive terminal of the reference voltage in the ADC12
VREF-/VeREF-
11
11
G1
I
Negative terminal for the reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
XIN
8
8
E1
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
9
F1
O
Output port for crystal oscillator XT1. Standard or watch crystals can be
connected.
Reserved
-
-
(4)
(3)
(4)
12
NA
Test data output port. TDO/TDI data output or programming data input
terminal.
Reserved pins. Connection to DVSS, AVSS recommended.
MSP430F261x devices only
Reserved pins are L2, E4, F4, G4, H4, D5, E5, F5, G5, H5, J5, D6, E6, H6, J6, D7, E7, H7, J7, D8, E8, F8, G8, H8, J8, E9, F9, G9, H9,
B11, L11.
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 -> R5
Single operands, destination only
CALL R8
PC ->(TOS), R8-> PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 4. Address Mode Descriptions
ADDRESS MODE
D
(1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 -> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)-> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) -> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) -> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) -> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) -> R11
R10 + 2-> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 -> M(TONI)
(1)
S
(1)
OPERATION
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– DCO's dc-generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
14
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU enters LPM4 immediately after power-up.
Table 5. Interrupt Sources
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV
See (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG (4)
Maskable
0FFFAh
29
Timer_B7
TBCCR1 to TBCCR6 CCIFGs,
TBIFG (2) (4)
Maskable
0FFF8h
28
Comparator_A+
CAIFG
Maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG
(4)
Maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG (2) (4)
Maskable
0FFF0h
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG (2) (5)
Maskable
0FFEEh
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG (2) (6)
Maskable
0FFECh
22
ADC12
ADC12IFG (2) (4)
Maskable
0FFEAh
21
0FFE8h
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
Maskable
0FFE6h
19
I/O port P1 (eight flags)
(2) (4)
Maskable
0FFE4h
18
(2) (5)
Maskable
0FFE2h
17
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG (2) (6)
Maskable
0FFE0h
16
DMA
DMA0IFG, DMA1IFG,
DMA2IFG (2) (4)
Maskable
0FFDEh
15
DAC12
DAC12_0IFG, DAC12_1IFG (2) (4)
Maskable
USCI_A1/USCI_B1 receive
USCI_B1 I2C status
See
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
P1IFG.0 to P1IFG.7
UCA1RXIFG, UCB1RXIFG
(7) (8)
0FFDCh
14
0FFDAh to 0FFC0h
15 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
The address 0FFBEh is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
2
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
16
3
2
1
0
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
4
NMIIFG
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
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MSP430F241x
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Memory Organization
Table 8. Memory Organization
MSP430F2416
MSP430F2616
MSP430F2417
MSP430F2617
MSP430F2418
MSP430F2618
MSP430F2419
MSP430F2619
Size
92KB
92KB
116KB
120KB
Main: interrupt vector
Flash
0x0FFFF-0x0FFC0
0x0FFFF-0x0FFC0
0x0FFFF-0x0FFC0
0x0FFFF-0x0FFC0
Main: code memory
Flash
0x18FFF-0x02100
0x19FFF-0x03100
0x1FFFF-0x03100
0x1FFFF-0x02100
RAM (total)
Size
4KB
0x020FF-0x01100
8KB
0x030FF-0x01100
8KB
0x030FF-0x01100
4KB
0x020FF-0x01100
Extended
Size
2KB
0x020FF-0x01900
6KB
0x030FF-0x01900
6KB
0x030FF-0x01900
2KB
0x020FF-0x01900
Mirrored
Size
2KB
0x018FF-0x01100
2KB
0x018FF-0x01100
2KB
0x018FF-0x01100
2KB
0x018FF-0x01100
Memory
Information memory
Boot memory
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
Size
256 Byte
256 Byte
256 Byte
256 Byte
Flash
0x010FF-0x01000
0x010FF-0x01000
0x010FF-0x01000
0x010FF-0x01000
Size
1KB
1KB
1KB
1KB
ROM
0x00FFF-0x00C00
0x00FFF-0x00C00
0x00FFF-0x00C00
0x00FFF-0x00C00
Size
2KB
0x009FF-0x00200
2KB
0x009FF-0x00200
2KB
0x009FF-0x00200
2KB
0x009FF-0x00200
16-bit
0x001FF-0x00100
0x001FF-0x00100
0x001FF-0x00100
0x001FF-0x00100
8-bit
0x000FF-0x00010
0x000FF-0x00010
0x000FF-0x00010
0x000FF-0x00010
8-bit SFR
0x0000F-0x00000
0x0000F-0x00000
0x0000F-0x00000
0x0000F-0x00000
Bootstrap Loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to
the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader (BSL)
User's Guide (SLAU319).
Table 9. BSL Pin Functions
BSL FUNCTION
PM, PN PACKAGE
PINS
ZQW PACKAGE
PINS
Data Transmit
13 - P1.1
H1 - P1.1
Data Receive
22 - P2.2
M3 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
• Flash content integrity check with marginal read modes
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the
DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power
consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a
peripheral.
Oscillator and System Clock
The clock system in the MSP430F241x and MSP430F261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low-frequency
oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.
Table 10. Tags Used by the TLV Structure
ADDRESS
VALUE
TAG_DCO_30
NAME
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration
TAG_ADC12_1
0x10DA
0x08
ADC12_1 calibration tag
-
0xFE
Identifier for empty memory areas
TAG_EMPTY
DESCRIPTION
Table 11. Labels Used by the ADC Calibration Structure
LABEL
CONDITION AT CALIBRATION / DESCRIPTION
SIZE
ADDRESS
OFFSET
CAL_ADC_25T85
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
word
0x000E
CAL_ADC_25T30
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
word
0x000C
CAL_ADC_25VREF_FACTOR
REF2_5 = 1, TA = 30°C
word
0x000A
CAL_ADC_15T85
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
word
0x0008
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
word
0x0006
CAL_ADC_15VREF_FACTOR
REF2_5 = 0, TA = 30°C
word
0x0004
CAL_ADC_OFFSET
External VREF = 1.5 V, fADC12CLK = 5 MHz
word
0x0002
CAL_ADC_GAIN_FACTOR
External VREF = 1.5 V, fADC12CLK = 5 MHz
word
0x0000
CAL_BC1_1MHZ
-
byte
0x0007
CAL_DCO_1MHZ
-
byte
0x0006
CAL_BC1_8MHZ
-
byte
0x0005
CAL_DCO_8MHZ
-
byte
0x0004
CAL_BC1_12MHZ
-
byte
0x0003
CAL_DCO_12MHZ
-
byte
0x0002
CAL_BC1_16MHZ
-
byte
0x0001
CAL_DCO_16MHZ
-
byte
0x0000
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Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is
not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have
ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
Digital I/O
There are up to eight 8-bit I/O ports implemented—ports P1 through P8:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
• Ports P7/P8 can be accessed word-wise.
Watchdog Timer (WDT+)
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as
signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) or I2C, and asynchronous combination protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI_A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The USCI_B module provides support for SPI (3 pin or 4 pin) and I2C
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer_A3 Signal Connections
INPUT PIN NUMBER
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
TA0
ZQW
PM, PN
DEVICE INPUT
SIGNAL
G2 - P1.0
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
OUTPUT PIN NUMBER
PM, PN
ZQW
M2 - P2.1
21 - P2.1
TAINCLK
INCLK
H1 - P1.1
13 - P1.1
TA0
CCI0A
13 - P1.1
H1 - P1.1
M3 - P2.2
22 - P2.2
TA0
CCI0B
17 - P1.5
K1 - P1.5
27 - P2.7
L5 - P2.7
H2 - P1.2
DVSS
GND
DVCC
VCC
14 - P1.2
TA1
CCI1A
14 - P1.2
H2 - P1.2
CAOUT
(internal)
CCI1B
CCR1
TA1
18 - P1.6
K2 - P1.6
DVSS
GND
23 - P2.3
L3 - P2.3
DVCC
VCC
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
J1 - P1.3
20
15 - P1.3
TA2
CCI2A
ACLK (internal)
15 - P1.3
J1 - P1.3
CCI2B
19 - P1.7
L1 - P1.7
DVSS
GND
24 - P2.4
L4 - P2.4
DVCC
VCC
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TA2
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Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 13. Timer_B3, Timer_B7 Signal Connections
INPUT PIN NUMBER
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
TB0
ZQW
PM, PN
DEVICE INPUT
SIGNAL
K11 - P4.7
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
K11 - P4.7
43 - P4.7
TBCLK
INCLK
M9 - P4.0
36 - P4.0
TB0
CCI0A
M9- P4.0
36 - P4.0
TB0
CCI0B
DVSS
GND
DVCC
VCC
J9 - P4.1
37 - P4.1
TB1
CCI1A
J9 - P4.1
37 - P4.1
TB1
CCI1B
DVSS
GND
OUTPUT PIN NUMBER
PM, PN
ZQW
36 - P4.0
M9 - P4.0
ADC12
(internal)
CCR1
TB1
37 - P4.1
ADC12
(internal)
DVCC
VCC
M10 - P4.2
38 - P4.2
TB2
CCI2A
M10 - P4.2
38 - P4.2
TB2
CCI2B
DAC_0
(internal)
DVSS
GND
DAC_1
(internal)
DVCC
VCC
L10 - P4.3
39 - P4.3
TB3
CCI3A
L10 - P4.3
39 - P4.3
TB3
CCI3B
DVSS
GND
DVCC
VCC
M11 - P4.4
40 - P4.4
TB4
CCI4A
M11 - P4.4
40 - P4.4
TB4
CCI4B
DVSS
GND
DVCC
VCC
M12 - P4.5
41 - P4.5
TB5
CCI5A
M12 - P4.5
41 - P4.5
TB5
CCI5B
DVSS
GND
L12 - P4.6
42 - P4.6
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
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J9 - P4.1
CCR2
TB2
38 - P4.2
M10 - P4.2
CCR3
TB3
39 - P4.3
L10 - P4.3
CCR4
TB4
40 - P4.4
M11 - P4.4
CCR5
TB5
41 - P4.5
M12 - P4.5
CCR6
TB6
42 - P4.6
L12 - P4.6
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Comparator_A+
The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
DAC12
The DAC12 module is a 12-bit R-ladder voltage-output digital-to-analog converter (DAC). The DAC12 may be
used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12
modules are present, they may be grouped together for synchronous operation.
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Peripheral File Map
Table 14. Peripherals File Map
MODULE
DMA
(1)
DAC12 (1)
(1)
REGISTER
SHORT FORM
ADDRESS
DMA channel 2 transfer size
DMA2SZ
0x01F2
DMA channel 2 destination address
DMA2DA
0x01EE
DMA channel 2 source address
DMA2SA
0x01EA
DMA channel 2 control
DMA2CTL
0x01E8
DMA channel 1 transfer size
DMA1SZ
0x01E6
DMA channel 1 destination address
DMA1DA
0x01E2
DMA channel 1 source address
DMA1SA
0x01DE
DMA channel 1 control
DMA1CTL
0x01DC
DMA channel 0 transfer size
DMA0SZ
0x01DA
DMA channel 0 destination address
DMA0DA
0x01D6
DMA channel 0 source address
DMA0SA
0x01D2
DMA channel 0 control
DMA0CTL
0x01D0
DMA module interrupt vector word
DMAIV
0x0126
DMA module control 1
DMACTL1
0x0124
DMA module control 0
DMACTL0
0x0122
DAC12_1 data
DAC12_1DAT
0x01CA
DAC12_1 control
DAC12_1CTL
0x01C2
DAC12_0 data
DAC12_0DAT
0x01C8
DAC12_0 control
DAC12_0CTL
0x01C0
MSP430F261x devices only
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Table 14. Peripherals File Map (continued)
MODULE
ADC12
24
REGISTER
SHORT FORM
ADDRESS
Interrupt vector word register
ADC12IV
0x01A8
Inerrupt enable register
ADC12IE
0x01A6
Inerrupt flag register
ADC12IFG
0x01A4
Control register 1
ADC12CTL1
0x01A2
Control register 0
ADC12CTL0
0x01A0
Conversion memory 15
ADC12MEM15
0x015E
Conversion memory 14
ADC12MEM14
0x015C
Conversion memory 13
ADC12MEM13
0x015A
Conversion memory 12
ADC12MEM12
0x0158
Conversion memory 11
ADC12MEM11
0x0156
Conversion memory 10
ADC12MEM10
0x0154
Conversion memory 9
ADC12MEM9
0x0152
Conversion memory 8
ADC12MEM8
0x0150
Conversion memory 7
ADC12MEM7
0x014E
Conversion memory 6
ADC12MEM6
0x014C
Conversion memory 5
ADC12MEM5
0x014A
Conversion memory 4
ADC12MEM4
0x0148
Conversion memory 3
ADC12MEM3
0x0146
Conversion memory 2
ADC12MEM2
0x0144
Conversion memory 1
ADC12MEM1
0x0142
Conversion memory 0
ADC12MEM0
0x0140
ADC memory-control register15
ADC12MCTL15
0x008F
ADC memory-control register14
ADC12MCTL14
0x008E
ADC memory-control register13
ADC12MCTL13
0x008D
ADC memory-control register12
ADC12MCTL12
0x008C
ADC memory-control register11
ADC12MCTL11
0x008B
ADC memory-control register10
ADC12MCTL10
0x008A
ADC memory-control register9
ADC12MCTL9
0x0089
ADC memory-control register8
ADC12MCTL8
0x0088
ADC memory-control register7
ADC12MCTL7
0x0087
ADC memory-control register6
ADC12MCTL6
0x0086
ADC memory-control register5
ADC12MCTL5
0x0085
ADC memory-control register4
ADC12MCTL4
0x0084
ADC memory-control register3
ADC12MCTL3
0x0083
ADC memory-control register2
ADC12MCTL2
0x0082
ADC memory-control register1
ADC12MCTL1
0x0081
ADC memory-control register0
ADC12MCTL0
0x0080
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Table 14. Peripherals File Map (continued)
MODULE
Timer_B7
Timer_A3
REGISTER
SHORT FORM
TBCCR6
0x019E
Capture/compare register 5
TBCCR5
0x019C
Capture/compare register 4
TBCCR4
0x019A
Capture/compare register 3
TBCCR3
0x0198
Capture/compare register 2
TBCCR2
0x0196
Capture/compare register 1
TBCCR1
0x0194
Capture/compare register 0
TBCCR0
0x0192
Timer_B register
TBR
0x0190
Capture/compare control 6
TBCCTL6
0x018E
Capture/compare control 5
TBCCTL5
0x018C
Capture/compare control 4
TBCCTL4
0x018A
Capture/compare control 3
TBCCTL3
0x0188
Capture/compare control 2
TBCCTL2
0x0186
Capture/compare control 1
TBCCTL1
0x0184
Capture/compare control 0
TBCCTL0
0x0182
Timer_B control
TBCTL
0x0180
Timer_B interrupt vector
TBIV
0x011E
Capture/compare register 2
TACCR2
0x0176
Capture/compare register 1
TACCR1
0x0174
Capture/compare register 0
TACCR0
0x0172
Timer_A register
TAR
0x0170
Reserved
0x016E
Reserved
0x016C
Reserved
0x016A
Reserved
Hardware
Multiplier
Flash
Watchdog
ADDRESS
Capture/compare register 6
0x0168
Capture/compare control 2
TACCTL2
0x0166
Capture/compare control 1
TACCTL1
0x0164
Capture/compare control 0
TACCTL0
0x0162
Timer_A control
TACTL
0x0160
Timer_A interrupt vector
TAIV
0x012E
Sum extend
SUMEXT
0x013E
Result high word
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
OP2
0x0138
Multiply signed +accumulate/operand 1
MACS
0x0136
Multiply+accumulate/operand 1
MAC
0x0134
Multiply signed/operand 1
MPYS
0x0132
Multiply unsigned/operand 1
MPY
0x0130
Flash control 4
FCTL4
0x01BE
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
Watchdog Timer control
WDTCTL
0x0120
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Table 14. Peripherals File Map (continued)
MODULE
USCI_A0/B0
USCI_A1/B1
Comparator_A+
26
REGISTER
SHORT FORM
ADDRESS
USCI_A0 auto baud rate control
UCA0ABCTL
0x005D
USCI_A0 transmit buffer
UCA0TXBUF
0x0067
USCI_A0 receive buffer
UCA0RXBUF
0x0066
USCI_A0 status
UCA0STAT
0x0065
USCI_A0 modulation control
UCA0MCTL
0x0064
USCI_A0 baud rate control 1
UCA0BR1
0x0063
USCI_A0 baud rate control 0
UCA0BR0
0x0062
USCI_A0 control 1
UCA0CTL1
0x0061
USCI_A0 control 0
UCA0CTL0
0x0060
USCI_A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI_A0 IrDA transmit control
UCA0IRTCLT
0x005E
USCI_B0 transmit buffer
UCB0TXBUF
0x006F
USCI_B0 receive buffer
UCB0RXBUF
0x006E
USCI_B0 status
UCB0STAT
0x006D
USCI_B0 I2C Interrupt enable
UCB0CIE
0x006C
USCI_B0 baud rate control 1
UCB0BR1
0x006B
USCI_B0 baud rate control 0
UCB0BR0
0x006A
USCI_B0 control 1
UCB0CTL1
0x0069
USCI_B0 control 0
UCB0CTL0
0x0068
USCI_B0 I2C slave address
UCB0SA
0x011A
USCI_B0 I2C own address
UCB0OA
0x0118
USCI_A1 auto baud rate control
UCA1ABCTL
0x00CD
USCI_A1 transmit buffer
UCA1TXBUF
0x00D7
USCI_A1 receive buffer
UCA1RXBUF
0x00D6
USCI_A1 status
UCA1STAT
0x00D5
USCI_A1 modulation control
UCA1MCTL
0x00D4
USCI_A1 baud rate control 1
UCA1BR1
0x00D3
USCI_A1 baud rate control 0
UCA1BR0
0x00D2
USCI_A1 control 1
UCA1CTL1
0x00D1
USCI_A1 control 0
UCA1CTL0
0x00D0
USCI_A1 IrDA receive control
UCA1IRRCTL
0x00CF
USCI_A1 IrDA transmit control
UCA1IRTCLT
0x00CE
USCI_B1 transmit buffer
UCB1TXBUF
0x00DF
USCI_B1 receive buffer
UCB1RXBUF
0x00DE
USCI_B1 status
UCB1STAT
0x00DD
USCI_B1 I2C Interrupt enable
UCB1CIE
0x00DC
USCI_B1 baud rate control 1
UCB1BR1
0x00DB
USCI_B1 baud rate control 0
UCB1BR0
0x00DA
USCI_B1 control 1
UCB1CTL1
0x00D9
USCI_B1 control 0
UCB1CTL0
0x00D8
USCI_B1 I2C slave address
UCB1SA
0x017E
USCI_B1 I2C own address
UCB1OA
0x017C
USCI_A1/B1 interrupt enable
UC1IE
0x0006
USCI_A1/B1 interrupt flag
UC1IFG
0x0007
Comparator_A port disable
CAPD
0x005B
Comparator_A control2
CACTL2
0x005A
Comparator_A control1
CACTL1
0x0059
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Table 14. Peripherals File Map (continued)
MODULE
Basic Clock
REGISTER
SHORT FORM
ADDRESS
Basic clock system control 3
BCSCTL3
0x0053
Basic clock system control 2
BCSCTL2
0x0058
Basic clock system control 1
BCSCTL1
0x0057
DCO clock frequency control
DCOCTL
0x0056
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
0x0055
Port PA (2)
Port PA resistor enable
PAREN
0x0014
Port PA selection
PASEL
0x003E
Port PA direction
PADIR
0x003C
Port PA output
PAOUT
0x003A
Port PA input
PAIN
0x0038
Port P8 resistor enable
P8REN
0x0015
Port P8 selection
P8SEL
0x003F
Port P8 direction
P8DIR
0x003D
Port P8 output
P8OUT
0x003B
Port P8 input
P8IN
0x0039
Port P7 resistor enable
P7REN
0x0014
Port P7 selection
P7SEL
0x003E
Port P7 direction
P7DIR
0x003C
Port P7 output
P7OUT
0x003A
Port P7 input
P7IN
0x0038
Port P6 resistor enable
P6REN
0x0013
Port P6 selection
P6SEL
0x0037
Port P6 direction
P6DIR
0x0036
Port P6 output
P6OUT
0x0035
Port P6 input
P6IN
0x0034
Port P5 resistor enable
P5REN
0x0012
Port P5 selection
P5SEL
0x0033
Port P5 direction
P5DIR
0x0032
Port P5 output
P5OUT
0x0031
Port P5 input
P5IN
0x0030
Port P4 selection
P4SEL
0x001F
Port P4 resistor enable
P4REN
0x0011
Port P4 direction
P4DIR
0x001E
Port P4 output
P4OUT
0x001D
Port P4 input
P4IN
0x001C
Port P3 resistor enable
P3REN
0x0010
Port P3 selection
P3SEL
0x001B
Port P3 direction
P3DIR
0x001A
Port P3 output
P3OUT
0x0019
Port P3 input
P3IN
0x0018
Port P8 (2)
Port P7 (3)
Port P6
Port P5
Port P4
Port P3
(2)
(3)
80-pin PN and 113-pin ZQW devices only
80-pin PN and 113-pin ZQW devices only
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Table 14. Peripherals File Map (continued)
MODULE
Port P2
REGISTER
SHORT FORM
ADDRESS
Port P2 resistor enable
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
Port P2 interrupt enable
P2IE
0x002D
Port P2 interrupt-edge select
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P2 input
P2IN
0x0028
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
Port P1 interrupt enable
P1IE
0x0025
Port P1 interrupt-edge select
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
P1OUT
0x0021
Port P1 input
P1IN
0x0020
Special Functions SFR interrupt flag 2
IFG2
0x0003
SFR interrupt flag 1
IFG1
0x0002
SFR interrupt enable 2
IE2
0x0001
SFR interrupt enable 1
IE1
0x0000
Port P1
28
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
Voltage applied to any pin (2)
-0.3 V to VCC + 0.3 V
Diode current at any device terminal
Storage temperature (3)
Tstg
(1)
±2 mA
Unprogrammed device
-55°C to 150°C
Programmed device
-55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions
VCC
Supply voltage (AVCC = DVCC = VCC (1))
VSS
Supply voltage (AVSS = DVSS = VSS)
TA
Operating free-air temperature
Processor frequency (maximum MCLK frequency) (2) (3)
fSYSTEM
(1)
(2)
(3)
MIN
MAX
During program execution
1.8
3.6
During flash program/erase
2.2
3.6
0
0
I version
-40
85
T version
-40
105
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
4.15
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
dc
16
UNIT
V
V
°C
MHz
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power-up.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
Note:
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
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MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,100kHz
30
Active mode (AM)
current (1 MHz)
Active mode (AM)
current (4 kHz)
IAM,4kHz
(1)
(2)
Active mode (AM)
current (1 MHz)
Active mode (AM)
current (100 kHz)
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
365
395
375
420
515
560
525
595
330
370
340
390
460
495
470
520
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
-40°C to 85°C
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
-40°C to 85°C
fMCLK = fSMCLK = fACLK = 32768 Hz/8
= 4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1,
SCG1 = 0, OSCOFF = 0
-40°C to 85°C
2.2 V
2.1
9
105°C
2.2 V
15
31
-40°C to 85°C
3V
3
11
105°C
3V
19
32
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
-40°C to 85°C
2.2 V
67
86
105°C
2.2 V
80
99
-40°C to 85°C
3V
84
107
105°C
3V
99
128
105°C
2.2 V
-40°C to 85°C
3V
105°C
105°C
2.2 V
-40°C to 85°C
3V
105°C
UNIT
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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Typical Characteristics - Active Mode Supply Current (Into VCC)
ACTIVE MODE CURRENT
vs
SUPPLY VOLTAGE
(TA = 25°C)
ACTIVE MODE CURRENT
vs
DCO FREQUENCY
7.0
10.0
6.0
TA = 25 °C
8.0
Active Mode Current − mA
Active Mode Current − mA
TA = 85 °C
f DCO = 16 MHz
9.0
f DCO = 12 MHz
7.0
6.0
5.0
f DCO = 8 MHz
4.0
3.0
4.0
TA = 85 °C
3.0
TA = 25 °C
2.0
2.0
f DCO = 1 MHz
1.0
1.0
0.0
1.5
2.0
2.5
3.0
3.5
VCC − Supply Voltage − V
Figure 2.
Copyright © 2007–2011, Texas Instruments Incorporated
4.0
VCC = 3 V
5.0
0.0
0.0
VCC = 2.2 V
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3.
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MSP430F261x
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
ILPM0,100kHz
Low-power mode 0
(LPM0) current (3)
Low-power mode 0
(LPM0) current (3)
Low-power mode 2
(LPM2) current (4)
ILPM2
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (3)
TEST CONDITIONS
TA
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
-40°C to 85°C
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
-40°C to 85°C
fMCLK = fSMCLK = 0 MHz, fDCO = 1
MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
-40°C to 85°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
105°C
ILPM3,VLO
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
Low-power mode 4
(LPM4) current (5)
68
63
98
100
125
37
49
50
62
40
55
57
73
23
33
35
46
25
36
40
55
-40°C
0.8
1.2
25°C
1
1.3
4.6
7
3V
105°C
105°C
2.2 V
-40°C to 85°C
3V
105°C
105°C
2.2 V
-40°C to 85°C
105°C
85°C
3V
2.2 V
105°C
14
24
-40°C
0.9
1.3
1.1
1.5
5.5
8
105°C
17
30
-40°C
0.4
1
25°C
0.5
1
4.3
6.5
25°C
85°C
3V
2.2 V
105°C
14
24
-40°C
0.6
1.2
0.6
1.2
25°C
3V
5
7.5
105°C
16.5
29.5
-40°C
0.1
0.5
0.1
0.5
85°C
2.2 V
4
6
105°C
13
23
-40°C
0.2
0.5
0.2
0.5
4.7
7
14
24
25°C
3V
105°C
32
MAX
105
85°C
(1)
(2)
(3)
(4)
(5)
TYP
87
25°C
ILPM4
2.2 V
-40°C to 85°C
85°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
MIN
83
85°C
Low-power mode 3
(LPM3) current (4)
VCC
(2)
UNIT
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Typical Characteristics - LPM4 Current
ILPM4 − Low−power mode current − µA
LPM4 CURRENT
vs
TEMPERATURE
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
Vcc = 3.6 V
7.0
Vcc = 3.0 V
6.0
5.0
Vcc = 2.2 V
4.0
3.0
2.0
1.0
Vcc = 1.8 V
0.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − °C
Figure 4.
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MSP430F261x
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Schmitt-Trigger Inputs (Ports P1 Through P8, RST/NMI, JTAG, XIN, and XT2IN) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT-)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
TYP
MAX
0.45 VCC
0.75 VCC
2.2 V
1.00
1.65
3V
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1
3V
0.3
1
20
35
50
5
UNIT
V
V
V
kΩ
pF
XIN and XT2IN in bypass mode only
Inputs (Ports P1 and P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
VCC
MIN
Port P1, P2: P1.x to P2.x, External trigger pulse width to set
interrupt flag (1)
2.2 V/3 V
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int).
Leakage Current (Ports P1 Through P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
VCC
(1) (2)
MIN
2.2 V/3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Standard Inputs (RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX
VIL
Low-level input voltage
PARAMETER
2.2 V/3 V
VSS
VSS + 0.6
V
VIH
High-level input voltage
2.2 V/3 V
0.8 VCC
VCC
V
34
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TEST CONDITIONS
UNIT
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MSP430F241x
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Outputs (Ports P1 Through P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = -1.5 mA
VOH
(1)
(2)
MAX
VCC - 0.25
VCC
VCC - 0.6
VCC
I(OHmax) = -1.5 mA (1)
3V
VCC - 0.25
VCC
I(OHmax) = -6 mA (2)
3V
VCC - 0.6
VCC
2.2 V
VSS
VSS + 0.25
2.2 V
VSS
VSS + 0.6
I(OLmax) = 1.5 mA (1)
3V
VSS
VSS + 0.25
I(OLmax) = 6 mA (2)
3V
VSS
VSS + 0.6
(2)
(1)
I(OLmax) = 6 mA (2)
Low-level output voltage
TYP
2.2 V
I(OLmax) = 1.5 mA
VOL
MIN
2.2 V
I(OHmax) = -6 mA
High-level output voltage
VCC
(1)
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1 Through P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (1)
fPort°CLK
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF (2)
t(Xdc)
Duty cycle of output
frequency
TYP
MAX
2.2 V
dc
10
3V
dc
12
2.2 V
dc
12
3V
dc
16
30
50
70
P5.6/ACLK, CL = 20 pF, XT1 mode
40
50
60
P5.4/MCLK, CL = 20 pF, XT1 mode
40
60
50% 15 ns
50% +
15 ns
P5.4/MCLK, CL = 20 pF, DCO
P1.4/SMCLK, CL = 20 pF, DCO
(2)
MIN
P5.6/ACLK, CL = 20 pF, LF mode
P1.4/SMCLK, CL = 20 pF, XT2 mode
(1)
(2)
VCC
40
60
50% 15 ns
50% +
15 ns
UNIT
MHz
MHz
%
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P4.5
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P4.5
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
2.0
2.5
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3.0
3.5
0.0
VCC = 2.2 V
P4.5
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
1.5
Figure 6.
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 7.
36
1.0
Figure 5.
0.0
−25.0
0.0
0.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
−20.0
TA = 25°C
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2.5
VCC = 3 V
P4.5
−10.0
−20.0
−30.0
TA = 85°C
−40.0
−50.0
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 8.
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MSP430F241x
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POR/Brownout Reset (BOR) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 9
dVCC/dt ≤ 3 V/s
V(B_IT-)
See Figure 9 through Figure 11
dVCC/dt ≤ 3 V/s
Vhys(B_IT-)
See Figure 9
dVCC/dt ≤ 3 V/s
td(BOR)
See Figure 9
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(1)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT-)
70
2.2 V/3 V
130
UNIT
V
1.71
V
210
mV
2000
µs
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-)is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
38
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MSP430F241x
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Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 12)
TYP
5
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
SVSon, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0 (1)
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 12)
2000
150
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 12)
Vhys(SVS_IT-)
VCC/dt ≤ 3 V/s (see Figure 12), external voltage
applied on A7
V(SVS_IT-)
VCC/dt ≤ 3V/s (see Figure 12 and Figure 13)
VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13),
external voltage applied on A7
ICC(SVS)
(1)
(2)
(3)
(3)
VLD ≠ 0, VCC = 2.2 V/3 V
MAX
70
µs
300
µs
12
µs
1.55
1.7
V
120
155
mV
0.004 ×
V(SVS_IT-)
0.016 ×
V(SVS_IT-)
VLD = 15
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.60
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61 (2)
VLD = 13
3.24
3.5
3.76 (2)
VLD = 14
3.43
3.7 (2)
3.99 (2)
VLD = 15
1.1
1.2
1.3
10
15
VLD = 2 to 14
UNIT
V
mV
V
µA
tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD
value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
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Software sets VLD >0:
SVS is active
AVCC
V(SVS_IT−)
V(SVSstart)
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
Brownout
Region
Brownout
Region
Brownout
1
0
SVS out
t d(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to V CC < V( B_IT−)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)
VCC(min) − V
1.5
Triangular Drop
1
1 ns
1 ns
VCC
0.5
t pw
3V
0
1
10
100
1000
t pw − Pulse Width − µs
VCC(min)
t f = tr
tf
tr
t − Pulse Width − µs
Figure 13. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
40
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MSP430F241x
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
UNIT
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
ratio
Duty cycle
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
-1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
MAX
UNIT
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
42
TA
VCC
1-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±0.5
+2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
12-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
16-MHz tolerance over
temperature
0°C to 85°C
3V
-3
±2.0
+3
%
2.2 V
0.970
1
1.030
3V
0.975
1
1.025
3.6 V
0.970
1
1.030
2.2 V
7.760
8
8.40
3V
7.800
8
8.20
3.6 V
7.600
8
8.24
2.2 V
11.64
12
12.36
3V
11.64
12
12.36
3.6 V
11.64
12
12.36
3V
15.52
16
16.48
3.6 V
15.00
16
16.48
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
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MIN
TYP
MHz
MHz
MHz
MHz
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Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
-3
±2
+3
%
1.8 V to 3.6 V
-3
±2
+3
%
25°C
2.2 V to 3.6 V
-3
±2
+3
%
25°C
3 V to 3.6 V
-6
±2
+3
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
MIN
TYP
MAX
UNIT
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz tolerance
overall
-40°C to 105°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz tolerance
overall
-40°C to 105°C
3 V to 3.6 V
-6
±3
+6
%
fCAL(1MHz)
1-MHz calibration
value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
8-MHz calibration
value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
12-MHz calibration
value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
-40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
16-MHz calibration
value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
-40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
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Typical Characteristics - Calibrated DCO Frequency
CALIBRATED 1-MHz FREQUENCY
vs
SUPPLY VOLTAGE
CALIBRATED 8-MHz FREQUENCY
vs
SUPPLY VOLTAGE
1.02
8.20
TA = 105 °C
8.15
8.10
Frequency − MHz
Frequency − MHz
1.01
TA = 105 °C
1.00
TA = 85 °C
TA = 25 °C
0.99
8.00
TA = 85 °C
TA = 25 °C
7.95
TA = −40 °C
7.90
7.85
TA = −40 °C
0.98
1.5
8.05
2.0
2.5
3.0
3.5
7.80
1.5
4.0
2.0
VCC − Supply Voltage − V
2.5
Figure 15.
CALIBRATED 12-MHz FREQUENCY
vs
SUPPLY VOLTAGE
CALIBRATED 16-MHz FREQUENCY
vs
SUPPLY VOLTAGE
16.0
TA = −40 °C
TA = −40 °C
Frequency − MHz
Frequency − MHz
4.0
16.1
12.1
TA = 25 °C
12.0
TA = 85 °C
11.9
TA = 105 °C
11.8
2.0
2.5
3.0
VCC − Supply Voltage − V
Figure 16.
44
3.5
Figure 14.
12.2
11.7
1.5
3.0
VCC − Supply Voltage − V
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3.5
15.9
TA = 25 °C
TA = 85 °C
15.8
TA = 105 °C
15.7
4.0
15.6
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 17.
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MSP430F241x
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Wake-Up From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
2.2 V/3 V
(1)
(2)
1.5
µs
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
UNIT
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
DCO clock wake-up time
from LPM3/4 (1)
MAX
1
3V
CPU wake-up time from
LPM3/4 (2)
1
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
DCO WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake Time − µs
10.00
RSELx = 12 to 15
1.00
RSELx = 0 to 11
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 18.
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DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
DT
Temperature drift
DV
Drift with VCC
(1)
VCC
TYP
UNIT
2.2 V
1.8
3V
1.95
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
10.00
RSELx = 4
1.00
0.10
0.01
10.00
100.00
1000.00
ROSC − External Resistor − kW
Figure 19.
46
DCO Frequency − MHz
DCO Frequency − MHz
10.00
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10000.00
RSELx = 4
1.00
0.10
0.01
10.00
100.00
1000.00
10000.00
ROSC − External Resistor − kW
Figure 20.
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MSP430F241x
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Typical Characteristics - DCO With External Resistor ROSC (continued)
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.50
2.50
2.25
ROSC = 100k
DCO Frequency − MHz
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
0.50
ROSC = 1M
0.25
0.00
−50.0
DCO Frequency − MHz
2.25
−25.0
0.0
25.0
50.0
TA − Temperature − °C
Figure 21.
Copyright © 2007–2011, Texas Instruments Incorporated
75.0
ROSC = 1M
0.25
100.0
0.00
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 22.
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Crystal Oscillator LFXT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, LFXT1Sx = 3, XCAPx = 0
LF mode
OALF
Oscillation allowance for
LF crystals
Integrated effective load
capacitance, LF mode (2)
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V/3 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, LFXT1Sx = 3, XCAPx = 0 (4)
2.2 V/3 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift (1)
dfVLO/dVCC
VLO frequency supply voltage drift (2)
(1)
(2)
48
TA
-40°C to 85°C
105°C
VCC
MIN
TYP
MAX
4
12
20
2.2 V/3 V
2.2 V/3 V
25°C
1.8 V to 3.6 V
22
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I: (MAX(-40 to 85°C) - MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C - (-40°C))
T: (MAX(-40 to 105°C) - MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C - (-40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V)
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
VCC
MIN
XTS = 1, LFXT1Sx = 0, XCAPx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1, XCAPx = 0
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2, XCAPx = 0
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF1
fLFXT1,HF2
TEST CONDITIONS
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level
square-wave input
frequency, HF mode
Oscillation allowance for HF
crystals (see Figure 23 and
Figure 24)
Integrated effective load
capacitance, HF mode (2)
(1)
(2)
(3)
(4)
(5)
Oscillator fault frequency
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
2700
XTS = 1, XCAPx = 0, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz, CL,eff = 15 pF
800
XTS = 1, XCAPx = 0, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz, CL,eff = 15 pF
300
XTS = 1, XCAPx = 0 (3)
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
Duty cycle, HF mode
fFault,HF
XTS = 1, LFXT1Sx = 3, XCAPx = 0
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
(4)
TYP
XTS = 1, LFXT1Sx = 3, XCAPx = 0 (5)
50
pF
60
2.2 V/3 V
%
40
2.2 V/3 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
Oscillation Allowance − W
100000.00
10000.00
1000.00
LFXT1Sx = 2
100.00
LFXT1Sx =0
10.00
0.10
1.00
LFXT1Sx = 1
10.00
100.00
Crystal Frequency − MHz
Figure 23.
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
1500
1400
XT Oscillator Supply Current − µA
1300
LFXT1Sx = 2
1200
1100
1000
900
800
700
600
500
400
300
LFXT1Sx = 1
200
100
LFXT1Sx = 0
0
0
4
8
12
16
20
Crystal Frequency − MHz
Figure 24.
50
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Crystal Oscillator XT2 (1)
PARAMETER
VCC
MIN
XT2Sx = 0
1.8 V to 3.6 V
XT2 oscillator crystal frequency,
mode 1
XT2Sx = 1
XT2 oscillator crystal frequency,
mode 2
XT2Sx = 2
fXT2
XT2 oscillator crystal frequency,
mode 0
fXT2
fXT2
TEST CONDITIONS
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 2.2 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
XT2 oscillator logic-level square-wave
XT2Sx = 3
input frequency
fXT2
Oscillation allowance (see Figure 25
and Figure 26)
OA
CL,eff
Integrated effective load capacitance,
HF mode (2)
Duty cycle
fFault
(1)
(2)
(3)
(4)
(5)
Oscillator fault frequency, HF mode (4)
TYP
2
16
1.8 V to 2.2 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XT2Sx = 0, fXT2 = 1 MHz,
CL,eff = 15 pF
2700
XT2Sx = 1, fXT2 = 4 MHz,
CL,eff = 15 pF
800
XT2Sx = 2, fXT2 = 16 MHz,
CL,eff = 15 pF
300
See
(3)
Measured at P1.4/SMCLK,
fXT2 = 10 MHz
Measured at P1.4/SMCLK,
fXT2 = 16 MHz
XT2Sx = 3 (5)
MHz
Ω
1
pF
40
50
60
40
50
60
2.2 V/3 V
2.2 V/3 V
MHz
%
30
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - XT2 Oscillator
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
Oscillation Allowance − W
100000.00
10000.00
1000.00
XT2Sx = 2
100.00
XT2Sx = 1
XT2Sx = 0
10.00
0.10
1.00
10.00
100.00
Crystal Frequency − MHz
Figure 25.
XT Oscillator Supply Current − µA
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
1600
1500
1400
1300
1200
1100
1000
900
XT2Sx = 2
800
700
600
500
400
300
200
100
0
XT2Sx = 1
XT2Sx = 0
0
4
8
12
16
20
Crystal Frequency − MHz
Figure 26.
52
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1, TA2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer_B capture timing
TB0, TB1, TB2
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VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
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UNIT
MHz
ns
53
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud) (1)
tτ
UART receive deglitch time (2)
(1)
(2)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V/3 V
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
600
3V
50
100
600
MIN
MAX
UNIT
fSYSTEM
MHz
ns
The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI Master Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 27 and Figure 28)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
TEST CONDITIONS
VCC
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid, CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 29 and Figure 30)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
tSTE,LEAD
STE lead time, STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
54
UCLK edge to SOMI valid,
CL = 20 pF
50
UNIT
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
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1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 27. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 28. SPI Master Mode, CKPH = 1
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 29. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 30. SPI Slave Mode, CKPH = 1
56
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 31)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V/3 V
0
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V/3 V
4
µs
tSP
Pulse width of spikes suppressed by input filter
2.2 V
50
150
600
3V
50
100
600
2.2 V/3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2.2 V/3 V
2.2 V/3 V
0
4
µs
0.6
4.7
µs
0.6
ns
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 31. I2C Mode Timing
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Comparator_A+ (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at P2 3/CA0/TA1 and P2.4/CA1/TA2
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
UNIT
µA
µA
VIC
Common-mode input
voltage range
CAON = 1
2.2 V/3 V
0
V(Ref025)
(Voltage at 0.25 VCC
node) ÷ VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P2 3/CA0/TA1 and P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
V(Ref050)
(Voltage at 0.5 VCC node) PCA0 = 1, CARSEL = 1, CAREF = 2,
÷ VCC
No load at P2 3/CA0/TA1 and P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
See Figure 35 and
Figure 36
2.2 V
390
480
540
V(RefVT)
3V
400
490
550
V(offset)
Offset voltage (2)
2.2 V/3 V
-30
30
mV
Vhys
Input hysteresis
2.2 V/3 V
0
0.7
1.4
mV
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
2.2 V
80
165
300
t(response)
Response time, low to
high and high to low (3)
(see Figure 32 and
Figure 33)
3V
70
120
240
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
(1)
(2)
(3)
58
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P2 3/CA0/TA1 and P2.4/CA1/TA2,
TA = 85°C
CAON = 1
VCC - 1
V
mV
ns
µs
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step and with Comparator_A+ already enabled
(CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
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0V
VCC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V−
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 32. Comparator_A+ Module Block Diagram
VCAOUT
Overdrive
V−
400 mV
t (response)
V+
Figure 33. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
−
Comparator_A+
CASHORT = 1
IOUT = 10µA
Figure 34. Comparator_A+ Short Resistance Test Condition
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Typical Characteristics, Comparator_A+
V(RefVT)
vs
TEMPERATURE
(VCC = 3 V)
V(RefVT)
vs
TEMPERATURE
(VCC = 2.2 V)
650
650
VCC = 2.2 V
600
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
TA − Free-Air Temperature − °C
−5
15
35
55
75
95
TA − Free-Air Temperature − °C
Figure 35.
Figure 36.
SHORT RESISTANCE
vs
VIN/VCC
Short Resistance − kW
100.00
VCC = 1.8V
VCC = 2.2V
10.00
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 37.
60
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12-Bit ADC Power Supply and Input Range Conditions
(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
AVCC
Analog supply voltage
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range (2)
All P6.0/A0 to P6.7/A7 terminals, Analog inputs
selected in ADC12MCTLx register,
P6Sel.x = 1, 0 ≤ × ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal (3)
fADC12CLK = 5 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
IREF+
Operating supply current
into AVCC terminal (4)
CI
Input capacitance
Input MUX ON resistance
RI
(1)
(2)
(3)
(4)
(5)
(5)
(5)
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 1
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 0
Only one terminal can be selected at one time,
P6.x/Ax
0 V ≤ VAx ≤ VAVCC
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
0.8
3V
0.8
1
3V
0.5
0.7
2.2 V
0.5
0.7
3V
0.5
0.7
2.2 V
3V
mA
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables settling of the built-in reference before starting an A/D conversion.
Not production tested, limits verified by design.
12-Bit ADC External Reference
(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
(2)
VeREF+
Positive external reference voltage input
VeREF+ > VREF-/VeREF-
VREF-/VeREF-
Negative external reference voltage input
VeREF+ > VREF-/VeREF- (3)
MIN
MAX
1.4 VAVCC
0
UNIT
V
1.2
V
1.4 VAVCC
V
(VeREF+ - VREF/VeREF-)
Differential external reference voltage input
VeREF+ > VREF-/VeREF-
IVeREF+
Static leakage current
0 V ≤ VeREF+ ≤ VAVCC
2.2 V/3 V
±1
µA
IVREF-/VeREF-
Static leakage current
0 V ≤ VeREF-≤ VAVCC
2.2 V/3 V
±1
µA
(1)
(2)
(3)
(4)
(4)
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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12-Bit ADC Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive built-in
reference voltage
output
VREF+
AVCC(min)
AVCC minimum
voltage, positive
built-in reference
active
TA
REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
-40°C to 85°C
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
-40°C to 85°C
105°C
105°C
Load-current
regulation, VREF+
terminal (1)
IL(VREF)+
3V
2.2 V/3 V
2.4
2.5
2.6
2.5
2.64
1.44
1.5
1.56
1.42
1.5
1.57
2.8
REF2_5V = 1,
-1 mA ≤ IVREF+ ≤ IVREF+min
2.9
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
MAX
2.37
REF2_5V = 1,
-0.5 mA ≤ IVREF+ ≤ IVREF+min
UNIT
V
V
2.2 V
0.01
-0.5
3V
0.01
-1
mA
2.2 V
±2
3V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
3V
±2
LSB
3V
20
ns
Load current
regulation, VREF+
terminal (2)
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at pin
VREF+ (3)
REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V/3 V
TREF+
Temperature
coefficient of built-in
reference (2)
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
tREFON
Settle time of
internal reference
voltage (see
Figure 38 ) (4) (2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
2.2 V
(4)
NOM
2.2
IDL(VREF) +
(1)
(2)
(3)
MIN
REF2_5V = 0,
IVREF+max ≤ IVREF+ ≤ IVREF+min
Load current out of
VREF+terminal
IVREF+
VCC
5
10
LSB
µF
±100
17
ppm/°C
ms
Not production tested, limits characterized.
Not production tested, limits verified by design.
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS: 10 µF tantalum and 100 nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
t REFON ≈ .66 x CVREF+ [ms] with C VREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
t REFON
Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
62
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From
Power
Supply
DVCC
+
−
DVSS
10 µ F
100 nF
AVCC
+
−
AVSS
10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
Apply
External
Reference
100 nF
VREF+ or V eREF+
+
−
10 µ F
100 nF
VREF−/VeREF−
+
−
10 µ F
MSP430F261x
MSP430F241x
100 nF
Figure 39. Supply Voltage and Reference Voltage Design VREF-/VeREF- External Supply
From
Power
Supply
DVCC
+
−
DVSS
10 µ F
100 nF
AVCC
+
−
AVSS
10 µ F
Apply External Reference [V eREF+]
or Use Internal Reference [V REF+]
100 nF
VREF+ or V eREF+
+
−
10 µ F
Reference Is Internally
Switched to A VSS
MSP430F261x
MSP430F241x
100 nF
VREF−/VeREF−
Figure 40. Supply Voltage and Reference Voltage Design VREF-/VeREF-= AVSS, Internally Connected
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12-Bit ADC Timing Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
tCONVERT
Internal ADC12 oscillator
Conversion time
tADC12ON
Turn-on settling time of the
ADC (1)
tSample
Sampling time
(1)
(2)
(3)
(1)
VCC
MIN
For specified performance of ADC12
linearity parameters
2.2 V/3 V
0.45
5
6.3 MHz
ADC12DIV = 0,
fADC12CLK = fADC12OSC
2.2 V/3 V
3.7
5
6.3 MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V/3 V
2.06
3.51
13 ×
ADC12DIV ×
1/fADC12CLK
External fADC12CLK from ACLK, MCLK,
or SMCLK, ADC12SSEL ≠ 0
See
TYP MAX UNIT
(2)
µs
100
RS = 400 Ω,RI = 1000 Ω, CI = 30 pF,
τ = [RS +RI] × CI (3)
3V
1220
2.2 V
1400
µs
ns
ns
Limits verified by design
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC Linearity Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ - VREF-/VeREF-) min ≤ 1.6 V
VCC
EI
Integral linearity
error
ED
Differential linearity (VeREF+ - VREF-/VeREF-) min ≤ (VeREF+ - VREF-/VeREF-),
error
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
EO
Offset error
(VeREF+ - VREF-/VeREF-) min ≤ (VeREF+ - VREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
EG
Gain error
(VeREF+ - VREF-/VeREF-) min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted
error
(VeREF+ - VREF-/VeREF-) min ≤ (VeREF+ -VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
64
1.6 V < (VeREF+ - VREF-/VeREF-) min ≤ VAVCC
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MIN
TYP
MAX
±2
2.2 V/3 V
±1.7
UNIT
LSB
±1
LSB
±2
±4
LSB
2.2 V/3 V
±1.1
±2
LSB
2.2 V/3 V
±2
±5
LSB
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
12-Bit ADC Temperature Sensor and Built-In VMID
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Operating supply
current into AVCC
terminal (1)
ISENSOR
VSENSOR
(2) (3)
TCSENSOR
REFON = 0, INCH = 0Ah,
ADC12ON = 1, TA = 25°C
ADC12ON = 1, INCH = 0Ah, TA = 0°C
(3)
tSENSOR(sample)
VCC
ADC12ON = 1, INCH = 0Ah
(3)
Sample time
required if channel
10 is selected (4)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
MIN
TYP
MAX
2.2 V
40
120
3V
60
160
2.2 V
986
3V
986
2.2 V
3.55
3V
3.55
2.2 V
30
3V
30
mV/°C
µs
Current into divider
ADC12ON = 1, INCH = 0Bh
at channel 11 (5)
2.2 V
NA (5)
3V
NA (5)
VMID
AVCC divider at
channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2.2 V
1.1
1.1 ± 0.04
3V
1.5
1.5 ± 0.04
tVMID(sample)
Sample time
required if channel
11 is selected (6)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
(1)
(2)
(3)
(4)
(5)
(6)
1400
3V
1220
µA
mV
IVMID
2.2 V
UNIT
µA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). Therefore it includes the constant current through the sensor and the reference.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended to minimize the offset error of the
built-in temperature sensor.
Limits characterized
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample), no additional on time is needed.
12-Bit DAC Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Supply current, single
DAC channel (1) (2)
IDD
PSRR
(1)
(2)
(3)
(4)
Analog supply voltage
Power-supply rejection
ratio (3) (4)
TEST CONDITIONS
VCC
TA
MIN
AVCC = DVCC, AVSS = DVSS = 0 V
TYP
2.2
MAX
3.6
-40°C to 85°C
50
110
105°C
69
150
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0x0800
2.2 V/3 V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2 V/3 V
50
130
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+= AVCC
2.2 V/3 V
200
440
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2 V/3 V
700
1500
2.2 V
70
3V
70
DAC12_xDAT = 800h, VREF = 1.5 V,
ΔAVCC = 100 mV
DAC12_xDAT = 800h,
VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
UNIT
V
µA
dB
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.
PSRR = 20 × log(ΔAVCC/ΔVDAC12_xOUT)
VREF is applied externally. The internal reference is not used.
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12-Bit DAC Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Resolution
12-bit monotonic
Integral nonlinearity (1)
INL
DNL
VCC
Differential nonlinearity
(1)
Offset voltage without
calibration (1) (2)
EO
Offset voltage with
calibration (1) (2)
dE(O)/dT
Offset error temperature
coefficient (3)
EG
Gain error (3)
dE(G)/dT
Gain temperature coefficient (3)
tOffset_Cal
Time for offset calibration (4)
MIN
TYP
12
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±2.0
(4)
±8.0
LSB
±0.4
±1.0
LSB
±21
mV
±2.5
2.2 V/3 V
VREF = 1.5 V
2.2 V
VREF = 2.5 V
3V
30
µV/C
±3.50
10
2.2 V/3 V
% FSR
ppm of
FSR/°C
100
DAC12AMPx = 3, 5
2.2 V/3 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
UNIT
bits
DAC12AMPx = 2
(1)
MAX
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx=
{0, 1}. The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect accuracy and is
not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
Ideal transfer
function
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
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Typical Characteristics - 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
INL − Integral Nonlinearity Error − LSB
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
2560
3072
3584
4095
DAC12_xDAT − Digital Code
Figure 42.
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL − Differential Nonlinearity Error − LSB
2.0
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
DAC12_xDAT − Digital Code
Figure 43.
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12-Bit DAC Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Output voltage range (1)
(see Figure 44)
VO
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Maximum DAC12 load
capacitance
IL(DAC12)
Maximum DAC12 load
current
0
0.005
AVCC 0.05
AVCC
0
0.1
AVCC 0.13
AVCC
2.2 V/3 V
2.2 V
3V
Output resistance (see
Figure 44)
RLoad = 3 kΩ, VO/P(DAC12) = AVCC,
DAC12AMPx = 7,
DAC12_xDAT = 0FFFh
100
-0.5
0.5
-1
1
2.2 V/3 V
RLoad = 3 kΩ,
0.3 V < VO/P(DAC12) < AVCC - 0.3 V,
DAC12AMPx = 7
(1)
UNIT
V
RLoad = 3 kΩ, VO/P(DAC12) = 0 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RO/P(DAC12)
MAX
2.2 V/3 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
TYP
150
250
150
250
1
4
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC −0.3V
VOUT
AV CC
Figure 44. DAC12_x Output Resistance Tests
12-Bit DAC Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Reference input
voltage range
VeREF+
TEST CONDITIONS
DAC12IR = 0 (1) (2)
DAC12IR = 1 (3) (4)
VCC
2.2 V/3 V
DAC12_0 IR = DAC12_1 IR = 0
Ri(VREF+),
Ri(VeREF+)
Reference input
resistance
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx (5)
(1)
(2)
(3)
(4)
(5)
68
TYP
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
20
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
MIN
2.2 V/3 V
UNIT
V
MΩ
40
48
56
20
24
28
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
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12-Bit DAC Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 45 and Figure 46), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
tON
DAC12 on-time
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1) (see
Figure 45)
VCC
MIN
DAC12AMPx = 0 → {5, 6}
Settling time,
full scale
DAC12_xDAT =
80h → F7Fh → 80h
MAX
60
120
15
30
6
12
100
200
40
80
15
30
2.2 V/3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
TYP
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 3, 5
2.2 V/3 V
DAC12AMPx = 4, 6, 7
tS(C-C)
Settling time,
code to code
DAC12AMPx = 2
DAC12_xDAT =
3F8h → 408h → 3F8h
BF8h → C08h → BF8h
Slew rate (2)
DAC12AMPx = 3, 5
2.2 V/3 V
2
DAC12AMPx = 4, 6, 7
DAC12_xDAT =
80h → F7Fh → 80h
DAC12AMPx = 3, 5
2.2 V/3 V
0.05
0.12
0.35
0.7
1.5
DAC12AMPx = 2
DAC12_xDAT =
80h → F7Fh → 80h
BW-3dB
Channel-tochannel
crosstalk (1) (see
Figure 48)
(1)
(2)
µs
V/µs
2.7
600
DAC12AMPx = 3, 5
2.2 V/3 V
150
DAC12AMPx = 4, 6, 7
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 47)
µs
1
DAC12AMPx = 4, 6, 7
Glitch energy,
full scale
µs
5
DAC12AMPx = 2
SR
UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
40
2.2 V/3 V
DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz, Duty cycle = 50%
nV-s
30
180
kHz
550
-80
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load, fDAC12_0OUT = 10 kHz,
Duty cycle = 50%
2.2 V/3 V
dB
-80
RLoad and CLoad are connected to AVSS (not AVCC/2) in Figure 45.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kΩ
Glitch
Energy
Conversion 2
Conversion 3
+/− 1/2 LSB
AV CC
2
RO/P(DAC12.x)
+/− 1/2 LSB
CLoad = 100pF
tsettleLH
tsettleHL
Figure 45. Settling Time and Glitch Energy Testing
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Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 46. Slew Rate Testing
ILoad
Ve REF+
RLoad = 3 kΩ
AV CC
DAC12_x
2
DACx
AC
CLoad = 100pF
DC
Figure 47. Test Conditions for 3-dB Bandwidth Specification
ILoad
RLoad
AV CC
DAC12_0
2
DAC0
DAC12_xDAT 080h
7F7h
080h
7F7h
080h
V OUT
CLoad= 100pF
VREF+
ILoad
Ve
V DAC12_yOUT
RLoad
AV CC
DAC12_1
V DAC12_xOUT
2
DAC1
fToggle
CLoad= 100pF
Figure 48. Crosstalk Test Conditions
70
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
7
mA
10
ms
tCPT
Cumulative program time
(1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
20
ms
104
Program/erase endurance
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
Block program time for first byte or word
(2)
25
tFTG
Block program time for each additional
byte or word
(2)
18
tFTG
Block program end-sequence wait time
(2)
6
tFTG
Mass erase time
(2)
10593
tFTG
Segment erase time
(2)
4819
tFTG
0
tBlock, 1-63
tBlock,
End
tMass Erase
tSeg Erase
(1)
(2)
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTCK
TCK input frequency (1)
RInternal
Internal pullup resistance on TMS, TCK, and TDI/TCLK (2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
0
5
3V
0
10
2.2 V/3 V
25
60
90
MIN
MAX
UNIT
MHz
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TCK, and TDI/TCLK pullup resistors are implemented in all versions.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible, and JTAG is switched to bypass mode.
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APPLICATION INFORMATION
Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x
Interrupt
Edge Select
P1IES.x
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Table 15. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.0/TACLK/CAOUT
0
FUNCTION
P1.0 (I/O)
1
2
0
0
1
CAOUT
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI1A
0
1
Timer_A3.TA1
1
1
I: 0; O: 1
0
Timer_A3.CCI2A
0
1
Timer_A3.TA2
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
P1.3 (I/O)
P1.3/TA2
3
P1.4/SMCLK
4
P1.5/TA0
5
P1.6/TA1
P1.7/TA2
6
7
P1SEL.x
I: 0; O: 1
P1.2 (I/O)
P1.2/TA1
P1DIR.x
Timer_A3.TACLK
P1.1 (I/O)
P1.1/TA0
CONTROL BITS / SIGNALS
P1.4 (I/O)
SMCLK
P1.5 (I/O)
Timer_A3.TA0
P1.6 (I/O)
Timer_A3.TA1
P1.7 (I/O)
Timer_A3.TA2
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1
1
I: 0; O: 1
0
1
1
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Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Bus
Keeper
EN
P2SEL.x
P2IN.x
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
EN
D
Module X IN
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
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Interrupt
Edge
Select
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MSP430F241x
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Table 16. Port P2 (P2.0 to P2.4, P2.6, and P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0 (2)/CA6
P2.7/TA0/CA7
(1)
(2)
x
0
1
2
3
4
6
7
FUNCTION
CONTROL BITS / SIGNALS (1)
CAPD.x
P2DIR.x
P2SEL.x
P2.0 (I/O)
0
I: 0; O: 1
0
ACLK
0
1
1
CA2
1
X
X
P2.1 (I/O)
0
I: 0; O: 1
0
Timer_A3.INCLK
0
0
1
DVSS
0
1
1
CA3
1
X
X
P2.2 (I/O)
0
I: 0; O: 1
0
CAOUT
0
1
1
Timer_A3.CCI0B
0
0
1
CA4
1
X
X
P2.3 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA1
0
1
1
CA0
1
X
X
P2.4 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA2
0
1
X
CA1
1
X
1
P2.6 (I/O)
0
I: 0; O: 1
0
ADC12CLK
0
1
1
DMAE0
0
0
1
CA6
1
X
X
P2.7 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA0
0
1
1
CA7
1
X
X
X = Don't care
MSP430F261x devices only
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Port P2 (P2.5), Input/Output With Schmitt Trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2SEL.5
P2IES.5
Interrupt
Edge
Select
Table 17. Port P2 (P2.5) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.5 (I/O)
P2.5/ROSC/CA5
(1)
(2)
76
5
ROSC
(2)
CONTROL BITS / SIGNALS (1)
CAPD
DCOR
P2DIR.5
P2SEL.5
0
0
I: 0; O: 1
0
X
0
1
X
DVSS
0
0
1
1
CA5
1 or selected
0
X
X
X = Don't care
If ROSC is used, it is connected to an external resistor.
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Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
Module direction
P3OUT.x
Module X OUT
0
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
0
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Table 18. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0STE/
UCA0CLK
x
0
P3.1/UCB0SIMO/
UCB0SDA
1
P3.2/UCB0SOMI/
UCB0SCL
2
P3.3/UCB0CLK/
UCA0STE
3
P3.4/UCA0TXD/
UCA0SIMO
4
P3.5/UCA0RXD/
UCA0SOMI
5
P3.6/UCA1TXD/
UCA1SIMO
6
P3.7/UCA1RXD/
UCA1SOMI
7
(1)
(2)
(3)
(4)
(5)
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK (2) (3)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (4) (5)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (4) (5)
P3.3 (I/O)
UCB0CLK/UCA0STE
(4)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (4)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (4)
P3.6 (I/O)
UCA1TXD/UCA1SIMO (4)
P3.7 (I/O)
UCA1RXD/UCA1SOMI (4)
CONTROL BITS / SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Table 19. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TB0
0
1
2
0
0
1
Timer_B7.TB0
1
1
I: 0; O: 1
0
Timer_B7.CCI1A and Timer_B7.CCI1B
0
1
Timer_B7.TB1
1
1
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB2
1
1
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3
1
1
I: 0; O: 1
0
0
1
P4.3 (I/O)
P4.3/TB3
3
P4.4 (I/O)
P4.4/TB4
4
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
P4.5 (I/O)
P4.5/TB5
5
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5
P4.6 (I/O)
P4.6/TB6
6
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6
P4.7/TBCLK
(1)
78
7
P4SEL.x
I: 0; O: 1
P4.2 (I/O)
P4.2/TB2
P4DIR.x
Timer_B7.CCI0A and Timer_B7.CCI0B
P4.1 (I/O)
P4.1/TB1
CONTROL BITS / SIGNALS (1)
P4.7 (I/O)
Timer_B7.TBCLK
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
1
1
X = Don't care
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Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
Pad Logic
P5REN.x
P5DIR.x
0
Module
Direction
1
P5OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5SEL.x
P5IN.x
EN
Module X IN
D
Table 20. Port P5 (P5.0 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.0/UCB1STE/
UCA1CLK
x
0
P5.1/UCB1SIMO/
UCB1SDA
1
P5.2/UCB1SOMI/
UCB1SCL
2
P5.3/UCB1CLK/
UCA1STE
3
P5.4/MCLK
4
P5.5/SMCLK
5
P5.6/ACLK
6
P5.7/TBOUTH/SVSOUT
7
(1)
(2)
(3)
(4)
FUNCTION
P5.0 (I/O)
UCB1STE/UCA1CLK (2) (3)
P5.1 (I/O)
UCB1SIMO/UCB1SDA (2) (4)
P5.2 (I/O)
UCB1SOMI/UCB1SCL (2) (4)
P5.3 (I/O)
UCB1CLK/UCA1STE
(2)
CONTROL BITS / SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
P5.7 (I/O)
I: 0; O: 1
0
TBOUTH
0
1
SVSOUT
1
1
P5.0 (I/O)
MCLK
P5.1 (I/O)
SMCLK
P5.2 (I/O)
ACLK
X = Don't care
The pin direction is controlled by the USCI module.
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI_A1/B1 will be
forced to 3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
Pad Logic
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Table 21. Port P6 (P6.0 to P6.4) Pin Functions
PIN NAME (P6.x)
x
P6.0/A0
0
P6.1/A1
1
P6.2/A2
2
P6.3/A3
3
P6.4/A4
(1)
(2)
80
4
FUNCTION
P6.0 (I/O)
A0 (2)
P6.1 (I/O)
A1 (2)
P6.2 (I/O)
A2 (2)
P6.3 (I/O)
A3
(2)
P6.4 (I/O)
A4 (2)
CONTROL BITS / SIGNALS (1)
P6DIR.x
P6SEL.x
INCH.x
I: 0; O: 1
0
0
X
1
1 (y = 0)
I: 0; O: 1
0
0
X
1
1 (y = 1)
I: 0; O: 1
0
0
X
1
1 (y = 2)
I: 0; O: 1
0
0
1 (y = 3)
X
1
I: 0; O: 1
0
0
X
1
1 (y = 4)
X = Don't care
The ADC12 channel Ax is connected to AVSS internally if not selected.
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MSP430F241x
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SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Table 22. Port P6 (P6.5 and P6.6) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.5 (I/O)
P6.5/A5/DAC1 (2)
5
CONTROL BITS / SIGNALS (1)
P6DIR.x
P6SEL.x
DAC12AMP > 0
INCH.y
0
I: 0; O: 1
0
0
DVSS
1
1
0
0
A5 (3)
X
X
0
1 (y = 5)
DAC1 (DAC12OPS = 1) (4)
X
X
1
0
I: 0; O: 1
0
0
0
DVSS
1
1
0
0
(6)
X
X
0
1 (y = 6)
X
X
1
0
P6.6 (I/O)
P6.6/A6/DAC0 (5)
6
A6
DAC0 (DAC12OPS = 0) (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
X = Don't care
MSP430F261x devices only
The ADC12 channel Ax is connected to AVSS internally if not selected.
The DAC outputs are floating if not selected.
MSP430F261x devices only
The ADC12 channel Ax is connected to AVSS internally if not selected.
The DAC outputs are floating if not selected.
Copyright © 2007–2011, Texas Instruments Incorporated
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MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
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Port P6 (P6.7), Input/Output With Schmitt Trigger
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
P6DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.7
DVSS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
Module X IN
D
Table 23. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
INCH.y
DAC12AMP>0
I: 0; O: 1
0
0
0
DVSS
1
1
0
0
(3)
P6.7 (I/O)
P6.7/A7/DAC1 (2)/
SVSIN (2)
(1)
(2)
(3)
(4)
82
7
CONTROL BITS / SIGNALS (1)
A7
X
1
1 (y = 7)
0
DAC1 (DAC12OPS = 0) (4)
X
1
0
1
SVSIN (VLD = 15)
X
1
0
0
X = Don't care
MSP430F261x devices only
The ADC12 channel Ax is connected to AVSS internally if not selected.
The DAC outputs are floating if not selected.
Submit Documentation Feedback
Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger (5)
Pad Logic
P7REN.x
P7DIR.x
0
0
1
P7OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P7SEL.x
P7IN.x
EN
D
Module X IN
Table 24. Port P7 (P7.0 to P7.7) Pin Functions (1)
PIN NAME (P7.x)
P7.0
P7.1
x
0
1
P7.2
2
P7.3
3
P7.4
4
P7.5
5
P7.6
P7.7
(5)
(1)
(2)
6
7
FUNCTION
P7.0 (I/O)
Input
P7.1 (I/O)
Input
P7.2 (I/O)
Input
P7.3 (I/O)
Input
P7.4 (I/O)
Input
P7.5 (I/O)
Input
P7.6 (I/O)
Input
P7.7 (I/O)
Input
CONTROL BITS / SIGNALS (2)
P7DIR.x
P7SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin devices only
80-pin devices only
X = Don't care
Copyright © 2007–2011, Texas Instruments Incorporated
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MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
www.ti.com
Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger (3)
Pad Logic
P8REN.x
P8DIR.x
0
0
1
P8OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
Module X IN
D
Table 25. Port P8 (P8.0 to P8.5) Pin Functions (1)
PIN NAME (P8.x)
P8.0
x
0
P8.1
1
P8.2
2
P8.3
3
P8.4
4
P8.5
5
(3)
(1)
(2)
84
FUNCTION
P8.0 (I/O)
Input
P8.1 (I/O)
Input
P8.2 (I/O)
Input
P8.3 (I/O)
Input
P8.4 (I/O)
Input
P8.5 (I/O)
Input
CONTROL BITS / SIGNALS (2)
P8DIR.x
P8SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin devices only
80-pin devices only
X = Don't care
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Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
Port P8 (P8.6), Input/Output With Schmitt Trigger (3)
BCSCTL3.XT2Sx = 11
0
XT2CLK
1
From
P8.7/XIN
P8.7/XT2IN
XT2 off
Pad Logic
P8SEL.7
P8REN.6
P8DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.6
DVSS
P8.6/XT2OUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
Module X IN
D
Table 26. Port P8 (P8.6) Pin Functions (1)
PIN NAME (P8.x)
x
FUNCTION
P8.6 (I/O)
P8.6/XT2OUT
(3)
(1)
6
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XT2OUT (default)
0
1
DVSS
1
1
80-pin devices only
80-pin devices only
Copyright © 2007–2011, Texas Instruments Incorporated
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MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
www.ti.com
Port P8 (P8.7), Input/Output With Schmitt Trigger (2)
BCSCTL3.XT2Sx = 11
P8.6/XT2OUT
XT2 off
0
XT2CLK
1
Pad Logic
P8SEL.6
P8REN.7
0
P8DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.7
DVSS
P8.7/XT2IN
P8SEL.7
Bus
Keeper
EN
P8IN.7
EN
D
Module X IN
Table 27. Port P8 (P8.7) Pin Functions (1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XT2IN (default)
0
1
VSS
1
1
P8.7 (I/O)
P8.7/XT2IN
(2)
(1)
86
7
CONTROL BITS / SIGNALS
80-pin devices only
80-pin devices only
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Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
JTAG Pins: TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger
TDO
Controlled by JT AG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn and Test
Fuse
Test
TDI/TCLK
and
Emulation
Module
DVCC
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
Copyright © 2007–2011, Texas Instruments Incorporated
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MSP430F261x
MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 49). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITDI/TCLK
Figure 49. Fuse Check Mode Current
88
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Copyright © 2007–2011, Texas Instruments Incorporated
MSP430F261x
MSP430F241x
www.ti.com
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011
REVISION HISTORY
LITERATURE
NUMBER
DESCRIPTION
SLAS541
Product Preview release
SLAS541A
Production Data release
Corrected the format and the content shown on the first page.
Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list.
Corrected the port schematics.
Corrected "calibration data" section (page 20). Typos and formatting corrected.
Added the figure "typical characteristics - LPM4 current" (Page 33).
SLAS541B
Added preview of MSP430F261x BGA devices.
SLAS541C
Release to market of MSP430F261x BGA devices
SLAS541D
Added the ESD disclaimer (page 1).
Added reserved BGA pins to the terminal function list (pages 10 and following).
Corrected the references in the output port parameters (page 36).
Corrected the cumulative program time of the flash (page 75).
SLAS541E
Corrected LFXT1Sx values in Figures 23 and 24 (page 52).
Corrected XT2Sx values in Figures 25 and 26 (page 54).
Corrected tCMErase MIN value from 200 ms to 20 ms and removed two notes in the flash memory table (page 75).
SLAS541F
Renamed Tags Used by the ADC Calibration Tags table to Tags used by the TLV Structure (page 20).
Changed value of TAG_ADC12_1 from 0x10 to 0x08 in Tags used by the TLV Structure (page 20).
Added CAOUT to P1.0/TACLK, Changed Timer_A3.CCI0A to Timer_A3.CCI1A and Timer_A3.TA0 to Timer_A3.TA1 in
P1.2/TA1 row, Changed Timer_A3.CCI0A to Timer_A3.CCI2A and Timer_A3.TA0 to Timer_A3.TA2 in P1.3/TA2 row in
Port P1 (P1.0 to P1.7) pin functions table (page 78).
Changed TA0 to Timer_A3.CCI0B in P2.2/CAOUT/TA0/CA4 row of Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
table (page 80).
SLAS541G
Changed limits on td(SVSon) parameter (page 40)
SLAS541H
Changed Control Bits/Signals in Table 21, Table 22, and Table 23.
Changed crystal signal names in Table 26 and Table 27.
SLAS541I
Changed Tstg, Programmed device, to -55°C to 150°C in Absolute Maximum Ratings.
SLAS541J
Added nonmagnetic package option to Description and Table 1.
Copyright © 2007–2011, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
MSP430F2416TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2416TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2416TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2416TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2416TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2416TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2417TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2417TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2417TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2417TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2417TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2417TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2418TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2418TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2418TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Dec-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2418TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
MSP430F2418TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2418TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2419TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2419TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2419TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2419TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2419TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2419TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2616TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2616TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2616TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2616TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2616TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2616TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Addendum-Page 2
Samples
(Requires Login)
CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Dec-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F2617TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2617TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2617TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2617TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2617TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2617TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2618TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2618TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2618TPMR-NM
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
MSP430F2618TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2618TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2618TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2618TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2619TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2619TPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2619TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 3
CU SN
Samples
(Requires Login)
Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Dec-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430F2619TPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F2619TZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2619TZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430F2618 :
• Enhanced Product: MSP430F2618-EP
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2011
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430F2416TPMR
MSP430F2416TPNR
MSP430F2416TZQWR
Package Package Pins
Type Drawing
LQFP
LQFP
BGA MI
CROSTA
R JUNI
OR
PM
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2417TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2417TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2417TZQWR
BGA MI
CROSTA
R JUNI
OR
MSP430F2418TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2418TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2418TZQWR
BGA MI
CROSTA
R JUNI
OR
MSP430F2419TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2419TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
MSP430F2419TZQWR
BGA MI
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CROSTA
R JUNI
OR
MSP430F2616TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2616TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2616TZQWR
BGA MI
CROSTA
R JUNI
OR
MSP430F2617TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2617TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2617TZQWR
BGA MI
CROSTA
R JUNI
OR
MSP430F2618TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2618TPMR-NM
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2618TPNR
MSP430F2618TZQWR
LQFP
BGA MI
CROSTA
R JUNI
OR
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2619TPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F2619TPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430F2619TZQWR
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F2416TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2416TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2416TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2417TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2417TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2417TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2418TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2418TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2418TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2419TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2419TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2419TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2616TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2616TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2616TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2617TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2617TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F2617TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2618TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2618TPMR-NM
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2618TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2618TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430F2619TPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430F2619TPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F2619TZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
Pack Materials-Page 4
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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