WEDC EDI816256LPAXN44M 256kx16 monolithic sram, smd 5962-96795 Datasheet

White Electronic Designs
EDI816256CA
256Kx16 MONOLITHIC SRAM, SMD 5962-96795
The EDI816256CA is a 4 megabit Monolithic CMOS Static
RAM.
FEATURES
256Kx16 bit CMOS Static
Random Access Memory
The EDI816256CA uses 16 common input and output
lines and has an output enable pin which operates faster
than address access time at read cycle. The device allows
upper and lower byte access by use of the data byte control
pins (LB#, UB#).
• Access Times of 17, 20, 25, 35ns
• Data Retention Function (LPA version)
• TTL Compatible Inputs and Outputs
The devices are available in a fully hermetic 44 lead
ceramic SOJ and a 44 lead Ceramic Flatpack. The Ceramic
SOJ is pin for pin compatible with the commercially
available plastic SOJ. This allows the user the luxury of
designing a board that can be used for both the commercial
and military market.
• Fully Static, No Clocks
44 lead JEDEC Approved Revolutionary Pinout
• Ceramic SOJ (Package 322)
• Ceramic Flatpack (Package 323)
Single +5V (±10%) Supply Operation
A Low Power version with Data Retention (EDI816256LPA)
is also available for battery backed applications. Military
product is available compliant to Appendix A of MIL-PRF38535.
PIN CONFIGURATION
TOP VIEW
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
August 2004
Rev. 8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PIN DESCRIPTION
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
1
A0-17
Address Inputs
LB# (I/O1-8)
Lower-Byte Control (I/O1-8)
UB# (I/O9-16)
Upper-Byte Control (I/O9-16)
I/O1-16
Data Input/Output
CS#
Chip Select
OE#
Output Enable
WE#
Write Enable
VCC
+5.0V Power
VSS
Ground
NC
No Connection
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI816256CA
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
Unit
V
-0.5 to 7.0
0 to +70
-40 to +85
-55 to +125
-65 to +125
1.5
20
175
CS# WE# OE# LB# UB#
°C
°C
°C
°C
W
mA
°C
H
L
L
X
H
X
X
H
X
L
H
L
L
L
X
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
Mode
Data I/O
I/O1-8
High Z
I/O9-16
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
Data Out
Data Out
High Z
Data In
Data In
Not Select
Output
Disable
Read
Write
Supply
Current
ICC2, ICC3
ICC1
ICC1
RECOMMENDED OPERATING CONDITIONS
CAPACITANCE
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
TA = +25°C
Parameter
Address Lines
Data Lines
Symbol Condition
CI
VIN = Vcc or Vss, f = 1.0MHz
CD/Q VIN = Vcc or Vss, f = 1.0MHz
Max
12
14
Unit
pF
pF
Sym
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
Units
5.5
V
0
V
Vcc +0.5 V
0.8
V
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Symbol
ILI
ILO
ICC1
ICC2
ICC3
Output Low Voltage
Output High Voltage
VOL
VOH
Conditions
VIN = 0V to VCC
VI/O = 0V to VCC
WE#, CS# = VIL, II/O = OmA, Min Cycle
CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH
CS# ≥ VCC -0.2V
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
IOL = 6.0mA
IOH = -4.0mA
Min
CA
LPA
—
—
Max
10
10
300
60
25
16
0.4
2.4
Units
µA
µA
mA
mA
mA
mA
V
V
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
480Ω
Q
480Ω
Input Rise and Fall Times
Input and Output Timing Levels
Q
Output Load
255Ω
August 2004
Rev. 8
30pF
255Ω
VSS to 3.0V
5ns
1.5V
Figure 1
5pF
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2)
2
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White Electronic Designs
EDI816256CA
AC CHARACTERISTICS – READ CYCLE
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
LB#, UB# Access Time
JEDEC
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tUBLQV
tLBLQV
tUBLQX
tLBLQX
tUBHQZ
tLBHQZ
LB#, UB# Enable to Low Z Output
LB#, UB# Disable to High Z Output
17ns
20ns
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
tOE
tOLZ
tOHZ
tBA
Min
17
Max
tBLZ
0
0
tBHZ
0
7
Min
20
17
17
2
0
0
7
7
10
Min
25
5
0
0
7
7
10
5
0
0
8
7
Max
10
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
10
ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
5
0
0
10
12
0
0
8
12
0
0
Min
35
25
25
10
0
0
35ns
Max
20
20
10
0
0
25ns
Max
15
0
0
0
0
8
0
NOTE:
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
LB, UB Valid to End of Write
JEDEC
tAVAV
tELWH
tELEH
tAVWL
tAVEL
tAVUBL
tAVWH
tAVEH
tAVUBH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
tLBLLBH
tUBLUBH
17ns
Alt.
tWC
tCW
tCW
tAS
tAS
tAS
tAW
tAW
tAW
tWP
tWP
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
tBW
Min
17
14
14
0
0
0
14
14
14
14
14
0
0
0
0
0
10
10
0
14
20ns
Max
8
Min
20
15
15
0
0
0
15
15
15
14
14
0
0
0
0
0
10
10
0
16
25ns
Max
8
Min
25
17
17
0
0
0
17
17
17
15
15
0
0
0
0
0
12
12
0
18
35ns
Max
8
Min
35
20
20
0
0
0
20
20
20
17
17
0
0
0
0
0
15
15
0
20
10
NOTE:
1. This parameter is guaranteed by design but not tested.
August 2004
Rev. 8
3
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White Electronic Designs
EDI816256CA
TIMING WAVEFORM – READ CYCLE
tAVAV
ADDRESS
tAVQV
CS#
tAVAV
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
OE#
ADDRESS
ADDRESS 1
ADDRESS 2
DATA I/O
tAVQX
tAVQV
DATA I/O
DATA 1
tLBLQX
tUBLQX
tLBLQV
tUBLQV
DATA 2
LB#, UB#
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
tLBHQZ
tUBHQZ
READ CYCLE 2 (WE# HIGH)
WRITE CYCLE – WE# CONTROLLED
tAVAV
ADDRESS
tAVWH
tELWH
tWHAX
CS#
tLBLLBH
tUBLUBH
LB#, UB#
tAVWL
tWLWH
WE#
tDVWH
DATA IN
tWHDX
DATA VALID
tWLQZ
tWHQX
HIGH
DATA OUT
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
WRITE CYCLE - LB#, UB# CONTROLLED
tAVAV
tAVAV
ADDRESS
ADDRESS
tAVEH
tELEH
tEHAX
CS#
CS#
tAVEL
tAVUBL
tWLEH
tAVUBH
tUBLUBH
WE#
tDVEH
LB#, UB#
tWLWH
tDVWH
DATA VALID
DATA IN
HIGH
tWHDX
DATA VALID
tWLQX
tLBLLBH
tUBLUBH
DATA OUT
HIGH Z
DATA UNDEFINED
HIGH Z
WRITE CYCLE 3, LB#, UB# CONTROLLED
WRITE CYCLE 2, CS# CONTROLLED
August 2004
Rev. 8
tWHAV
tAVWH
tEHDX
WE#
DATA IN
DATA OUT
tUBHAV
LB#, UB#
4
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White Electronic Designs
EDI816256CA
DATA RETENTION CHARACTERISTICS (EDI816256LPA ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Sym
VCC
ICCDR
TCDR
TR
Conditions
VCC = 2.0V
CS# ≥ VCC -0.2V
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
Min
2
–
0
TAVAV
Typ
–
–
–
–
Max
–
2.2
–
–
Units
V
mA
ns
ns
NOTE:
1. This parameter is guaranteed by design but not tested.
* Read Cycle Time
DATA RETENTION – CS# CONTROLLED
DATA RETENTION MODE
4.5V
VCC
VCC
WS32K32-XHX
4.5V
tCDR
CS#
tR
CS# = VCC -0.2V
DATA RETENTION, CS# CONTROLLED
August 2004
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI816256CA
PACKAGE 322: 44 LEAD, CERAMIC SOJ
0.050 Typ
0.445
0.435
1.130
1.110
0.155
0.120
DIMENSIONS ARE IN INCHES
PACKAGE 323: 44 PIN, CERAMIC FLATPACK
1.130
1.110
0.007
0.003
0.515
0.505
0.395
0.385
1.00 Ref
0.038
0.032
Pin 1
0.045
0.015
0.370
0.250
0.019
0.015
0.050 Typ
0.115 Max.
DIMENSIONS ARE IN INCHES
August 2004
Rev. 8
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI816256CA
ORDERING INFORMATION
EDI 8 16256 CA X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 256Kx16
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
F44 = 44 pin Ceramic Flatpack (Package 323)
N44 = 44 lead Ceramic SOJ (Package 322)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened
August 2004
Rev. 8
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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