A-Data ADS6632A4A Synchronous DRAM 512K x 32 Bit x 4 Banks General Description Features The ADS6632A4A are four-bank Synchronous DRAMs organized as 524,288 words x 32 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system clock •Burst Read single write operation •Auto & Self refresh •4096 refresh cycle •DQM for masking •Package:86-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package ADS6632A4A-5 200Mhz LVTTL 400mil 86pin TSOPII ADS6632A4A-5.5 183Mhz LVTTL 400mil 86pin TSOPII ADS6632A4A-6 166Mhz LVTTL 400mil 86pin TSOPII Pin Assignment V DD D Q0 VDD Q D Q1 D Q2 VSSQ D Q3 D Q4 VDD Q DQ 5 DQ 6 VSSQ DQ 7 NC V DD DQM 0 WE CA S RA S CS NC BA0 BA1 A1 0/A P A0 A1 A2 D QM 2 V DD NC DQ 16 V S SQ DQ 17 DQ 18 V DD Q DQ 19 DQ 20 V S SQ DQ 21 DQ 22 V DD Q D Q 23 V DD Rev 1.0 April, 2001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 VS S DQ15 V S SQ DQ14 DQ13 VDDQ DQ12 DQ11 V S SQ DQ10 DQ9 VDD Q DQ8 NC VS S DQM 1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM 3 VS S NC DQ31 VDD Q DQ30 DQ29 VSSQ DQ28 DQ27 VDD Q DQ26 DQ25 VSSQ DQ24 VS S 86-pin plastic TSOP II 400mil A-Data ADS6632A4A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and DQM0 ~ DQM3 A0~A11 Address Row / Column address are multiplexed on the same pins. Row address : RA0~RA10 Column address : CA0~CA7 BA0~BA1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ31 Data DQM0~3 Data inputs / outputs are multiplexed on the same pins. Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Bank3 Bank2 Bank1 Mode Register Address Buffer & Refresh Counter Row Decoder Address Bank0 /CAS /WE Rev 1.0 April, 2001 Column Address Buffer & Refresh Counter DQM Column Decoder Data Control Circuit 2 Data Latch /RAS Control Logic /CS Command Decoder Amplifier DQ A-Data ADS6632A4A Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -1.0 ~ 4.6 V VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 ℃ Power dissipation PD 1 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH=-2mA Output logic low voltage VOL - - 0.4 V IOL=2mA Input leakage current IIL -5 - 5 uA 3 Output leakage current IOL -5 - 5 uA 4 Note Supply voltage Note Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable. 2.VIL(min)=-1.5V AC for pulse width ≦ 10ns acceptable. 3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≦ VOUT ≦ VDD. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input rise / fall time TR / tF 1 Ns Output timing measurement reference level Voutfef 1.4 V CL 30 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V ≦ VDD 2 ≦ 3.6V is applied for ADS6632A4A5. 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Rev 1.0 April, 2001 3 A-Data ADS6632A4A Capacitance TA=25℃, f-=1Mhz, VDD=3.3V Parameter Pin Input capacitance Symbol Min Max Unit CLK Cl1 2.5 4 pF A0~A11,BA0,BA1,CKE,/CS,/RAS, Cl2 2.5 5 pF CI/O 4 6.5 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit 3.3 V 1200 ohms VOH(DC) = 2.4V,I OH= -2mA Output VOL(DC) = 0.4V,I OL= 2mA 50 pF 870 ohms DC Characteristics I Parameter Symbol Min Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1.5 1.5 uA 2 Output high voltage VOH 2.4 - V IOH = -2mA Output low voltage VOL - 0.4 V IOL = 2mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1.0 April, 2001 4 A-Data ADS6632A4A DC Characteristics II Speed Parameter Symbol Test condition -5 -5.5 -6 210 200 190 Unit Note mA 1 Burst length=1, One bank active Operating Current Precharge standby IDD1 tRC≧tRC(min),IOL=0mA IDD2P CKE≦VIL(max), tCK=min 2 IDD2PS CKE≦VIL(max), tCK=∞ 2 current in power down mode mA CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Precharge standby IDD2N changed one time during 2clks. All current in Non power other pins ≧VDD-0.2V or ≦ down mode 0.2V 15 mA CKE≧VIH(min), tCK=∞ IDD2NS 12 Input signals are stable. Active standby current IDD3P CKE≦VIL(max), tCK=min 6 in power down mode CKE≦VIL(max), tCK=∞ 5 mA IDD3PS CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Active standby current IDD3N changed one time during 2clks. All in Non power down other pins ≧VDD-0.2V or ≦ mode 0.2V 30 mA CKE≧VIH(min), tCK=∞ IDD3NS 20 Input signals are stable. tCK≧tCK(min),IOL=0 mA Burst mode operating IDD4 current 280 270 260 mA 1 250 240 230 mA 2 All banks active tRRC≧tRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE≦0.2V 1 mA Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 1.0 April, 2001 5 A-Data ADS6632A4A AC Characteristics -5 Parameter System clock /CAS Latency = 3 -5.5 -6 Symbol tCK3 Unit Min Max Min 5 1000 5.5 Max Min Note Max 6 1000 1000 ns 2.5 - ns 1 - 2.5 - ns 1 - 5 - 5.5 ns 2 6 - 6 - 6 55 - 55 - 60 - tRRC 55 - 55 - 60 - /RAS to /CAS delay tRCD 15 - 16.5 - 18 - ns /RAS active time tRAS 40 100K 38.5 100K 42 100K ns /RAS precharge time tRP 15 - 16.5 - 18 - ns /RAS to /RAS bank active delay tRRD 10 - 11 - 12 - ns /CAS to /CAS delay tCCD 1 - 1 - 1 - CLK Write command to data – in delay tWTL 0 - 0 - 0 - CLK Data – in to precharge command tDPL 1 - 1 - 1 - CLK Data – in active command tDAL 5 - 5 - 5 - CLK DQM to data – out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to data – in mask tDQM 0 - 0 - 0 - CLK Data – out hold time tOH 1.5 - 2 - 2 - ns Data – input setup time tDS 1.5 - 1.5 - 1.5 - ns 1 Data – input hold time tDH 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - ns 1 Address hold time tAH 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - ns 1 CKE hold time tCKH 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - ns 1 Command hold time tCH 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - ns MRS to new command tMRD 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - CLK Refresh time tREF - 64 - 64 - 64 ms Cycle time /CAS Latency = 2 tCK2 10 10 10 Clock high pulse width tCHW 2 - 2.25 - Clock low pulse width tCLW 2 - 2.25 Access time form /CAS Latency = 3 tAC3 - 4.5 clock /CAS Latency = 2 tAC2 - Operation tRC Auto Refresh /RAS cycle time ns Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1.0 April, 2001 6 3 A-Data ADS6632A4A Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR A10/AP RA Read BA V L CA Read with Auto Precharge Write H X L H L L X CA Write with Auto Precharge H X L L H L X Precharge select Bank Burst Stop H DQM H Auto Refresh H H L L L Entry H L L L X L H H H X Exit L H L X X L H X X X H X X X Precharge L H H H Power down H X X X L H H H H X X X L V V V Exit Rev 1.0 April, 2001 L X X L X H X X L Clock Suspend V H H H L X H L X V H H H X L Entry V X X X Self Refresh Exit L H Precharge All Bank Entry V H X H X 7 X X A-Data ADS6632A4A Package Information Symbol Dimension in mm Norm Min A A1 A2 b b1 c c1 D ZD E E1 L L1 e R1 R2 1 0.05 0.95 0.17 0.17 0.12 0.10 0.10 1.00 0.20 0.127 22.22 BSC 0.61 REF 11.76 BSC 10.16 BSC 0.40 Max 1.20 0.15 1.05 0.27 0.23 0.21 0.16 0.50 0.60 Min 0.002 0.037 0.007 0.007 0.005 0.004 0.016 Dimension in inch Norm 0.004 0.039 0.008 0.005 0.875 BSC 0.024 REF 0.463 BSC 0.400 BSC 0.020 0.80 REF 0.50 BSC Max 0.047 0.006 0.011 0.018 0.009 0.008 0.006 0.024 0.031 REF 0.020 BSC 0.12 0.12 0.25 0.005 0.005 0.010 0 8 0 8 0 0 2 10 15 20 10 15 20 3 10 15 20 10 15 20 400mil 86pin TSOP II Package Rev 1.0 April, 2001 8