AD ADA4092-4ARUZ Micropower rrio operational amplifier Datasheet

Micropower RRIO Operational Amplifier
ADA4092-4
PIN CONFIGURATION
Single-supply operation: 3 V to 30 V
Wide input voltage range
Rail-to-rail output swing
Low supply current: 200 μA/amplifier
Wide bandwidth: 1.4 MHz
High phase margin: 69°
Slew rate: 0.4 V/μs
Low offset voltage: 1.50 mV maximum
No phase reversal
Overvoltage protection (OVP)
25 V above/below supply rails at ±5 V
12 V above/below supply rails at ±15 V
14
OUTD
–INA
2
13
–IND
+INA
3
ADA4092-4
12
+IND
+V
4
TOP VIEW
(Not to Scale)
11
–V
+INB 5
10
+INC
–INB
6
9
–INC
OUTB
7
8
OUTC
OUTA 1
08803-001
FEATURES
Figure 1. 14-Lead TSSOP (RU-14)
APPLICATIONS
Industrial process control
Battery-powered instrumentation
Power supply control and protection
Telecommunications
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifiers
GENERAL DESCRIPTION
The ADA4092-4 quad is a micropower, single-supply, 1.4 MHz
bandwidth amplifier featuring rail-to-rail inputs and outputs. It
is guaranteed to operate from a +3 V to +30 V single supply as
well as from ±1.5 V to ±15 V dual supplies.
The ADA4092-4 is specified over the extended industrial
temperature range of −40°C to +125°C. The ADA4092-4 is
part of the growing selection of 30 V, low power op amps from
Analog Devices, Inc., see Table 1.
The ADA4092-4 features a unique input stage that allows the
input voltage to exceed either supply safely without any phase
reversal or latch-up; this is called overvoltage protection (OVP).
The ADA4092-4 is available in the 14–lead TSSOP surface-mount
package.
Applications for these amplifiers include portable telecommunications equipment, power supply control and protection,
and interface for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers.
Table 1. Low Power, 30 V Operational Amplifiers
Family
Single
Dual
Quad
Rail-to-Rail I/O
RRIO
Precision
PJFET
ADA4092-4
ADA4091-2
ADA4091-4
AD8682
AD8684
Low
Noise
OP1177
OP2177
OP4177
The ability to swing rail-to-rail at both the input and output enables
designers, for example, to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios (SNR).
Rev. B
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Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
ADA4092-4* Product Page Quick Links
Last Content Update: 11/01/2016
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ADA4092-4
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................7
Pin Configuration ............................................................................. 1
Theory of Operation ...................................................................... 15
General Description ......................................................................... 1
Input Stage ................................................................................... 15
Revision History ............................................................................... 2
Output Stage................................................................................ 15
Specifications..................................................................................... 3
Input Overvoltage Protection ................................................... 16
Electrical Specifications ............................................................... 3
Comparator Operation .............................................................. 16
Absolute Maximum Ratings ............................................................ 6
Outline Dimensions ....................................................................... 17
Thermal Resistance ...................................................................... 6
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/11—Rev. A to Rev. B
Changes to Single-Supply Operating Range ................................. 1
5/10—Rev. 0 to Rev. A
Changes to Data Sheet Title, General Description,
and Table 1 ......................................................................................... 1
4/10—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADA4092-4
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VSY = ±1.5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−1.5
−2.5
+0.2
−40°C ≤ TA ≤ +125°C
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
VOS
ΔVOS/ΔT
IB
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
VOH
VOL
ISC
ZOUT
PSRR
ISY
VCM = −1.5 V to +1.5 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
−60
−60
−275
−4
−5
−75
−1.5
70
68
106
101
92
85
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C to +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
f = 1 MHz, AV = +1
1.485
1.480
1.470
1.455
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
98
90
3
−45
+1
+60
+275
+4
+5
+75
+1.5
85
113
94
1.495
1.480
−1.497
−1.495
−1.490
−1.480
−1.485
−1.475
±30
130
112
165
200
300
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
µA
µA
SR
tS
GBP
ΦM
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.4
25
1.2
66
V/µs
µs
MHz
Degrees
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Rev. B | Page 3 of 20
ADA4092-4
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−1.5
−2.5
+0.2
−40°C ≤ TA ≤ +125°C
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
VOS
ΔVOS/ΔT
IB
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
VOH
VOL
ISC
ZOUT
PSRR
ISY
VCM = −5.0 V to +5.0 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = ±4.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = ±4.7 V
−40°C ≤ TA ≤ +125°C
−60
−80
−350
−4
−7
−100
−5
82
78
113
106
98
90
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
f = 1 MHz, AV = +1
4.980
4.975
4.945
4.900
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
98
90
3
−53
+1
+80
+350
+4
+7
+100
+5
95
117
100
4.990
4.960
−4.997
−4.990
−4.990
−4.980
−4.980
−4.975
±20
90
112
180
225
300
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
µA
µA
SR
tS
GBP
ΦM
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.4
25
1.3
67
V/µs
µs
MHz
Degrees
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Rev. B | Page 4 of 20
ADA4092-4
VSY = ±15.0 V, VCM = 0 V, VO = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−1.5
−2.5
+0.2
−40°C ≤ TA ≤ +125°C
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
VOS
ΔVOS/ΔT
IB
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
VOH
VOL
ISC
ZOUT
PSRR
ISY
VCM = −15.0 V to +15.0 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = ±14.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = ±14.7 V
−40°C ≤ TA ≤ +125°C
−60
−80
−500
−4
−10
−140
−15
90
87
116
108
102
93
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
f = 1 MHz, AV = +1
14.970
14.950
14.900
14.800
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
98
90
SR
tS
GBP
ΦM
CS
RL = 100 kΩ, CL = 30 pF
To 0.01%
en p-p
en
3
−50
+1
+80
+500
+4
+10
+140
+15
103
118
104
14.980
14.915
−14.985
−14.970
−14.980
−14.965
−14.950
−14.940
±20
68
112
200
250
350
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
µA
µA
f = 1 kHz
0.4
25
1.4
69
100
V/µs
µs
MHz
Degrees
dB
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Rev. B | Page 5 of 20
ADA4092-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Input Current
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
θJA is specified for the device soldered on a 4-layer JEDEC standard
printed circuit board (PCB) with zero airflow.
Rating
36 V
Refer to the Input
Overvoltage
Protection
section
±VSY
±5 mA
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 6. Thermal Resistance
Package Type
14-Lead TSSOP (RU-14)
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 6 of 20
θJA
112
θJC
35
Unit
°C/W
ADA4092-4
TYPICAL PERFORMANCE CHARACTERISTICS
180
40
100
80
60
40
30
25
20
15
10
1200
OFFSET VOLTAGE (µV)
–2
–1
Figure 2. Input Offset Voltage Distribution, 3 V
1
2
3
4
TCVOS (μV/°C)
5
6
7
8
6
7
8
6
7
8
Figure 5. TCVOS Distribution, 3 V
180
70
ADA4092-4
VSY = ±5V
TA = 25°C
160
ADA4092-4
VSY = ±5V
TA = 25°C
60
NUMBER OF AMPLIFIERS
140
NUMBER OF PARTS
0
08803-002
800
1000
600
400
200
0
–200
–400
–600
0
–800
0
–1000
5
–1200
20
08803-005
120
08803-006
NUMBER OF AMPLIFIERS
NUMBER OF PARTS
140
ADA4092-4
VSY = ±1.5V
TA = 25°C
35
08803-007
ADA4092-4
VSY = ±1.5V
TA = 25°C
160
120
100
80
60
50
40
30
20
40
10
20
0
1200
OFFSET VOLTAGE (µV)
–2
–1
1
2
3
4
TCVOS (μV/°C)
5
Figure 6. TCVOS Distribution, 10 V
Figure 3. Input Offset Voltage Distribution, 10 V
70
180
ADA4092-4
VSY = ±15V
TA = 25°C
160
ADA4092-4
VSY = ±15V
TA = 25°C
60
NUMBER OF AMPLIFIERS
140
120
100
80
60
50
40
30
20
40
10
20
1200
–2
08803-004
800
OFFSET VOLTAGE (µV)
1000
600
400
200
0
–200
–400
–600
–800
–1000
0
–1200
NUMBER OF PARTS
0
08803-003
800
1000
600
400
200
0
–200
–400
–600
–800
–1000
–1200
0
–1
0
1
2
3
4
TCVOS (μV/°C)
5
Figure 7. TCVOS Distribution, 30 V
Figure 4. Input Offset Voltage Distribution, 30 V
Rev. B | Page 7 of 20
ADA4092-4
60
600
500
40
20
ADA4092-4
VSY = ±1.5V
TA = 25°C
300
IB (nA)
VOS (µV)
400
ADA4092-4
VSY = ±1.5V
T = 25°C
IOS
IB–
0
200
–20
100
–1.0
–0.5
0
0.5
1.0
1.5
VCM (V)
–40
–1.5
08803-008
0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
VCM (V)
Figure 8. Input Offset Voltage vs. Common-Mode Voltage, 3 V
Figure 11. Input Bias Current vs. Common-Mode Voltage, 3 V
600
60
500
08803-011
IB+
ADA4092-4
VSY = ±5V
T = 25°C
40
20
IB (nA)
VOS (µV)
400
300
0
ADA4092-4
VSY = ±5V
TA = 25°C
200
IOS
IB–
–20
100
–4
–3
–2
–1
0
1
VCM (V)
2
3
4
5
–40
–5
08803-009
0
–5
–3
–2
–1
0
1
2
3
4
5
VCM (V)
Figure 12. Input Bias Current vs. Common-Mode Voltage, 10 V
Figure 9. Input Offset Voltage vs. Common-Mode Voltage, 10 V
60
600
500
40
400
20
ADA4092-4
VSY = ±15V
TA = 25°C
300
IB (nA)
VOS (µV)
–4
08803-012
IB+
ADA4092-4
VSY = ±15V
T = 25°C
IOS
IB–
0
200
–5
0
5
10
15
VCM (V)
–40
–15
–10
–05
0
5
10
15
VCM (V)
Figure 10. Input Offset Voltage vs. Common-Mode Voltage, 30 V
Figure 13. Input Bias Current vs. Common-Mode Voltage, 30 V
Rev. B | Page 8 of 20
08803-013
–10
08803-010
0
–15
IB+
–20
100
ADA4092-4
120
10k
ADA4092-4
VSY = ±1.5V
TA = 25°C
GAIN (dB) AND PHASE (Degrees)
100
100
VDD – VOH
VOL – VSS
10
PHASE
80
60
40
GAIN
20
0
–20
ADA4092-4
VSY = ±1.5V
TA = 25°C
–40
–60
0.1
1
10
100
LOAD CURRENT (mA)
1k
1M
10M
Figure 17. Open-Loop Gain and Phase vs. Frequency, 3 V
120
10k
ADA4092-4
VSY = ±5V
TA = 25°C
100
VDD – VOH
VOL – VSS
10
PHASE
80
60
40
GAIN
20
0
–20
–40
ADA4092-4
VSY = ±5V
TA = 25°C
–60
–80
0.01
0.1
1
10
100
LOAD CURRENT (mA)
–100
08803-015
1
0.001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Dropout Voltage vs. Load Current, 10 V
08803-018
GAIN (dB) AND PHASE (Degrees)
100
1k
VOUT TO RAIL (mV)
100k
FREQUENCY (Hz)
Figure 14. Dropout Voltage vs. Load Current, 3 V
Figure 18. Open-Loop Gain and Phase vs. Frequency, 10 V
140
10k
ADA4092-4
VSY = ±15V
TA = 25°C
GAIN (dB) AND PHASE (Degrees)
120
1k
100
VDD – VOH
VOL – VSS
10
100
PHASE
80
60
40
GAIN
20
0
–20
ADA4092-4
VSY = ±15V
TA = 25°C
–40
–60
1
0.001
–80
0.01
0.1
1
10
LOAD CURRENT (mA)
100
08803-016
VOUT TO RAIL (mV)
10k
08803-017
0.01
08803-014
–80
1
0.001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. Dropout Voltage vs. Load Current, 30 V
Figure 19. Open-Loop Gain and Phase vs. Frequency, 30 V
Rev. B | Page 9 of 20
08803-019
VOUT TO RAIL (mV)
1k
ADA4092-4
50
ADA4092-4
VSY = ±1.5V
TA = 25°C
100
30
GAIN = +10
ZOUT (Ω)
20
10
AV = +100
10
AV = +10
GAIN = +1
0
1
AV = +1
–10
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
10
08803-020
–20
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
08803-023
CLOSED-LOOP GAIN (dB)
1k
ADA4092-4
VSY = ±1.5V
TA = 25°C
GAIN = +100
40
Figure 23. Closed-Loop Output Impedance vs. Frequency, 3 V
Figure 20. Closed-Loop Gain vs. Frequency, 3 V
50
ADA4092-4
VSY = ±5V
TA = 25°C
100
30
GAIN = +10
ZOUT (Ω)
20
10
AV = +100
10
AV = +10
GAIN = +1
0
1
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
10
08803-021
–20
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 21. Closed-Loop Gain vs. Frequency, 10 V
Figure 24. Closed-Loop Output Impedance vs. Frequency, 10 V
50
1k
ADA4092-4
VSY = ±15V
TA = 25°C
GAIN = +100
40
ADA4092-4
VSY = ±15V
TA = 25°C
100
30
GAIN = +10
ZOUT (Ω)
20
10
AV = +100
10
AV = +10
GAIN = +1
0
1
AV = +1
–10
–20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
08803-022
CLOSED-LOOP GAIN (dB)
100
08803-024
AV = +1
–10
Figure 22. Closed-Loop Gain vs. Frequency, 30 V
0.1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 25. Output Impedance vs. Frequency, 30 V
Rev. B | Page 10 of 20
10M
08803-025
CLOSED-LOOP GAIN (dB)
1k
ADA4092-4
VSY = ±5V
TA = 25°C
GAIN = +100
40
ADA4092-4
90
120
80
100
70
80
PSRR+
PSRR (dB)
CMRR (dB)
60
50
40
30
ADA4092-4
VSY = ±1.5V
TA = 25°C
60
40
PSRR–
20
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–20
100
08803-026
0
100
1k
10k
100k
1M
10M
08803-029
10
ADA4092-4
VSY = ±1.5V
TA = 25°C
1M
10M
08803-030
0
10M
08803-031
20
FREQUENCY (Hz)
Figure 29. PSRR vs. Frequency, 3 V
Figure 26. CMRR vs. Frequency, 3 V
120
100
90
100
80
80
60
PSRR (dB)
CMRR (dB)
70
50
40
ADA4092-4
VSY = ±5V
TA = 25°C
30
40
PSRR–
20
20
0
10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–20
100
08803-027
0
100
PSRR+
60
ADA4092-4
VSY = ±5V
TA = 25°C
1k
10k
100k
FREQUENCY (Hz)
Figure 30. PSRR vs. Frequency, 10 V
Figure 27. CMRR vs. Frequency, 10 V
120
100
90
100
80
80
PSRR (dB)
60
50
40
ADA4092-4
VSY = ±15V
TA = 25°C
30
60
PSRR–
40
20
0
10
0
100
PSRR+
20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
08803-028
CMRR (dB)
70
–20
100
ADA4092-4
VSY = ±15V
TA = 25°C
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 31. PSRR vs. Frequency, 30 V
Figure 28. CMRR vs. Frequency, 30 V
Rev. B | Page 11 of 20
ADA4092-4
2.0
0.06
1.5
0.04
1.0
0.02
0
ADA4092-4
VSY = ±1.5V
TA = 25°C
RL = 100kΩ
CL = 100pF
–1.0
–0.04
–1.5
0
20
10
40
30
50
60
70
80
TIME (µs)
–0.06
08803-032
–2.0
ADA4092-4
VSY = ±1.5V
TA = 25°C
RL = 100kΩ
CL = 100pF
–0.02
0
6
0.06
4
0.04
2
0.02
0
ADA4092-4
VSY = ±5V
TA = 25°C
RL = 100kΩ
CL = 100pF
60
100
80
120
140
160
TIME (µs)
–0.06
08803-033
–6
40
10
12
14
16
18
16
18
ADA4092-4
VSY = ±5V
TA = 25°C
RL = 100kΩ
CL = 100pF
–0.04
20
8
0
–0.02
–4
0
6
Figure 35. Small Signal Transient Response, 3 V
VOUT (V)
VOUT (V)
4
TIME (µs)
Figure 32. Large Signal Transient Response, 3 V
–2
2
0
2
4
6
8
10
12
14
TIME (µs)
Figure 33. Large Signal Transient Response, 10 V
08803-036
–0.5
0
08803-035
VOUT (V)
VOUT (V)
0.5
Figure 36. Small Signal Transient Response, 10 V
2.0
0.06
1.5
0.04
1.0
0.02
ADA4092-4
VSY = ±15V
TA = 25°C
RL = 100kΩ
CL = 100pF
–0.5
–1.0
0
ADA4092-4
VSY = ±15V
TA = 25°C
RL = 100kΩ
CL = 100pF
–0.02
–0.04
–1.5
–2.0
0
40
80
120
160
TIME (µs)
200
Figure 34. Large Signal Transient Response, 30 V
–0.06
0
2
4
6
8
10
12
14
16
TIME (µs)
Figure 37. Small Signal Transient Response, 30 V
Rev. B | Page 12 of 20
18
08803-037
VOUT (V)
0
08803-034
VOUT (V)
0.5
1.4
–0.2
1.2
–0.4
1.0
–0.6
0.8
ADA4092-4
VSY = ±1.5V
TA = 25°C
0.6
–0.8
–1.0
0.4
–1.2
0.2
–1.4
0
0
10
20
30
40
ADA4092-4
VSY = ±1.5V
TA = 25°C
60
50
70
80
90
TIME (µs)
–1.6
0
10
20
40
30
60
50
70
90
80
100
TIME (µs)
Figure 38. Positive Overload Recovery, 3 V
08803-041
0
VOUT (V)
1.6
08803-038
VOUT (V)
ADA4092-4
Figure 41. Negative Overload Recovery, 3 V
6
0
5
–1
4
VOUT (V)
VOUT (V)
–2
3
ADA4092-4
VSY = ±5V
TA = 25°C
2
–3
ADA4092-4
VSY = ±5V
TA = 25°C
–4
1
0
10
20
30
50
40
60
90
70
TIME (µs)
–6
08803-039
–1
0
10
20
30
50
40
60
80
70
90
TIME (µs)
Figure 39. Positive Overload Recovery, 10 V
08803-042
–5
0
Figure 42. Negative Overload Recovery, 10 V
16
0
14
–2
12
–4
10
VOUT (V)
ADA4092-4
VSY = ±15V
TA = 25°C
6
4
ADA4092-4
VSY = ±15V
TA = 25°C
–12
2
0
10
20
30
40
50
60
70
TIME (µs)
80
90
Figure 40. Positive Overload Recovery, 30 V
–16
0
10
20
30
40
50
60
70
TIME (µs)
Figure 43. Negative Overload Recovery, 30 V
Rev. B | Page 13 of 20
80
08803-043
–14
0
–2
–8
–10
08803-040
VOUT (V)
–6
8
ADA4092-4
0.5
1000
ADA4092-4
VSY = ±15V
TA = 25°C
0.4
ADA4092-4
VSY = ±15V
T = 25°C
0.3
en (nV/√Hz)
VOUT (µV)
0.2
0.1
0
100
–0.1
–0.2
1
2
3
4
6
5
7
8
9
10
TIME (µs)
10
0.01
10
100
1000
50k
Figure 46. Voltage Noise Density
200
–50
180
–60
CHANNEL SEPARATION (dB)
160
140
120
100
80
ADA4092-4
TA = 25°C
40
–70
–80
–90
–100
–110
–120
ADA4092-4
VSY = ±1.5V, ±5V, ±15V
TA = 25°C
–130
20
0
–140
0
4
8
12
16
20
24
28
VSUPPLY (V)
32
36
08803-045
ISUPPLY (µA)
1
FREQUENCY (Hz)
Figure 44. Peak-to-Peak Voltage Noise
60
0.10
08803-046
0
08803-044
–0.4
08803-047
–0.3
20
100
1k
10k
FREQUENCY (Hz)
Figure 47. Channel Separation vs. Frequency
Figure 45. Supply Current vs. Supply Voltage
Rev. B | Page 14 of 20
ADA4092-4
THEORY OF OPERATION
A common practice in bipolar amplifiers to protect the input
transistors from large differential voltages is to include series
resistors and differential diodes. See Figure 49 for the full input
protection circuitry. These diodes turn on whenever the differential
voltage exceeds approximately 0.6 V. In this condition, current
flows between the input pins, limited only by the two 5 kΩ
resistors. Evaluate each application carefully to make sure that
the increase in current does not affect performance.
The ADA4092-4 is a single-supply, micropower amplifier
featuring rail-to-rail inputs and outputs. To achieve wide input
and output ranges, these amplifiers employ unique input and
output stages.
INPUT STAGE
In Figure 48, the input stage comprises two differential pairs, a
PNP pair (PNP input stage) and an NPN pair (NPN input stage).
These input stages do not work in parallel. Instead, only one
stage is on for any given input common-mode signal level. The
PNP stage (Transistor Q1 and Transistor Q2) is required to ensure
that the amplifier remains in the linear region when the input
voltage approaches and reaches the negative rail. Alternatively,
the NPN stage (Transistor Q5 and Transistor Q6) is needed for
input voltages up to, and including, the positive rail.
OUTPUT STAGE
The output stage in the ADA4092-4 device uses a PNP and an
NPN transistor, as do most output stages. However, Q32 and
Q33, the output transistors, connect with their collectors to an
output pin to achieve the rail-to-rail output swing.
As the output voltage approaches either the positive or the
negative rail, these transistors begin to saturate. Thus, the final
limit on output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage has inherent gain arising
from the transistor output impedance, as well as any external load
impedance; consequently, the open-loop gain of the op amp is
dependent on the load resistance and decreases when the output
voltage is close to either rail.
For the majority of the input common-mode range, the PNP
stage is active, as shown in Figure 8 through Figure 13. Notice
that the VOS shifts and that the bias current switches direction at
approximately 1.5 V below the positive rail. At voltages below this
level, the bias current flows out of the ADA4092-4 input, from
the PNP input stage. However, above this voltage, the bias
current enters the device due to the NPN stage. The actual
mechanism within the amplifier for switching between the input
stages comprises Q3, Q4, and Q7. As the input common-mode
voltage increases, the emitters of Q1 and Q2 follow that voltage
plus a diode drop. Eventually, the emitters of Q1 and Q2 are
high enough to turn on Q3, which diverts the tail current away
from the PNP input stage, turning it off. The tail current of the
PNP pair is diverted to the Q4/Q7 current mirror to activate the
NPN input stage, as shown in Figure 48.
–IN
Q32
Q3
Q16
Q5 Q6
Q1 Q2
Q8
Q10
Q12
Q17
Q14
OUT
Q9
Q11
Q13
Q15
Q18
Q4
Q19
Q33
08803-124
+IN
Q7
Figure 48. Simplified Schematic Without Input Protection (See Figure 49)
Rev. B | Page 15 of 20
ADA4092-4
INPUT OVERVOLTAGE PROTECTION
The ADA4092-4 has two different ESD circuits for enhanced
protection, as shown in Figure 49.
+V
D3 R1
D7 R2
D8
D6
D1
D2
D5
D4
Additional resistance can be added externally in series with
each input to protect against higher peak voltages; however, the
additional thermal noise of the resistors must be considered.
08803-123
–V
Figure 49. Complete Input Protection Network
One circuit is a series resistor of 5 kΩ to the internal inputs and
diodes (D1 and D2 or D5 and D6) from the internal inputs to the
supply rails. The other protection circuit is a circuit with two
DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC
can be considered a bidirectional Zener diode with a transfer
characteristic, as shown in Figure 50.
5
4
3
CURRENT (mA)
Therefore, consider two conditions to determine which case is
the limiting factor.
1. Consider, for example, that when operating on ±15 V, the
inputs can go +42 V above the negative supply rail. With
the −V pin equal to −15 V, +42 V above this supply (the
negative supply) is +27 V.
2. There is a restriction on the input current of 5 mA through
a 5 kΩ resistor to the ESD structure to the positive rail. In
the first condition, +27 V through the 5 kΩ resistor to +15 V
gives a current of 2.4 mA. Thus, the DIAC is the limiting
factor. If the ADA4092-4 supply voltages are changed to ±5 V,
then −5 V + 42 V = +37 V. However, +5 V + (5 kΩ × 5 mA) =
30 V. Thus, the normal resistor diode structure is the
limitation when running on lower supply voltages.
2
1
0
–1
–2
The flatband voltage noise of the ADA4092-4 is approximately
25 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding
an additional 5 kΩ resistor increases the total noise by less than
15% root sum square (rss). Therefore, maintain resistor values
below this value (5 kΩ) when overall noise performance is critical.
Note that this represents input protection under abnormal
conditions only. The correct amplifier operation input voltage
range (IVR) is specified in Table 2, Table 3, and Table 4.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp
can be pressed into service as a comparator; however, this is not
recommended. For rail-to-rail output op amps, the output stage
is generally a ratioed current mirror with bipolar or MOSFET
transistors. With the part operating open loop, the second stage
increases the current drive to the ratioed mirror to close the loop,
but it cannot, which results in an increase in supply current. With
three of the op amps operating normally and the fourth one in
comparator mode, the supply current increases by about 200 µA
(see Figure 51).
1000
ONE COMPARATOR, VOUT HIGH
–30
–20
–10
0
10
20
30
VOLTAGE (V)
40
50
900
ONE COMPARATOR, VOUT LOW
800
Figure 50. DIAC Transfer Characteristic
700
NORMAL OPERATION
600
ISY (µA)
For a worst-case design analysis, consider two cases. The
ADA4092-4 has a normal ESD structure from the internal op
amp inputs to the supply rails. In addition, it has 42 V DIACs
from the external inputs to the rails, as shown in Figure 48.
500
400
300
200
100
0
0
4
8
12
16
20
VSY (V)
24
28
Figure 51. Comparator Supply Current
Rev. B | Page 16 of 20
32
36
08803-051
–40
08803-100
–3
–50
ADA4092-4
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
0.15
0.05
COPLANARITY
0.10
1.20
MAX
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
1.05
1.00
0.80
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4092-4ARUZ
ADA4092-4ARUZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
Rev. B | Page 17 of 20
Package Option
RU-14
RU-14
ADA4092-4
NOTES
Rev. B | Page 18 of 20
ADA4092-4
NOTES
Rev. B | Page 19 of 20
ADA4092-4
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08803-0-6/11(B)
Rev. B | Page 20 of 20